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Searched refs:LW (Results 1 – 25 of 68) sorted by relevance

123

/third_party/skia/third_party/externals/libpng/mips/
Dfilter_msa_intrinsics.c45 #define LW(psrc) \ macro
116 #define LW(psrc) \ macro
184 #define LW(psrc) \ macro
472 inp0 = LW(src); in png_read_filter_row_sub4_msa()
513 inp0 = LW(src); in png_read_filter_row_sub3_msa()
554 inp0 = LW(pp); in png_read_filter_row_avg4_msa()
556 inp1 = LW(src); in png_read_filter_row_avg4_msa()
609 inp0 = LW(pp); in png_read_filter_row_avg3_msa()
611 inp1 = LW(src); in png_read_filter_row_avg3_msa()
670 inp0 = LW(nxt); in png_read_filter_row_paeth4_msa()
[all …]
/third_party/ffmpeg/libavcodec/mips/
Dvp9_intra_msa.c68 inp = LW(src); in ff_hor_16x16_msa()
89 inp = LW(src); in ff_hor_32x32_msa()
117 val0 = LW(src_top); in ff_dc_4x4_msa()
118 val1 = LW(src_left); in ff_dc_4x4_msa()
140 val0 = LW(dir); \
368 left = LW(src_left); in ff_tm_4x4_msa()
399 left = LW(src_left); in ff_tm_8x8_msa()
431 left = LW(src_left); in ff_tm_16x16_msa()
483 left = LW(src_left); in ff_tm_32x32_msa()
Dh264idct_msa.c291 src0_m = LW(dst); in ff_h264_idct_add_msa()
292 src1_m = LW(dst1); in ff_h264_idct_add_msa()
294 src2_m = LW(dst2); in ff_h264_idct_add_msa()
295 src3_m = LW(dst3); in ff_h264_idct_add_msa()
325 const uint32_t src0 = LW(dst); in ff_h264_idct4x4_addblk_dc_msa()
326 const uint32_t src1 = LW(dst + dst_stride); in ff_h264_idct4x4_addblk_dc_msa()
327 const uint32_t src2 = LW(dst + 2 * dst_stride); in ff_h264_idct4x4_addblk_dc_msa()
328 const uint32_t src3 = LW(dst + 3 * dst_stride); in ff_h264_idct4x4_addblk_dc_msa()
Dhevcpred_msa.c71 src_data = LW(src_top); in hevc_intra_pred_vert_4x4_msa()
75 src_data = LW(src_left); in hevc_intra_pred_vert_4x4_msa()
207 val0 = LW(src_top); in hevc_intra_pred_horiz_4x4_msa()
353 val0 = LW(src_top); in hevc_intra_pred_dc_4x4_msa()
354 val1 = LW(src_left); in hevc_intra_pred_dc_4x4_msa()
559 src0 = LW(src_top); in hevc_intra_pred_plane_4x4_msa()
560 src1 = LW(src_left); in hevc_intra_pred_plane_4x4_msa()
1046 tmp0 = LW(ref); in hevc_intra_pred_angular_upper_8width_msa()
1047 tmp1 = LW(ref + 4); in hevc_intra_pred_angular_upper_8width_msa()
1048 tmp2 = LW(ref + 8); in hevc_intra_pred_angular_upper_8width_msa()
[all …]
Dhevc_idct_msa.c465 cnst0 = LW(filter_ptr2); in hevc_idct_8x32_column_msa()
466 cnst1 = LW(filter_ptr2 + 2); in hevc_idct_8x32_column_msa()
476 cnst0 = LW(filter_ptr2 + 4); in hevc_idct_8x32_column_msa()
477 cnst1 = LW(filter_ptr2 + 6); in hevc_idct_8x32_column_msa()
493 cnst0 = LW(filter_ptr3); in hevc_idct_8x32_column_msa()
494 cnst1 = LW(filter_ptr3 + 2); in hevc_idct_8x32_column_msa()
Dhpeldsp_msa.c231 dst0 = LW(dst); in common_hz_bil_and_aver_dst_4w_msa()
232 dst1 = LW(dst + dst_stride); in common_hz_bil_and_aver_dst_4w_msa()
458 dst0 = LW(dst); in common_vt_bil_and_aver_dst_4w_msa()
459 dst1 = LW(dst + dst_stride); in common_vt_bil_and_aver_dst_4w_msa()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp205 return Mips::LW; in selectLoadStoreOpCode()
355 MachineInstr *LW = in select() local
356 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
362 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) in select()
367 LW->getOperand(0).setReg(DestTmp); in select()
570 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
626 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
DMicroMipsSizeReduction.cpp240 {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,
242 {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
355 !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM || in CheckXWPInstr()
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) || in ReduceXWtoXWP()
DMipsSEInstrInfo.cpp49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
333 Opc = Mips::LW; in loadRegFromStack()
362 Opc = Mips::LW; in loadRegFromStack()
366 Opc = Mips::LW; in loadRegFromStack()
DRelocation.txt79 register classes. In some cases, such as LW/LW64, this also accounts
DMipsFastISel.cpp422 emitInst(Mips::LW, DestReg) in materializeGV()
439 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
766 Opc = Mips::LW; in emitLoad()
/third_party/ffmpeg/libavutil/mips/
Dgeneric_macros_msa.h54 #define LW(psrc) \ macro
73 val0_ld_m = LW(psrc_ld_m); \
74 val1_ld_m = LW(psrc_ld_m + 4); \
104 #define LW(psrc) \ macro
143 val0_ld_m = LW(psrc_ld_m); \
144 val1_ld_m = LW(psrc_ld_m + 4); \
204 out0 = LW((psrc)); \
205 out1 = LW((psrc) + stride); \
206 out2 = LW((psrc) + 2 * stride); \
207 out3 = LW((psrc) + 3 * stride); \
[all …]
/third_party/skia/third_party/externals/libwebp/src/dsp/
Dmsa_macro.h101 #define LW(psrc) MSA_LOAD(psrc, msa_lw) macro
120 #define LW(psrc) MSA_LOAD(psrc, msa_ulw) macro
152 out0 = LW(ptmp); \
154 out1 = LW(ptmp); \
156 out2 = LW(ptmp); \
158 out3 = LW(ptmp); \
Ddec_msa.c709 const uint32_t val0 = LW(ptop + 0); in VE4()
710 const uint32_t val1 = LW(ptop + 4); in VE4()
726 uint32_t val0 = LW(ptop + 0); in RD4()
727 uint32_t val1 = LW(ptop + 4); in RD4()
754 uint32_t val0 = LW(ptop + 0); in LD4()
755 uint32_t val1 = LW(ptop + 4); in LD4()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp224 case Mips::LW: in isBasePlusOffsetMemoryAccess()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp214 case RISCV::LW: in detectAndFoldOffset()
DRISCVISelDAGToDAG.cpp221 case RISCV::LW: in doPeepholeLoadStoreADDI()
DRISCVInstrInfo.cpp48 case RISCV::LW: in isLoadFromStackSlot()
153 RISCV::LW : RISCV::LD; in loadRegFromStackSlot()
DRISCVExpandPseudoInsts.cpp681 SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; in expandLoadAddress()
696 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; in expandLoadTLSIEAddress()
DRISCVInstrInfo.td399 def LW : Load_ri<0b010, "lw">, Sched<[WriteLDW, ReadMemBase]>;
692 (LW GPR:$rd, GPR:$rs1, 0)>;
1008 defm : LdPat<load, LW>, Requires<[IsRV32]>;
1089 defm : LdPat<sextloadi32, LW>;
1090 defm : LdPat<extloadi32, LW>;
/third_party/openh264/codec/common/inc/
Dmsa_macros.h45 #define LW(psrc) \ macro
64 val0_ld_m = LW(psrc_ld_m); \
65 val1_ld_m = LW(psrc_ld_m + 4); \
95 #define LW(psrc) \ macro
132 val0_ld_m = LW(psrc_ld_m); \
133 val1_ld_m = LW(psrc_ld_m + 4); \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp1722 SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadAddress()
1741 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadTLSIEAddress()
1846 emitLoadStoreSymbol(Inst, RISCV::LW, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
/third_party/node/deps/v8/src/codegen/mips/
Dconstants-mips.h471 LW = ((4U << 3) + 3) << kOpcodeShift, enumerator
1267 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
/third_party/node/deps/v8/src/codegen/mips64/
Dconstants-mips64.h460 LW = ((4U << 3) + 3) << kOpcodeShift, enumerator
1316 OpcodeToBitNumber(LWL) | OpcodeToBitNumber(LW) | OpcodeToBitNumber(LWU) |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DP9InstrResources.td130 (instregex "CMP(WI|LWI|W|LW)(8)?$"),
402 (instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?(O)?$")
1388 (instregex "EVR(LW|LWI|NDW)$"),

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