Searched refs:MAX_SETS (Results 1 – 25 of 39) sorted by relevance
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108 if (tex_idx > PANVK_MAX_TEXTURES / MAX_SETS || in panvk_GetDescriptorSetLayoutSupport()109 sampler_idx > PANVK_MAX_SAMPLERS / MAX_SETS || in panvk_GetDescriptorSetLayoutSupport()110 ubo_idx > PANVK_MAX_UBOS / MAX_SETS || in panvk_GetDescriptorSetLayoutSupport()111 img_idx > PANVK_MAX_IMAGES / MAX_SETS) in panvk_GetDescriptorSetLayoutSupport()
339 #define MAX_SETS 4 macro429 } sets[MAX_SETS];575 const struct panvk_descriptor_set *sets[MAX_SETS];
678 .maxBoundDescriptorSets = MAX_SETS, in panvk_GetPhysicalDeviceProperties2()
14 #define MAX_SETS 4 macro86 } set[MAX_SETS];
179 set = MAX_SETS; in lower_vulkan_resource_index()263 nir_ssa_def *results[MAX_SETS + 1] = { NULL }; in lower_ssbo_ubo_intrinsic()273 for (unsigned i = 0; i < MAX_SETS + 1; i++) { in lower_ssbo_ubo_intrinsic()312 for (int i = MAX_SETS; i >= 0; i--) { in lower_ssbo_ubo_intrinsic()
48 struct tu_descriptor_set *sets[MAX_SETS];
443 assert(set < MAX_SETS); in tu_CreatePipelineLayout()1160 assert(pCreateInfo->set < MAX_SETS); in tu_CreateDescriptorUpdateTemplate()
2032 uint64_t addr[MAX_SETS + 1] = {}; in tu_CmdBindDescriptorSets()2035 for (uint32_t i = 0; i < MAX_SETS; i++) { in tu_CmdBindDescriptorSets()2054 addr[MAX_SETS] = dynamic_desc_set.iova | 3; in tu_CmdBindDescriptorSets()
313 #define MAX_SETS 4 macro339 } sets[MAX_SETS];657 } sets[MAX_SETS];661 } binding_translation[MAX_SETS];702 DZN_REGISTER_SPACE_SYSVALS = MAX_SETS,751 } sets[MAX_SETS];
481 sampler_count <= (MAX_DESCS_PER_SAMPLER_HEAP / MAX_SETS) && in dzn_GetDescriptorSetLayoutSupport()482 other_desc_count <= (MAX_DESCS_PER_CBV_SRV_UAV_HEAP / MAX_SETS); in dzn_GetDescriptorSetLayoutSupport()
36 #define MAX_SETS 16 macro
1232 struct v3dv_descriptor_set *descriptor_sets[MAX_SETS];1796 } set[MAX_SETS];
83 #define MAX_SETS 32 macro
38 struct ac_arg descriptor_sets[MAX_SETS];
97 } set[MAX_SETS];
195 struct radv_userdata_info descriptor_sets[MAX_SETS];
248 for (i = 0; i < MAX_SETS; i++) { in radv_dump_descriptors()
552 for (int i = 0; i < MAX_SETS; i++) in radv_declare_shader_args()
84 #define MAX_SETS 8 macro417 uint16_t uniform_block_sizes[MAX_PER_STAGE_DESCRIPTOR_UNIFORM_BLOCKS * MAX_SETS];
244 …ert(layout->stage[i].uniform_block_count + j < MAX_PER_STAGE_DESCRIPTOR_UNIFORM_BLOCKS * MAX_SETS); in lvp_CreatePipelineLayout()
276 .maxBoundDescriptorSets = MAX_SETS, in lvp_physical_device_init()1141 …TotalSize = MAX_DESCRIPTOR_UNIFORM_BLOCK_SIZE * MAX_PER_STAGE_DESCRIPTOR_UNIFORM_BLOCKS * MAX_SETS; in lvp_get_physical_device_properties_1_3()
243 if (binding->set < MAX_SETS && robust_buffer_access) { in anv_nir_compute_push_layout()
207 #define MAX_SETS 32 macro2203 } set[MAX_SETS];2515 uint64_t desc_sets[MAX_SETS];2628 struct anv_descriptor_set *descriptors[MAX_SETS];2629 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
589 assert(firstSet + descriptorSetCount <= MAX_SETS); in anv_CmdBindDescriptorSets()935 assert(_set < MAX_SETS); in anv_CmdPushDescriptorSetKHR()
61 } set[MAX_SETS];