Searched refs:OP_FVF (Results 1 – 4 of 4) sorted by relevance
/third_party/node/deps/v8/src/codegen/riscv64/ |
D | constants-riscv64.h | 640 OP_FVF = OP_V | (0b101 << kFunct3Shift), enumerator 832 RO_V_VFMV_VF = OP_FVF | (VMV_FUNCT6 << kRvvFunct6Shift), 928 RO_V_VFMV_SF = OP_FVF | (VRFUNARY0_FUNCT6 << kRvvFunct6Shift), 965 RO_V_VFADD_VF = OP_FVF | (VFADD_FUNCT6 << kRvvFunct6Shift), 969 RO_V_VFSUB_VF = OP_FVF | (VFSUB_FUNCT6 << kRvvFunct6Shift), 973 RO_V_VFDIV_VF = OP_FVF | (VFDIV_FUNCT6 << kRvvFunct6Shift), 977 RO_V_VFMUL_VF = OP_FVF | (VFMUL_FUNCT6 << kRvvFunct6Shift), 982 RO_V_VFWADD_VF = OP_FVF | (VFWADD_FUNCT6 << kRvvFunct6Shift), 986 RO_V_VFWSUB_VF = OP_FVF | (VFWSUB_FUNCT6 << kRvvFunct6Shift), 990 RO_V_VFWADD_W_VF = OP_FVF | (VFWADD_W_FUNCT6 << kRvvFunct6Shift), [all …]
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D | assembler-riscv64.cc | 1201 DCHECK(opcode == OP_FVF); in GenInstrV() 2633 GenInstrV(funct6, OP_FVF, vd, fs1, vs2, mask); \ 2639 GenInstrV(funct6, OP_FVF, vd, fs1, vs2, mask); \ 2651 GenInstrV(funct6, OP_FVF, vd, fs1, vs2, mask); \ 2661 GenInstrV(VMV_FUNCT6, OP_FVF, vd, fs1, v0, mask); in vfmv_vf() 2669 GenInstrV(VRFUNARY0_FUNCT6, OP_FVF, vd, fs, v0, NoMask); in vfmv_sf()
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/third_party/node/deps/v8/src/diagnostics/riscv64/ |
D | disasm-riscv64.cc | 2538 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_FVF); in DecodeRvvFVF() 2626 case OP_FVF: in DecodeVType()
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/third_party/node/deps/v8/src/execution/riscv64/ |
D | simulator-riscv64.cc | 6653 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_FVF); in DecodeRvvFVF() 6797 case OP_FVF: in DecodeVType()
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