1 // Copyright 2021 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // Copyright(c) 2010 - 2017,
6 // The Regents of the University of California(Regents).All Rights Reserved.
7 //
8 // Redistribution and use in source and binary forms,
9 // with or without modification,
10 // are permitted provided that the following
11 // conditions are met : 1. Redistributions of source code must retain the
12 // above copyright notice, this list of conditions and the following
13 // disclaimer.2. Redistributions in binary form must reproduce the above
14 // copyright notice, this list of conditions and the following disclaimer in
15 // the
16 // documentation and /
17 // or
18 // other materials provided with the distribution.3. Neither the name of
19 // the Regents nor the names of its contributors may be used to endorse
20 // or
21 // promote products derived from
22 // this software without specific prior written permission.
23 //
24 // IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT,
25 // INDIRECT, SPECIAL,
26 // INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
27 // ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
28 // EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 //
30 // REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES,
31 // INCLUDING, BUT NOT LIMITED TO,
32 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
33 // PARTICULAR PURPOSE.THE SOFTWARE AND ACCOMPANYING DOCUMENTATION,
34 // IF ANY,
35 // PROVIDED HEREUNDER IS PROVIDED
36 // "AS IS".REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE,
37 // SUPPORT, UPDATES, ENHANCEMENTS,
38 // OR MODIFICATIONS.
39
40 // The original source code covered by the above license above has been
41 // modified significantly by the v8 project authors.
42
43 #include "src/execution/riscv64/simulator-riscv64.h"
44
45 // Only build the simulator if not compiling for real RISCV hardware.
46 #if defined(USE_SIMULATOR)
47
48 #include <limits.h>
49 #include <math.h>
50 #include <stdarg.h>
51 #include <stdlib.h>
52
53 #include "src/base/bits.h"
54 #include "src/base/overflowing-math.h"
55 #include "src/base/vector.h"
56 #include "src/codegen/assembler-inl.h"
57 #include "src/codegen/macro-assembler.h"
58 #include "src/codegen/riscv64/constants-riscv64.h"
59 #include "src/diagnostics/disasm.h"
60 #include "src/heap/combined-heap.h"
61 #include "src/runtime/runtime-utils.h"
62 #include "src/utils/ostreams.h"
63 #include "src/utils/utils.h"
64
65 // The following code about RVV was based from:
66 // https://github.com/riscv/riscv-isa-sim
67 // Copyright (c) 2010-2017, The Regents of the University of California
68 // (Regents). All Rights Reserved.
69
70 // Redistribution and use in source and binary forms, with or without
71 // modification, are permitted provided that the following conditions are met:
72 // 1. Redistributions of source code must retain the above copyright
73 // notice, this list of conditions and the following disclaimer.
74 // 2. Redistributions in binary form must reproduce the above copyright
75 // notice, this list of conditions and the following disclaimer in the
76 // documentation and/or other materials provided with the distribution.
77 // 3. Neither the name of the Regents nor the
78 // names of its contributors may be used to endorse or promote products
79 // derived from this software without specific prior written permission.
80
81 // IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
82 // SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
83 // ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
84 // REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
85
86 // REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
87 // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
88 // PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
89 // HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
90 // MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
is_aligned(const unsigned val,const unsigned pos)91 static inline bool is_aligned(const unsigned val, const unsigned pos) {
92 return pos ? (val & (pos - 1)) == 0 : true;
93 }
94
is_overlapped(const int astart,int asize,const int bstart,int bsize)95 static inline bool is_overlapped(const int astart, int asize, const int bstart,
96 int bsize) {
97 asize = asize == 0 ? 1 : asize;
98 bsize = bsize == 0 ? 1 : bsize;
99
100 const int aend = astart + asize;
101 const int bend = bstart + bsize;
102
103 return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize;
104 }
is_overlapped_widen(const int astart,int asize,const int bstart,int bsize)105 static inline bool is_overlapped_widen(const int astart, int asize,
106 const int bstart, int bsize) {
107 asize = asize == 0 ? 1 : asize;
108 bsize = bsize == 0 ? 1 : bsize;
109
110 const int aend = astart + asize;
111 const int bend = bstart + bsize;
112
113 if (astart < bstart && is_overlapped(astart, asize, bstart, bsize) &&
114 !is_overlapped(astart, asize, bstart + bsize, bsize)) {
115 return false;
116 } else {
117 return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize;
118 }
119 }
120
121 #ifdef DEBUG
122 #define require_align(val, pos) \
123 if (!is_aligned(val, pos)) { \
124 std::cout << val << " " << pos << std::endl; \
125 } \
126 CHECK_EQ(is_aligned(val, pos), true)
127 #else
128 #define require_align(val, pos) CHECK_EQ(is_aligned(val, pos), true)
129 #endif
130
131 // RVV
132 // The following code about RVV was based from:
133 // https://github.com/riscv/riscv-isa-sim
134 // Copyright (c) 2010-2017, The Regents of the University of California
135 // (Regents). All Rights Reserved.
136
137 // Redistribution and use in source and binary forms, with or without
138 // modification, are permitted provided that the following conditions are met:
139 // 1. Redistributions of source code must retain the above copyright
140 // notice, this list of conditions and the following disclaimer.
141 // 2. Redistributions in binary form must reproduce the above copyright
142 // notice, this list of conditions and the following disclaimer in the
143 // documentation and/or other materials provided with the distribution.
144 // 3. Neither the name of the Regents nor the
145 // names of its contributors may be used to endorse or promote products
146 // derived from this software without specific prior written permission.
147
148 // IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
149 // SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
150 // ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
151 // REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
152
153 // REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
154 // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
155 // PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
156 // HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
157 // MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
158 #ifdef CAN_USE_RVV_INSTRUCTIONS
159 template <uint64_t N>
160 struct type_usew_t;
161 template <>
162 struct type_usew_t<8> {
163 using type = uint8_t;
164 };
165
166 template <>
167 struct type_usew_t<16> {
168 using type = uint16_t;
169 };
170
171 template <>
172 struct type_usew_t<32> {
173 using type = uint32_t;
174 };
175
176 template <>
177 struct type_usew_t<64> {
178 using type = uint64_t;
179 };
180
181 template <>
182 struct type_usew_t<128> {
183 using type = __uint128_t;
184 };
185 template <uint64_t N>
186 struct type_sew_t;
187
188 template <>
189 struct type_sew_t<8> {
190 using type = int8_t;
191 };
192
193 template <>
194 struct type_sew_t<16> {
195 using type = int16_t;
196 };
197
198 template <>
199 struct type_sew_t<32> {
200 using type = int32_t;
201 };
202
203 template <>
204 struct type_sew_t<64> {
205 using type = int64_t;
206 };
207
208 template <>
209 struct type_sew_t<128> {
210 using type = __int128_t;
211 };
212
213 #define VV_PARAMS(x) \
214 type_sew_t<x>::type& vd = \
215 Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
216 type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
217 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
218
219 #define VV_UPARAMS(x) \
220 type_usew_t<x>::type& vd = \
221 Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
222 type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
223 type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
224
225 #define VX_PARAMS(x) \
226 type_sew_t<x>::type& vd = \
227 Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
228 type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
229 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
230
231 #define VX_UPARAMS(x) \
232 type_usew_t<x>::type& vd = \
233 Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
234 type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
235 type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
236
237 #define VI_PARAMS(x) \
238 type_sew_t<x>::type& vd = \
239 Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
240 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
241 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
242
243 #define VI_UPARAMS(x) \
244 type_usew_t<x>::type& vd = \
245 Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
246 type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
247 type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
248
249 #define VN_PARAMS(x) \
250 constexpr int half_x = x >> 1; \
251 type_sew_t<half_x>::type& vd = \
252 Rvvelt<type_sew_t<half_x>::type>(rvv_vd_reg(), i, true); \
253 type_sew_t<x>::type uimm5 = (type_sew_t<x>::type)(instr_.RvvUimm5()); \
254 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
255
256 #define VN_UPARAMS(x) \
257 constexpr int half_x = x >> 1; \
258 type_usew_t<half_x>::type& vd = \
259 Rvvelt<type_usew_t<half_x>::type>(rvv_vd_reg(), i, true); \
260 type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
261 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
262
263 #define VXI_PARAMS(x) \
264 type_sew_t<x>::type& vd = \
265 Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
266 type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
267 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
268 type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
269 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
270
271 #define VI_XI_SLIDEDOWN_PARAMS(x, off) \
272 auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
273 auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
274
275 #define VI_XI_SLIDEUP_PARAMS(x, offset) \
276 auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
277 auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
278
279 /* Vector Integer Extension */
280 #define VI_VIE_PARAMS(x, scale) \
281 if ((x / scale) < 8) UNREACHABLE(); \
282 auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
283 auto vs2 = Rvvelt<type_sew_t<x / scale>::type>(rvv_vs2_reg(), i);
284
285 #define VI_VIE_UPARAMS(x, scale) \
286 if ((x / scale) < 8) UNREACHABLE(); \
287 auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
288 auto vs2 = Rvvelt<type_usew_t<x / scale>::type>(rvv_vs2_reg(), i);
289
290 #define require_noover(astart, asize, bstart, bsize) \
291 CHECK_EQ(!is_overlapped(astart, asize, bstart, bsize), true)
292 #define require_noover_widen(astart, asize, bstart, bsize) \
293 CHECK_EQ(!is_overlapped_widen(astart, asize, bstart, bsize), true)
294
295 #define RVV_VI_GENERAL_LOOP_BASE \
296 for (uint64_t i = rvv_vstart(); i < rvv_vl(); i++) {
297 #define RVV_VI_LOOP_END \
298 set_rvv_vstart(0); \
299 }
300
301 #define RVV_VI_MASK_VARS \
302 const uint8_t midx = i / 64; \
303 const uint8_t mpos = i % 64;
304
305 #define RVV_VI_LOOP_MASK_SKIP(BODY) \
306 RVV_VI_MASK_VARS \
307 if (instr_.RvvVM() == 0) { \
308 bool skip = ((Rvvelt<uint64_t>(0, midx) >> mpos) & 0x1) == 0; \
309 if (skip) { \
310 continue; \
311 } \
312 }
313
314 #define RVV_VI_VV_LOOP(BODY) \
315 RVV_VI_GENERAL_LOOP_BASE \
316 RVV_VI_LOOP_MASK_SKIP() \
317 if (rvv_vsew() == E8) { \
318 VV_PARAMS(8); \
319 BODY \
320 } else if (rvv_vsew() == E16) { \
321 VV_PARAMS(16); \
322 BODY \
323 } else if (rvv_vsew() == E32) { \
324 VV_PARAMS(32); \
325 BODY \
326 } else if (rvv_vsew() == E64) { \
327 VV_PARAMS(64); \
328 BODY \
329 } else { \
330 UNREACHABLE(); \
331 } \
332 RVV_VI_LOOP_END \
333 rvv_trace_vd();
334
335 #define RVV_VI_VV_ULOOP(BODY) \
336 RVV_VI_GENERAL_LOOP_BASE \
337 RVV_VI_LOOP_MASK_SKIP() \
338 if (rvv_vsew() == E8) { \
339 VV_UPARAMS(8); \
340 BODY \
341 } else if (rvv_vsew() == E16) { \
342 VV_UPARAMS(16); \
343 BODY \
344 } else if (rvv_vsew() == E32) { \
345 VV_UPARAMS(32); \
346 BODY \
347 } else if (rvv_vsew() == E64) { \
348 VV_UPARAMS(64); \
349 BODY \
350 } else { \
351 UNREACHABLE(); \
352 } \
353 RVV_VI_LOOP_END \
354 rvv_trace_vd();
355
356 #define RVV_VI_VX_LOOP(BODY) \
357 RVV_VI_GENERAL_LOOP_BASE \
358 RVV_VI_LOOP_MASK_SKIP() \
359 if (rvv_vsew() == E8) { \
360 VX_PARAMS(8); \
361 BODY \
362 } else if (rvv_vsew() == E16) { \
363 VX_PARAMS(16); \
364 BODY \
365 } else if (rvv_vsew() == E32) { \
366 VX_PARAMS(32); \
367 BODY \
368 } else if (rvv_vsew() == E64) { \
369 VX_PARAMS(64); \
370 BODY \
371 } else { \
372 UNREACHABLE(); \
373 } \
374 RVV_VI_LOOP_END \
375 rvv_trace_vd();
376
377 #define RVV_VI_VX_ULOOP(BODY) \
378 RVV_VI_GENERAL_LOOP_BASE \
379 RVV_VI_LOOP_MASK_SKIP() \
380 if (rvv_vsew() == E8) { \
381 VX_UPARAMS(8); \
382 BODY \
383 } else if (rvv_vsew() == E16) { \
384 VX_UPARAMS(16); \
385 BODY \
386 } else if (rvv_vsew() == E32) { \
387 VX_UPARAMS(32); \
388 BODY \
389 } else if (rvv_vsew() == E64) { \
390 VX_UPARAMS(64); \
391 BODY \
392 } else { \
393 UNREACHABLE(); \
394 } \
395 RVV_VI_LOOP_END \
396 rvv_trace_vd();
397
398 #define RVV_VI_VI_LOOP(BODY) \
399 RVV_VI_GENERAL_LOOP_BASE \
400 RVV_VI_LOOP_MASK_SKIP() \
401 if (rvv_vsew() == E8) { \
402 VI_PARAMS(8); \
403 BODY \
404 } else if (rvv_vsew() == E16) { \
405 VI_PARAMS(16); \
406 BODY \
407 } else if (rvv_vsew() == E32) { \
408 VI_PARAMS(32); \
409 BODY \
410 } else if (rvv_vsew() == E64) { \
411 VI_PARAMS(64); \
412 BODY \
413 } else { \
414 UNREACHABLE(); \
415 } \
416 RVV_VI_LOOP_END \
417 rvv_trace_vd();
418
419 #define RVV_VI_VI_ULOOP(BODY) \
420 RVV_VI_GENERAL_LOOP_BASE \
421 RVV_VI_LOOP_MASK_SKIP() \
422 if (rvv_vsew() == E8) { \
423 VI_UPARAMS(8); \
424 BODY \
425 } else if (rvv_vsew() == E16) { \
426 VI_UPARAMS(16); \
427 BODY \
428 } else if (rvv_vsew() == E32) { \
429 VI_UPARAMS(32); \
430 BODY \
431 } else if (rvv_vsew() == E64) { \
432 VI_UPARAMS(64); \
433 BODY \
434 } else { \
435 UNREACHABLE(); \
436 } \
437 RVV_VI_LOOP_END \
438 rvv_trace_vd();
439
440 // widen operation loop
441
442 #define VI_WIDE_CHECK_COMMON \
443 CHECK_LE(rvv_vflmul(), 4); \
444 CHECK_LE(rvv_vsew() * 2, kRvvELEN); \
445 require_align(rvv_vd_reg(), rvv_vflmul() * 2); \
446 require_vm;
447
448 #define VI_NARROW_CHECK_COMMON \
449 CHECK_LE(rvv_vflmul(), 4); \
450 CHECK_LE(rvv_vsew() * 2, kRvvELEN); \
451 require_align(rvv_vs2_reg(), rvv_vflmul() * 2); \
452 require_align(rvv_vd_reg(), rvv_vflmul()); \
453 require_vm;
454
455 #define RVV_VI_CHECK_SLIDE(is_over) \
456 require_align(rvv_vs2_reg(), rvv_vflmul()); \
457 require_align(rvv_vd_reg(), rvv_vflmul()); \
458 require_vm; \
459 if (is_over) require(rvv_vd_reg() != rvv_vs2_reg());
460
461 #define RVV_VI_CHECK_DDS(is_rs) \
462 VI_WIDE_CHECK_COMMON; \
463 require_align(rvv_vs2_reg(), rvv_vflmul() * 2); \
464 if (is_rs) { \
465 require_align(rvv_vs1_reg(), rvv_vflmul()); \
466 if (rvv_vflmul() < 1) { \
467 require_noover(rvv_vd_reg(), rvv_vflmul() * 2, rvv_vs1_reg(), \
468 rvv_vflmul()); \
469 } else { \
470 require_noover_widen(rvv_vd_reg(), rvv_vflmul() * 2, rvv_vs1_reg(), \
471 rvv_vflmul()); \
472 } \
473 }
474
475 #define RVV_VI_CHECK_DSS(is_vs1) \
476 VI_WIDE_CHECK_COMMON; \
477 require_align(rvv_vs2_reg(), rvv_vflmul()); \
478 if (rvv_vflmul() < 1) { \
479 require_noover(rvv_vd_reg(), rvv_vflmul() * 2, rvv_vs2_reg(), \
480 rvv_vflmul()); \
481 } else { \
482 require_noover_widen(rvv_vd_reg(), rvv_vflmul() * 2, rvv_vs2_reg(), \
483 rvv_vflmul()); \
484 } \
485 if (is_vs1) { \
486 require_align(rvv_vs1_reg(), rvv_vflmul()); \
487 if (rvv_vflmul() < 1) { \
488 require_noover(rvv_vd_reg(), rvv_vflmul() * 2, rvv_vs1_reg(), \
489 rvv_vflmul()); \
490 } else { \
491 require_noover_widen(rvv_vd_reg(), rvv_vflmul() * 2, rvv_vs1_reg(), \
492 rvv_vflmul()); \
493 } \
494 }
495
496 #define RVV_VI_CHECK_SDS(is_vs1) \
497 VI_NARROW_CHECK_COMMON; \
498 if (rvv_vd_reg() != rvv_vs2_reg()) \
499 require_noover(rvv_vd_reg(), rvv_vflmul(), rvv_vs2_reg(), \
500 rvv_vflmul() * 2); \
501 if (is_vs1) require_align(rvv_vs1_reg(), rvv_vflmul());
502
503 #define RVV_VI_VV_LOOP_WIDEN(BODY) \
504 RVV_VI_GENERAL_LOOP_BASE \
505 RVV_VI_LOOP_MASK_SKIP() \
506 if (rvv_vsew() == E8) { \
507 VV_PARAMS(8); \
508 BODY; \
509 } else if (rvv_vsew() == E16) { \
510 VV_PARAMS(16); \
511 BODY; \
512 } else if (rvv_vsew() == E32) { \
513 VV_PARAMS(32); \
514 BODY; \
515 } \
516 RVV_VI_LOOP_END \
517 rvv_trace_vd();
518
519 #define RVV_VI_VX_LOOP_WIDEN(BODY) \
520 RVV_VI_GENERAL_LOOP_BASE \
521 if (rvv_vsew() == E8) { \
522 VX_PARAMS(8); \
523 BODY; \
524 } else if (rvv_vsew() == E16) { \
525 VX_PARAMS(16); \
526 BODY; \
527 } else if (rvv_vsew() == E32) { \
528 VX_PARAMS(32); \
529 BODY; \
530 } \
531 RVV_VI_LOOP_END \
532 rvv_trace_vd();
533
534 #define VI_WIDE_OP_AND_ASSIGN(var0, var1, var2, op0, op1, sign) \
535 switch (rvv_vsew()) { \
536 case E8: { \
537 Rvvelt<uint16_t>(rvv_vd_reg(), i, true) = \
538 op1((sign##16_t)(sign##8_t)var0 op0(sign##16_t)(sign##8_t) var1) + \
539 var2; \
540 } break; \
541 case E16: { \
542 Rvvelt<uint32_t>(rvv_vd_reg(), i, true) = \
543 op1((sign##32_t)(sign##16_t)var0 op0(sign##32_t)(sign##16_t) var1) + \
544 var2; \
545 } break; \
546 default: { \
547 Rvvelt<uint64_t>(rvv_vd_reg(), i, true) = \
548 op1((sign##64_t)(sign##32_t)var0 op0(sign##64_t)(sign##32_t) var1) + \
549 var2; \
550 } break; \
551 }
552
553 #define VI_WIDE_WVX_OP(var0, op0, sign) \
554 switch (rvv_vsew()) { \
555 case E8: { \
556 sign##16_t & vd_w = Rvvelt<sign##16_t>(rvv_vd_reg(), i, true); \
557 sign##16_t vs2_w = Rvvelt<sign##16_t>(rvv_vs2_reg(), i); \
558 vd_w = vs2_w op0(sign##16_t)(sign##8_t) var0; \
559 } break; \
560 case E16: { \
561 sign##32_t & vd_w = Rvvelt<sign##32_t>(rvv_vd_reg(), i, true); \
562 sign##32_t vs2_w = Rvvelt<sign##32_t>(rvv_vs2_reg(), i); \
563 vd_w = vs2_w op0(sign##32_t)(sign##16_t) var0; \
564 } break; \
565 default: { \
566 sign##64_t & vd_w = Rvvelt<sign##64_t>(rvv_vd_reg(), i, true); \
567 sign##64_t vs2_w = Rvvelt<sign##64_t>(rvv_vs2_reg(), i); \
568 vd_w = vs2_w op0(sign##64_t)(sign##32_t) var0; \
569 } break; \
570 }
571
572 #define RVV_VI_VVXI_MERGE_LOOP(BODY) \
573 RVV_VI_GENERAL_LOOP_BASE \
574 if (rvv_vsew() == E8) { \
575 VXI_PARAMS(8); \
576 BODY; \
577 } else if (rvv_vsew() == E16) { \
578 VXI_PARAMS(16); \
579 BODY; \
580 } else if (rvv_vsew() == E32) { \
581 VXI_PARAMS(32); \
582 BODY; \
583 } else if (rvv_vsew() == E64) { \
584 VXI_PARAMS(64); \
585 BODY; \
586 } \
587 RVV_VI_LOOP_END \
588 rvv_trace_vd();
589
590 #define VV_WITH_CARRY_PARAMS(x) \
591 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
592 type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
593 type_sew_t<x>::type& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true);
594
595 #define XI_WITH_CARRY_PARAMS(x) \
596 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
597 type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
598 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)instr_.RvvSimm5(); \
599 type_sew_t<x>::type& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true);
600
601 // carry/borrow bit loop
602 #define RVV_VI_VV_LOOP_WITH_CARRY(BODY) \
603 CHECK_NE(rvv_vd_reg(), 0); \
604 RVV_VI_GENERAL_LOOP_BASE \
605 RVV_VI_MASK_VARS \
606 if (rvv_vsew() == E8) { \
607 VV_WITH_CARRY_PARAMS(8) \
608 BODY; \
609 } else if (rvv_vsew() == E16) { \
610 VV_WITH_CARRY_PARAMS(16) \
611 BODY; \
612 } else if (rvv_vsew() == E32) { \
613 VV_WITH_CARRY_PARAMS(32) \
614 BODY; \
615 } else if (rvv_vsew() == E64) { \
616 VV_WITH_CARRY_PARAMS(64) \
617 BODY; \
618 } \
619 RVV_VI_LOOP_END
620
621 #define RVV_VI_XI_LOOP_WITH_CARRY(BODY) \
622 CHECK_NE(rvv_vd_reg(), 0); \
623 RVV_VI_GENERAL_LOOP_BASE \
624 RVV_VI_MASK_VARS \
625 if (rvv_vsew() == E8) { \
626 XI_WITH_CARRY_PARAMS(8) \
627 BODY; \
628 } else if (rvv_vsew() == E16) { \
629 XI_WITH_CARRY_PARAMS(16) \
630 BODY; \
631 } else if (rvv_vsew() == E32) { \
632 XI_WITH_CARRY_PARAMS(32) \
633 BODY; \
634 } else if (rvv_vsew() == E64) { \
635 XI_WITH_CARRY_PARAMS(64) \
636 BODY; \
637 } \
638 RVV_VI_LOOP_END
639
640 #define VV_CMP_PARAMS(x) \
641 type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
642 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
643
644 #define VX_CMP_PARAMS(x) \
645 type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
646 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
647
648 #define VI_CMP_PARAMS(x) \
649 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)instr_.RvvSimm5(); \
650 type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
651
652 #define VV_UCMP_PARAMS(x) \
653 type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
654 type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
655
656 #define VX_UCMP_PARAMS(x) \
657 type_usew_t<x>::type rs1 = \
658 (type_sew_t<x>::type)(get_register(rvv_vs1_reg())); \
659 type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
660
661 #define VI_UCMP_PARAMS(x) \
662 type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)instr_.RvvUimm5(); \
663 type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
664
665 #define float32_t float
666 #define float64_t double
667
668 #define RVV_VI_LOOP_CMP_BASE \
669 CHECK(rvv_vsew() >= E8 && rvv_vsew() <= E64); \
670 for (reg_t i = rvv_vstart(); i < rvv_vl(); ++i) { \
671 RVV_VI_LOOP_MASK_SKIP(); \
672 uint64_t mmask = uint64_t(1) << mpos; \
673 uint64_t& vdi = Rvvelt<uint64_t>(rvv_vd_reg(), midx, true); \
674 uint64_t res = 0;
675
676 #define RVV_VI_LOOP_CMP_END \
677 vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \
678 } \
679 rvv_trace_vd(); \
680 set_rvv_vstart(0);
681
682 // comparision result to masking register
683 #define RVV_VI_VV_LOOP_CMP(BODY) \
684 RVV_VI_LOOP_CMP_BASE \
685 if (rvv_vsew() == E8) { \
686 VV_CMP_PARAMS(8); \
687 BODY; \
688 } else if (rvv_vsew() == E16) { \
689 VV_CMP_PARAMS(16); \
690 BODY; \
691 } else if (rvv_vsew() == E32) { \
692 VV_CMP_PARAMS(32); \
693 BODY; \
694 } else if (rvv_vsew() == E64) { \
695 VV_CMP_PARAMS(64); \
696 BODY; \
697 } \
698 RVV_VI_LOOP_CMP_END
699
700 #define RVV_VI_VX_LOOP_CMP(BODY) \
701 RVV_VI_LOOP_CMP_BASE \
702 if (rvv_vsew() == E8) { \
703 VX_CMP_PARAMS(8); \
704 BODY; \
705 } else if (rvv_vsew() == E16) { \
706 VX_CMP_PARAMS(16); \
707 BODY; \
708 } else if (rvv_vsew() == E32) { \
709 VX_CMP_PARAMS(32); \
710 BODY; \
711 } else if (rvv_vsew() == E64) { \
712 VX_CMP_PARAMS(64); \
713 BODY; \
714 } \
715 RVV_VI_LOOP_CMP_END
716
717 #define RVV_VI_VI_LOOP_CMP(BODY) \
718 RVV_VI_LOOP_CMP_BASE \
719 if (rvv_vsew() == E8) { \
720 VI_CMP_PARAMS(8); \
721 BODY; \
722 } else if (rvv_vsew() == E16) { \
723 VI_CMP_PARAMS(16); \
724 BODY; \
725 } else if (rvv_vsew() == E32) { \
726 VI_CMP_PARAMS(32); \
727 BODY; \
728 } else if (rvv_vsew() == E64) { \
729 VI_CMP_PARAMS(64); \
730 BODY; \
731 } \
732 RVV_VI_LOOP_CMP_END
733
734 #define RVV_VI_VV_ULOOP_CMP(BODY) \
735 RVV_VI_LOOP_CMP_BASE \
736 if (rvv_vsew() == E8) { \
737 VV_UCMP_PARAMS(8); \
738 BODY; \
739 } else if (rvv_vsew() == E16) { \
740 VV_UCMP_PARAMS(16); \
741 BODY; \
742 } else if (rvv_vsew() == E32) { \
743 VV_UCMP_PARAMS(32); \
744 BODY; \
745 } else if (rvv_vsew() == E64) { \
746 VV_UCMP_PARAMS(64); \
747 BODY; \
748 } \
749 RVV_VI_LOOP_CMP_END
750
751 #define RVV_VI_VX_ULOOP_CMP(BODY) \
752 RVV_VI_LOOP_CMP_BASE \
753 if (rvv_vsew() == E8) { \
754 VX_UCMP_PARAMS(8); \
755 BODY; \
756 } else if (rvv_vsew() == E16) { \
757 VX_UCMP_PARAMS(16); \
758 BODY; \
759 } else if (rvv_vsew() == E32) { \
760 VX_UCMP_PARAMS(32); \
761 BODY; \
762 } else if (rvv_vsew() == E64) { \
763 VX_UCMP_PARAMS(64); \
764 BODY; \
765 } \
766 RVV_VI_LOOP_CMP_END
767
768 #define RVV_VI_VI_ULOOP_CMP(BODY) \
769 RVV_VI_LOOP_CMP_BASE \
770 if (rvv_vsew() == E8) { \
771 VI_UCMP_PARAMS(8); \
772 BODY; \
773 } else if (rvv_vsew() == E16) { \
774 VI_UCMP_PARAMS(16); \
775 BODY; \
776 } else if (rvv_vsew() == E32) { \
777 VI_UCMP_PARAMS(32); \
778 BODY; \
779 } else if (rvv_vsew() == E64) { \
780 VI_UCMP_PARAMS(64); \
781 BODY; \
782 } \
783 RVV_VI_LOOP_CMP_END
784
785 #define RVV_VI_VFP_LOOP_BASE \
786 for (uint64_t i = rvv_vstart(); i < rvv_vl(); ++i) { \
787 RVV_VI_LOOP_MASK_SKIP();
788
789 #define RVV_VI_VFP_LOOP_END \
790 } \
791 set_rvv_vstart(0);
792
793 #define RVV_VI_VFP_VF_LOOP(BODY16, BODY32, BODY64) \
794 RVV_VI_VFP_LOOP_BASE \
795 switch (rvv_vsew()) { \
796 case E16: { \
797 UNIMPLEMENTED(); \
798 } \
799 case E32: { \
800 float& vd = Rvvelt<float>(rvv_vd_reg(), i, true); \
801 float fs1 = get_fpu_register_float(rs1_reg()); \
802 float vs2 = Rvvelt<float>(rvv_vs2_reg(), i); \
803 BODY32; \
804 break; \
805 } \
806 case E64: { \
807 double& vd = Rvvelt<double>(rvv_vd_reg(), i, true); \
808 double fs1 = get_fpu_register_double(rs1_reg()); \
809 double vs2 = Rvvelt<double>(rvv_vs2_reg(), i); \
810 BODY64; \
811 break; \
812 } \
813 default: \
814 UNREACHABLE(); \
815 break; \
816 } \
817 RVV_VI_VFP_LOOP_END \
818 rvv_trace_vd();
819
820 #define RVV_VI_VFP_VV_LOOP(BODY16, BODY32, BODY64) \
821 RVV_VI_VFP_LOOP_BASE \
822 switch (rvv_vsew()) { \
823 case E16: { \
824 UNIMPLEMENTED(); \
825 break; \
826 } \
827 case E32: { \
828 float& vd = Rvvelt<float>(rvv_vd_reg(), i, true); \
829 float vs1 = Rvvelt<float>(rvv_vs1_reg(), i); \
830 float vs2 = Rvvelt<float>(rvv_vs2_reg(), i); \
831 BODY32; \
832 break; \
833 } \
834 case E64: { \
835 double& vd = Rvvelt<double>(rvv_vd_reg(), i, true); \
836 double vs1 = Rvvelt<double>(rvv_vs1_reg(), i); \
837 double vs2 = Rvvelt<double>(rvv_vs2_reg(), i); \
838 BODY64; \
839 break; \
840 } \
841 default: \
842 require(0); \
843 break; \
844 } \
845 RVV_VI_VFP_LOOP_END \
846 rvv_trace_vd();
847
848 #define RVV_VI_VFP_VF_LOOP_WIDEN(BODY32, vs2_is_widen) \
849 RVV_VI_VFP_LOOP_BASE \
850 switch (rvv_vsew()) { \
851 case E16: \
852 case E64: { \
853 UNIMPLEMENTED(); \
854 break; \
855 } \
856 case E32: { \
857 double& vd = Rvvelt<double>(rvv_vd_reg(), i, true); \
858 double fs1 = static_cast<double>(get_fpu_register_float(rs1_reg())); \
859 double vs2 = vs2_is_widen \
860 ? Rvvelt<double>(rvv_vs2_reg(), i) \
861 : static_cast<double>(Rvvelt<float>(rvv_vs2_reg(), i)); \
862 double vs3 = static_cast<double>(Rvvelt<float>(rvv_vd_reg(), i)); \
863 BODY32; \
864 break; \
865 } \
866 default: \
867 UNREACHABLE(); \
868 break; \
869 } \
870 RVV_VI_VFP_LOOP_END \
871 rvv_trace_vd();
872
873 #define RVV_VI_VFP_VV_LOOP_WIDEN(BODY32, vs2_is_widen) \
874 RVV_VI_VFP_LOOP_BASE \
875 switch (rvv_vsew()) { \
876 case E16: \
877 case E64: { \
878 UNIMPLEMENTED(); \
879 break; \
880 } \
881 case E32: { \
882 double& vd = Rvvelt<double>(rvv_vd_reg(), i, true); \
883 double vs2 = vs2_is_widen \
884 ? static_cast<double>(Rvvelt<double>(rvv_vs2_reg(), i)) \
885 : static_cast<double>(Rvvelt<float>(rvv_vs2_reg(), i)); \
886 double vs1 = static_cast<double>(Rvvelt<float>(rvv_vs1_reg(), i)); \
887 double vs3 = static_cast<double>(Rvvelt<float>(rvv_vd_reg(), i)); \
888 BODY32; \
889 break; \
890 } \
891 default: \
892 require(0); \
893 break; \
894 } \
895 RVV_VI_VFP_LOOP_END \
896 rvv_trace_vd();
897
898 #define RVV_VI_VFP_VV_ARITH_CHECK_COMPUTE(type, check_fn, op) \
899 auto fn = [this](type frs1, type frs2) { \
900 if (check_fn(frs1, frs2)) { \
901 this->set_fflags(kInvalidOperation); \
902 return std::numeric_limits<type>::quiet_NaN(); \
903 } else { \
904 return frs2 op frs1; \
905 } \
906 }; \
907 auto alu_out = fn(vs1, vs2); \
908 /** if any input or result is NaN, the result is quiet_NaN*/ \
909 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) { \
910 /** signaling_nan sets kInvalidOperation bit*/ \
911 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2)) \
912 set_fflags(kInvalidOperation); \
913 alu_out = std::numeric_limits<type>::quiet_NaN(); \
914 } \
915 vd = alu_out;
916
917 #define RVV_VI_VFP_VF_ARITH_CHECK_COMPUTE(type, check_fn, op) \
918 auto fn = [this](type frs1, type frs2) { \
919 if (check_fn(frs1, frs2)) { \
920 this->set_fflags(kInvalidOperation); \
921 return std::numeric_limits<type>::quiet_NaN(); \
922 } else { \
923 return frs2 op frs1; \
924 } \
925 }; \
926 auto alu_out = fn(fs1, vs2); \
927 /** if any input or result is NaN, the result is quiet_NaN*/ \
928 if (std::isnan(alu_out) || std::isnan(fs1) || std::isnan(vs2)) { \
929 /** signaling_nan sets kInvalidOperation bit*/ \
930 if (isSnan(alu_out) || isSnan(fs1) || isSnan(vs2)) \
931 set_fflags(kInvalidOperation); \
932 alu_out = std::numeric_limits<type>::quiet_NaN(); \
933 } \
934 vd = alu_out;
935
936 #define RVV_VI_VFP_FMA(type, _f1, _f2, _a) \
937 auto fn = [](type f1, type f2, type a) { return std::fma(f1, f2, a); }; \
938 vd = CanonicalizeFPUOpFMA<type>(fn, _f1, _f2, _a);
939
940 #define RVV_VI_VFP_FMA_VV_LOOP(BODY32, BODY64) \
941 RVV_VI_VFP_LOOP_BASE \
942 switch (rvv_vsew()) { \
943 case E16: { \
944 UNIMPLEMENTED(); \
945 } \
946 case E32: { \
947 float& vd = Rvvelt<float>(rvv_vd_reg(), i, true); \
948 float vs1 = Rvvelt<float>(rvv_vs1_reg(), i); \
949 float vs2 = Rvvelt<float>(rvv_vs2_reg(), i); \
950 BODY32; \
951 break; \
952 } \
953 case E64: { \
954 double& vd = Rvvelt<double>(rvv_vd_reg(), i, true); \
955 double vs1 = Rvvelt<double>(rvv_vs1_reg(), i); \
956 double vs2 = Rvvelt<double>(rvv_vs2_reg(), i); \
957 BODY64; \
958 break; \
959 } \
960 default: \
961 require(0); \
962 break; \
963 } \
964 RVV_VI_VFP_LOOP_END \
965 rvv_trace_vd();
966
967 #define RVV_VI_VFP_FMA_VF_LOOP(BODY32, BODY64) \
968 RVV_VI_VFP_LOOP_BASE \
969 switch (rvv_vsew()) { \
970 case E16: { \
971 UNIMPLEMENTED(); \
972 } \
973 case E32: { \
974 float& vd = Rvvelt<float>(rvv_vd_reg(), i, true); \
975 float fs1 = get_fpu_register_float(rs1_reg()); \
976 float vs2 = Rvvelt<float>(rvv_vs2_reg(), i); \
977 BODY32; \
978 break; \
979 } \
980 case E64: { \
981 double& vd = Rvvelt<double>(rvv_vd_reg(), i, true); \
982 float fs1 = get_fpu_register_float(rs1_reg()); \
983 double vs2 = Rvvelt<double>(rvv_vs2_reg(), i); \
984 BODY64; \
985 break; \
986 } \
987 default: \
988 require(0); \
989 break; \
990 } \
991 RVV_VI_VFP_LOOP_END \
992 rvv_trace_vd();
993
994 #define RVV_VI_VFP_LOOP_CMP_BASE \
995 for (reg_t i = rvv_vstart(); i < rvv_vl(); ++i) { \
996 RVV_VI_LOOP_MASK_SKIP(); \
997 uint64_t mmask = uint64_t(1) << mpos; \
998 uint64_t& vdi = Rvvelt<uint64_t>(rvv_vd_reg(), midx, true); \
999 uint64_t res = 0;
1000
1001 #define RVV_VI_VFP_LOOP_CMP_END \
1002 switch (rvv_vsew()) { \
1003 case E16: \
1004 case E32: \
1005 case E64: { \
1006 vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \
1007 break; \
1008 } \
1009 default: \
1010 UNREACHABLE(); \
1011 break; \
1012 } \
1013 } \
1014 set_rvv_vstart(0); \
1015 rvv_trace_vd();
1016
1017 #define RVV_VI_VFP_LOOP_CMP(BODY16, BODY32, BODY64, is_vs1) \
1018 RVV_VI_VFP_LOOP_CMP_BASE \
1019 switch (rvv_vsew()) { \
1020 case E16: { \
1021 UNIMPLEMENTED(); \
1022 } \
1023 case E32: { \
1024 float vs2 = Rvvelt<float>(rvv_vs2_reg(), i); \
1025 float vs1 = Rvvelt<float>(rvv_vs1_reg(), i); \
1026 BODY32; \
1027 break; \
1028 } \
1029 case E64: { \
1030 double vs2 = Rvvelt<double>(rvv_vs2_reg(), i); \
1031 double vs1 = Rvvelt<double>(rvv_vs1_reg(), i); \
1032 BODY64; \
1033 break; \
1034 } \
1035 default: \
1036 UNREACHABLE(); \
1037 break; \
1038 } \
1039 RVV_VI_VFP_LOOP_CMP_END
1040
1041 // reduction loop - signed
1042 #define RVV_VI_LOOP_REDUCTION_BASE(x) \
1043 auto& vd_0_des = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), 0, true); \
1044 auto vd_0_res = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), 0); \
1045 for (uint64_t i = rvv_vstart(); i < rvv_vl(); ++i) { \
1046 RVV_VI_LOOP_MASK_SKIP(); \
1047 auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
1048
1049 #define RVV_VI_LOOP_REDUCTION_END(x) \
1050 } \
1051 if (rvv_vl() > 0) { \
1052 vd_0_des = vd_0_res; \
1053 } \
1054 set_rvv_vstart(0);
1055
1056 #define REDUCTION_LOOP(x, BODY) \
1057 RVV_VI_LOOP_REDUCTION_BASE(x) \
1058 BODY; \
1059 RVV_VI_LOOP_REDUCTION_END(x)
1060
1061 #define RVV_VI_VV_LOOP_REDUCTION(BODY) \
1062 if (rvv_vsew() == E8) { \
1063 REDUCTION_LOOP(8, BODY) \
1064 } else if (rvv_vsew() == E16) { \
1065 REDUCTION_LOOP(16, BODY) \
1066 } else if (rvv_vsew() == E32) { \
1067 REDUCTION_LOOP(32, BODY) \
1068 } else if (rvv_vsew() == E64) { \
1069 REDUCTION_LOOP(64, BODY) \
1070 } \
1071 rvv_trace_vd();
1072
1073 #define VI_VFP_LOOP_REDUCTION_BASE(width) \
1074 float##width##_t vd_0 = Rvvelt<float##width##_t>(rvv_vd_reg(), 0); \
1075 float##width##_t vs1_0 = Rvvelt<float##width##_t>(rvv_vs1_reg(), 0); \
1076 vd_0 = vs1_0; \
1077 /*bool is_active = false;*/ \
1078 for (reg_t i = rvv_vstart(); i < rvv_vl(); ++i) { \
1079 RVV_VI_LOOP_MASK_SKIP(); \
1080 float##width##_t vs2 = Rvvelt<float##width##_t>(rvv_vs2_reg(), i); \
1081 /*is_active = true;*/
1082
1083 #define VI_VFP_LOOP_REDUCTION_END(x) \
1084 } \
1085 set_rvv_vstart(0); \
1086 if (rvv_vl() > 0) { \
1087 Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), 0, true) = vd_0; \
1088 }
1089
1090 #define RVV_VI_VFP_VV_LOOP_REDUCTION(BODY16, BODY32, BODY64) \
1091 if (rvv_vsew() == E16) { \
1092 UNIMPLEMENTED(); \
1093 } else if (rvv_vsew() == E32) { \
1094 VI_VFP_LOOP_REDUCTION_BASE(32) \
1095 BODY32; \
1096 VI_VFP_LOOP_REDUCTION_END(32) \
1097 } else if (rvv_vsew() == E64) { \
1098 VI_VFP_LOOP_REDUCTION_BASE(64) \
1099 BODY64; \
1100 VI_VFP_LOOP_REDUCTION_END(64) \
1101 } \
1102 rvv_trace_vd();
1103
1104 // reduction loop - unsgied
1105 #define RVV_VI_ULOOP_REDUCTION_BASE(x) \
1106 auto& vd_0_des = Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), 0, true); \
1107 auto vd_0_res = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), 0); \
1108 for (reg_t i = rvv_vstart(); i < rvv_vl(); ++i) { \
1109 RVV_VI_LOOP_MASK_SKIP(); \
1110 auto vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
1111
1112 #define REDUCTION_ULOOP(x, BODY) \
1113 RVV_VI_ULOOP_REDUCTION_BASE(x) \
1114 BODY; \
1115 RVV_VI_LOOP_REDUCTION_END(x)
1116
1117 #define RVV_VI_VV_ULOOP_REDUCTION(BODY) \
1118 if (rvv_vsew() == E8) { \
1119 REDUCTION_ULOOP(8, BODY) \
1120 } else if (rvv_vsew() == E16) { \
1121 REDUCTION_ULOOP(16, BODY) \
1122 } else if (rvv_vsew() == E32) { \
1123 REDUCTION_ULOOP(32, BODY) \
1124 } else if (rvv_vsew() == E64) { \
1125 REDUCTION_ULOOP(64, BODY) \
1126 } \
1127 rvv_trace_vd();
1128
1129 #define VI_STRIP(inx) reg_t vreg_inx = inx;
1130
1131 #define VI_ELEMENT_SKIP(inx) \
1132 if (inx >= vl) { \
1133 continue; \
1134 } else if (inx < rvv_vstart()) { \
1135 continue; \
1136 } else { \
1137 RVV_VI_LOOP_MASK_SKIP(); \
1138 }
1139
1140 #define require_vm \
1141 do { \
1142 if (instr_.RvvVM() == 0) CHECK_NE(rvv_vd_reg(), 0); \
1143 } while (0);
1144
1145 #define VI_CHECK_STORE(elt_width, is_mask_ldst) \
1146 reg_t veew = is_mask_ldst ? 1 : sizeof(elt_width##_t) * 8;
1147 // float vemul = is_mask_ldst ? 1 : ((float)veew / rvv_vsew() * Rvvvflmul);
1148 // reg_t emul = vemul < 1 ? 1 : vemul;
1149 // require(vemul >= 0.125 && vemul <= 8);
1150 // require_align(rvv_rd(), vemul);
1151 // require((nf * emul) <= (NVPR / 4) && (rvv_rd() + nf * emul) <= NVPR);
1152
1153 #define VI_CHECK_LOAD(elt_width, is_mask_ldst) \
1154 VI_CHECK_STORE(elt_width, is_mask_ldst); \
1155 require_vm;
1156
1157 /*vd + fn * emul*/
1158 #define RVV_VI_LD(stride, offset, elt_width, is_mask_ldst) \
1159 const reg_t nf = rvv_nf() + 1; \
1160 const reg_t vl = is_mask_ldst ? ((rvv_vl() + 7) / 8) : rvv_vl(); \
1161 const int64_t baseAddr = rs1(); \
1162 for (reg_t i = 0; i < vl; ++i) { \
1163 VI_ELEMENT_SKIP(i); \
1164 VI_STRIP(i); \
1165 set_rvv_vstart(i); \
1166 for (reg_t fn = 0; fn < nf; ++fn) { \
1167 auto val = ReadMem<elt_width##_t>( \
1168 baseAddr + (stride) + (offset) * sizeof(elt_width##_t), \
1169 instr_.instr()); \
1170 type_sew_t<sizeof(elt_width##_t)* 8>::type& vd = \
1171 Rvvelt<type_sew_t<sizeof(elt_width##_t) * 8>::type>(rvv_vd_reg(), \
1172 vreg_inx, true); \
1173 vd = val; \
1174 } \
1175 } \
1176 set_rvv_vstart(0); \
1177 if (::v8::internal::FLAG_trace_sim) { \
1178 __int128_t value = Vregister_[rvv_vd_reg()]; \
1179 SNPrintF(trace_buf_, "%016" PRIx64 "%016" PRIx64 " <-- 0x%016" PRIx64, \
1180 *(reinterpret_cast<int64_t*>(&value) + 1), \
1181 *reinterpret_cast<int64_t*>(&value), \
1182 (uint64_t)(get_register(rs1_reg()))); \
1183 }
1184
1185 #define RVV_VI_ST(stride, offset, elt_width, is_mask_ldst) \
1186 const reg_t nf = rvv_nf() + 1; \
1187 const reg_t vl = is_mask_ldst ? ((rvv_vl() + 7) / 8) : rvv_vl(); \
1188 const int64_t baseAddr = rs1(); \
1189 for (reg_t i = 0; i < vl; ++i) { \
1190 VI_STRIP(i) \
1191 VI_ELEMENT_SKIP(i); \
1192 set_rvv_vstart(i); \
1193 for (reg_t fn = 0; fn < nf; ++fn) { \
1194 elt_width##_t vs1 = Rvvelt<type_sew_t<sizeof(elt_width##_t) * 8>::type>( \
1195 rvv_vs3_reg(), vreg_inx); \
1196 WriteMem(baseAddr + (stride) + (offset) * sizeof(elt_width##_t), vs1, \
1197 instr_.instr()); \
1198 } \
1199 } \
1200 set_rvv_vstart(0); \
1201 if (::v8::internal::FLAG_trace_sim) { \
1202 __int128_t value = Vregister_[rvv_vd_reg()]; \
1203 SNPrintF(trace_buf_, "%016" PRIx64 "%016" PRIx64 " --> 0x%016" PRIx64, \
1204 *(reinterpret_cast<int64_t*>(&value) + 1), \
1205 *reinterpret_cast<int64_t*>(&value), \
1206 (uint64_t)(get_register(rs1_reg()))); \
1207 }
1208
1209 #define VI_VFP_LOOP_SCALE_BASE \
1210 /*require(STATE.frm < 0x5);*/ \
1211 for (reg_t i = rvv_vstart(); i < rvv_vl(); ++i) { \
1212 RVV_VI_LOOP_MASK_SKIP();
1213
1214 #define RVV_VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, CHECK8, CHECK16, CHECK32, \
1215 is_widen, eew_check) \
1216 if (is_widen) { \
1217 RVV_VI_CHECK_DSS(false); \
1218 } else { \
1219 RVV_VI_CHECK_SDS(false); \
1220 } \
1221 CHECK(eew_check); \
1222 switch (rvv_vsew()) { \
1223 case E8: { \
1224 CHECK8 \
1225 VI_VFP_LOOP_SCALE_BASE \
1226 BODY8 /*set_fp_exceptions*/; \
1227 RVV_VI_VFP_LOOP_END \
1228 } break; \
1229 case E16: { \
1230 CHECK16 \
1231 VI_VFP_LOOP_SCALE_BASE \
1232 BODY16 /*set_fp_exceptions*/; \
1233 RVV_VI_VFP_LOOP_END \
1234 } break; \
1235 case E32: { \
1236 CHECK32 \
1237 VI_VFP_LOOP_SCALE_BASE \
1238 BODY32 /*set_fp_exceptions*/; \
1239 RVV_VI_VFP_LOOP_END \
1240 } break; \
1241 default: \
1242 require(0); \
1243 break; \
1244 } \
1245 rvv_trace_vd();
1246
1247 // calculate the value of r used in rounding
get_round(int vxrm,uint64_t v,uint8_t shift)1248 static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift) {
1249 uint8_t d = v8::internal::unsigned_bitextract_64(shift, shift, v);
1250 uint8_t d1;
1251 uint64_t D1, D2;
1252
1253 if (shift == 0 || shift > 64) {
1254 return 0;
1255 }
1256
1257 d1 = v8::internal::unsigned_bitextract_64(shift - 1, shift - 1, v);
1258 D1 = v8::internal::unsigned_bitextract_64(shift - 1, 0, v);
1259 if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */
1260 return d1;
1261 } else if (vxrm == 1) { /* round-to-nearest-even */
1262 if (shift > 1) {
1263 D2 = v8::internal::unsigned_bitextract_64(shift - 2, 0, v);
1264 return d1 & ((D2 != 0) | d);
1265 } else {
1266 return d1 & d;
1267 }
1268 } else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */
1269 return !d & (D1 != 0);
1270 }
1271 return 0; /* round-down (truncate) */
1272 }
1273
1274 template <typename Src, typename Dst>
signed_saturation(Src v,uint n)1275 inline Dst signed_saturation(Src v, uint n) {
1276 Dst smax = (Dst)(INT64_MAX >> (64 - n));
1277 Dst smin = (Dst)(INT64_MIN >> (64 - n));
1278 return (v > smax) ? smax : ((v < smin) ? smin : (Dst)v);
1279 }
1280
1281 template <typename Src, typename Dst>
unsigned_saturation(Src v,uint n)1282 inline Dst unsigned_saturation(Src v, uint n) {
1283 Dst umax = (Dst)(UINT64_MAX >> (64 - n));
1284 return (v > umax) ? umax : ((v < 0) ? 0 : (Dst)v);
1285 }
1286
1287 #define RVV_VN_CLIPU_VI_LOOP() \
1288 RVV_VI_GENERAL_LOOP_BASE \
1289 RVV_VI_LOOP_MASK_SKIP() \
1290 if (rvv_vsew() == E8) { \
1291 VN_UPARAMS(16); \
1292 vd = unsigned_saturation<uint16_t, uint8_t>( \
1293 (static_cast<uint16_t>(vs2) >> uimm5) + \
1294 get_round(static_cast<int>(rvv_vxrm()), vs2, uimm5), \
1295 8); \
1296 } else if (rvv_vsew() == E16) { \
1297 VN_UPARAMS(32); \
1298 vd = unsigned_saturation<uint32_t, uint16_t>( \
1299 (static_cast<uint32_t>(vs2) >> uimm5) + \
1300 get_round(static_cast<int>(rvv_vxrm()), vs2, uimm5), \
1301 16); \
1302 } else if (rvv_vsew() == E32) { \
1303 VN_UPARAMS(64); \
1304 vd = unsigned_saturation<uint64_t, uint32_t>( \
1305 (static_cast<uint64_t>(vs2) >> uimm5) + \
1306 get_round(static_cast<int>(rvv_vxrm()), vs2, uimm5), \
1307 32); \
1308 } else if (rvv_vsew() == E64) { \
1309 UNREACHABLE(); \
1310 } else { \
1311 UNREACHABLE(); \
1312 } \
1313 RVV_VI_LOOP_END \
1314 rvv_trace_vd();
1315
1316 #define RVV_VN_CLIP_VI_LOOP() \
1317 RVV_VI_GENERAL_LOOP_BASE \
1318 RVV_VI_LOOP_MASK_SKIP() \
1319 if (rvv_vsew() == E8) { \
1320 VN_PARAMS(16); \
1321 vd = signed_saturation<int16_t, int8_t>( \
1322 (vs2 >> uimm5) + get_round(static_cast<int>(rvv_vxrm()), vs2, uimm5), \
1323 8); \
1324 } else if (rvv_vsew() == E16) { \
1325 VN_PARAMS(32); \
1326 vd = signed_saturation<int32_t, int16_t>( \
1327 (vs2 >> uimm5) + get_round(static_cast<int>(rvv_vxrm()), vs2, uimm5), \
1328 16); \
1329 } else if (rvv_vsew() == E32) { \
1330 VN_PARAMS(64); \
1331 vd = signed_saturation<int64_t, int32_t>( \
1332 (vs2 >> uimm5) + get_round(static_cast<int>(rvv_vxrm()), vs2, uimm5), \
1333 32); \
1334 } else if (rvv_vsew() == E64) { \
1335 UNREACHABLE(); \
1336 } else { \
1337 UNREACHABLE(); \
1338 } \
1339 RVV_VI_LOOP_END \
1340 rvv_trace_vd();
1341
1342 #define CHECK_EXT(div) \
1343 CHECK_NE(rvv_vd_reg(), rvv_vs2_reg()); \
1344 reg_t from = rvv_vsew() / div; \
1345 CHECK(from >= E8 && from <= E64); \
1346 CHECK_GE((float)rvv_vflmul() / div, 0.125); \
1347 CHECK_LE((float)rvv_vflmul() / div, 8); \
1348 require_align(rvv_vd_reg(), rvv_vflmul()); \
1349 require_align(rvv_vs2_reg(), rvv_vflmul() / div); \
1350 if ((rvv_vflmul() / div) < 1) { \
1351 require_noover(rvv_vd_reg(), rvv_vflmul(), rvv_vs2_reg(), \
1352 rvv_vflmul() / div); \
1353 } else { \
1354 require_noover_widen(rvv_vd_reg(), rvv_vflmul(), rvv_vs2_reg(), \
1355 rvv_vflmul() / div); \
1356 }
1357
1358 #define RVV_VI_VIE_8_LOOP(signed) \
1359 CHECK_EXT(8) \
1360 RVV_VI_GENERAL_LOOP_BASE \
1361 RVV_VI_LOOP_MASK_SKIP() \
1362 if (rvv_vsew() == E64) { \
1363 if (signed) { \
1364 VI_VIE_PARAMS(64, 8); \
1365 vd = static_cast<int64_t>(vs2); \
1366 } else { \
1367 VI_VIE_UPARAMS(64, 8); \
1368 vd = static_cast<uint64_t>(vs2); \
1369 } \
1370 } else { \
1371 UNREACHABLE(); \
1372 } \
1373 RVV_VI_LOOP_END \
1374 rvv_trace_vd();
1375
1376 #define RVV_VI_VIE_4_LOOP(signed) \
1377 CHECK_EXT(4) \
1378 RVV_VI_GENERAL_LOOP_BASE \
1379 RVV_VI_LOOP_MASK_SKIP() \
1380 if (rvv_vsew() == E32) { \
1381 if (signed) { \
1382 VI_VIE_PARAMS(32, 4); \
1383 vd = static_cast<int32_t>(vs2); \
1384 } else { \
1385 VI_VIE_UPARAMS(32, 4); \
1386 vd = static_cast<uint32_t>(vs2); \
1387 } \
1388 } else if (rvv_vsew() == E64) { \
1389 if (signed) { \
1390 VI_VIE_PARAMS(64, 4); \
1391 vd = static_cast<int64_t>(vs2); \
1392 } else { \
1393 VI_VIE_UPARAMS(64, 4); \
1394 vd = static_cast<uint64_t>(vs2); \
1395 } \
1396 } else { \
1397 UNREACHABLE(); \
1398 } \
1399 RVV_VI_LOOP_END \
1400 rvv_trace_vd();
1401
1402 #define RVV_VI_VIE_2_LOOP(signed) \
1403 CHECK_EXT(2) \
1404 RVV_VI_GENERAL_LOOP_BASE \
1405 RVV_VI_LOOP_MASK_SKIP() \
1406 if (rvv_vsew() == E16) { \
1407 if (signed) { \
1408 VI_VIE_PARAMS(16, 2); \
1409 vd = static_cast<int16_t>(vs2); \
1410 } else { \
1411 VI_VIE_UPARAMS(16, 2); \
1412 vd = static_cast<uint16_t>(vs2); \
1413 } \
1414 } else if (rvv_vsew() == E32) { \
1415 if (signed) { \
1416 VI_VIE_PARAMS(32, 2); \
1417 vd = static_cast<int32_t>(vs2); \
1418 } else { \
1419 VI_VIE_UPARAMS(32, 2); \
1420 vd = static_cast<uint32_t>(vs2); \
1421 } \
1422 } else if (rvv_vsew() == E64) { \
1423 if (signed) { \
1424 VI_VIE_PARAMS(64, 2); \
1425 vd = static_cast<int64_t>(vs2); \
1426 } else { \
1427 VI_VIE_UPARAMS(64, 2); \
1428 vd = static_cast<uint64_t>(vs2); \
1429 } \
1430 } else { \
1431 UNREACHABLE(); \
1432 } \
1433 RVV_VI_LOOP_END \
1434 rvv_trace_vd();
1435 #endif
1436
1437 namespace v8 {
1438 namespace internal {
1439
DEFINE_LAZY_LEAKY_OBJECT_GETTER(Simulator::GlobalMonitor,Simulator::GlobalMonitor::Get)1440 DEFINE_LAZY_LEAKY_OBJECT_GETTER(Simulator::GlobalMonitor,
1441 Simulator::GlobalMonitor::Get)
1442
1443 // Util functions.
1444 inline bool HaveSameSign(int64_t a, int64_t b) { return ((a ^ b) >= 0); }
1445
get_fcsr_condition_bit(uint32_t cc)1446 uint32_t get_fcsr_condition_bit(uint32_t cc) {
1447 if (cc == 0) {
1448 return 23;
1449 } else {
1450 return 24 + cc;
1451 }
1452 }
1453
1454 // Generated by Assembler::break_()/stop(), ebreak code is passed as immediate
1455 // field of a subsequent LUI instruction; otherwise returns -1
get_ebreak_code(Instruction * instr)1456 static inline int32_t get_ebreak_code(Instruction* instr) {
1457 DCHECK(instr->InstructionBits() == kBreakInstr);
1458 byte* cur = reinterpret_cast<byte*>(instr);
1459 Instruction* next_instr = reinterpret_cast<Instruction*>(cur + kInstrSize);
1460 if (next_instr->BaseOpcodeFieldRaw() == RO_LUI)
1461 return (next_instr->Imm20UValue());
1462 else
1463 return -1;
1464 }
1465
1466 // This macro provides a platform independent use of sscanf. The reason for
1467 // SScanF not being implemented in a platform independent was through
1468 // ::v8::internal::OS in the same way as SNPrintF is that the Windows C Run-Time
1469 // Library does not provide vsscanf.
1470 #define SScanF sscanf
1471
1472 // The RiscvDebugger class is used by the simulator while debugging simulated
1473 // code.
1474 class RiscvDebugger {
1475 public:
RiscvDebugger(Simulator * sim)1476 explicit RiscvDebugger(Simulator* sim) : sim_(sim) {}
1477
1478 void Debug();
1479 // Print all registers with a nice formatting.
1480 void PrintRegs(char name_prefix, int start_index, int end_index);
1481 void PrintAllRegs();
1482 void PrintAllRegsIncludingFPU();
1483
1484 static const Instr kNopInstr = 0x0;
1485
1486 private:
1487 Simulator* sim_;
1488
1489 int64_t GetRegisterValue(int regnum);
1490 int64_t GetFPURegisterValue(int regnum);
1491 float GetFPURegisterValueFloat(int regnum);
1492 double GetFPURegisterValueDouble(int regnum);
1493 #ifdef CAN_USE_RVV_INSTRUCTIONS
1494 __int128_t GetVRegisterValue(int regnum);
1495 #endif
1496 bool GetValue(const char* desc, int64_t* value);
1497 };
1498
1499 #define UNSUPPORTED() \
1500 printf("Sim: Unsupported instruction. Func:%s Line:%d\n", __FUNCTION__, \
1501 __LINE__); \
1502 base::OS::Abort();
1503
GetRegisterValue(int regnum)1504 int64_t RiscvDebugger::GetRegisterValue(int regnum) {
1505 if (regnum == kNumSimuRegisters) {
1506 return sim_->get_pc();
1507 } else {
1508 return sim_->get_register(regnum);
1509 }
1510 }
1511
GetFPURegisterValue(int regnum)1512 int64_t RiscvDebugger::GetFPURegisterValue(int regnum) {
1513 if (regnum == kNumFPURegisters) {
1514 return sim_->get_pc();
1515 } else {
1516 return sim_->get_fpu_register(regnum);
1517 }
1518 }
1519
GetFPURegisterValueFloat(int regnum)1520 float RiscvDebugger::GetFPURegisterValueFloat(int regnum) {
1521 if (regnum == kNumFPURegisters) {
1522 return sim_->get_pc();
1523 } else {
1524 return sim_->get_fpu_register_float(regnum);
1525 }
1526 }
1527
GetFPURegisterValueDouble(int regnum)1528 double RiscvDebugger::GetFPURegisterValueDouble(int regnum) {
1529 if (regnum == kNumFPURegisters) {
1530 return sim_->get_pc();
1531 } else {
1532 return sim_->get_fpu_register_double(regnum);
1533 }
1534 }
1535
1536 #ifdef CAN_USE_RVV_INSTRUCTIONS
GetVRegisterValue(int regnum)1537 __int128_t RiscvDebugger::GetVRegisterValue(int regnum) {
1538 if (regnum == kNumVRegisters) {
1539 return sim_->get_pc();
1540 } else {
1541 return sim_->get_vregister(regnum);
1542 }
1543 }
1544 #endif
1545
GetValue(const char * desc,int64_t * value)1546 bool RiscvDebugger::GetValue(const char* desc, int64_t* value) {
1547 int regnum = Registers::Number(desc);
1548 int fpuregnum = FPURegisters::Number(desc);
1549
1550 if (regnum != kInvalidRegister) {
1551 *value = GetRegisterValue(regnum);
1552 return true;
1553 } else if (fpuregnum != kInvalidFPURegister) {
1554 *value = GetFPURegisterValue(fpuregnum);
1555 return true;
1556 } else if (strncmp(desc, "0x", 2) == 0) {
1557 return SScanF(desc + 2, "%" SCNx64, reinterpret_cast<uint64_t*>(value)) ==
1558 1;
1559 } else {
1560 return SScanF(desc, "%" SCNu64, reinterpret_cast<uint64_t*>(value)) == 1;
1561 }
1562 }
1563
1564 #define REG_INFO(name) \
1565 name, GetRegisterValue(Registers::Number(name)), \
1566 GetRegisterValue(Registers::Number(name))
1567
PrintRegs(char name_prefix,int start_index,int end_index)1568 void RiscvDebugger::PrintRegs(char name_prefix, int start_index,
1569 int end_index) {
1570 base::EmbeddedVector<char, 10> name1, name2;
1571 DCHECK(name_prefix == 'a' || name_prefix == 't' || name_prefix == 's');
1572 DCHECK(start_index >= 0 && end_index <= 99);
1573 int num_registers = (end_index - start_index) + 1;
1574 for (int i = 0; i < num_registers / 2; i++) {
1575 SNPrintF(name1, "%c%d", name_prefix, start_index + 2 * i);
1576 SNPrintF(name2, "%c%d", name_prefix, start_index + 2 * i + 1);
1577 PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 " \t%3s: 0x%016" PRIx64
1578 " %14" PRId64 " \n",
1579 REG_INFO(name1.begin()), REG_INFO(name2.begin()));
1580 }
1581 if (num_registers % 2 == 1) {
1582 SNPrintF(name1, "%c%d", name_prefix, end_index);
1583 PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 " \n", REG_INFO(name1.begin()));
1584 }
1585 }
1586
PrintAllRegs()1587 void RiscvDebugger::PrintAllRegs() {
1588 PrintF("\n");
1589 // ra, sp, gp
1590 PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 "\t%3s: 0x%016" PRIx64 " %14" PRId64
1591 "\t%3s: 0x%016" PRIx64 " %14" PRId64 "\n",
1592 REG_INFO("ra"), REG_INFO("sp"), REG_INFO("gp"));
1593
1594 // tp, fp, pc
1595 PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 "\t%3s: 0x%016" PRIx64 " %14" PRId64
1596 "\t%3s: 0x%016" PRIx64 " %14" PRId64 "\n",
1597 REG_INFO("tp"), REG_INFO("fp"), REG_INFO("pc"));
1598
1599 // print register a0, .., a7
1600 PrintRegs('a', 0, 7);
1601 // print registers s1, ..., s11
1602 PrintRegs('s', 1, 11);
1603 // print registers t0, ..., t6
1604 PrintRegs('t', 0, 6);
1605 }
1606
1607 #undef REG_INFO
1608
PrintAllRegsIncludingFPU()1609 void RiscvDebugger::PrintAllRegsIncludingFPU() {
1610 #define FPU_REG_INFO(n) \
1611 FPURegisters::Name(n), GetFPURegisterValue(n), GetFPURegisterValueDouble(n)
1612
1613 PrintAllRegs();
1614
1615 PrintF("\n\n");
1616 // f0, f1, f2, ... f31.
1617 DCHECK_EQ(kNumFPURegisters % 2, 0);
1618 for (int i = 0; i < kNumFPURegisters; i += 2)
1619 PrintF("%3s: 0x%016" PRIx64 " %16.4e \t%3s: 0x%016" PRIx64 " %16.4e\n",
1620 FPU_REG_INFO(i), FPU_REG_INFO(i + 1));
1621 #undef FPU_REG_INFO
1622 }
1623
Debug()1624 void RiscvDebugger::Debug() {
1625 intptr_t last_pc = -1;
1626 bool done = false;
1627
1628 #define COMMAND_SIZE 63
1629 #define ARG_SIZE 255
1630
1631 #define STR(a) #a
1632 #define XSTR(a) STR(a)
1633
1634 char cmd[COMMAND_SIZE + 1];
1635 char arg1[ARG_SIZE + 1];
1636 char arg2[ARG_SIZE + 1];
1637 char* argv[3] = {cmd, arg1, arg2};
1638
1639 // Make sure to have a proper terminating character if reaching the limit.
1640 cmd[COMMAND_SIZE] = 0;
1641 arg1[ARG_SIZE] = 0;
1642 arg2[ARG_SIZE] = 0;
1643
1644 while (!done && (sim_->get_pc() != Simulator::end_sim_pc)) {
1645 if (last_pc != sim_->get_pc()) {
1646 disasm::NameConverter converter;
1647 disasm::Disassembler dasm(converter);
1648 // Use a reasonably large buffer.
1649 v8::base::EmbeddedVector<char, 256> buffer;
1650 const char* name = sim_->builtins_.Lookup((Address)sim_->get_pc());
1651 if (name != nullptr) {
1652 PrintF("Call builtin: %s\n", name);
1653 }
1654 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(sim_->get_pc()));
1655 PrintF(" 0x%016" PRIx64 " %s\n", sim_->get_pc(), buffer.begin());
1656 last_pc = sim_->get_pc();
1657 }
1658 char* line = ReadLine("sim> ");
1659 if (line == nullptr) {
1660 break;
1661 } else {
1662 char* last_input = sim_->last_debugger_input();
1663 if (strcmp(line, "\n") == 0 && last_input != nullptr) {
1664 line = last_input;
1665 } else {
1666 // Ownership is transferred to sim_;
1667 sim_->set_last_debugger_input(line);
1668 }
1669 // Use sscanf to parse the individual parts of the command line. At the
1670 // moment no command expects more than two parameters.
1671 int argc = SScanF(
1672 line,
1673 "%" XSTR(COMMAND_SIZE) "s "
1674 "%" XSTR(ARG_SIZE) "s "
1675 "%" XSTR(ARG_SIZE) "s",
1676 cmd, arg1, arg2);
1677 if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
1678 Instruction* instr = reinterpret_cast<Instruction*>(sim_->get_pc());
1679 if (!(instr->IsTrap()) ||
1680 instr->InstructionBits() == rtCallRedirInstr) {
1681 sim_->InstructionDecode(
1682 reinterpret_cast<Instruction*>(sim_->get_pc()));
1683 } else {
1684 // Allow si to jump over generated breakpoints.
1685 PrintF("/!\\ Jumping over generated breakpoint.\n");
1686 sim_->set_pc(sim_->get_pc() + kInstrSize);
1687 }
1688 } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
1689 // Execute the one instruction we broke at with breakpoints disabled.
1690 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
1691 // Leave the debugger shell.
1692 done = true;
1693 } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
1694 if (argc == 2) {
1695 int64_t value;
1696 double dvalue;
1697 if (strcmp(arg1, "all") == 0) {
1698 PrintAllRegs();
1699 } else if (strcmp(arg1, "allf") == 0) {
1700 PrintAllRegsIncludingFPU();
1701 } else {
1702 int regnum = Registers::Number(arg1);
1703 int fpuregnum = FPURegisters::Number(arg1);
1704 #ifdef CAN_USE_RVV_INSTRUCTIONS
1705 int vregnum = VRegisters::Number(arg1);
1706 #endif
1707 if (regnum != kInvalidRegister) {
1708 value = GetRegisterValue(regnum);
1709 PrintF("%s: 0x%08" PRIx64 " %" PRId64 " \n", arg1, value,
1710 value);
1711 } else if (fpuregnum != kInvalidFPURegister) {
1712 value = GetFPURegisterValue(fpuregnum);
1713 dvalue = GetFPURegisterValueDouble(fpuregnum);
1714 PrintF("%3s: 0x%016" PRIx64 " %16.4e\n",
1715 FPURegisters::Name(fpuregnum), value, dvalue);
1716 #ifdef CAN_USE_RVV_INSTRUCTIONS
1717 } else if (vregnum != kInvalidVRegister) {
1718 __int128_t v = GetVRegisterValue(vregnum);
1719 PrintF("\t%s:0x%016" PRIx64 "%016" PRIx64 "\n",
1720 VRegisters::Name(vregnum), (uint64_t)(v >> 64),
1721 (uint64_t)v);
1722 #endif
1723 } else {
1724 PrintF("%s unrecognized\n", arg1);
1725 }
1726 }
1727 } else {
1728 if (argc == 3) {
1729 if (strcmp(arg2, "single") == 0) {
1730 int64_t value;
1731 float fvalue;
1732 int fpuregnum = FPURegisters::Number(arg1);
1733
1734 if (fpuregnum != kInvalidFPURegister) {
1735 value = GetFPURegisterValue(fpuregnum);
1736 value &= 0xFFFFFFFFUL;
1737 fvalue = GetFPURegisterValueFloat(fpuregnum);
1738 PrintF("%s: 0x%08" PRIx64 " %11.4e\n", arg1, value, fvalue);
1739 } else {
1740 PrintF("%s unrecognized\n", arg1);
1741 }
1742 } else {
1743 PrintF("print <fpu register> single\n");
1744 }
1745 } else {
1746 PrintF("print <register> or print <fpu register> single\n");
1747 }
1748 }
1749 } else if ((strcmp(cmd, "po") == 0) ||
1750 (strcmp(cmd, "printobject") == 0)) {
1751 if (argc == 2) {
1752 int64_t value;
1753 StdoutStream os;
1754 if (GetValue(arg1, &value)) {
1755 Object obj(value);
1756 os << arg1 << ": \n";
1757 #ifdef DEBUG
1758 obj.Print(os);
1759 os << "\n";
1760 #else
1761 os << Brief(obj) << "\n";
1762 #endif
1763 } else {
1764 os << arg1 << " unrecognized\n";
1765 }
1766 } else {
1767 PrintF("printobject <value>\n");
1768 }
1769 } else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) {
1770 int64_t* cur = nullptr;
1771 int64_t* end = nullptr;
1772 int next_arg = 1;
1773
1774 if (strcmp(cmd, "stack") == 0) {
1775 cur = reinterpret_cast<int64_t*>(sim_->get_register(Simulator::sp));
1776 } else { // Command "mem".
1777 if (argc < 2) {
1778 PrintF("Need to specify <address> to mem command\n");
1779 continue;
1780 }
1781 int64_t value;
1782 if (!GetValue(arg1, &value)) {
1783 PrintF("%s unrecognized\n", arg1);
1784 continue;
1785 }
1786 cur = reinterpret_cast<int64_t*>(value);
1787 next_arg++;
1788 }
1789
1790 int64_t words;
1791 if (argc == next_arg) {
1792 words = 10;
1793 } else {
1794 if (!GetValue(argv[next_arg], &words)) {
1795 words = 10;
1796 }
1797 }
1798 end = cur + words;
1799
1800 while (cur < end) {
1801 PrintF(" 0x%012" PRIxPTR " : 0x%016" PRIx64 " %14" PRId64 " ",
1802 reinterpret_cast<intptr_t>(cur), *cur, *cur);
1803 Object obj(*cur);
1804 Heap* current_heap = sim_->isolate_->heap();
1805 if (obj.IsSmi() ||
1806 IsValidHeapObject(current_heap, HeapObject::cast(obj))) {
1807 PrintF(" (");
1808 if (obj.IsSmi()) {
1809 PrintF("smi %d", Smi::ToInt(obj));
1810 } else {
1811 obj.ShortPrint();
1812 }
1813 PrintF(")");
1814 }
1815 PrintF("\n");
1816 cur++;
1817 }
1818
1819 } else if ((strcmp(cmd, "disasm") == 0) || (strcmp(cmd, "dpc") == 0) ||
1820 (strcmp(cmd, "di") == 0)) {
1821 disasm::NameConverter converter;
1822 disasm::Disassembler dasm(converter);
1823 // Use a reasonably large buffer.
1824 v8::base::EmbeddedVector<char, 256> buffer;
1825
1826 byte* cur = nullptr;
1827 byte* end = nullptr;
1828
1829 if (argc == 1) {
1830 cur = reinterpret_cast<byte*>(sim_->get_pc());
1831 end = cur + (10 * kInstrSize);
1832 } else if (argc == 2) {
1833 int regnum = Registers::Number(arg1);
1834 if (regnum != kInvalidRegister || strncmp(arg1, "0x", 2) == 0) {
1835 // The argument is an address or a register name.
1836 int64_t value;
1837 if (GetValue(arg1, &value)) {
1838 cur = reinterpret_cast<byte*>(value);
1839 // Disassemble 10 instructions at <arg1>.
1840 end = cur + (10 * kInstrSize);
1841 }
1842 } else {
1843 // The argument is the number of instructions.
1844 int64_t value;
1845 if (GetValue(arg1, &value)) {
1846 cur = reinterpret_cast<byte*>(sim_->get_pc());
1847 // Disassemble <arg1> instructions.
1848 end = cur + (value * kInstrSize);
1849 }
1850 }
1851 } else {
1852 int64_t value1;
1853 int64_t value2;
1854 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
1855 cur = reinterpret_cast<byte*>(value1);
1856 end = cur + (value2 * kInstrSize);
1857 }
1858 }
1859
1860 while (cur < end) {
1861 dasm.InstructionDecode(buffer, cur);
1862 PrintF(" 0x%08" PRIxPTR " %s\n", reinterpret_cast<intptr_t>(cur),
1863 buffer.begin());
1864 cur += kInstrSize;
1865 }
1866 } else if (strcmp(cmd, "gdb") == 0) {
1867 PrintF("relinquishing control to gdb\n");
1868 v8::base::OS::DebugBreak();
1869 PrintF("regaining control from gdb\n");
1870 } else if (strcmp(cmd, "break") == 0 || strcmp(cmd, "b") == 0 ||
1871 strcmp(cmd, "tbreak") == 0) {
1872 bool is_tbreak = strcmp(cmd, "tbreak") == 0;
1873 if (argc == 2) {
1874 int64_t value;
1875 if (GetValue(arg1, &value)) {
1876 sim_->SetBreakpoint(reinterpret_cast<Instruction*>(value),
1877 is_tbreak);
1878 } else {
1879 PrintF("%s unrecognized\n", arg1);
1880 }
1881 } else {
1882 sim_->ListBreakpoints();
1883 PrintF("Use `break <address>` to set or disable a breakpoint\n");
1884 PrintF(
1885 "Use `tbreak <address>` to set or disable a temporary "
1886 "breakpoint\n");
1887 }
1888 } else if (strcmp(cmd, "flags") == 0) {
1889 PrintF("No flags on RISC-V !\n");
1890 } else if (strcmp(cmd, "stop") == 0) {
1891 int64_t value;
1892 if (argc == 3) {
1893 // Print information about all/the specified breakpoint(s).
1894 if (strcmp(arg1, "info") == 0) {
1895 if (strcmp(arg2, "all") == 0) {
1896 PrintF("Stop information:\n");
1897 for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
1898 i++) {
1899 sim_->PrintStopInfo(i);
1900 }
1901 } else if (GetValue(arg2, &value)) {
1902 sim_->PrintStopInfo(value);
1903 } else {
1904 PrintF("Unrecognized argument.\n");
1905 }
1906 } else if (strcmp(arg1, "enable") == 0) {
1907 // Enable all/the specified breakpoint(s).
1908 if (strcmp(arg2, "all") == 0) {
1909 for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
1910 i++) {
1911 sim_->EnableStop(i);
1912 }
1913 } else if (GetValue(arg2, &value)) {
1914 sim_->EnableStop(value);
1915 } else {
1916 PrintF("Unrecognized argument.\n");
1917 }
1918 } else if (strcmp(arg1, "disable") == 0) {
1919 // Disable all/the specified breakpoint(s).
1920 if (strcmp(arg2, "all") == 0) {
1921 for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
1922 i++) {
1923 sim_->DisableStop(i);
1924 }
1925 } else if (GetValue(arg2, &value)) {
1926 sim_->DisableStop(value);
1927 } else {
1928 PrintF("Unrecognized argument.\n");
1929 }
1930 }
1931 } else {
1932 PrintF("Wrong usage. Use help command for more information.\n");
1933 }
1934 } else if ((strcmp(cmd, "stat") == 0) || (strcmp(cmd, "st") == 0)) {
1935 // Print registers and disassemble.
1936 PrintAllRegs();
1937 PrintF("\n");
1938
1939 disasm::NameConverter converter;
1940 disasm::Disassembler dasm(converter);
1941 // Use a reasonably large buffer.
1942 v8::base::EmbeddedVector<char, 256> buffer;
1943
1944 byte* cur = nullptr;
1945 byte* end = nullptr;
1946
1947 if (argc == 1) {
1948 cur = reinterpret_cast<byte*>(sim_->get_pc());
1949 end = cur + (10 * kInstrSize);
1950 } else if (argc == 2) {
1951 int64_t value;
1952 if (GetValue(arg1, &value)) {
1953 cur = reinterpret_cast<byte*>(value);
1954 // no length parameter passed, assume 10 instructions
1955 end = cur + (10 * kInstrSize);
1956 }
1957 } else {
1958 int64_t value1;
1959 int64_t value2;
1960 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
1961 cur = reinterpret_cast<byte*>(value1);
1962 end = cur + (value2 * kInstrSize);
1963 }
1964 }
1965
1966 while (cur < end) {
1967 dasm.InstructionDecode(buffer, cur);
1968 PrintF(" 0x%08" PRIxPTR " %s\n", reinterpret_cast<intptr_t>(cur),
1969 buffer.begin());
1970 cur += kInstrSize;
1971 }
1972 } else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
1973 PrintF("cont (alias 'c')\n");
1974 PrintF(" Continue execution\n");
1975 PrintF("stepi (alias 'si')\n");
1976 PrintF(" Step one instruction\n");
1977 PrintF("print (alias 'p')\n");
1978 PrintF(" print <register>\n");
1979 PrintF(" Print register content\n");
1980 PrintF(" Use register name 'all' to print all GPRs\n");
1981 PrintF(" Use register name 'allf' to print all GPRs and FPRs\n");
1982 PrintF("printobject (alias 'po')\n");
1983 PrintF(" printobject <register>\n");
1984 PrintF(" Print an object from a register\n");
1985 PrintF("stack\n");
1986 PrintF(" stack [<words>]\n");
1987 PrintF(" Dump stack content, default dump 10 words)\n");
1988 PrintF("mem\n");
1989 PrintF(" mem <address> [<words>]\n");
1990 PrintF(" Dump memory content, default dump 10 words)\n");
1991 PrintF("flags\n");
1992 PrintF(" print flags\n");
1993 PrintF("disasm (alias 'di')\n");
1994 PrintF(" disasm [<instructions>]\n");
1995 PrintF(" disasm [<address/register>] (e.g., disasm pc) \n");
1996 PrintF(" disasm [[<address/register>] <instructions>]\n");
1997 PrintF(" Disassemble code, default is 10 instructions\n");
1998 PrintF(" from pc\n");
1999 PrintF("gdb \n");
2000 PrintF(" Return to gdb if the simulator was started with gdb\n");
2001 PrintF("break (alias 'b')\n");
2002 PrintF(" break : list all breakpoints\n");
2003 PrintF(" break <address> : set / enable / disable a breakpoint.\n");
2004 PrintF("tbreak\n");
2005 PrintF(" tbreak : list all breakpoints\n");
2006 PrintF(
2007 " tbreak <address> : set / enable / disable a temporary "
2008 "breakpoint.\n");
2009 PrintF(" Set a breakpoint enabled only for one stop. \n");
2010 PrintF("stop feature:\n");
2011 PrintF(" Description:\n");
2012 PrintF(" Stops are debug instructions inserted by\n");
2013 PrintF(" the Assembler::stop() function.\n");
2014 PrintF(" When hitting a stop, the Simulator will\n");
2015 PrintF(" stop and give control to the Debugger.\n");
2016 PrintF(" All stop codes are watched:\n");
2017 PrintF(" - They can be enabled / disabled: the Simulator\n");
2018 PrintF(" will / won't stop when hitting them.\n");
2019 PrintF(" - The Simulator keeps track of how many times they \n");
2020 PrintF(" are met. (See the info command.) Going over a\n");
2021 PrintF(" disabled stop still increases its counter. \n");
2022 PrintF(" Commands:\n");
2023 PrintF(" stop info all/<code> : print infos about number <code>\n");
2024 PrintF(" or all stop(s).\n");
2025 PrintF(" stop enable/disable all/<code> : enables / disables\n");
2026 PrintF(" all or number <code> stop(s)\n");
2027 } else {
2028 PrintF("Unknown command: %s\n", cmd);
2029 }
2030 }
2031 }
2032
2033 #undef COMMAND_SIZE
2034 #undef ARG_SIZE
2035
2036 #undef STR
2037 #undef XSTR
2038 }
2039
SetBreakpoint(Instruction * location,bool is_tbreak)2040 void Simulator::SetBreakpoint(Instruction* location, bool is_tbreak) {
2041 for (unsigned i = 0; i < breakpoints_.size(); i++) {
2042 if (breakpoints_.at(i).location == location) {
2043 if (breakpoints_.at(i).is_tbreak != is_tbreak) {
2044 PrintF("Change breakpoint at %p to %s breakpoint\n",
2045 reinterpret_cast<void*>(location),
2046 is_tbreak ? "temporary" : "regular");
2047 breakpoints_.at(i).is_tbreak = is_tbreak;
2048 return;
2049 }
2050 PrintF("Existing breakpoint at %p was %s\n",
2051 reinterpret_cast<void*>(location),
2052 breakpoints_.at(i).enabled ? "disabled" : "enabled");
2053 breakpoints_.at(i).enabled = !breakpoints_.at(i).enabled;
2054 return;
2055 }
2056 }
2057 Breakpoint new_breakpoint = {location, true, is_tbreak};
2058 breakpoints_.push_back(new_breakpoint);
2059 PrintF("Set a %sbreakpoint at %p\n", is_tbreak ? "temporary " : "",
2060 reinterpret_cast<void*>(location));
2061 }
2062
ListBreakpoints()2063 void Simulator::ListBreakpoints() {
2064 PrintF("Breakpoints:\n");
2065 for (unsigned i = 0; i < breakpoints_.size(); i++) {
2066 PrintF("%p : %s %s\n",
2067 reinterpret_cast<void*>(breakpoints_.at(i).location),
2068 breakpoints_.at(i).enabled ? "enabled" : "disabled",
2069 breakpoints_.at(i).is_tbreak ? ": temporary" : "");
2070 }
2071 }
2072
CheckBreakpoints()2073 void Simulator::CheckBreakpoints() {
2074 bool hit_a_breakpoint = false;
2075 bool is_tbreak = false;
2076 Instruction* pc_ = reinterpret_cast<Instruction*>(get_pc());
2077 for (unsigned i = 0; i < breakpoints_.size(); i++) {
2078 if ((breakpoints_.at(i).location == pc_) && breakpoints_.at(i).enabled) {
2079 hit_a_breakpoint = true;
2080 if (breakpoints_.at(i).is_tbreak) {
2081 // Disable a temporary breakpoint.
2082 is_tbreak = true;
2083 breakpoints_.at(i).enabled = false;
2084 }
2085 break;
2086 }
2087 }
2088 if (hit_a_breakpoint) {
2089 PrintF("Hit %sa breakpoint at %p.\n", is_tbreak ? "and disabled " : "",
2090 reinterpret_cast<void*>(pc_));
2091 RiscvDebugger dbg(this);
2092 dbg.Debug();
2093 }
2094 }
2095
ICacheMatch(void * one,void * two)2096 bool Simulator::ICacheMatch(void* one, void* two) {
2097 DCHECK_EQ(reinterpret_cast<intptr_t>(one) & CachePage::kPageMask, 0);
2098 DCHECK_EQ(reinterpret_cast<intptr_t>(two) & CachePage::kPageMask, 0);
2099 return one == two;
2100 }
2101
ICacheHash(void * key)2102 static uint32_t ICacheHash(void* key) {
2103 return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
2104 }
2105
AllOnOnePage(uintptr_t start,size_t size)2106 static bool AllOnOnePage(uintptr_t start, size_t size) {
2107 intptr_t start_page = (start & ~CachePage::kPageMask);
2108 intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
2109 return start_page == end_page;
2110 }
2111
set_last_debugger_input(char * input)2112 void Simulator::set_last_debugger_input(char* input) {
2113 DeleteArray(last_debugger_input_);
2114 last_debugger_input_ = input;
2115 }
2116
SetRedirectInstruction(Instruction * instruction)2117 void Simulator::SetRedirectInstruction(Instruction* instruction) {
2118 instruction->SetInstructionBits(rtCallRedirInstr);
2119 }
2120
FlushICache(base::CustomMatcherHashMap * i_cache,void * start_addr,size_t size)2121 void Simulator::FlushICache(base::CustomMatcherHashMap* i_cache,
2122 void* start_addr, size_t size) {
2123 int64_t start = reinterpret_cast<int64_t>(start_addr);
2124 int64_t intra_line = (start & CachePage::kLineMask);
2125 start -= intra_line;
2126 size += intra_line;
2127 size = ((size - 1) | CachePage::kLineMask) + 1;
2128 int offset = (start & CachePage::kPageMask);
2129 while (!AllOnOnePage(start, size - 1)) {
2130 int bytes_to_flush = CachePage::kPageSize - offset;
2131 FlushOnePage(i_cache, start, bytes_to_flush);
2132 start += bytes_to_flush;
2133 size -= bytes_to_flush;
2134 DCHECK_EQ((int64_t)0, start & CachePage::kPageMask);
2135 offset = 0;
2136 }
2137 if (size != 0) {
2138 FlushOnePage(i_cache, start, size);
2139 }
2140 }
2141
GetCachePage(base::CustomMatcherHashMap * i_cache,void * page)2142 CachePage* Simulator::GetCachePage(base::CustomMatcherHashMap* i_cache,
2143 void* page) {
2144 base::HashMap::Entry* entry = i_cache->LookupOrInsert(page, ICacheHash(page));
2145 if (entry->value == nullptr) {
2146 CachePage* new_page = new CachePage();
2147 entry->value = new_page;
2148 }
2149 return reinterpret_cast<CachePage*>(entry->value);
2150 }
2151
2152 // Flush from start up to and not including start + size.
FlushOnePage(base::CustomMatcherHashMap * i_cache,intptr_t start,size_t size)2153 void Simulator::FlushOnePage(base::CustomMatcherHashMap* i_cache,
2154 intptr_t start, size_t size) {
2155 DCHECK_LE(size, CachePage::kPageSize);
2156 DCHECK(AllOnOnePage(start, size - 1));
2157 DCHECK_EQ(start & CachePage::kLineMask, 0);
2158 DCHECK_EQ(size & CachePage::kLineMask, 0);
2159 void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
2160 int offset = (start & CachePage::kPageMask);
2161 CachePage* cache_page = GetCachePage(i_cache, page);
2162 char* valid_bytemap = cache_page->ValidityByte(offset);
2163 memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
2164 }
2165
CheckICache(base::CustomMatcherHashMap * i_cache,Instruction * instr)2166 void Simulator::CheckICache(base::CustomMatcherHashMap* i_cache,
2167 Instruction* instr) {
2168 int64_t address = reinterpret_cast<int64_t>(instr);
2169 void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
2170 void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
2171 int offset = (address & CachePage::kPageMask);
2172 CachePage* cache_page = GetCachePage(i_cache, page);
2173 char* cache_valid_byte = cache_page->ValidityByte(offset);
2174 bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
2175 char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
2176 if (cache_hit) {
2177 // Check that the data in memory matches the contents of the I-cache.
2178 CHECK_EQ(0, memcmp(reinterpret_cast<void*>(instr),
2179 cache_page->CachedData(offset), kInstrSize));
2180 } else {
2181 // Cache miss. Load memory into the cache.
2182 memcpy(cached_line, line, CachePage::kLineLength);
2183 *cache_valid_byte = CachePage::LINE_VALID;
2184 }
2185 }
2186
Simulator(Isolate * isolate)2187 Simulator::Simulator(Isolate* isolate) : isolate_(isolate), builtins_(isolate) {
2188 // Set up simulator support first. Some of this information is needed to
2189 // setup the architecture state.
2190 stack_size_ = FLAG_sim_stack_size * KB;
2191 stack_ = reinterpret_cast<char*>(malloc(stack_size_));
2192 pc_modified_ = false;
2193 icount_ = 0;
2194 break_count_ = 0;
2195 // Reset debug helpers.
2196 breakpoints_.clear();
2197 // TODO(riscv): 'next' command
2198 // break_on_next_ = false;
2199
2200 // Set up architecture state.
2201 // All registers are initialized to zero to start with.
2202 for (int i = 0; i < kNumSimuRegisters; i++) {
2203 registers_[i] = 0;
2204 }
2205
2206 for (int i = 0; i < kNumFPURegisters; i++) {
2207 FPUregisters_[i] = 0;
2208 }
2209
2210 FCSR_ = 0;
2211
2212 // The sp is initialized to point to the bottom (high address) of the
2213 // allocated stack area. To be safe in potential stack underflows we leave
2214 // some buffer below.
2215 registers_[sp] = reinterpret_cast<int64_t>(stack_) + stack_size_ - 64;
2216 // The ra and pc are initialized to a known bad value that will cause an
2217 // access violation if the simulator ever tries to execute it.
2218 registers_[pc] = bad_ra;
2219 registers_[ra] = bad_ra;
2220
2221 last_debugger_input_ = nullptr;
2222 }
2223
~Simulator()2224 Simulator::~Simulator() {
2225 GlobalMonitor::Get()->RemoveLinkedAddress(&global_monitor_thread_);
2226 free(stack_);
2227 }
2228
2229 // Get the active Simulator for the current thread.
current(Isolate * isolate)2230 Simulator* Simulator::current(Isolate* isolate) {
2231 v8::internal::Isolate::PerIsolateThreadData* isolate_data =
2232 isolate->FindOrAllocatePerThreadDataForThisThread();
2233 DCHECK_NOT_NULL(isolate_data);
2234
2235 Simulator* sim = isolate_data->simulator();
2236 if (sim == nullptr) {
2237 // TODO(146): delete the simulator object when a thread/isolate goes away.
2238 sim = new Simulator(isolate);
2239 isolate_data->set_simulator(sim);
2240 }
2241 return sim;
2242 }
2243
2244 // Sets the register in the architecture state. It will also deal with
2245 // updating Simulator internal state for special registers such as PC.
set_register(int reg,int64_t value)2246 void Simulator::set_register(int reg, int64_t value) {
2247 DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
2248 if (reg == pc) {
2249 pc_modified_ = true;
2250 }
2251
2252 // Zero register always holds 0.
2253 registers_[reg] = (reg == 0) ? 0 : value;
2254 }
2255
set_dw_register(int reg,const int * dbl)2256 void Simulator::set_dw_register(int reg, const int* dbl) {
2257 DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
2258 registers_[reg] = dbl[1];
2259 registers_[reg] = registers_[reg] << 32;
2260 registers_[reg] += dbl[0];
2261 }
2262
set_fpu_register(int fpureg,int64_t value)2263 void Simulator::set_fpu_register(int fpureg, int64_t value) {
2264 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2265 FPUregisters_[fpureg] = value;
2266 }
2267
set_fpu_register_word(int fpureg,int32_t value)2268 void Simulator::set_fpu_register_word(int fpureg, int32_t value) {
2269 // Set ONLY lower 32-bits, leaving upper bits untouched.
2270 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2271 int32_t* pword;
2272 if (kArchEndian == kLittle) {
2273 pword = reinterpret_cast<int32_t*>(&FPUregisters_[fpureg]);
2274 } else {
2275 pword = reinterpret_cast<int32_t*>(&FPUregisters_[fpureg]) + 1;
2276 }
2277 *pword = value;
2278 }
2279
set_fpu_register_hi_word(int fpureg,int32_t value)2280 void Simulator::set_fpu_register_hi_word(int fpureg, int32_t value) {
2281 // Set ONLY upper 32-bits, leaving lower bits untouched.
2282 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2283 int32_t* phiword;
2284 if (kArchEndian == kLittle) {
2285 phiword = (reinterpret_cast<int32_t*>(&FPUregisters_[fpureg])) + 1;
2286 } else {
2287 phiword = reinterpret_cast<int32_t*>(&FPUregisters_[fpureg]);
2288 }
2289 *phiword = value;
2290 }
2291
set_fpu_register_float(int fpureg,float value)2292 void Simulator::set_fpu_register_float(int fpureg, float value) {
2293 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2294 FPUregisters_[fpureg] = box_float(value);
2295 }
2296
set_fpu_register_double(int fpureg,double value)2297 void Simulator::set_fpu_register_double(int fpureg, double value) {
2298 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2299 *bit_cast<double*>(&FPUregisters_[fpureg]) = value;
2300 }
2301
2302 // Get the register from the architecture state. This function does handle
2303 // the special case of accessing the PC register.
get_register(int reg) const2304 int64_t Simulator::get_register(int reg) const {
2305 DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
2306 if (reg == 0)
2307 return 0;
2308 else
2309 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
2310 }
2311
get_double_from_register_pair(int reg)2312 double Simulator::get_double_from_register_pair(int reg) {
2313 // TODO(plind): bad ABI stuff, refactor or remove.
2314 DCHECK((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0));
2315
2316 double dm_val = 0.0;
2317 // Read the bits from the unsigned integer register_[] array
2318 // into the double precision floating point value and return it.
2319 char buffer[sizeof(registers_[0])];
2320 memcpy(buffer, ®isters_[reg], sizeof(registers_[0]));
2321 memcpy(&dm_val, buffer, sizeof(registers_[0]));
2322 return (dm_val);
2323 }
2324
get_fpu_register(int fpureg) const2325 int64_t Simulator::get_fpu_register(int fpureg) const {
2326 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2327 return FPUregisters_[fpureg];
2328 }
2329
get_fpu_register_word(int fpureg) const2330 int32_t Simulator::get_fpu_register_word(int fpureg) const {
2331 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2332 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xFFFFFFFF);
2333 }
2334
get_fpu_register_signed_word(int fpureg) const2335 int32_t Simulator::get_fpu_register_signed_word(int fpureg) const {
2336 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2337 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xFFFFFFFF);
2338 }
2339
get_fpu_register_hi_word(int fpureg) const2340 int32_t Simulator::get_fpu_register_hi_word(int fpureg) const {
2341 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2342 return static_cast<int32_t>((FPUregisters_[fpureg] >> 32) & 0xFFFFFFFF);
2343 }
2344
get_fpu_register_float(int fpureg) const2345 float Simulator::get_fpu_register_float(int fpureg) const {
2346 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2347 if (!is_boxed_float(FPUregisters_[fpureg])) {
2348 return std::numeric_limits<float>::quiet_NaN();
2349 }
2350 return *bit_cast<float*>(const_cast<int64_t*>(&FPUregisters_[fpureg]));
2351 }
2352
get_fpu_register_double(int fpureg) const2353 double Simulator::get_fpu_register_double(int fpureg) const {
2354 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
2355 return *bit_cast<double*>(&FPUregisters_[fpureg]);
2356 }
2357
2358 #ifdef CAN_USE_RVV_INSTRUCTIONS
get_vregister(int vreg) const2359 __int128_t Simulator::get_vregister(int vreg) const {
2360 DCHECK((vreg >= 0) && (vreg < kNumVRegisters));
2361 return Vregister_[vreg];
2362 }
2363 #endif
2364
2365 // Runtime FP routines take up to two double arguments and zero
2366 // or one integer arguments. All are constructed here,
2367 // from fa0, fa1, and a0.
GetFpArgs(double * x,double * y,int32_t * z)2368 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
2369 *x = get_fpu_register_double(fa0);
2370 *y = get_fpu_register_double(fa1);
2371 *z = static_cast<int32_t>(get_register(a0));
2372 }
2373
2374 // The return value is in fa0.
SetFpResult(const double & result)2375 void Simulator::SetFpResult(const double& result) {
2376 set_fpu_register_double(fa0, result);
2377 }
2378
2379 // helper functions to read/write/set/clear CRC values/bits
read_csr_value(uint32_t csr)2380 uint32_t Simulator::read_csr_value(uint32_t csr) {
2381 switch (csr) {
2382 case csr_fflags: // Floating-Point Accrued Exceptions (RW)
2383 return (FCSR_ & kFcsrFlagsMask);
2384 case csr_frm: // Floating-Point Dynamic Rounding Mode (RW)
2385 return (FCSR_ & kFcsrFrmMask) >> kFcsrFrmShift;
2386 case csr_fcsr: // Floating-Point Control and Status Register (RW)
2387 return (FCSR_ & kFcsrMask);
2388 default:
2389 UNIMPLEMENTED();
2390 }
2391 }
2392
get_dynamic_rounding_mode()2393 uint32_t Simulator::get_dynamic_rounding_mode() {
2394 return read_csr_value(csr_frm);
2395 }
2396
write_csr_value(uint32_t csr,uint64_t val)2397 void Simulator::write_csr_value(uint32_t csr, uint64_t val) {
2398 uint32_t value = (uint32_t)val;
2399 switch (csr) {
2400 case csr_fflags: // Floating-Point Accrued Exceptions (RW)
2401 DCHECK(value <= ((1 << kFcsrFlagsBits) - 1));
2402 FCSR_ = (FCSR_ & (~kFcsrFlagsMask)) | value;
2403 break;
2404 case csr_frm: // Floating-Point Dynamic Rounding Mode (RW)
2405 DCHECK(value <= ((1 << kFcsrFrmBits) - 1));
2406 FCSR_ = (FCSR_ & (~kFcsrFrmMask)) | (value << kFcsrFrmShift);
2407 break;
2408 case csr_fcsr: // Floating-Point Control and Status Register (RW)
2409 DCHECK(value <= ((1 << kFcsrBits) - 1));
2410 FCSR_ = (FCSR_ & (~kFcsrMask)) | value;
2411 break;
2412 default:
2413 UNIMPLEMENTED();
2414 }
2415 }
2416
set_csr_bits(uint32_t csr,uint64_t val)2417 void Simulator::set_csr_bits(uint32_t csr, uint64_t val) {
2418 uint32_t value = (uint32_t)val;
2419 switch (csr) {
2420 case csr_fflags: // Floating-Point Accrued Exceptions (RW)
2421 DCHECK(value <= ((1 << kFcsrFlagsBits) - 1));
2422 FCSR_ = FCSR_ | value;
2423 break;
2424 case csr_frm: // Floating-Point Dynamic Rounding Mode (RW)
2425 DCHECK(value <= ((1 << kFcsrFrmBits) - 1));
2426 FCSR_ = FCSR_ | (value << kFcsrFrmShift);
2427 break;
2428 case csr_fcsr: // Floating-Point Control and Status Register (RW)
2429 DCHECK(value <= ((1 << kFcsrBits) - 1));
2430 FCSR_ = FCSR_ | value;
2431 break;
2432 default:
2433 UNIMPLEMENTED();
2434 }
2435 }
2436
clear_csr_bits(uint32_t csr,uint64_t val)2437 void Simulator::clear_csr_bits(uint32_t csr, uint64_t val) {
2438 uint32_t value = (uint32_t)val;
2439 switch (csr) {
2440 case csr_fflags: // Floating-Point Accrued Exceptions (RW)
2441 DCHECK(value <= ((1 << kFcsrFlagsBits) - 1));
2442 FCSR_ = FCSR_ & (~value);
2443 break;
2444 case csr_frm: // Floating-Point Dynamic Rounding Mode (RW)
2445 DCHECK(value <= ((1 << kFcsrFrmBits) - 1));
2446 FCSR_ = FCSR_ & (~(value << kFcsrFrmShift));
2447 break;
2448 case csr_fcsr: // Floating-Point Control and Status Register (RW)
2449 DCHECK(value <= ((1 << kFcsrBits) - 1));
2450 FCSR_ = FCSR_ & (~value);
2451 break;
2452 default:
2453 UNIMPLEMENTED();
2454 }
2455 }
2456
test_fflags_bits(uint32_t mask)2457 bool Simulator::test_fflags_bits(uint32_t mask) {
2458 return (FCSR_ & kFcsrFlagsMask & mask) != 0;
2459 }
2460
2461 template <typename T>
FMaxMinHelper(T a,T b,MaxMinKind kind)2462 T Simulator::FMaxMinHelper(T a, T b, MaxMinKind kind) {
2463 // set invalid bit for signaling nan
2464 if ((a == std::numeric_limits<T>::signaling_NaN()) ||
2465 (b == std::numeric_limits<T>::signaling_NaN())) {
2466 set_csr_bits(csr_fflags, kInvalidOperation);
2467 }
2468
2469 T result = 0;
2470 if (std::isnan(a) && std::isnan(b)) {
2471 result = std::numeric_limits<float>::quiet_NaN();
2472 } else if (std::isnan(a)) {
2473 result = b;
2474 } else if (std::isnan(b)) {
2475 result = a;
2476 } else if (b == a) { // Handle -0.0 == 0.0 case.
2477 if (kind == MaxMinKind::kMax) {
2478 result = std::signbit(b) ? a : b;
2479 } else {
2480 result = std::signbit(b) ? b : a;
2481 }
2482 } else {
2483 result = (kind == MaxMinKind::kMax) ? fmax(a, b) : fmin(a, b);
2484 }
2485
2486 return result;
2487 }
2488
2489 // Raw access to the PC register.
set_pc(int64_t value)2490 void Simulator::set_pc(int64_t value) {
2491 pc_modified_ = true;
2492 registers_[pc] = value;
2493 DCHECK(has_bad_pc() || ((value % kInstrSize) == 0) ||
2494 ((value % kShortInstrSize) == 0));
2495 }
2496
has_bad_pc() const2497 bool Simulator::has_bad_pc() const {
2498 return ((registers_[pc] == bad_ra) || (registers_[pc] == end_sim_pc));
2499 }
2500
2501 // Raw access to the PC register without the special adjustment when reading.
get_pc() const2502 int64_t Simulator::get_pc() const { return registers_[pc]; }
2503
2504 // The RISC-V spec leaves it open to the implementation on how to handle
2505 // unaligned reads and writes. For now, we simply disallow unaligned reads but
2506 // at some point, we may want to implement some other behavior.
2507
2508 // TODO(plind): refactor this messy debug code when we do unaligned access.
DieOrDebug()2509 void Simulator::DieOrDebug() {
2510 if (FLAG_riscv_trap_to_simulator_debugger) {
2511 RiscvDebugger dbg(this);
2512 dbg.Debug();
2513 } else {
2514 base::OS::Abort();
2515 }
2516 }
2517
TraceRegWr(int64_t value,TraceType t)2518 void Simulator::TraceRegWr(int64_t value, TraceType t) {
2519 if (::v8::internal::FLAG_trace_sim) {
2520 union {
2521 int64_t fmt_int64;
2522 int32_t fmt_int32[2];
2523 float fmt_float[2];
2524 double fmt_double;
2525 } v;
2526 v.fmt_int64 = value;
2527
2528 switch (t) {
2529 case WORD:
2530 SNPrintF(trace_buf_,
2531 "%016" PRIx64 " (%" PRId64 ") int32:%" PRId32
2532 " uint32:%" PRIu32,
2533 v.fmt_int64, icount_, v.fmt_int32[0], v.fmt_int32[0]);
2534 break;
2535 case DWORD:
2536 SNPrintF(trace_buf_,
2537 "%016" PRIx64 " (%" PRId64 ") int64:%" PRId64
2538 " uint64:%" PRIu64,
2539 value, icount_, value, value);
2540 break;
2541 case FLOAT:
2542 SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") flt:%e",
2543 v.fmt_int64, icount_, v.fmt_float[0]);
2544 break;
2545 case DOUBLE:
2546 SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") dbl:%e",
2547 v.fmt_int64, icount_, v.fmt_double);
2548 break;
2549 default:
2550 UNREACHABLE();
2551 }
2552 }
2553 }
2554
2555 // TODO(plind): consider making icount_ printing a flag option.
2556 template <typename T>
TraceMemRd(int64_t addr,T value,int64_t reg_value)2557 void Simulator::TraceMemRd(int64_t addr, T value, int64_t reg_value) {
2558 if (::v8::internal::FLAG_trace_sim) {
2559 if (std::is_integral<T>::value) {
2560 switch (sizeof(T)) {
2561 case 1:
2562 SNPrintF(trace_buf_,
2563 "%016" PRIx64 " (%" PRId64 ") int8:%" PRId8
2564 " uint8:%" PRIu8 " <-- [addr: %" PRIx64 "]",
2565 reg_value, icount_, static_cast<int8_t>(value),
2566 static_cast<uint8_t>(value), addr);
2567 break;
2568 case 2:
2569 SNPrintF(trace_buf_,
2570 "%016" PRIx64 " (%" PRId64 ") int16:%" PRId16
2571 " uint16:%" PRIu16 " <-- [addr: %" PRIx64 "]",
2572 reg_value, icount_, static_cast<int16_t>(value),
2573 static_cast<uint16_t>(value), addr);
2574 break;
2575 case 4:
2576 SNPrintF(trace_buf_,
2577 "%016" PRIx64 " (%" PRId64 ") int32:%" PRId32
2578 " uint32:%" PRIu32 " <-- [addr: %" PRIx64 "]",
2579 reg_value, icount_, static_cast<int32_t>(value),
2580 static_cast<uint32_t>(value), addr);
2581 break;
2582 case 8:
2583 SNPrintF(trace_buf_,
2584 "%016" PRIx64 " (%" PRId64 ") int64:%" PRId64
2585 " uint64:%" PRIu64 " <-- [addr: %" PRIx64 "]",
2586 reg_value, icount_, static_cast<int64_t>(value),
2587 static_cast<uint64_t>(value), addr);
2588 break;
2589 default:
2590 UNREACHABLE();
2591 }
2592 } else if (std::is_same<float, T>::value) {
2593 SNPrintF(trace_buf_,
2594 "%016" PRIx64 " (%" PRId64 ") flt:%e <-- [addr: %" PRIx64
2595 "]",
2596 reg_value, icount_, static_cast<float>(value), addr);
2597 } else if (std::is_same<double, T>::value) {
2598 SNPrintF(trace_buf_,
2599 "%016" PRIx64 " (%" PRId64 ") dbl:%e <-- [addr: %" PRIx64
2600 "]",
2601 reg_value, icount_, static_cast<double>(value), addr);
2602 } else {
2603 UNREACHABLE();
2604 }
2605 }
2606 }
2607
2608 template <typename T>
TraceMemWr(int64_t addr,T value)2609 void Simulator::TraceMemWr(int64_t addr, T value) {
2610 if (::v8::internal::FLAG_trace_sim) {
2611 switch (sizeof(T)) {
2612 case 1:
2613 SNPrintF(trace_buf_,
2614 " (%" PRIu64 ") int8:%" PRId8
2615 " uint8:%" PRIu8 " --> [addr: %" PRIx64 "]",
2616 icount_, static_cast<int8_t>(value),
2617 static_cast<uint8_t>(value), addr);
2618 break;
2619 case 2:
2620 SNPrintF(trace_buf_,
2621 " (%" PRIu64 ") int16:%" PRId16
2622 " uint16:%" PRIu16 " --> [addr: %" PRIx64 "]",
2623 icount_, static_cast<int16_t>(value),
2624 static_cast<uint16_t>(value), addr);
2625 break;
2626 case 4:
2627 if (std::is_integral<T>::value) {
2628 SNPrintF(trace_buf_,
2629 " (%" PRIu64 ") int32:%" PRId32
2630 " uint32:%" PRIu32 " --> [addr: %" PRIx64 "]",
2631 icount_, static_cast<int32_t>(value),
2632 static_cast<uint32_t>(value), addr);
2633 } else {
2634 SNPrintF(trace_buf_,
2635 " (%" PRIu64
2636 ") flt:%e --> [addr: %" PRIx64 "]",
2637 icount_, static_cast<float>(value), addr);
2638 }
2639 break;
2640 case 8:
2641 if (std::is_integral<T>::value) {
2642 SNPrintF(trace_buf_,
2643 " (%" PRIu64 ") int64:%" PRId64
2644 " uint64:%" PRIu64 " --> [addr: %" PRIx64 "]",
2645 icount_, static_cast<int64_t>(value),
2646 static_cast<uint64_t>(value), addr);
2647 } else {
2648 SNPrintF(trace_buf_,
2649 " (%" PRIu64
2650 ") dbl:%e --> [addr: %" PRIx64 "]",
2651 icount_, static_cast<double>(value), addr);
2652 }
2653 break;
2654 default:
2655 UNREACHABLE();
2656 }
2657 }
2658 }
2659
2660 // RISCV Memory Read/Write functions
2661
2662 // TODO(RISCV): check whether the specific board supports unaligned load/store
2663 // (determined by EEI). For now, we assume the board does not support unaligned
2664 // load/store (e.g., trapping)
2665 template <typename T>
ReadMem(int64_t addr,Instruction * instr)2666 T Simulator::ReadMem(int64_t addr, Instruction* instr) {
2667 if (addr >= 0 && addr < 0x400) {
2668 // This has to be a nullptr-dereference, drop into debugger.
2669 PrintF("Memory read from bad address: 0x%08" PRIx64 " , pc=0x%08" PRIxPTR
2670 " \n",
2671 addr, reinterpret_cast<intptr_t>(instr));
2672 DieOrDebug();
2673 }
2674 #if !defined(V8_COMPRESS_POINTERS) && defined(RISCV_HAS_NO_UNALIGNED)
2675 // check for natural alignment
2676 if (!FLAG_riscv_c_extension && ((addr & (sizeof(T) - 1)) != 0)) {
2677 PrintF("Unaligned read at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n",
2678 addr,
2679 reinterpret_cast<intptr_t>(instr));
2680 DieOrDebug();
2681 }
2682 #endif
2683 T* ptr = reinterpret_cast<T*>(addr);
2684 T value = *ptr;
2685 return value;
2686 }
2687
2688 template <typename T>
WriteMem(int64_t addr,T value,Instruction * instr)2689 void Simulator::WriteMem(int64_t addr, T value, Instruction* instr) {
2690 if (addr >= 0 && addr < 0x400) {
2691 // This has to be a nullptr-dereference, drop into debugger.
2692 PrintF("Memory write to bad address: 0x%08" PRIx64 " , pc=0x%08" PRIxPTR
2693 " \n",
2694 addr, reinterpret_cast<intptr_t>(instr));
2695 DieOrDebug();
2696 }
2697 #if !defined(V8_COMPRESS_POINTERS) && defined(RISCV_HAS_NO_UNALIGNED)
2698 // check for natural alignment
2699 if (!FLAG_riscv_c_extension && ((addr & (sizeof(T) - 1)) != 0)) {
2700 PrintF("Unaligned write at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n", addr,
2701 reinterpret_cast<intptr_t>(instr));
2702 DieOrDebug();
2703 }
2704 #endif
2705 T* ptr = reinterpret_cast<T*>(addr);
2706 TraceMemWr(addr, value);
2707 // PrintF("Unaligned read at 0x%08" PRIx64 " , pc=0x%08" PRId64 "\n",
2708 // (int64_t)ptr,
2709 // (int64_t)value);
2710 *ptr = value;
2711 }
2712
2713 // Returns the limit of the stack area to enable checking for stack overflows.
StackLimit(uintptr_t c_limit) const2714 uintptr_t Simulator::StackLimit(uintptr_t c_limit) const {
2715 // The simulator uses a separate JS stack. If we have exhausted the C stack,
2716 // we also drop down the JS limit to reflect the exhaustion on the JS stack.
2717 if (GetCurrentStackPosition() < c_limit) {
2718 return reinterpret_cast<uintptr_t>(get_sp());
2719 }
2720
2721 // Otherwise the limit is the JS stack. Leave a safety margin of 4 KiB
2722 // to prevent overrunning the stack when pushing values.
2723 return reinterpret_cast<uintptr_t>(stack_) + 4 * KB;
2724 }
2725
2726 // Unsupported instructions use Format to print an error and stop execution.
Format(Instruction * instr,const char * format)2727 void Simulator::Format(Instruction* instr, const char* format) {
2728 PrintF("Simulator found unsupported instruction:\n 0x%08" PRIxPTR " : %s\n",
2729 reinterpret_cast<intptr_t>(instr), format);
2730 UNIMPLEMENTED_RISCV();
2731 }
2732
2733 // Calls into the V8 runtime are based on this very simple interface.
2734 // Note: To be able to return two values from some calls the code in
2735 // runtime.cc uses the ObjectPair which is essentially two 32-bit values
2736 // stuffed into a 64-bit value. With the code below we assume that all runtime
2737 // calls return 64 bits of result. If they don't, the a1 result register
2738 // contains a bogus value, which is fine because it is caller-saved.
2739
2740 using SimulatorRuntimeCall = ObjectPair (*)(
2741 int64_t arg0, int64_t arg1, int64_t arg2, int64_t arg3, int64_t arg4,
2742 int64_t arg5, int64_t arg6, int64_t arg7, int64_t arg8, int64_t arg9,
2743 int64_t arg10, int64_t arg11, int64_t arg12, int64_t arg13, int64_t arg14,
2744 int64_t arg15, int64_t arg16, int64_t arg17, int64_t arg18, int64_t arg19);
2745
2746 // These prototypes handle the four types of FP calls.
2747 using SimulatorRuntimeCompareCall = int64_t (*)(double darg0, double darg1);
2748 using SimulatorRuntimeFPFPCall = double (*)(double darg0, double darg1);
2749 using SimulatorRuntimeFPCall = double (*)(double darg0);
2750 using SimulatorRuntimeFPIntCall = double (*)(double darg0, int32_t arg0);
2751
2752 // This signature supports direct call in to API function native callback
2753 // (refer to InvocationCallback in v8.h).
2754 using SimulatorRuntimeDirectApiCall = void (*)(int64_t arg0);
2755 using SimulatorRuntimeProfilingApiCall = void (*)(int64_t arg0, void* arg1);
2756
2757 // This signature supports direct call to accessor getter callback.
2758 using SimulatorRuntimeDirectGetterCall = void (*)(int64_t arg0, int64_t arg1);
2759 using SimulatorRuntimeProfilingGetterCall = void (*)(int64_t arg0, int64_t arg1,
2760 void* arg2);
2761
2762 // Software interrupt instructions are used by the simulator to call into the
2763 // C-based V8 runtime. They are also used for debugging with simulator.
SoftwareInterrupt()2764 void Simulator::SoftwareInterrupt() {
2765 // There are two instructions that could get us here, the ebreak or ecall
2766 // instructions are "SYSTEM" class opcode distinuished by Imm12Value field w/
2767 // the rest of instruction fields being zero
2768 int32_t func = instr_.Imm12Value();
2769 // We first check if we met a call_rt_redirected.
2770 if (instr_.InstructionBits() == rtCallRedirInstr) { // ECALL
2771 Redirection* redirection = Redirection::FromInstruction(instr_.instr());
2772
2773 int64_t* stack_pointer = reinterpret_cast<int64_t*>(get_register(sp));
2774
2775 const int64_t arg0 = get_register(a0);
2776 const int64_t arg1 = get_register(a1);
2777 const int64_t arg2 = get_register(a2);
2778 const int64_t arg3 = get_register(a3);
2779 const int64_t arg4 = get_register(a4);
2780 const int64_t arg5 = get_register(a5);
2781 const int64_t arg6 = get_register(a6);
2782 const int64_t arg7 = get_register(a7);
2783 const int64_t arg8 = stack_pointer[0];
2784 const int64_t arg9 = stack_pointer[1];
2785 const int64_t arg10 = stack_pointer[2];
2786 const int64_t arg11 = stack_pointer[3];
2787 const int64_t arg12 = stack_pointer[4];
2788 const int64_t arg13 = stack_pointer[5];
2789 const int64_t arg14 = stack_pointer[6];
2790 const int64_t arg15 = stack_pointer[7];
2791 const int64_t arg16 = stack_pointer[8];
2792 const int64_t arg17 = stack_pointer[9];
2793 const int64_t arg18 = stack_pointer[10];
2794 const int64_t arg19 = stack_pointer[11];
2795 STATIC_ASSERT(kMaxCParameters == 20);
2796
2797 bool fp_call =
2798 (redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) ||
2799 (redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) ||
2800 (redirection->type() == ExternalReference::BUILTIN_FP_CALL) ||
2801 (redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL);
2802
2803 // This is dodgy but it works because the C entry stubs are never moved.
2804 // See comment in codegen-arm.cc and bug 1242173.
2805 int64_t saved_ra = get_register(ra);
2806
2807 int64_t pc = get_pc();
2808
2809 intptr_t external =
2810 reinterpret_cast<intptr_t>(redirection->external_function());
2811
2812 if (fp_call) {
2813 double dval0, dval1; // one or two double parameters
2814 int32_t ival; // zero or one integer parameters
2815 int64_t iresult = 0; // integer return value
2816 double dresult = 0; // double return value
2817 GetFpArgs(&dval0, &dval1, &ival);
2818 SimulatorRuntimeCall generic_target =
2819 reinterpret_cast<SimulatorRuntimeCall>(external);
2820 if (::v8::internal::FLAG_trace_sim) {
2821 switch (redirection->type()) {
2822 case ExternalReference::BUILTIN_FP_FP_CALL:
2823 case ExternalReference::BUILTIN_COMPARE_CALL:
2824 PrintF("Call to host function %s at %p with args %f, %f",
2825 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2826 reinterpret_cast<void*>(FUNCTION_ADDR(generic_target)),
2827 dval0, dval1);
2828 break;
2829 case ExternalReference::BUILTIN_FP_CALL:
2830 PrintF("Call to host function %s at %p with arg %f",
2831 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2832 reinterpret_cast<void*>(FUNCTION_ADDR(generic_target)),
2833 dval0);
2834 break;
2835 case ExternalReference::BUILTIN_FP_INT_CALL:
2836 PrintF("Call to host function %s at %p with args %f, %d",
2837 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2838 reinterpret_cast<void*>(FUNCTION_ADDR(generic_target)),
2839 dval0, ival);
2840 break;
2841 default:
2842 UNREACHABLE();
2843 }
2844 }
2845 switch (redirection->type()) {
2846 case ExternalReference::BUILTIN_COMPARE_CALL: {
2847 SimulatorRuntimeCompareCall target =
2848 reinterpret_cast<SimulatorRuntimeCompareCall>(external);
2849 iresult = target(dval0, dval1);
2850 set_register(a0, static_cast<int64_t>(iresult));
2851 // set_register(a1, static_cast<int64_t>(iresult >> 32));
2852 break;
2853 }
2854 case ExternalReference::BUILTIN_FP_FP_CALL: {
2855 SimulatorRuntimeFPFPCall target =
2856 reinterpret_cast<SimulatorRuntimeFPFPCall>(external);
2857 dresult = target(dval0, dval1);
2858 SetFpResult(dresult);
2859 break;
2860 }
2861 case ExternalReference::BUILTIN_FP_CALL: {
2862 SimulatorRuntimeFPCall target =
2863 reinterpret_cast<SimulatorRuntimeFPCall>(external);
2864 dresult = target(dval0);
2865 SetFpResult(dresult);
2866 break;
2867 }
2868 case ExternalReference::BUILTIN_FP_INT_CALL: {
2869 SimulatorRuntimeFPIntCall target =
2870 reinterpret_cast<SimulatorRuntimeFPIntCall>(external);
2871 dresult = target(dval0, ival);
2872 SetFpResult(dresult);
2873 break;
2874 }
2875 default:
2876 UNREACHABLE();
2877 }
2878 if (::v8::internal::FLAG_trace_sim) {
2879 switch (redirection->type()) {
2880 case ExternalReference::BUILTIN_COMPARE_CALL:
2881 PrintF("Returned %08x\n", static_cast<int32_t>(iresult));
2882 break;
2883 case ExternalReference::BUILTIN_FP_FP_CALL:
2884 case ExternalReference::BUILTIN_FP_CALL:
2885 case ExternalReference::BUILTIN_FP_INT_CALL:
2886 PrintF("Returned %f\n", dresult);
2887 break;
2888 default:
2889 UNREACHABLE();
2890 }
2891 }
2892 } else if (redirection->type() == ExternalReference::DIRECT_API_CALL) {
2893 if (::v8::internal::FLAG_trace_sim) {
2894 PrintF("Call to host function %s at %p args %08" PRIx64 " \n",
2895 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2896 reinterpret_cast<void*>(external), arg0);
2897 }
2898 SimulatorRuntimeDirectApiCall target =
2899 reinterpret_cast<SimulatorRuntimeDirectApiCall>(external);
2900 target(arg0);
2901 } else if (redirection->type() == ExternalReference::PROFILING_API_CALL) {
2902 if (::v8::internal::FLAG_trace_sim) {
2903 PrintF("Call to host function %s at %p args %08" PRIx64 " %08" PRIx64
2904 " \n",
2905 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2906 reinterpret_cast<void*>(external), arg0, arg1);
2907 }
2908 SimulatorRuntimeProfilingApiCall target =
2909 reinterpret_cast<SimulatorRuntimeProfilingApiCall>(external);
2910 target(arg0, Redirection::ReverseRedirection(arg1));
2911 } else if (redirection->type() == ExternalReference::DIRECT_GETTER_CALL) {
2912 if (::v8::internal::FLAG_trace_sim) {
2913 PrintF("Call to host function %s at %p args %08" PRIx64 " %08" PRIx64
2914 " \n",
2915 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2916 reinterpret_cast<void*>(external), arg0, arg1);
2917 }
2918 SimulatorRuntimeDirectGetterCall target =
2919 reinterpret_cast<SimulatorRuntimeDirectGetterCall>(external);
2920 target(arg0, arg1);
2921 } else if (redirection->type() ==
2922 ExternalReference::PROFILING_GETTER_CALL) {
2923 if (::v8::internal::FLAG_trace_sim) {
2924 PrintF("Call to host function %s at %p args %08" PRIx64 " %08" PRIx64
2925 " %08" PRIx64 " \n",
2926 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2927 reinterpret_cast<void*>(external), arg0, arg1, arg2);
2928 }
2929 SimulatorRuntimeProfilingGetterCall target =
2930 reinterpret_cast<SimulatorRuntimeProfilingGetterCall>(external);
2931 target(arg0, arg1, Redirection::ReverseRedirection(arg2));
2932 } else {
2933 DCHECK(
2934 redirection->type() == ExternalReference::BUILTIN_CALL ||
2935 redirection->type() == ExternalReference::BUILTIN_CALL_PAIR ||
2936 // FAST_C_CALL is temporarily handled here as well, because we lack
2937 // proper support for direct C calls with FP params in the simulator.
2938 // The generic BUILTIN_CALL path assumes all parameters are passed in
2939 // the GP registers, thus supporting calling the slow callback without
2940 // crashing. The reason for that is that in the mjsunit tests we check
2941 // the `fast_c_api.supports_fp_params` (which is false on
2942 // non-simulator builds for arm/arm64), thus we expect that the slow
2943 // path will be called. And since the slow path passes the arguments
2944 // as a `const FunctionCallbackInfo<Value>&` (which is a GP argument),
2945 // the call is made correctly.
2946 redirection->type() == ExternalReference::FAST_C_CALL);
2947 SimulatorRuntimeCall target =
2948 reinterpret_cast<SimulatorRuntimeCall>(external);
2949 if (::v8::internal::FLAG_trace_sim) {
2950 PrintF(
2951 "Call to host function %s at %p "
2952 "args %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64
2953 " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64
2954 " , %08" PRIx64 " , %08" PRIx64 " , %016" PRIx64 " , %016" PRIx64
2955 " , %016" PRIx64 " , %016" PRIx64 " , %016" PRIx64 " , %016" PRIx64
2956 " , %016" PRIx64 " , %016" PRIx64 " , %016" PRIx64 " , %016" PRIx64
2957 " \n",
2958 ExternalReferenceTable::NameOfIsolateIndependentAddress(pc),
2959 reinterpret_cast<void*>(FUNCTION_ADDR(target)), arg0, arg1, arg2,
2960 arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12,
2961 arg13, arg14, arg15, arg16, arg17, arg18, arg19);
2962 }
2963 ObjectPair result = target(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7,
2964 arg8, arg9, arg10, arg11, arg12, arg13, arg14,
2965 arg15, arg16, arg17, arg18, arg19);
2966 set_register(a0, (int64_t)(result.x));
2967 set_register(a1, (int64_t)(result.y));
2968 }
2969 if (::v8::internal::FLAG_trace_sim) {
2970 PrintF("Returned %08" PRIx64 " : %08" PRIx64 " \n", get_register(a1),
2971 get_register(a0));
2972 }
2973 set_register(ra, saved_ra);
2974 set_pc(get_register(ra));
2975
2976 } else if (func == 1) { // EBREAK
2977 int32_t code = get_ebreak_code(instr_.instr());
2978 set_pc(get_pc() + kInstrSize * 2);
2979 if (code != -1 && static_cast<uint32_t>(code) <= kMaxStopCode) {
2980 if (IsWatchpoint(code)) {
2981 PrintWatchpoint(code);
2982 } else {
2983 IncreaseStopCounter(code);
2984 HandleStop(code);
2985 }
2986 } else {
2987 // All remaining break_ codes, and all traps are handled here.
2988 RiscvDebugger dbg(this);
2989 dbg.Debug();
2990 }
2991 } else {
2992 UNREACHABLE();
2993 }
2994 }
2995
2996 // Stop helper functions.
IsWatchpoint(uint64_t code)2997 bool Simulator::IsWatchpoint(uint64_t code) {
2998 return (code <= kMaxWatchpointCode);
2999 }
3000
PrintWatchpoint(uint64_t code)3001 void Simulator::PrintWatchpoint(uint64_t code) {
3002 RiscvDebugger dbg(this);
3003 ++break_count_;
3004 PrintF("\n---- watchpoint %" PRId64 " marker: %3d (instr count: %8" PRId64
3005 " ) ----------"
3006 "----------------------------------",
3007 code, break_count_, icount_);
3008 dbg.PrintAllRegs(); // Print registers and continue running.
3009 }
3010
HandleStop(uint64_t code)3011 void Simulator::HandleStop(uint64_t code) {
3012 // Stop if it is enabled, otherwise go on jumping over the stop
3013 // and the message address.
3014 if (IsEnabledStop(code)) {
3015 RiscvDebugger dbg(this);
3016 PrintF("Simulator hit stop (%" PRId64 ")\n", code);
3017 dbg.Debug();
3018 }
3019 }
3020
IsStopInstruction(Instruction * instr)3021 bool Simulator::IsStopInstruction(Instruction* instr) {
3022 if (instr->InstructionBits() != kBreakInstr) return false;
3023 int32_t code = get_ebreak_code(instr);
3024 return code != -1 && static_cast<uint32_t>(code) > kMaxWatchpointCode &&
3025 static_cast<uint32_t>(code) <= kMaxStopCode;
3026 }
3027
IsEnabledStop(uint64_t code)3028 bool Simulator::IsEnabledStop(uint64_t code) {
3029 DCHECK_LE(code, kMaxStopCode);
3030 DCHECK_GT(code, kMaxWatchpointCode);
3031 return !(watched_stops_[code].count & kStopDisabledBit);
3032 }
3033
EnableStop(uint64_t code)3034 void Simulator::EnableStop(uint64_t code) {
3035 if (!IsEnabledStop(code)) {
3036 watched_stops_[code].count &= ~kStopDisabledBit;
3037 }
3038 }
3039
DisableStop(uint64_t code)3040 void Simulator::DisableStop(uint64_t code) {
3041 if (IsEnabledStop(code)) {
3042 watched_stops_[code].count |= kStopDisabledBit;
3043 }
3044 }
3045
IncreaseStopCounter(uint64_t code)3046 void Simulator::IncreaseStopCounter(uint64_t code) {
3047 DCHECK_LE(code, kMaxStopCode);
3048 if ((watched_stops_[code].count & ~(1 << 31)) == 0x7FFFFFFF) {
3049 PrintF("Stop counter for code %" PRId64
3050 " has overflowed.\n"
3051 "Enabling this code and reseting the counter to 0.\n",
3052 code);
3053 watched_stops_[code].count = 0;
3054 EnableStop(code);
3055 } else {
3056 watched_stops_[code].count++;
3057 }
3058 }
3059
3060 // Print a stop status.
PrintStopInfo(uint64_t code)3061 void Simulator::PrintStopInfo(uint64_t code) {
3062 if (code <= kMaxWatchpointCode) {
3063 PrintF("That is a watchpoint, not a stop.\n");
3064 return;
3065 } else if (code > kMaxStopCode) {
3066 PrintF("Code too large, only %u stops can be used\n", kMaxStopCode + 1);
3067 return;
3068 }
3069 const char* state = IsEnabledStop(code) ? "Enabled" : "Disabled";
3070 int32_t count = watched_stops_[code].count & ~kStopDisabledBit;
3071 // Don't print the state of unused breakpoints.
3072 if (count != 0) {
3073 if (watched_stops_[code].desc) {
3074 PrintF("stop %" PRId64 " - 0x%" PRIx64 " : \t%s, \tcounter = %i, \t%s\n",
3075 code, code, state, count, watched_stops_[code].desc);
3076 } else {
3077 PrintF("stop %" PRId64 " - 0x%" PRIx64 " : \t%s, \tcounter = %i\n", code,
3078 code, state, count);
3079 }
3080 }
3081 }
3082
SignalException(Exception e)3083 void Simulator::SignalException(Exception e) {
3084 FATAL("Error: Exception %i raised.", static_cast<int>(e));
3085 }
3086
3087 // RISCV Instruction Decode Routine
DecodeRVRType()3088 void Simulator::DecodeRVRType() {
3089 switch (instr_.InstructionBits() & kRTypeMask) {
3090 case RO_ADD: {
3091 set_rd(sext_xlen(rs1() + rs2()));
3092 break;
3093 }
3094 case RO_SUB: {
3095 set_rd(sext_xlen(rs1() - rs2()));
3096 break;
3097 }
3098 case RO_SLL: {
3099 set_rd(sext_xlen(rs1() << (rs2() & (xlen - 1))));
3100 break;
3101 }
3102 case RO_SLT: {
3103 set_rd(sreg_t(rs1()) < sreg_t(rs2()));
3104 break;
3105 }
3106 case RO_SLTU: {
3107 set_rd(reg_t(rs1()) < reg_t(rs2()));
3108 break;
3109 }
3110 case RO_XOR: {
3111 set_rd(rs1() ^ rs2());
3112 break;
3113 }
3114 case RO_SRL: {
3115 set_rd(sext_xlen(zext_xlen(rs1()) >> (rs2() & (xlen - 1))));
3116 break;
3117 }
3118 case RO_SRA: {
3119 set_rd(sext_xlen(sext_xlen(rs1()) >> (rs2() & (xlen - 1))));
3120 break;
3121 }
3122 case RO_OR: {
3123 set_rd(rs1() | rs2());
3124 break;
3125 }
3126 case RO_AND: {
3127 set_rd(rs1() & rs2());
3128 break;
3129 }
3130 #ifdef V8_TARGET_ARCH_64_BIT
3131 case RO_ADDW: {
3132 set_rd(sext32(rs1() + rs2()));
3133 break;
3134 }
3135 case RO_SUBW: {
3136 set_rd(sext32(rs1() - rs2()));
3137 break;
3138 }
3139 case RO_SLLW: {
3140 set_rd(sext32(rs1() << (rs2() & 0x1F)));
3141 break;
3142 }
3143 case RO_SRLW: {
3144 set_rd(sext32(uint32_t(rs1()) >> (rs2() & 0x1F)));
3145 break;
3146 }
3147 case RO_SRAW: {
3148 set_rd(sext32(int32_t(rs1()) >> (rs2() & 0x1F)));
3149 break;
3150 }
3151 #endif /* V8_TARGET_ARCH_64_BIT */
3152 // TODO(riscv): Add RISCV M extension macro
3153 case RO_MUL: {
3154 set_rd(rs1() * rs2());
3155 break;
3156 }
3157 case RO_MULH: {
3158 set_rd(mulh(rs1(), rs2()));
3159 break;
3160 }
3161 case RO_MULHSU: {
3162 set_rd(mulhsu(rs1(), rs2()));
3163 break;
3164 }
3165 case RO_MULHU: {
3166 set_rd(mulhu(rs1(), rs2()));
3167 break;
3168 }
3169 case RO_DIV: {
3170 sreg_t lhs = sext_xlen(rs1());
3171 sreg_t rhs = sext_xlen(rs2());
3172 if (rhs == 0) {
3173 set_rd(-1);
3174 } else if (lhs == INT64_MIN && rhs == -1) {
3175 set_rd(lhs);
3176 } else {
3177 set_rd(sext_xlen(lhs / rhs));
3178 }
3179 break;
3180 }
3181 case RO_DIVU: {
3182 reg_t lhs = zext_xlen(rs1());
3183 reg_t rhs = zext_xlen(rs2());
3184 if (rhs == 0) {
3185 set_rd(UINT64_MAX);
3186 } else {
3187 set_rd(zext_xlen(lhs / rhs));
3188 }
3189 break;
3190 }
3191 case RO_REM: {
3192 sreg_t lhs = sext_xlen(rs1());
3193 sreg_t rhs = sext_xlen(rs2());
3194 if (rhs == 0) {
3195 set_rd(lhs);
3196 } else if (lhs == INT64_MIN && rhs == -1) {
3197 set_rd(0);
3198 } else {
3199 set_rd(sext_xlen(lhs % rhs));
3200 }
3201 break;
3202 }
3203 case RO_REMU: {
3204 reg_t lhs = zext_xlen(rs1());
3205 reg_t rhs = zext_xlen(rs2());
3206 if (rhs == 0) {
3207 set_rd(lhs);
3208 } else {
3209 set_rd(zext_xlen(lhs % rhs));
3210 }
3211 break;
3212 }
3213 #ifdef V8_TARGET_ARCH_64_BIT
3214 case RO_MULW: {
3215 set_rd(sext32(sext32(rs1()) * sext32(rs2())));
3216 break;
3217 }
3218 case RO_DIVW: {
3219 sreg_t lhs = sext32(rs1());
3220 sreg_t rhs = sext32(rs2());
3221 if (rhs == 0) {
3222 set_rd(-1);
3223 } else if (lhs == INT32_MIN && rhs == -1) {
3224 set_rd(lhs);
3225 } else {
3226 set_rd(sext32(lhs / rhs));
3227 }
3228 break;
3229 }
3230 case RO_DIVUW: {
3231 reg_t lhs = zext32(rs1());
3232 reg_t rhs = zext32(rs2());
3233 if (rhs == 0) {
3234 set_rd(UINT32_MAX);
3235 } else {
3236 set_rd(zext32(lhs / rhs));
3237 }
3238 break;
3239 }
3240 case RO_REMW: {
3241 sreg_t lhs = sext32(rs1());
3242 sreg_t rhs = sext32(rs2());
3243 if (rhs == 0) {
3244 set_rd(lhs);
3245 } else if (lhs == INT32_MIN && rhs == -1) {
3246 set_rd(0);
3247 } else {
3248 set_rd(sext32(lhs % rhs));
3249 }
3250 break;
3251 }
3252 case RO_REMUW: {
3253 reg_t lhs = zext32(rs1());
3254 reg_t rhs = zext32(rs2());
3255 if (rhs == 0) {
3256 set_rd(zext32(lhs));
3257 } else {
3258 set_rd(zext32(lhs % rhs));
3259 }
3260 break;
3261 }
3262 #endif /*V8_TARGET_ARCH_64_BIT*/
3263 // TODO(riscv): End Add RISCV M extension macro
3264 default: {
3265 switch (instr_.BaseOpcode()) {
3266 case AMO:
3267 DecodeRVRAType();
3268 break;
3269 case OP_FP:
3270 DecodeRVRFPType();
3271 break;
3272 default:
3273 UNSUPPORTED();
3274 }
3275 }
3276 }
3277 }
3278
RoundF2FHelper(float input_val,int rmode)3279 float Simulator::RoundF2FHelper(float input_val, int rmode) {
3280 if (rmode == DYN) rmode = get_dynamic_rounding_mode();
3281
3282 float rounded = 0;
3283 switch (rmode) {
3284 case RNE: { // Round to Nearest, tiest to Even
3285 rounded = floorf(input_val);
3286 float error = input_val - rounded;
3287
3288 // Take care of correctly handling the range [-0.5, -0.0], which must
3289 // yield -0.0.
3290 if ((-0.5 <= input_val) && (input_val < 0.0)) {
3291 rounded = -0.0;
3292
3293 // If the error is greater than 0.5, or is equal to 0.5 and the integer
3294 // result is odd, round up.
3295 } else if ((error > 0.5) ||
3296 ((error == 0.5) && (std::fmod(rounded, 2) != 0))) {
3297 rounded++;
3298 }
3299 break;
3300 }
3301 case RTZ: // Round towards Zero
3302 rounded = std::truncf(input_val);
3303 break;
3304 case RDN: // Round Down (towards -infinity)
3305 rounded = floorf(input_val);
3306 break;
3307 case RUP: // Round Up (towards +infinity)
3308 rounded = ceilf(input_val);
3309 break;
3310 case RMM: // Round to Nearest, tiest to Max Magnitude
3311 rounded = std::roundf(input_val);
3312 break;
3313 default:
3314 UNREACHABLE();
3315 }
3316
3317 return rounded;
3318 }
3319
RoundF2FHelper(double input_val,int rmode)3320 double Simulator::RoundF2FHelper(double input_val, int rmode) {
3321 if (rmode == DYN) rmode = get_dynamic_rounding_mode();
3322
3323 double rounded = 0;
3324 switch (rmode) {
3325 case RNE: { // Round to Nearest, tiest to Even
3326 rounded = std::floor(input_val);
3327 double error = input_val - rounded;
3328
3329 // Take care of correctly handling the range [-0.5, -0.0], which must
3330 // yield -0.0.
3331 if ((-0.5 <= input_val) && (input_val < 0.0)) {
3332 rounded = -0.0;
3333
3334 // If the error is greater than 0.5, or is equal to 0.5 and the integer
3335 // result is odd, round up.
3336 } else if ((error > 0.5) ||
3337 ((error == 0.5) && (std::fmod(rounded, 2) != 0))) {
3338 rounded++;
3339 }
3340 break;
3341 }
3342 case RTZ: // Round towards Zero
3343 rounded = std::trunc(input_val);
3344 break;
3345 case RDN: // Round Down (towards -infinity)
3346 rounded = std::floor(input_val);
3347 break;
3348 case RUP: // Round Up (towards +infinity)
3349 rounded = std::ceil(input_val);
3350 break;
3351 case RMM: // Round to Nearest, tiest to Max Magnitude
3352 rounded = std::round(input_val);
3353 break;
3354 default:
3355 UNREACHABLE();
3356 }
3357 return rounded;
3358 }
3359
3360 // convert rounded floating-point to integer types, handle input values that
3361 // are out-of-range, underflow, or NaN, and set appropriate fflags
3362 template <typename I_TYPE, typename F_TYPE>
RoundF2IHelper(F_TYPE original,int rmode)3363 I_TYPE Simulator::RoundF2IHelper(F_TYPE original, int rmode) {
3364 DCHECK(std::is_integral<I_TYPE>::value);
3365
3366 DCHECK((std::is_same<F_TYPE, float>::value ||
3367 std::is_same<F_TYPE, double>::value));
3368
3369 I_TYPE max_i = std::numeric_limits<I_TYPE>::max();
3370 I_TYPE min_i = std::numeric_limits<I_TYPE>::min();
3371
3372 if (!std::isfinite(original)) {
3373 set_fflags(kInvalidOperation);
3374 if (std::isnan(original) ||
3375 original == std::numeric_limits<F_TYPE>::infinity()) {
3376 return max_i;
3377 } else {
3378 DCHECK(original == -std::numeric_limits<F_TYPE>::infinity());
3379 return min_i;
3380 }
3381 }
3382
3383 F_TYPE rounded = RoundF2FHelper(original, rmode);
3384 if (original != rounded) set_fflags(kInexact);
3385
3386 if (!std::isfinite(rounded)) {
3387 set_fflags(kInvalidOperation);
3388 if (std::isnan(rounded) ||
3389 rounded == std::numeric_limits<F_TYPE>::infinity()) {
3390 return max_i;
3391 } else {
3392 DCHECK(rounded == -std::numeric_limits<F_TYPE>::infinity());
3393 return min_i;
3394 }
3395 }
3396
3397 // Since integer max values are either all 1s (for unsigned) or all 1s
3398 // except for sign-bit (for signed), they cannot be represented precisely in
3399 // floating point, in order to precisely tell whether the rounded floating
3400 // point is within the max range, we compare against (max_i+1) which would
3401 // have a single 1 w/ many trailing zeros
3402 float max_i_plus_1 =
3403 std::is_same<uint64_t, I_TYPE>::value
3404 ? 0x1p64f // uint64_t::max + 1 cannot be represented in integers,
3405 // so use its float representation directly
3406 : static_cast<float>(static_cast<uint64_t>(max_i) + 1);
3407 if (rounded >= max_i_plus_1) {
3408 set_fflags(kOverflow | kInvalidOperation);
3409 return max_i;
3410 }
3411
3412 // Since min_i (either 0 for unsigned, or for signed) is represented
3413 // precisely in floating-point, comparing rounded directly against min_i
3414 if (rounded <= min_i) {
3415 if (rounded < min_i) set_fflags(kOverflow | kInvalidOperation);
3416 return min_i;
3417 }
3418
3419 F_TYPE underflow_fval =
3420 std::is_same<F_TYPE, float>::value ? FLT_MIN : DBL_MIN;
3421 if (rounded < underflow_fval && rounded > -underflow_fval && rounded != 0) {
3422 set_fflags(kUnderflow);
3423 }
3424
3425 return static_cast<I_TYPE>(rounded);
3426 }
3427
3428 template <typename T>
FclassHelper(T value)3429 static int64_t FclassHelper(T value) {
3430 switch (std::fpclassify(value)) {
3431 case FP_INFINITE:
3432 return (std::signbit(value) ? kNegativeInfinity : kPositiveInfinity);
3433 case FP_NAN:
3434 return (isSnan(value) ? kSignalingNaN : kQuietNaN);
3435 case FP_NORMAL:
3436 return (std::signbit(value) ? kNegativeNormalNumber
3437 : kPositiveNormalNumber);
3438 case FP_SUBNORMAL:
3439 return (std::signbit(value) ? kNegativeSubnormalNumber
3440 : kPositiveSubnormalNumber);
3441 case FP_ZERO:
3442 return (std::signbit(value) ? kNegativeZero : kPositiveZero);
3443 default:
3444 UNREACHABLE();
3445 }
3446 }
3447
3448 template <typename T>
CompareFHelper(T input1,T input2,FPUCondition cc)3449 bool Simulator::CompareFHelper(T input1, T input2, FPUCondition cc) {
3450 DCHECK(std::is_floating_point<T>::value);
3451 bool result = false;
3452 switch (cc) {
3453 case LT:
3454 case LE:
3455 // FLT, FLE are signaling compares
3456 if (std::isnan(input1) || std::isnan(input2)) {
3457 set_fflags(kInvalidOperation);
3458 result = false;
3459 } else {
3460 result = (cc == LT) ? (input1 < input2) : (input1 <= input2);
3461 }
3462 break;
3463
3464 case EQ:
3465 if (std::numeric_limits<T>::signaling_NaN() == input1 ||
3466 std::numeric_limits<T>::signaling_NaN() == input2) {
3467 set_fflags(kInvalidOperation);
3468 }
3469 if (std::isnan(input1) || std::isnan(input2)) {
3470 result = false;
3471 } else {
3472 result = (input1 == input2);
3473 }
3474 break;
3475 case NE:
3476 if (std::numeric_limits<T>::signaling_NaN() == input1 ||
3477 std::numeric_limits<T>::signaling_NaN() == input2) {
3478 set_fflags(kInvalidOperation);
3479 }
3480 if (std::isnan(input1) || std::isnan(input2)) {
3481 result = true;
3482 } else {
3483 result = (input1 != input2);
3484 }
3485 break;
3486 default:
3487 UNREACHABLE();
3488 }
3489 return result;
3490 }
3491
3492 template <typename T>
is_invalid_fmul(T src1,T src2)3493 static inline bool is_invalid_fmul(T src1, T src2) {
3494 return (isinf(src1) && src2 == static_cast<T>(0.0)) ||
3495 (src1 == static_cast<T>(0.0) && isinf(src2));
3496 }
3497
3498 template <typename T>
is_invalid_fadd(T src1,T src2)3499 static inline bool is_invalid_fadd(T src1, T src2) {
3500 return (isinf(src1) && isinf(src2) &&
3501 std::signbit(src1) != std::signbit(src2));
3502 }
3503
3504 template <typename T>
is_invalid_fsub(T src1,T src2)3505 static inline bool is_invalid_fsub(T src1, T src2) {
3506 return (isinf(src1) && isinf(src2) &&
3507 std::signbit(src1) == std::signbit(src2));
3508 }
3509
3510 template <typename T>
is_invalid_fdiv(T src1,T src2)3511 static inline bool is_invalid_fdiv(T src1, T src2) {
3512 return ((src1 == 0 && src2 == 0) || (isinf(src1) && isinf(src2)));
3513 }
3514
3515 template <typename T>
is_invalid_fsqrt(T src1)3516 static inline bool is_invalid_fsqrt(T src1) {
3517 return (src1 < 0);
3518 }
3519
DecodeRVRAType()3520 void Simulator::DecodeRVRAType() {
3521 // TODO(riscv): Add macro for RISCV A extension
3522 // Special handling for A extension instructions because it uses func5
3523 // For all A extension instruction, V8 simulator is pure sequential. No
3524 // Memory address lock or other synchronizaiton behaviors.
3525 switch (instr_.InstructionBits() & kRATypeMask) {
3526 case RO_LR_W: {
3527 base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex);
3528 int64_t addr = rs1();
3529 auto val = ReadMem<int32_t>(addr, instr_.instr());
3530 set_rd(sext32(val), false);
3531 TraceMemRd(addr, val, get_register(rd_reg()));
3532 local_monitor_.NotifyLoadLinked(addr, TransactionSize::Word);
3533 GlobalMonitor::Get()->NotifyLoadLinked_Locked(addr,
3534 &global_monitor_thread_);
3535 break;
3536 }
3537 case RO_SC_W: {
3538 int64_t addr = rs1();
3539 base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex);
3540 if (local_monitor_.NotifyStoreConditional(addr, TransactionSize::Word) &&
3541 GlobalMonitor::Get()->NotifyStoreConditional_Locked(
3542 addr, &global_monitor_thread_)) {
3543 local_monitor_.NotifyStore();
3544 GlobalMonitor::Get()->NotifyStore_Locked(&global_monitor_thread_);
3545 WriteMem<int32_t>(rs1(), (int32_t)rs2(), instr_.instr());
3546 set_rd(0, false);
3547 } else {
3548 set_rd(1, false);
3549 }
3550 break;
3551 }
3552 case RO_AMOSWAP_W: {
3553 set_rd(sext32(amo<uint32_t>(
3554 rs1(), [&](uint32_t lhs) { return (uint32_t)rs2(); }, instr_.instr(),
3555 WORD)));
3556 break;
3557 }
3558 case RO_AMOADD_W: {
3559 set_rd(sext32(amo<uint32_t>(
3560 rs1(), [&](uint32_t lhs) { return lhs + (uint32_t)rs2(); },
3561 instr_.instr(), WORD)));
3562 break;
3563 }
3564 case RO_AMOXOR_W: {
3565 set_rd(sext32(amo<uint32_t>(
3566 rs1(), [&](uint32_t lhs) { return lhs ^ (uint32_t)rs2(); },
3567 instr_.instr(), WORD)));
3568 break;
3569 }
3570 case RO_AMOAND_W: {
3571 set_rd(sext32(amo<uint32_t>(
3572 rs1(), [&](uint32_t lhs) { return lhs & (uint32_t)rs2(); },
3573 instr_.instr(), WORD)));
3574 break;
3575 }
3576 case RO_AMOOR_W: {
3577 set_rd(sext32(amo<uint32_t>(
3578 rs1(), [&](uint32_t lhs) { return lhs | (uint32_t)rs2(); },
3579 instr_.instr(), WORD)));
3580 break;
3581 }
3582 case RO_AMOMIN_W: {
3583 set_rd(sext32(amo<int32_t>(
3584 rs1(), [&](int32_t lhs) { return std::min(lhs, (int32_t)rs2()); },
3585 instr_.instr(), WORD)));
3586 break;
3587 }
3588 case RO_AMOMAX_W: {
3589 set_rd(sext32(amo<int32_t>(
3590 rs1(), [&](int32_t lhs) { return std::max(lhs, (int32_t)rs2()); },
3591 instr_.instr(), WORD)));
3592 break;
3593 }
3594 case RO_AMOMINU_W: {
3595 set_rd(sext32(amo<uint32_t>(
3596 rs1(), [&](uint32_t lhs) { return std::min(lhs, (uint32_t)rs2()); },
3597 instr_.instr(), WORD)));
3598 break;
3599 }
3600 case RO_AMOMAXU_W: {
3601 set_rd(sext32(amo<uint32_t>(
3602 rs1(), [&](uint32_t lhs) { return std::max(lhs, (uint32_t)rs2()); },
3603 instr_.instr(), WORD)));
3604 break;
3605 }
3606 #ifdef V8_TARGET_ARCH_64_BIT
3607 case RO_LR_D: {
3608 base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex);
3609 int64_t addr = rs1();
3610 auto val = ReadMem<int64_t>(addr, instr_.instr());
3611 set_rd(val, false);
3612 TraceMemRd(addr, val, get_register(rd_reg()));
3613 local_monitor_.NotifyLoadLinked(addr, TransactionSize::DoubleWord);
3614 GlobalMonitor::Get()->NotifyLoadLinked_Locked(addr,
3615 &global_monitor_thread_);
3616 break;
3617 }
3618 case RO_SC_D: {
3619 int64_t addr = rs1();
3620 base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex);
3621 if (local_monitor_.NotifyStoreConditional(addr,
3622 TransactionSize::DoubleWord) &&
3623 (GlobalMonitor::Get()->NotifyStoreConditional_Locked(
3624 addr, &global_monitor_thread_))) {
3625 GlobalMonitor::Get()->NotifyStore_Locked(&global_monitor_thread_);
3626 WriteMem<int64_t>(rs1(), rs2(), instr_.instr());
3627 set_rd(0, false);
3628 } else {
3629 set_rd(1, false);
3630 }
3631 break;
3632 }
3633 case RO_AMOSWAP_D: {
3634 set_rd(amo<int64_t>(
3635 rs1(), [&](int64_t lhs) { return rs2(); }, instr_.instr(), DWORD));
3636 break;
3637 }
3638 case RO_AMOADD_D: {
3639 set_rd(amo<int64_t>(
3640 rs1(), [&](int64_t lhs) { return lhs + rs2(); }, instr_.instr(),
3641 DWORD));
3642 break;
3643 }
3644 case RO_AMOXOR_D: {
3645 set_rd(amo<int64_t>(
3646 rs1(), [&](int64_t lhs) { return lhs ^ rs2(); }, instr_.instr(),
3647 DWORD));
3648 break;
3649 }
3650 case RO_AMOAND_D: {
3651 set_rd(amo<int64_t>(
3652 rs1(), [&](int64_t lhs) { return lhs & rs2(); }, instr_.instr(),
3653 DWORD));
3654 break;
3655 }
3656 case RO_AMOOR_D: {
3657 set_rd(amo<int64_t>(
3658 rs1(), [&](int64_t lhs) { return lhs | rs2(); }, instr_.instr(),
3659 DWORD));
3660 break;
3661 }
3662 case RO_AMOMIN_D: {
3663 set_rd(amo<int64_t>(
3664 rs1(), [&](int64_t lhs) { return std::min(lhs, rs2()); },
3665 instr_.instr(), DWORD));
3666 break;
3667 }
3668 case RO_AMOMAX_D: {
3669 set_rd(amo<int64_t>(
3670 rs1(), [&](int64_t lhs) { return std::max(lhs, rs2()); },
3671 instr_.instr(), DWORD));
3672 break;
3673 }
3674 case RO_AMOMINU_D: {
3675 set_rd(amo<uint64_t>(
3676 rs1(), [&](uint64_t lhs) { return std::min(lhs, (uint64_t)rs2()); },
3677 instr_.instr(), DWORD));
3678 break;
3679 }
3680 case RO_AMOMAXU_D: {
3681 set_rd(amo<uint64_t>(
3682 rs1(), [&](uint64_t lhs) { return std::max(lhs, (uint64_t)rs2()); },
3683 instr_.instr(), DWORD));
3684 break;
3685 }
3686 #endif /*V8_TARGET_ARCH_64_BIT*/
3687 // TODO(riscv): End Add macro for RISCV A extension
3688 default: {
3689 UNSUPPORTED();
3690 }
3691 }
3692 }
3693
DecodeRVRFPType()3694 void Simulator::DecodeRVRFPType() {
3695 // OP_FP instructions (F/D) uses func7 first. Some further uses func3 and
3696 // rs2()
3697
3698 // kRATypeMask is only for func7
3699 switch (instr_.InstructionBits() & kRFPTypeMask) {
3700 // TODO(riscv): Add macro for RISCV F extension
3701 case RO_FADD_S: {
3702 // TODO(riscv): use rm value (round mode)
3703 auto fn = [this](float frs1, float frs2) {
3704 if (is_invalid_fadd(frs1, frs2)) {
3705 this->set_fflags(kInvalidOperation);
3706 return std::numeric_limits<float>::quiet_NaN();
3707 } else {
3708 return frs1 + frs2;
3709 }
3710 };
3711 set_frd(CanonicalizeFPUOp2<float>(fn));
3712 break;
3713 }
3714 case RO_FSUB_S: {
3715 // TODO(riscv): use rm value (round mode)
3716 auto fn = [this](float frs1, float frs2) {
3717 if (is_invalid_fsub(frs1, frs2)) {
3718 this->set_fflags(kInvalidOperation);
3719 return std::numeric_limits<float>::quiet_NaN();
3720 } else {
3721 return frs1 - frs2;
3722 }
3723 };
3724 set_frd(CanonicalizeFPUOp2<float>(fn));
3725 break;
3726 }
3727 case RO_FMUL_S: {
3728 // TODO(riscv): use rm value (round mode)
3729 auto fn = [this](float frs1, float frs2) {
3730 if (is_invalid_fmul(frs1, frs2)) {
3731 this->set_fflags(kInvalidOperation);
3732 return std::numeric_limits<float>::quiet_NaN();
3733 } else {
3734 return frs1 * frs2;
3735 }
3736 };
3737 set_frd(CanonicalizeFPUOp2<float>(fn));
3738 break;
3739 }
3740 case RO_FDIV_S: {
3741 // TODO(riscv): use rm value (round mode)
3742 auto fn = [this](float frs1, float frs2) {
3743 if (is_invalid_fdiv(frs1, frs2)) {
3744 this->set_fflags(kInvalidOperation);
3745 return std::numeric_limits<float>::quiet_NaN();
3746 } else if (frs2 == 0.0f) {
3747 this->set_fflags(kDivideByZero);
3748 return (std::signbit(frs1) == std::signbit(frs2)
3749 ? std::numeric_limits<float>::infinity()
3750 : -std::numeric_limits<float>::infinity());
3751 } else {
3752 return frs1 / frs2;
3753 }
3754 };
3755 set_frd(CanonicalizeFPUOp2<float>(fn));
3756 break;
3757 }
3758 case RO_FSQRT_S: {
3759 if (instr_.Rs2Value() == 0b00000) {
3760 // TODO(riscv): use rm value (round mode)
3761 auto fn = [this](float frs) {
3762 if (is_invalid_fsqrt(frs)) {
3763 this->set_fflags(kInvalidOperation);
3764 return std::numeric_limits<float>::quiet_NaN();
3765 } else {
3766 return std::sqrt(frs);
3767 }
3768 };
3769 set_frd(CanonicalizeFPUOp1<float>(fn));
3770 } else {
3771 UNSUPPORTED();
3772 }
3773 break;
3774 }
3775 case RO_FSGNJ_S: { // RO_FSGNJN_S RO_FSQNJX_S
3776 switch (instr_.Funct3Value()) {
3777 case 0b000: { // RO_FSGNJ_S
3778 set_frd(fsgnj32(frs1(), frs2(), false, false));
3779 break;
3780 }
3781 case 0b001: { // RO_FSGNJN_S
3782 set_frd(fsgnj32(frs1(), frs2(), true, false));
3783 break;
3784 }
3785 case 0b010: { // RO_FSQNJX_S
3786 set_frd(fsgnj32(frs1(), frs2(), false, true));
3787 break;
3788 }
3789 default: {
3790 UNSUPPORTED();
3791 }
3792 }
3793 break;
3794 }
3795 case RO_FMIN_S: { // RO_FMAX_S
3796 switch (instr_.Funct3Value()) {
3797 case 0b000: { // RO_FMIN_S
3798 set_frd(FMaxMinHelper(frs1(), frs2(), MaxMinKind::kMin));
3799 break;
3800 }
3801 case 0b001: { // RO_FMAX_S
3802 set_frd(FMaxMinHelper(frs1(), frs2(), MaxMinKind::kMax));
3803 break;
3804 }
3805 default: {
3806 UNSUPPORTED();
3807 }
3808 }
3809 break;
3810 }
3811 case RO_FCVT_W_S: { // RO_FCVT_WU_S , 64F RO_FCVT_L_S RO_FCVT_LU_S
3812 float original_val = frs1();
3813 switch (instr_.Rs2Value()) {
3814 case 0b00000: { // RO_FCVT_W_S
3815 set_rd(RoundF2IHelper<int32_t>(original_val, instr_.RoundMode()));
3816 break;
3817 }
3818 case 0b00001: { // RO_FCVT_WU_S
3819 set_rd(sext32(
3820 RoundF2IHelper<uint32_t>(original_val, instr_.RoundMode())));
3821 break;
3822 }
3823 #ifdef V8_TARGET_ARCH_64_BIT
3824 case 0b00010: { // RO_FCVT_L_S
3825 set_rd(RoundF2IHelper<int64_t>(original_val, instr_.RoundMode()));
3826 break;
3827 }
3828 case 0b00011: { // RO_FCVT_LU_S
3829 set_rd(RoundF2IHelper<uint64_t>(original_val, instr_.RoundMode()));
3830 break;
3831 }
3832 #endif /* V8_TARGET_ARCH_64_BIT */
3833 default: {
3834 UNSUPPORTED();
3835 }
3836 }
3837 break;
3838 }
3839 case RO_FMV: { // RO_FCLASS_S
3840 switch (instr_.Funct3Value()) {
3841 case 0b000: {
3842 if (instr_.Rs2Value() == 0b00000) {
3843 // RO_FMV_X_W
3844 set_rd(sext_xlen(get_fpu_register_word(rs1_reg())));
3845 } else {
3846 UNSUPPORTED();
3847 }
3848 break;
3849 }
3850 case 0b001: { // RO_FCLASS_S
3851 set_rd(FclassHelper(frs1()));
3852 break;
3853 }
3854 default: {
3855 UNSUPPORTED();
3856 }
3857 }
3858 break;
3859 }
3860 case RO_FLE_S: { // RO_FEQ_S RO_FLT_S RO_FLE_S
3861 switch (instr_.Funct3Value()) {
3862 case 0b010: { // RO_FEQ_S
3863 set_rd(CompareFHelper(frs1(), frs2(), EQ));
3864 break;
3865 }
3866 case 0b001: { // RO_FLT_S
3867 set_rd(CompareFHelper(frs1(), frs2(), LT));
3868 break;
3869 }
3870 case 0b000: { // RO_FLE_S
3871 set_rd(CompareFHelper(frs1(), frs2(), LE));
3872 break;
3873 }
3874 default: {
3875 UNSUPPORTED();
3876 }
3877 }
3878 break;
3879 }
3880 case RO_FCVT_S_W: { // RO_FCVT_S_WU , 64F RO_FCVT_S_L RO_FCVT_S_LU
3881 switch (instr_.Rs2Value()) {
3882 case 0b00000: { // RO_FCVT_S_W
3883 set_frd(static_cast<float>((int32_t)rs1()));
3884 break;
3885 }
3886 case 0b00001: { // RO_FCVT_S_WU
3887 set_frd(static_cast<float>((uint32_t)rs1()));
3888 break;
3889 }
3890 #ifdef V8_TARGET_ARCH_64_BIT
3891 case 0b00010: { // RO_FCVT_S_L
3892 set_frd(static_cast<float>((int64_t)rs1()));
3893 break;
3894 }
3895 case 0b00011: { // RO_FCVT_S_LU
3896 set_frd(static_cast<float>((uint64_t)rs1()));
3897 break;
3898 }
3899 #endif /* V8_TARGET_ARCH_64_BIT */
3900 default: {
3901 UNSUPPORTED();
3902 }
3903 }
3904 break;
3905 }
3906 case RO_FMV_W_X: {
3907 if (instr_.Funct3Value() == 0b000) {
3908 // since FMV preserves source bit-pattern, no need to canonize
3909 set_frd(bit_cast<float>((uint32_t)rs1()));
3910 } else {
3911 UNSUPPORTED();
3912 }
3913 break;
3914 }
3915 // TODO(riscv): Add macro for RISCV D extension
3916 case RO_FADD_D: {
3917 // TODO(riscv): use rm value (round mode)
3918 auto fn = [this](double drs1, double drs2) {
3919 if (is_invalid_fadd(drs1, drs2)) {
3920 this->set_fflags(kInvalidOperation);
3921 return std::numeric_limits<double>::quiet_NaN();
3922 } else {
3923 return drs1 + drs2;
3924 }
3925 };
3926 set_drd(CanonicalizeFPUOp2<double>(fn));
3927 break;
3928 }
3929 case RO_FSUB_D: {
3930 // TODO(riscv): use rm value (round mode)
3931 auto fn = [this](double drs1, double drs2) {
3932 if (is_invalid_fsub(drs1, drs2)) {
3933 this->set_fflags(kInvalidOperation);
3934 return std::numeric_limits<double>::quiet_NaN();
3935 } else {
3936 return drs1 - drs2;
3937 }
3938 };
3939 set_drd(CanonicalizeFPUOp2<double>(fn));
3940 break;
3941 }
3942 case RO_FMUL_D: {
3943 // TODO(riscv): use rm value (round mode)
3944 auto fn = [this](double drs1, double drs2) {
3945 if (is_invalid_fmul(drs1, drs2)) {
3946 this->set_fflags(kInvalidOperation);
3947 return std::numeric_limits<double>::quiet_NaN();
3948 } else {
3949 return drs1 * drs2;
3950 }
3951 };
3952 set_drd(CanonicalizeFPUOp2<double>(fn));
3953 break;
3954 }
3955 case RO_FDIV_D: {
3956 // TODO(riscv): use rm value (round mode)
3957 auto fn = [this](double drs1, double drs2) {
3958 if (is_invalid_fdiv(drs1, drs2)) {
3959 this->set_fflags(kInvalidOperation);
3960 return std::numeric_limits<double>::quiet_NaN();
3961 } else if (drs2 == 0.0) {
3962 this->set_fflags(kDivideByZero);
3963 return (std::signbit(drs1) == std::signbit(drs2)
3964 ? std::numeric_limits<double>::infinity()
3965 : -std::numeric_limits<double>::infinity());
3966 } else {
3967 return drs1 / drs2;
3968 }
3969 };
3970 set_drd(CanonicalizeFPUOp2<double>(fn));
3971 break;
3972 }
3973 case RO_FSQRT_D: {
3974 if (instr_.Rs2Value() == 0b00000) {
3975 // TODO(riscv): use rm value (round mode)
3976 auto fn = [this](double drs) {
3977 if (is_invalid_fsqrt(drs)) {
3978 this->set_fflags(kInvalidOperation);
3979 return std::numeric_limits<double>::quiet_NaN();
3980 } else {
3981 return std::sqrt(drs);
3982 }
3983 };
3984 set_drd(CanonicalizeFPUOp1<double>(fn));
3985 } else {
3986 UNSUPPORTED();
3987 }
3988 break;
3989 }
3990 case RO_FSGNJ_D: { // RO_FSGNJN_D RO_FSQNJX_D
3991 switch (instr_.Funct3Value()) {
3992 case 0b000: { // RO_FSGNJ_D
3993 set_drd(fsgnj64(drs1(), drs2(), false, false));
3994 break;
3995 }
3996 case 0b001: { // RO_FSGNJN_D
3997 set_drd(fsgnj64(drs1(), drs2(), true, false));
3998 break;
3999 }
4000 case 0b010: { // RO_FSQNJX_D
4001 set_drd(fsgnj64(drs1(), drs2(), false, true));
4002 break;
4003 }
4004 default: {
4005 UNSUPPORTED();
4006 }
4007 }
4008 break;
4009 }
4010 case RO_FMIN_D: { // RO_FMAX_D
4011 switch (instr_.Funct3Value()) {
4012 case 0b000: { // RO_FMIN_D
4013 set_drd(FMaxMinHelper(drs1(), drs2(), MaxMinKind::kMin));
4014 break;
4015 }
4016 case 0b001: { // RO_FMAX_D
4017 set_drd(FMaxMinHelper(drs1(), drs2(), MaxMinKind::kMax));
4018 break;
4019 }
4020 default: {
4021 UNSUPPORTED();
4022 }
4023 }
4024 break;
4025 }
4026 case (RO_FCVT_S_D & kRFPTypeMask): {
4027 if (instr_.Rs2Value() == 0b00001) {
4028 auto fn = [](double drs) { return static_cast<float>(drs); };
4029 set_frd(CanonicalizeDoubleToFloatOperation(fn));
4030 } else {
4031 UNSUPPORTED();
4032 }
4033 break;
4034 }
4035 case RO_FCVT_D_S: {
4036 if (instr_.Rs2Value() == 0b00000) {
4037 auto fn = [](float frs) { return static_cast<double>(frs); };
4038 set_drd(CanonicalizeFloatToDoubleOperation(fn));
4039 } else {
4040 UNSUPPORTED();
4041 }
4042 break;
4043 }
4044 case RO_FLE_D: { // RO_FEQ_D RO_FLT_D RO_FLE_D
4045 switch (instr_.Funct3Value()) {
4046 case 0b010: { // RO_FEQ_S
4047 set_rd(CompareFHelper(drs1(), drs2(), EQ));
4048 break;
4049 }
4050 case 0b001: { // RO_FLT_D
4051 set_rd(CompareFHelper(drs1(), drs2(), LT));
4052 break;
4053 }
4054 case 0b000: { // RO_FLE_D
4055 set_rd(CompareFHelper(drs1(), drs2(), LE));
4056 break;
4057 }
4058 default: {
4059 UNSUPPORTED();
4060 }
4061 }
4062 break;
4063 }
4064 case (RO_FCLASS_D & kRFPTypeMask): { // RO_FCLASS_D , 64D RO_FMV_X_D
4065 if (instr_.Rs2Value() != 0b00000) {
4066 UNSUPPORTED();
4067 }
4068 switch (instr_.Funct3Value()) {
4069 case 0b001: { // RO_FCLASS_D
4070 set_rd(FclassHelper(drs1()));
4071 break;
4072 }
4073 #ifdef V8_TARGET_ARCH_64_BIT
4074 case 0b000: { // RO_FMV_X_D
4075 set_rd(bit_cast<int64_t>(drs1()));
4076 break;
4077 }
4078 #endif /* V8_TARGET_ARCH_64_BIT */
4079 default: {
4080 UNSUPPORTED();
4081 }
4082 }
4083 break;
4084 }
4085 case RO_FCVT_W_D: { // RO_FCVT_WU_D , 64F RO_FCVT_L_D RO_FCVT_LU_D
4086 double original_val = drs1();
4087 switch (instr_.Rs2Value()) {
4088 case 0b00000: { // RO_FCVT_W_D
4089 set_rd(RoundF2IHelper<int32_t>(original_val, instr_.RoundMode()));
4090 break;
4091 }
4092 case 0b00001: { // RO_FCVT_WU_D
4093 set_rd(sext32(
4094 RoundF2IHelper<uint32_t>(original_val, instr_.RoundMode())));
4095 break;
4096 }
4097 #ifdef V8_TARGET_ARCH_64_BIT
4098 case 0b00010: { // RO_FCVT_L_D
4099 set_rd(RoundF2IHelper<int64_t>(original_val, instr_.RoundMode()));
4100 break;
4101 }
4102 case 0b00011: { // RO_FCVT_LU_D
4103 set_rd(RoundF2IHelper<uint64_t>(original_val, instr_.RoundMode()));
4104 break;
4105 }
4106 #endif /* V8_TARGET_ARCH_64_BIT */
4107 default: {
4108 UNSUPPORTED();
4109 }
4110 }
4111 break;
4112 }
4113 case RO_FCVT_D_W: { // RO_FCVT_D_WU , 64F RO_FCVT_D_L RO_FCVT_D_LU
4114 switch (instr_.Rs2Value()) {
4115 case 0b00000: { // RO_FCVT_D_W
4116 set_drd((int32_t)rs1());
4117 break;
4118 }
4119 case 0b00001: { // RO_FCVT_D_WU
4120 set_drd((uint32_t)rs1());
4121 break;
4122 }
4123 #ifdef V8_TARGET_ARCH_64_BIT
4124 case 0b00010: { // RO_FCVT_D_L
4125 set_drd((int64_t)rs1());
4126 break;
4127 }
4128 case 0b00011: { // RO_FCVT_D_LU
4129 set_drd((uint64_t)rs1());
4130 break;
4131 }
4132 #endif /* V8_TARGET_ARCH_64_BIT */
4133 default: {
4134 UNSUPPORTED();
4135 }
4136 }
4137 break;
4138 }
4139 #ifdef V8_TARGET_ARCH_64_BIT
4140 case RO_FMV_D_X: {
4141 if (instr_.Funct3Value() == 0b000 && instr_.Rs2Value() == 0b00000) {
4142 // Since FMV preserves source bit-pattern, no need to canonize
4143 set_drd(bit_cast<double>(rs1()));
4144 } else {
4145 UNSUPPORTED();
4146 }
4147 break;
4148 }
4149 #endif /* V8_TARGET_ARCH_64_BIT */
4150 default: {
4151 UNSUPPORTED();
4152 }
4153 }
4154 }
4155
DecodeRVR4Type()4156 void Simulator::DecodeRVR4Type() {
4157 switch (instr_.InstructionBits() & kR4TypeMask) {
4158 // TODO(riscv): use F Extension macro block
4159 case RO_FMADD_S: {
4160 // TODO(riscv): use rm value (round mode)
4161 auto fn = [this](float frs1, float frs2, float frs3) {
4162 if (is_invalid_fmul(frs1, frs2) || is_invalid_fadd(frs1 * frs2, frs3)) {
4163 this->set_fflags(kInvalidOperation);
4164 return std::numeric_limits<float>::quiet_NaN();
4165 } else {
4166 return std::fma(frs1, frs2, frs3);
4167 }
4168 };
4169 set_frd(CanonicalizeFPUOp3<float>(fn));
4170 break;
4171 }
4172 case RO_FMSUB_S: {
4173 // TODO(riscv): use rm value (round mode)
4174 auto fn = [this](float frs1, float frs2, float frs3) {
4175 if (is_invalid_fmul(frs1, frs2) || is_invalid_fsub(frs1 * frs2, frs3)) {
4176 this->set_fflags(kInvalidOperation);
4177 return std::numeric_limits<float>::quiet_NaN();
4178 } else {
4179 return std::fma(frs1, frs2, -frs3);
4180 }
4181 };
4182 set_frd(CanonicalizeFPUOp3<float>(fn));
4183 break;
4184 }
4185 case RO_FNMSUB_S: {
4186 // TODO(riscv): use rm value (round mode)
4187 auto fn = [this](float frs1, float frs2, float frs3) {
4188 if (is_invalid_fmul(frs1, frs2) || is_invalid_fsub(frs3, frs1 * frs2)) {
4189 this->set_fflags(kInvalidOperation);
4190 return std::numeric_limits<float>::quiet_NaN();
4191 } else {
4192 return -std::fma(frs1, frs2, -frs3);
4193 }
4194 };
4195 set_frd(CanonicalizeFPUOp3<float>(fn));
4196 break;
4197 }
4198 case RO_FNMADD_S: {
4199 // TODO(riscv): use rm value (round mode)
4200 auto fn = [this](float frs1, float frs2, float frs3) {
4201 if (is_invalid_fmul(frs1, frs2) || is_invalid_fadd(frs1 * frs2, frs3)) {
4202 this->set_fflags(kInvalidOperation);
4203 return std::numeric_limits<float>::quiet_NaN();
4204 } else {
4205 return -std::fma(frs1, frs2, frs3);
4206 }
4207 };
4208 set_frd(CanonicalizeFPUOp3<float>(fn));
4209 break;
4210 }
4211 // TODO(riscv): use F Extension macro block
4212 case RO_FMADD_D: {
4213 // TODO(riscv): use rm value (round mode)
4214 auto fn = [this](double drs1, double drs2, double drs3) {
4215 if (is_invalid_fmul(drs1, drs2) || is_invalid_fadd(drs1 * drs2, drs3)) {
4216 this->set_fflags(kInvalidOperation);
4217 return std::numeric_limits<double>::quiet_NaN();
4218 } else {
4219 return std::fma(drs1, drs2, drs3);
4220 }
4221 };
4222 set_drd(CanonicalizeFPUOp3<double>(fn));
4223 break;
4224 }
4225 case RO_FMSUB_D: {
4226 // TODO(riscv): use rm value (round mode)
4227 auto fn = [this](double drs1, double drs2, double drs3) {
4228 if (is_invalid_fmul(drs1, drs2) || is_invalid_fsub(drs1 * drs2, drs3)) {
4229 this->set_fflags(kInvalidOperation);
4230 return std::numeric_limits<double>::quiet_NaN();
4231 } else {
4232 return std::fma(drs1, drs2, -drs3);
4233 }
4234 };
4235 set_drd(CanonicalizeFPUOp3<double>(fn));
4236 break;
4237 }
4238 case RO_FNMSUB_D: {
4239 // TODO(riscv): use rm value (round mode)
4240 auto fn = [this](double drs1, double drs2, double drs3) {
4241 if (is_invalid_fmul(drs1, drs2) || is_invalid_fsub(drs3, drs1 * drs2)) {
4242 this->set_fflags(kInvalidOperation);
4243 return std::numeric_limits<double>::quiet_NaN();
4244 } else {
4245 return -std::fma(drs1, drs2, -drs3);
4246 }
4247 };
4248 set_drd(CanonicalizeFPUOp3<double>(fn));
4249 break;
4250 }
4251 case RO_FNMADD_D: {
4252 // TODO(riscv): use rm value (round mode)
4253 auto fn = [this](double drs1, double drs2, double drs3) {
4254 if (is_invalid_fmul(drs1, drs2) || is_invalid_fadd(drs1 * drs2, drs3)) {
4255 this->set_fflags(kInvalidOperation);
4256 return std::numeric_limits<double>::quiet_NaN();
4257 } else {
4258 return -std::fma(drs1, drs2, drs3);
4259 }
4260 };
4261 set_drd(CanonicalizeFPUOp3<double>(fn));
4262 break;
4263 }
4264 default:
4265 UNSUPPORTED();
4266 }
4267 }
4268
4269 #ifdef CAN_USE_RVV_INSTRUCTIONS
DecodeRvvVL()4270 bool Simulator::DecodeRvvVL() {
4271 uint32_t instr_temp =
4272 instr_.InstructionBits() & (kRvvMopMask | kRvvNfMask | kBaseOpcodeMask);
4273 if (RO_V_VL == instr_temp) {
4274 if (!(instr_.InstructionBits() & (kRvvRs2Mask))) {
4275 switch (instr_.vl_vs_width()) {
4276 case 8: {
4277 RVV_VI_LD(0, (i * nf + fn), int8, false);
4278 break;
4279 }
4280 case 16: {
4281 RVV_VI_LD(0, (i * nf + fn), int16, false);
4282 break;
4283 }
4284 case 32: {
4285 RVV_VI_LD(0, (i * nf + fn), int32, false);
4286 break;
4287 }
4288 case 64: {
4289 RVV_VI_LD(0, (i * nf + fn), int64, false);
4290 break;
4291 }
4292 default:
4293 UNIMPLEMENTED_RISCV();
4294 break;
4295 }
4296 return true;
4297 } else {
4298 UNIMPLEMENTED_RISCV();
4299 return true;
4300 }
4301 } else if (RO_V_VLS == instr_temp) {
4302 UNIMPLEMENTED_RISCV();
4303 return true;
4304 } else if (RO_V_VLX == instr_temp) {
4305 UNIMPLEMENTED_RISCV();
4306 return true;
4307 } else if (RO_V_VLSEG2 == instr_temp || RO_V_VLSEG3 == instr_temp ||
4308 RO_V_VLSEG4 == instr_temp || RO_V_VLSEG5 == instr_temp ||
4309 RO_V_VLSEG6 == instr_temp || RO_V_VLSEG7 == instr_temp ||
4310 RO_V_VLSEG8 == instr_temp) {
4311 if (!(instr_.InstructionBits() & (kRvvRs2Mask))) {
4312 UNIMPLEMENTED_RISCV();
4313 return true;
4314 } else {
4315 UNIMPLEMENTED_RISCV();
4316 return true;
4317 }
4318 } else if (RO_V_VLSSEG2 == instr_temp || RO_V_VLSSEG3 == instr_temp ||
4319 RO_V_VLSSEG4 == instr_temp || RO_V_VLSSEG5 == instr_temp ||
4320 RO_V_VLSSEG6 == instr_temp || RO_V_VLSSEG7 == instr_temp ||
4321 RO_V_VLSSEG8 == instr_temp) {
4322 UNIMPLEMENTED_RISCV();
4323 return true;
4324 } else if (RO_V_VLXSEG2 == instr_temp || RO_V_VLXSEG3 == instr_temp ||
4325 RO_V_VLXSEG4 == instr_temp || RO_V_VLXSEG5 == instr_temp ||
4326 RO_V_VLXSEG6 == instr_temp || RO_V_VLXSEG7 == instr_temp ||
4327 RO_V_VLXSEG8 == instr_temp) {
4328 UNIMPLEMENTED_RISCV();
4329 return true;
4330 } else {
4331 return false;
4332 }
4333 }
4334
DecodeRvvVS()4335 bool Simulator::DecodeRvvVS() {
4336 uint32_t instr_temp =
4337 instr_.InstructionBits() & (kRvvMopMask | kRvvNfMask | kBaseOpcodeMask);
4338 if (RO_V_VS == instr_temp) {
4339 if (!(instr_.InstructionBits() & (kRvvRs2Mask))) {
4340 switch (instr_.vl_vs_width()) {
4341 case 8: {
4342 RVV_VI_ST(0, (i * nf + fn), uint8, false);
4343 break;
4344 }
4345 case 16: {
4346 RVV_VI_ST(0, (i * nf + fn), uint16, false);
4347 break;
4348 }
4349 case 32: {
4350 RVV_VI_ST(0, (i * nf + fn), uint32, false);
4351 break;
4352 }
4353 case 64: {
4354 RVV_VI_ST(0, (i * nf + fn), uint64, false);
4355 break;
4356 }
4357 default:
4358 UNIMPLEMENTED_RISCV();
4359 break;
4360 }
4361 } else {
4362 UNIMPLEMENTED_RISCV();
4363 }
4364 return true;
4365 } else if (RO_V_VSS == instr_temp) {
4366 UNIMPLEMENTED_RISCV();
4367 return true;
4368 } else if (RO_V_VSX == instr_temp) {
4369 UNIMPLEMENTED_RISCV();
4370 return true;
4371 } else if (RO_V_VSU == instr_temp) {
4372 UNIMPLEMENTED_RISCV();
4373 return true;
4374 } else if (RO_V_VSSEG2 == instr_temp || RO_V_VSSEG3 == instr_temp ||
4375 RO_V_VSSEG4 == instr_temp || RO_V_VSSEG5 == instr_temp ||
4376 RO_V_VSSEG6 == instr_temp || RO_V_VSSEG7 == instr_temp ||
4377 RO_V_VSSEG8 == instr_temp) {
4378 UNIMPLEMENTED_RISCV();
4379 return true;
4380 } else if (RO_V_VSSSEG2 == instr_temp || RO_V_VSSSEG3 == instr_temp ||
4381 RO_V_VSSSEG4 == instr_temp || RO_V_VSSSEG5 == instr_temp ||
4382 RO_V_VSSSEG6 == instr_temp || RO_V_VSSSEG7 == instr_temp ||
4383 RO_V_VSSSEG8 == instr_temp) {
4384 UNIMPLEMENTED_RISCV();
4385 return true;
4386 } else if (RO_V_VSXSEG2 == instr_temp || RO_V_VSXSEG3 == instr_temp ||
4387 RO_V_VSXSEG4 == instr_temp || RO_V_VSXSEG5 == instr_temp ||
4388 RO_V_VSXSEG6 == instr_temp || RO_V_VSXSEG7 == instr_temp ||
4389 RO_V_VSXSEG8 == instr_temp) {
4390 UNIMPLEMENTED_RISCV();
4391 return true;
4392 } else {
4393 return false;
4394 }
4395 }
4396 #endif
4397
LookUp(Address pc)4398 Builtin Simulator::LookUp(Address pc) {
4399 for (Builtin builtin = Builtins::kFirst; builtin <= Builtins::kLast;
4400 ++builtin) {
4401 if (builtins_.code(builtin).contains(isolate_, pc)) return builtin;
4402 }
4403 return Builtin::kNoBuiltinId;
4404 }
4405
DecodeRVIType()4406 void Simulator::DecodeRVIType() {
4407 switch (instr_.InstructionBits() & kITypeMask) {
4408 case RO_JALR: {
4409 set_rd(get_pc() + kInstrSize);
4410 // Note: No need to shift 2 for JALR's imm12, but set lowest bit to 0.
4411 int64_t next_pc = (rs1() + imm12()) & ~reg_t(1);
4412 set_pc(next_pc);
4413 if (::v8::internal::FLAG_trace_sim) {
4414 Builtin builtin = LookUp((Address)get_pc());
4415 if (builtin != Builtin::kNoBuiltinId) {
4416 auto code = builtins_.code(builtin);
4417 if ((rs1_reg() != ra || imm12() != 0)) {
4418 if ((Address)get_pc() == code.InstructionStart()) {
4419 int64_t arg0 = get_register(a0);
4420 int64_t arg1 = get_register(a1);
4421 int64_t arg2 = get_register(a2);
4422 int64_t arg3 = get_register(a3);
4423 int64_t arg4 = get_register(a4);
4424 int64_t arg5 = get_register(a5);
4425 int64_t arg6 = get_register(a6);
4426 int64_t arg7 = get_register(a7);
4427 int64_t* stack_pointer =
4428 reinterpret_cast<int64_t*>(get_register(sp));
4429 int64_t arg8 = stack_pointer[0];
4430 int64_t arg9 = stack_pointer[1];
4431 PrintF(
4432 "Call to Builtin at %s "
4433 "a0 %08" PRIx64 " ,a1 %08" PRIx64 " ,a2 %08" PRIx64
4434 " ,a3 %08" PRIx64 " ,a4 %08" PRIx64 " ,a5 %08" PRIx64
4435 " ,a6 %08" PRIx64 " ,a7 %08" PRIx64 " ,0(sp) %08" PRIx64
4436 " ,8(sp) %08" PRIx64 " ,sp %08" PRIx64 ",fp %08" PRIx64 " \n",
4437 builtins_.name(builtin), arg0, arg1, arg2, arg3, arg4, arg5,
4438 arg6, arg7, arg8, arg9, get_register(sp), get_register(fp));
4439 }
4440 } else if (rd_reg() == zero_reg) {
4441 PrintF("Return to Builtin at %s \n", builtins_.name(builtin));
4442 }
4443 }
4444 }
4445 break;
4446 }
4447 case RO_LB: {
4448 int64_t addr = rs1() + imm12();
4449 int8_t val = ReadMem<int8_t>(addr, instr_.instr());
4450 set_rd(sext_xlen(val), false);
4451 TraceMemRd(addr, val, get_register(rd_reg()));
4452 break;
4453 }
4454 case RO_LH: {
4455 int64_t addr = rs1() + imm12();
4456 int16_t val = ReadMem<int16_t>(addr, instr_.instr());
4457 set_rd(sext_xlen(val), false);
4458 TraceMemRd(addr, val, get_register(rd_reg()));
4459 break;
4460 }
4461 case RO_LW: {
4462 int64_t addr = rs1() + imm12();
4463 int32_t val = ReadMem<int32_t>(addr, instr_.instr());
4464 set_rd(sext_xlen(val), false);
4465 TraceMemRd(addr, val, get_register(rd_reg()));
4466 break;
4467 }
4468 case RO_LBU: {
4469 int64_t addr = rs1() + imm12();
4470 uint8_t val = ReadMem<uint8_t>(addr, instr_.instr());
4471 set_rd(zext_xlen(val), false);
4472 TraceMemRd(addr, val, get_register(rd_reg()));
4473 break;
4474 }
4475 case RO_LHU: {
4476 int64_t addr = rs1() + imm12();
4477 uint16_t val = ReadMem<uint16_t>(addr, instr_.instr());
4478 set_rd(zext_xlen(val), false);
4479 TraceMemRd(addr, val, get_register(rd_reg()));
4480 break;
4481 }
4482 #ifdef V8_TARGET_ARCH_64_BIT
4483 case RO_LWU: {
4484 int64_t addr = rs1() + imm12();
4485 uint32_t val = ReadMem<uint32_t>(addr, instr_.instr());
4486 set_rd(zext_xlen(val), false);
4487 TraceMemRd(addr, val, get_register(rd_reg()));
4488 break;
4489 }
4490 case RO_LD: {
4491 int64_t addr = rs1() + imm12();
4492 int64_t val = ReadMem<int64_t>(addr, instr_.instr());
4493 set_rd(sext_xlen(val), false);
4494 TraceMemRd(addr, val, get_register(rd_reg()));
4495 break;
4496 }
4497 #endif /*V8_TARGET_ARCH_64_BIT*/
4498 case RO_ADDI: {
4499 set_rd(sext_xlen(rs1() + imm12()));
4500 break;
4501 }
4502 case RO_SLTI: {
4503 set_rd(sreg_t(rs1()) < sreg_t(imm12()));
4504 break;
4505 }
4506 case RO_SLTIU: {
4507 set_rd(reg_t(rs1()) < reg_t(imm12()));
4508 break;
4509 }
4510 case RO_XORI: {
4511 set_rd(imm12() ^ rs1());
4512 break;
4513 }
4514 case RO_ORI: {
4515 set_rd(imm12() | rs1());
4516 break;
4517 }
4518 case RO_ANDI: {
4519 set_rd(imm12() & rs1());
4520 break;
4521 }
4522 case RO_SLLI: {
4523 require(shamt6() < xlen);
4524 set_rd(sext_xlen(rs1() << shamt6()));
4525 break;
4526 }
4527 case RO_SRLI: { // RO_SRAI
4528 if (!instr_.IsArithShift()) {
4529 require(shamt6() < xlen);
4530 set_rd(sext_xlen(zext_xlen(rs1()) >> shamt6()));
4531 } else {
4532 require(shamt6() < xlen);
4533 set_rd(sext_xlen(sext_xlen(rs1()) >> shamt6()));
4534 }
4535 break;
4536 }
4537 #ifdef V8_TARGET_ARCH_64_BIT
4538 case RO_ADDIW: {
4539 set_rd(sext32(rs1() + imm12()));
4540 break;
4541 }
4542 case RO_SLLIW: {
4543 set_rd(sext32(rs1() << shamt5()));
4544 break;
4545 }
4546 case RO_SRLIW: { // RO_SRAIW
4547 if (!instr_.IsArithShift()) {
4548 set_rd(sext32(uint32_t(rs1()) >> shamt5()));
4549 } else {
4550 set_rd(sext32(int32_t(rs1()) >> shamt5()));
4551 }
4552 break;
4553 }
4554 #endif /*V8_TARGET_ARCH_64_BIT*/
4555 case RO_FENCE: {
4556 // DO nothing in sumulator
4557 break;
4558 }
4559 case RO_ECALL: { // RO_EBREAK
4560 if (instr_.Imm12Value() == 0) { // ECALL
4561 SoftwareInterrupt();
4562 } else if (instr_.Imm12Value() == 1) { // EBREAK
4563 SoftwareInterrupt();
4564 } else {
4565 UNSUPPORTED();
4566 }
4567 break;
4568 }
4569 // TODO(riscv): use Zifencei Standard Extension macro block
4570 case RO_FENCE_I: {
4571 // spike: flush icache.
4572 break;
4573 }
4574 // TODO(riscv): use Zicsr Standard Extension macro block
4575 case RO_CSRRW: {
4576 if (rd_reg() != zero_reg) {
4577 set_rd(zext_xlen(read_csr_value(csr_reg())));
4578 }
4579 write_csr_value(csr_reg(), rs1());
4580 break;
4581 }
4582 case RO_CSRRS: {
4583 set_rd(zext_xlen(read_csr_value(csr_reg())));
4584 if (rs1_reg() != zero_reg) {
4585 set_csr_bits(csr_reg(), rs1());
4586 }
4587 break;
4588 }
4589 case RO_CSRRC: {
4590 set_rd(zext_xlen(read_csr_value(csr_reg())));
4591 if (rs1_reg() != zero_reg) {
4592 clear_csr_bits(csr_reg(), rs1());
4593 }
4594 break;
4595 }
4596 case RO_CSRRWI: {
4597 if (rd_reg() != zero_reg) {
4598 set_rd(zext_xlen(read_csr_value(csr_reg())));
4599 }
4600 write_csr_value(csr_reg(), imm5CSR());
4601 break;
4602 }
4603 case RO_CSRRSI: {
4604 set_rd(zext_xlen(read_csr_value(csr_reg())));
4605 if (imm5CSR() != 0) {
4606 set_csr_bits(csr_reg(), imm5CSR());
4607 }
4608 break;
4609 }
4610 case RO_CSRRCI: {
4611 set_rd(zext_xlen(read_csr_value(csr_reg())));
4612 if (imm5CSR() != 0) {
4613 clear_csr_bits(csr_reg(), imm5CSR());
4614 }
4615 break;
4616 }
4617 // TODO(riscv): use F Extension macro block
4618 case RO_FLW: {
4619 int64_t addr = rs1() + imm12();
4620 float val = ReadMem<float>(addr, instr_.instr());
4621 set_frd(val, false);
4622 TraceMemRd(addr, val, get_fpu_register(frd_reg()));
4623 break;
4624 }
4625 // TODO(riscv): use D Extension macro block
4626 case RO_FLD: {
4627 int64_t addr = rs1() + imm12();
4628 double val = ReadMem<double>(addr, instr_.instr());
4629 set_drd(val, false);
4630 TraceMemRd(addr, val, get_fpu_register(frd_reg()));
4631 break;
4632 }
4633 default: {
4634 #ifdef CAN_USE_RVV_INSTRUCTIONS
4635 if (!DecodeRvvVL()) {
4636 UNSUPPORTED();
4637 }
4638 #else
4639 UNSUPPORTED();
4640 #endif
4641 break;
4642 }
4643 }
4644 }
4645
DecodeRVSType()4646 void Simulator::DecodeRVSType() {
4647 switch (instr_.InstructionBits() & kSTypeMask) {
4648 case RO_SB:
4649 WriteMem<uint8_t>(rs1() + s_imm12(), (uint8_t)rs2(), instr_.instr());
4650 break;
4651 case RO_SH:
4652 WriteMem<uint16_t>(rs1() + s_imm12(), (uint16_t)rs2(), instr_.instr());
4653 break;
4654 case RO_SW:
4655 WriteMem<uint32_t>(rs1() + s_imm12(), (uint32_t)rs2(), instr_.instr());
4656 break;
4657 #ifdef V8_TARGET_ARCH_64_BIT
4658 case RO_SD:
4659 WriteMem<uint64_t>(rs1() + s_imm12(), (uint64_t)rs2(), instr_.instr());
4660 break;
4661 #endif /*V8_TARGET_ARCH_64_BIT*/
4662 // TODO(riscv): use F Extension macro block
4663 case RO_FSW: {
4664 WriteMem<uint32_t>(rs1() + s_imm12(),
4665 (uint32_t)get_fpu_register_word(rs2_reg()),
4666 instr_.instr());
4667 break;
4668 }
4669 // TODO(riscv): use D Extension macro block
4670 case RO_FSD: {
4671 WriteMem<double>(rs1() + s_imm12(), drs2(), instr_.instr());
4672 break;
4673 }
4674 default:
4675 #ifdef CAN_USE_RVV_INSTRUCTIONS
4676 if (!DecodeRvvVS()) {
4677 UNSUPPORTED();
4678 }
4679 #else
4680 UNSUPPORTED();
4681 #endif
4682 break;
4683 }
4684 }
4685
DecodeRVBType()4686 void Simulator::DecodeRVBType() {
4687 switch (instr_.InstructionBits() & kBTypeMask) {
4688 case RO_BEQ:
4689 if (rs1() == rs2()) {
4690 int64_t next_pc = get_pc() + boffset();
4691 set_pc(next_pc);
4692 }
4693 break;
4694 case RO_BNE:
4695 if (rs1() != rs2()) {
4696 int64_t next_pc = get_pc() + boffset();
4697 set_pc(next_pc);
4698 }
4699 break;
4700 case RO_BLT:
4701 if (rs1() < rs2()) {
4702 int64_t next_pc = get_pc() + boffset();
4703 set_pc(next_pc);
4704 }
4705 break;
4706 case RO_BGE:
4707 if (rs1() >= rs2()) {
4708 int64_t next_pc = get_pc() + boffset();
4709 set_pc(next_pc);
4710 }
4711 break;
4712 case RO_BLTU:
4713 if ((reg_t)rs1() < (reg_t)rs2()) {
4714 int64_t next_pc = get_pc() + boffset();
4715 set_pc(next_pc);
4716 }
4717 break;
4718 case RO_BGEU:
4719 if ((reg_t)rs1() >= (reg_t)rs2()) {
4720 int64_t next_pc = get_pc() + boffset();
4721 set_pc(next_pc);
4722 }
4723 break;
4724 default:
4725 UNSUPPORTED();
4726 }
4727 }
DecodeRVUType()4728 void Simulator::DecodeRVUType() {
4729 // U Type doesn't have additoinal mask
4730 switch (instr_.BaseOpcodeFieldRaw()) {
4731 case RO_LUI:
4732 set_rd(u_imm20());
4733 break;
4734 case RO_AUIPC:
4735 set_rd(sext_xlen(u_imm20() + get_pc()));
4736 break;
4737 default:
4738 UNSUPPORTED();
4739 }
4740 }
DecodeRVJType()4741 void Simulator::DecodeRVJType() {
4742 // J Type doesn't have additional mask
4743 switch (instr_.BaseOpcodeValue()) {
4744 case RO_JAL: {
4745 set_rd(get_pc() + kInstrSize);
4746 int64_t next_pc = get_pc() + imm20J();
4747 set_pc(next_pc);
4748 break;
4749 }
4750 default:
4751 UNSUPPORTED();
4752 }
4753 }
DecodeCRType()4754 void Simulator::DecodeCRType() {
4755 switch (instr_.RvcFunct4Value()) {
4756 case 0b1000:
4757 if (instr_.RvcRs1Value() != 0 && instr_.RvcRs2Value() == 0) { // c.jr
4758 set_pc(rvc_rs1());
4759 } else if (instr_.RvcRdValue() != 0 &&
4760 instr_.RvcRs2Value() != 0) { // c.mv
4761 set_rvc_rd(sext_xlen(rvc_rs2()));
4762 } else {
4763 UNSUPPORTED_RISCV();
4764 }
4765 break;
4766 case 0b1001:
4767 if (instr_.RvcRs1Value() == 0 && instr_.RvcRs2Value() == 0) { // c.ebreak
4768 RiscvDebugger dbg(this);
4769 dbg.Debug();
4770 } else if (instr_.RvcRdValue() != 0 &&
4771 instr_.RvcRs2Value() == 0) { // c.jalr
4772 set_register(ra, get_pc() + kShortInstrSize);
4773 set_pc(rvc_rs1());
4774 } else if (instr_.RvcRdValue() != 0 &&
4775 instr_.RvcRs2Value() != 0) { // c.add
4776 set_rvc_rd(sext_xlen(rvc_rs1() + rvc_rs2()));
4777 } else {
4778 UNSUPPORTED();
4779 }
4780 break;
4781 default:
4782 UNSUPPORTED();
4783 }
4784 }
4785
DecodeCAType()4786 void Simulator::DecodeCAType() {
4787 switch (instr_.InstructionBits() & kCATypeMask) {
4788 case RO_C_SUB:
4789 set_rvc_rs1s(sext_xlen(rvc_rs1s() - rvc_rs2s()));
4790 break;
4791 case RO_C_XOR:
4792 set_rvc_rs1s(rvc_rs1s() ^ rvc_rs2s());
4793 break;
4794 case RO_C_OR:
4795 set_rvc_rs1s(rvc_rs1s() | rvc_rs2s());
4796 break;
4797 case RO_C_AND:
4798 set_rvc_rs1s(rvc_rs1s() & rvc_rs2s());
4799 break;
4800 case RO_C_SUBW:
4801 set_rvc_rs1s(sext32(rvc_rs1s() - rvc_rs2s()));
4802 break;
4803 case RO_C_ADDW:
4804 set_rvc_rs1s(sext32(rvc_rs1s() + rvc_rs2s()));
4805 break;
4806 default:
4807 UNSUPPORTED();
4808 }
4809 }
4810
DecodeCIType()4811 void Simulator::DecodeCIType() {
4812 switch (instr_.RvcOpcode()) {
4813 case RO_C_NOP_ADDI:
4814 if (instr_.RvcRdValue() == 0) // c.nop
4815 break;
4816 else // c.addi
4817 set_rvc_rd(sext_xlen(rvc_rs1() + rvc_imm6()));
4818 break;
4819 case RO_C_ADDIW:
4820 set_rvc_rd(sext32(rvc_rs1() + rvc_imm6()));
4821 break;
4822 case RO_C_LI:
4823 set_rvc_rd(sext_xlen(rvc_imm6()));
4824 break;
4825 case RO_C_LUI_ADD:
4826 if (instr_.RvcRdValue() == 2) {
4827 // c.addi16sp
4828 int64_t value = get_register(sp) + rvc_imm6_addi16sp();
4829 set_register(sp, value);
4830 } else if (instr_.RvcRdValue() != 0 && instr_.RvcRdValue() != 2) {
4831 // c.lui
4832 set_rvc_rd(rvc_u_imm6());
4833 } else {
4834 UNSUPPORTED();
4835 }
4836 break;
4837 case RO_C_SLLI:
4838 set_rvc_rd(sext_xlen(rvc_rs1() << rvc_shamt6()));
4839 break;
4840 case RO_C_FLDSP: {
4841 int64_t addr = get_register(sp) + rvc_imm6_ldsp();
4842 double val = ReadMem<double>(addr, instr_.instr());
4843 set_rvc_drd(val, false);
4844 TraceMemRd(addr, val, get_fpu_register(rvc_frd_reg()));
4845 break;
4846 }
4847 case RO_C_LWSP: {
4848 int64_t addr = get_register(sp) + rvc_imm6_lwsp();
4849 int64_t val = ReadMem<int32_t>(addr, instr_.instr());
4850 set_rvc_rd(sext_xlen(val), false);
4851 TraceMemRd(addr, val, get_register(rvc_rd_reg()));
4852 break;
4853 }
4854 case RO_C_LDSP: {
4855 int64_t addr = get_register(sp) + rvc_imm6_ldsp();
4856 int64_t val = ReadMem<int64_t>(addr, instr_.instr());
4857 set_rvc_rd(sext_xlen(val), false);
4858 TraceMemRd(addr, val, get_register(rvc_rd_reg()));
4859 break;
4860 }
4861 default:
4862 UNSUPPORTED();
4863 }
4864 }
4865
DecodeCIWType()4866 void Simulator::DecodeCIWType() {
4867 switch (instr_.RvcOpcode()) {
4868 case RO_C_ADDI4SPN: {
4869 set_rvc_rs2s(get_register(sp) + rvc_imm8_addi4spn());
4870 break;
4871 default:
4872 UNSUPPORTED();
4873 }
4874 }
4875 }
4876
DecodeCSSType()4877 void Simulator::DecodeCSSType() {
4878 switch (instr_.RvcOpcode()) {
4879 case RO_C_FSDSP: {
4880 int64_t addr = get_register(sp) + rvc_imm6_sdsp();
4881 WriteMem<double>(addr, static_cast<double>(rvc_drs2()), instr_.instr());
4882 break;
4883 }
4884 case RO_C_SWSP: {
4885 int64_t addr = get_register(sp) + rvc_imm6_swsp();
4886 WriteMem<int32_t>(addr, (int32_t)rvc_rs2(), instr_.instr());
4887 break;
4888 }
4889 case RO_C_SDSP: {
4890 int64_t addr = get_register(sp) + rvc_imm6_sdsp();
4891 WriteMem<int64_t>(addr, (int64_t)rvc_rs2(), instr_.instr());
4892 break;
4893 }
4894 default:
4895 UNSUPPORTED();
4896 }
4897 }
4898
DecodeCLType()4899 void Simulator::DecodeCLType() {
4900 switch (instr_.RvcOpcode()) {
4901 case RO_C_LW: {
4902 int64_t addr = rvc_rs1s() + rvc_imm5_w();
4903 int64_t val = ReadMem<int32_t>(addr, instr_.instr());
4904 set_rvc_rs2s(sext_xlen(val), false);
4905 TraceMemRd(addr, val, get_register(rvc_rs2s_reg()));
4906 break;
4907 }
4908 case RO_C_LD: {
4909 int64_t addr = rvc_rs1s() + rvc_imm5_d();
4910 int64_t val = ReadMem<int64_t>(addr, instr_.instr());
4911 set_rvc_rs2s(sext_xlen(val), false);
4912 TraceMemRd(addr, val, get_register(rvc_rs2s_reg()));
4913 break;
4914 }
4915 case RO_C_FLD: {
4916 int64_t addr = rvc_rs1s() + rvc_imm5_d();
4917 double val = ReadMem<double>(addr, instr_.instr());
4918 set_rvc_drs2s(val, false);
4919 break;
4920 }
4921 default:
4922 UNSUPPORTED();
4923 }
4924 }
4925
DecodeCSType()4926 void Simulator::DecodeCSType() {
4927 switch (instr_.RvcOpcode()) {
4928 case RO_C_SW: {
4929 int64_t addr = rvc_rs1s() + rvc_imm5_w();
4930 WriteMem<int32_t>(addr, (int32_t)rvc_rs2s(), instr_.instr());
4931 break;
4932 }
4933 case RO_C_SD: {
4934 int64_t addr = rvc_rs1s() + rvc_imm5_d();
4935 WriteMem<int64_t>(addr, (int64_t)rvc_rs2s(), instr_.instr());
4936 break;
4937 }
4938 case RO_C_FSD: {
4939 int64_t addr = rvc_rs1s() + rvc_imm5_d();
4940 WriteMem<double>(addr, static_cast<double>(rvc_drs2s()), instr_.instr());
4941 break;
4942 }
4943 default:
4944 UNSUPPORTED();
4945 }
4946 }
4947
DecodeCJType()4948 void Simulator::DecodeCJType() {
4949 switch (instr_.RvcOpcode()) {
4950 case RO_C_J: {
4951 set_pc(get_pc() + instr_.RvcImm11CJValue());
4952 break;
4953 }
4954 default:
4955 UNSUPPORTED();
4956 }
4957 }
4958
DecodeCBType()4959 void Simulator::DecodeCBType() {
4960 switch (instr_.RvcOpcode()) {
4961 case RO_C_BNEZ:
4962 if (rvc_rs1() != 0) {
4963 int64_t next_pc = get_pc() + rvc_imm8_b();
4964 set_pc(next_pc);
4965 }
4966 break;
4967 case RO_C_BEQZ:
4968 if (rvc_rs1() == 0) {
4969 int64_t next_pc = get_pc() + rvc_imm8_b();
4970 set_pc(next_pc);
4971 }
4972 break;
4973 case RO_C_MISC_ALU:
4974 if (instr_.RvcFunct2BValue() == 0b00) { // c.srli
4975 set_rvc_rs1s(sext_xlen(sext_xlen(rvc_rs1s()) >> rvc_shamt6()));
4976 } else if (instr_.RvcFunct2BValue() == 0b01) { // c.srai
4977 require(rvc_shamt6() < xlen);
4978 set_rvc_rs1s(sext_xlen(sext_xlen(rvc_rs1s()) >> rvc_shamt6()));
4979 } else if (instr_.RvcFunct2BValue() == 0b10) { // c.andi
4980 set_rvc_rs1s(rvc_imm6() & rvc_rs1s());
4981 } else {
4982 UNSUPPORTED();
4983 }
4984 break;
4985 default:
4986 UNSUPPORTED();
4987 }
4988 }
4989
4990 /**
4991 * RISCV-ISA-SIM
4992 *
4993 * @link https://github.com/riscv/riscv-isa-sim/
4994 * @copyright Copyright (c) The Regents of the University of California
4995 * @license hhttps://github.com/riscv/riscv-isa-sim/blob/master/LICENSE
4996 */
4997 // ref: https://locklessinc.com/articles/sat_arithmetic/
4998 template <typename T, typename UT>
sat_add(T x,T y,bool & sat)4999 static inline T sat_add(T x, T y, bool& sat) {
5000 UT ux = x;
5001 UT uy = y;
5002 UT res = ux + uy;
5003 sat = false;
5004 int sh = sizeof(T) * 8 - 1;
5005
5006 /* Calculate overflowed result. (Don't change the sign bit of ux) */
5007 ux = (ux >> sh) + (((UT)0x1 << sh) - 1);
5008
5009 /* Force compiler to use cmovns instruction */
5010 if ((T)((ux ^ uy) | ~(uy ^ res)) >= 0) {
5011 res = ux;
5012 sat = true;
5013 }
5014
5015 return res;
5016 }
5017
5018 template <typename T, typename UT>
sat_sub(T x,T y,bool & sat)5019 static inline T sat_sub(T x, T y, bool& sat) {
5020 UT ux = x;
5021 UT uy = y;
5022 UT res = ux - uy;
5023 sat = false;
5024 int sh = sizeof(T) * 8 - 1;
5025
5026 /* Calculate overflowed result. (Don't change the sign bit of ux) */
5027 ux = (ux >> sh) + (((UT)0x1 << sh) - 1);
5028
5029 /* Force compiler to use cmovns instruction */
5030 if ((T)((ux ^ uy) & (ux ^ res)) < 0) {
5031 res = ux;
5032 sat = true;
5033 }
5034
5035 return res;
5036 }
5037
5038 template <typename T>
sat_addu(T x,T y,bool & sat)5039 T sat_addu(T x, T y, bool& sat) {
5040 T res = x + y;
5041 sat = false;
5042
5043 sat = res < x;
5044 res |= -(res < x);
5045
5046 return res;
5047 }
5048
5049 template <typename T>
sat_subu(T x,T y,bool & sat)5050 T sat_subu(T x, T y, bool& sat) {
5051 T res = x - y;
5052 sat = false;
5053
5054 sat = !(res <= x);
5055 res &= -(res <= x);
5056
5057 return res;
5058 }
5059
5060 #ifdef CAN_USE_RVV_INSTRUCTIONS
DecodeRvvIVV()5061 void Simulator::DecodeRvvIVV() {
5062 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_IVV);
5063 switch (instr_.InstructionBits() & kVTypeMask) {
5064 case RO_V_VADD_VV: {
5065 RVV_VI_VV_LOOP({ vd = vs1 + vs2; });
5066 break;
5067 }
5068 case RO_V_VSADD_VV: {
5069 RVV_VI_GENERAL_LOOP_BASE
5070 bool sat = false;
5071 switch (rvv_vsew()) {
5072 case E8: {
5073 VV_PARAMS(8);
5074 vd = sat_add<int8_t, uint8_t>(vs2, vs1, sat);
5075 break;
5076 }
5077 case E16: {
5078 VV_PARAMS(16);
5079 vd = sat_add<int16_t, uint16_t>(vs2, vs1, sat);
5080 break;
5081 }
5082 case E32: {
5083 VV_PARAMS(32);
5084 vd = sat_add<int32_t, uint32_t>(vs2, vs1, sat);
5085 break;
5086 }
5087 default: {
5088 VV_PARAMS(64);
5089 vd = sat_add<int64_t, uint64_t>(vs2, vs1, sat);
5090 break;
5091 }
5092 }
5093 set_rvv_vxsat(sat);
5094 RVV_VI_LOOP_END
5095 break;
5096 }
5097 case RO_V_VSADDU_VV:
5098 RVV_VI_VV_ULOOP({
5099 vd = vs2 + vs1;
5100 vd |= -(vd < vs2);
5101 })
5102 break;
5103 case RO_V_VSUB_VV: {
5104 RVV_VI_VV_LOOP({ vd = vs2 - vs1; })
5105 break;
5106 }
5107 case RO_V_VSSUB_VV: {
5108 RVV_VI_GENERAL_LOOP_BASE
5109 bool sat = false;
5110 switch (rvv_vsew()) {
5111 case E8: {
5112 VV_PARAMS(8);
5113 vd = sat_sub<int8_t, uint8_t>(vs2, vs1, sat);
5114 break;
5115 }
5116 case E16: {
5117 VV_PARAMS(16);
5118 vd = sat_sub<int16_t, uint16_t>(vs2, vs1, sat);
5119 break;
5120 }
5121 case E32: {
5122 VV_PARAMS(32);
5123 vd = sat_sub<int32_t, uint32_t>(vs2, vs1, sat);
5124 break;
5125 }
5126 default: {
5127 VV_PARAMS(64);
5128 vd = sat_sub<int64_t, uint64_t>(vs2, vs1, sat);
5129 break;
5130 }
5131 }
5132 set_rvv_vxsat(sat);
5133 RVV_VI_LOOP_END
5134 break;
5135 }
5136 case RO_V_VSSUBU_VV: {
5137 RVV_VI_GENERAL_LOOP_BASE
5138 bool sat = false;
5139 switch (rvv_vsew()) {
5140 case E8: {
5141 VV_UPARAMS(8);
5142 vd = sat_subu<uint8_t>(vs2, vs1, sat);
5143 break;
5144 }
5145 case E16: {
5146 VV_UPARAMS(16);
5147 vd = sat_subu<uint16_t>(vs2, vs1, sat);
5148 break;
5149 }
5150 case E32: {
5151 VV_UPARAMS(32);
5152 vd = sat_subu<uint32_t>(vs2, vs1, sat);
5153 break;
5154 }
5155 default: {
5156 VV_UPARAMS(64);
5157 vd = sat_subu<uint64_t>(vs2, vs1, sat);
5158 break;
5159 }
5160 }
5161 set_rvv_vxsat(sat);
5162 RVV_VI_LOOP_END
5163 break;
5164 }
5165 case RO_V_VAND_VV: {
5166 RVV_VI_VV_LOOP({ vd = vs1 & vs2; })
5167 break;
5168 }
5169 case RO_V_VOR_VV: {
5170 RVV_VI_VV_LOOP({ vd = vs1 | vs2; })
5171 break;
5172 }
5173 case RO_V_VXOR_VV: {
5174 RVV_VI_VV_LOOP({ vd = vs1 ^ vs2; })
5175 break;
5176 }
5177 case RO_V_VMAXU_VV: {
5178 RVV_VI_VV_ULOOP({
5179 if (vs1 <= vs2) {
5180 vd = vs2;
5181 } else {
5182 vd = vs1;
5183 }
5184 })
5185 break;
5186 }
5187 case RO_V_VMAX_VV: {
5188 RVV_VI_VV_LOOP({
5189 if (vs1 <= vs2) {
5190 vd = vs2;
5191 } else {
5192 vd = vs1;
5193 }
5194 })
5195 break;
5196 }
5197 case RO_V_VMINU_VV: {
5198 RVV_VI_VV_ULOOP({
5199 if (vs1 <= vs2) {
5200 vd = vs1;
5201 } else {
5202 vd = vs2;
5203 }
5204 })
5205 break;
5206 }
5207 case RO_V_VMIN_VV: {
5208 RVV_VI_VV_LOOP({
5209 if (vs1 <= vs2) {
5210 vd = vs1;
5211 } else {
5212 vd = vs2;
5213 }
5214 })
5215 break;
5216 }
5217 case RO_V_VMV_VV: {
5218 if (instr_.RvvVM()) {
5219 RVV_VI_VVXI_MERGE_LOOP({
5220 vd = vs1;
5221 USE(simm5);
5222 USE(vs2);
5223 USE(rs1);
5224 });
5225 } else {
5226 RVV_VI_VVXI_MERGE_LOOP({
5227 bool use_first = (Rvvelt<uint64_t>(0, (i / 64)) >> (i % 64)) & 0x1;
5228 vd = use_first ? vs1 : vs2;
5229 USE(simm5);
5230 USE(rs1);
5231 });
5232 }
5233 break;
5234 }
5235 case RO_V_VMSEQ_VV: {
5236 RVV_VI_VV_LOOP_CMP({ res = vs1 == vs2; })
5237 break;
5238 }
5239 case RO_V_VMSNE_VV: {
5240 RVV_VI_VV_LOOP_CMP({ res = vs1 != vs2; })
5241 break;
5242 }
5243 case RO_V_VMSLTU_VV: {
5244 RVV_VI_VV_ULOOP_CMP({ res = vs2 < vs1; })
5245 break;
5246 }
5247 case RO_V_VMSLT_VV: {
5248 RVV_VI_VV_LOOP_CMP({ res = vs2 < vs1; })
5249 break;
5250 }
5251 case RO_V_VMSLE_VV: {
5252 RVV_VI_VV_LOOP_CMP({ res = vs2 <= vs1; })
5253 break;
5254 }
5255 case RO_V_VMSLEU_VV: {
5256 RVV_VI_VV_ULOOP_CMP({ res = vs2 <= vs1; })
5257 break;
5258 }
5259 case RO_V_VADC_VV:
5260 if (instr_.RvvVM()) {
5261 RVV_VI_VV_LOOP_WITH_CARRY({
5262 auto& v0 = Rvvelt<uint64_t>(0, midx);
5263 vd = vs1 + vs2 + (v0 >> mpos) & 0x1;
5264 })
5265 } else {
5266 UNREACHABLE();
5267 }
5268 break;
5269 case RO_V_VSLL_VV: {
5270 RVV_VI_VV_LOOP({ vd = vs2 << vs1; })
5271 break;
5272 }
5273 case RO_V_VSRL_VV:
5274 RVV_VI_VV_ULOOP({ vd = vs2 >> vs1; })
5275 break;
5276 case RO_V_VSRA_VV:
5277 RVV_VI_VV_LOOP({ vd = vs2 >> vs1; })
5278 break;
5279 case RO_V_VSMUL_VV: {
5280 RVV_VI_GENERAL_LOOP_BASE
5281 RVV_VI_LOOP_MASK_SKIP()
5282 if (rvv_vsew() == E8) {
5283 VV_PARAMS(8);
5284 int16_t result = (int16_t)vs1 * (int16_t)vs2;
5285 uint8_t round = get_round(static_cast<int>(rvv_vxrm()), result, 7);
5286 result = (result >> 7) + round;
5287 vd = signed_saturation<int16_t, int8_t>(result, 8);
5288 } else if (rvv_vsew() == E16) {
5289 VV_PARAMS(16);
5290 int32_t result = (int32_t)vs1 * (int32_t)vs2;
5291 uint8_t round = get_round(static_cast<int>(rvv_vxrm()), result, 15);
5292 result = (result >> 15) + round;
5293 vd = signed_saturation<int32_t, int16_t>(result, 16);
5294 } else if (rvv_vsew() == E32) {
5295 VV_PARAMS(32);
5296 int64_t result = (int64_t)vs1 * (int64_t)vs2;
5297 uint8_t round = get_round(static_cast<int>(rvv_vxrm()), result, 31);
5298 result = (result >> 31) + round;
5299 vd = signed_saturation<int64_t, int32_t>(result, 32);
5300 } else if (rvv_vsew() == E64) {
5301 VV_PARAMS(64);
5302 __int128_t result = (__int128_t)vs1 * (__int128_t)vs2;
5303 uint8_t round = get_round(static_cast<int>(rvv_vxrm()), result, 63);
5304 result = (result >> 63) + round;
5305 vd = signed_saturation<__int128_t, int64_t>(result, 64);
5306 } else {
5307 UNREACHABLE();
5308 }
5309 RVV_VI_LOOP_END
5310 rvv_trace_vd();
5311 break;
5312 }
5313 case RO_V_VRGATHER_VV: {
5314 RVV_VI_GENERAL_LOOP_BASE
5315 CHECK_NE(rvv_vs1_reg(), rvv_vd_reg());
5316 CHECK_NE(rvv_vs2_reg(), rvv_vd_reg());
5317 switch (rvv_vsew()) {
5318 case E8: {
5319 auto vs1 = Rvvelt<uint8_t>(rvv_vs1_reg(), i);
5320 // if (i > 255) continue;
5321 Rvvelt<uint8_t>(rvv_vd_reg(), i, true) =
5322 vs1 >= rvv_vlmax() ? 0 : Rvvelt<uint8_t>(rvv_vs2_reg(), vs1);
5323 break;
5324 }
5325 case E16: {
5326 auto vs1 = Rvvelt<uint16_t>(rvv_vs1_reg(), i);
5327 Rvvelt<uint16_t>(rvv_vd_reg(), i, true) =
5328 vs1 >= rvv_vlmax() ? 0 : Rvvelt<uint16_t>(rvv_vs2_reg(), vs1);
5329 break;
5330 }
5331 case E32: {
5332 auto vs1 = Rvvelt<uint32_t>(rvv_vs1_reg(), i);
5333 Rvvelt<uint32_t>(rvv_vd_reg(), i, true) =
5334 vs1 >= rvv_vlmax() ? 0 : Rvvelt<uint32_t>(rvv_vs2_reg(), vs1);
5335 break;
5336 }
5337 default: {
5338 auto vs1 = Rvvelt<uint64_t>(rvv_vs1_reg(), i);
5339 Rvvelt<uint64_t>(rvv_vd_reg(), i, true) =
5340 vs1 >= rvv_vlmax() ? 0 : Rvvelt<uint64_t>(rvv_vs2_reg(), vs1);
5341 break;
5342 }
5343 }
5344 RVV_VI_LOOP_END;
5345 rvv_trace_vd();
5346 break;
5347 }
5348 default:
5349 // v8::base::EmbeddedVector<char, 256> buffer;
5350 // SNPrintF(trace_buf_, " ");
5351 // disasm::NameConverter converter;
5352 // disasm::Disassembler dasm(converter);
5353 // // Use a reasonably large buffer.
5354 // dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(&instr_));
5355
5356 // PrintF("EXECUTING 0x%08" PRIxPTR " %-44s\n",
5357 // reinterpret_cast<intptr_t>(&instr_), buffer.begin());
5358 UNIMPLEMENTED_RISCV();
5359 break;
5360 }
5361 set_rvv_vstart(0);
5362 }
5363
DecodeRvvIVI()5364 void Simulator::DecodeRvvIVI() {
5365 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_IVI);
5366 switch (instr_.InstructionBits() & kVTypeMask) {
5367 case RO_V_VADD_VI: {
5368 RVV_VI_VI_LOOP({ vd = simm5 + vs2; })
5369 break;
5370 }
5371 case RO_V_VSADD_VI: {
5372 RVV_VI_GENERAL_LOOP_BASE
5373 bool sat = false;
5374 switch (rvv_vsew()) {
5375 case E8: {
5376 VI_PARAMS(8);
5377 vd = sat_add<int8_t, uint8_t>(vs2, simm5, sat);
5378 break;
5379 }
5380 case E16: {
5381 VI_PARAMS(16);
5382 vd = sat_add<int16_t, uint16_t>(vs2, simm5, sat);
5383 break;
5384 }
5385 case E32: {
5386 VI_PARAMS(32);
5387 vd = sat_add<int32_t, uint32_t>(vs2, simm5, sat);
5388 break;
5389 }
5390 default: {
5391 VI_PARAMS(64);
5392 vd = sat_add<int64_t, uint64_t>(vs2, simm5, sat);
5393 break;
5394 }
5395 }
5396 set_rvv_vxsat(sat);
5397 RVV_VI_LOOP_END
5398 break;
5399 }
5400 case RO_V_VSADDU_VI: {
5401 RVV_VI_VI_ULOOP({
5402 vd = vs2 + uimm5;
5403 vd |= -(vd < vs2);
5404 })
5405 break;
5406 }
5407 case RO_V_VRSUB_VI: {
5408 RVV_VI_VI_LOOP({ vd = simm5 - vs2; })
5409 break;
5410 }
5411 case RO_V_VAND_VI: {
5412 RVV_VI_VI_LOOP({ vd = simm5 & vs2; })
5413 break;
5414 }
5415 case RO_V_VOR_VI: {
5416 RVV_VI_VI_LOOP({ vd = simm5 | vs2; })
5417 break;
5418 }
5419 case RO_V_VXOR_VI: {
5420 RVV_VI_VI_LOOP({ vd = simm5 ^ vs2; })
5421 break;
5422 }
5423 case RO_V_VMV_VI:
5424 if (instr_.RvvVM()) {
5425 RVV_VI_VVXI_MERGE_LOOP({
5426 vd = simm5;
5427 USE(vs1);
5428 USE(vs2);
5429 USE(rs1);
5430 });
5431 } else {
5432 RVV_VI_VVXI_MERGE_LOOP({
5433 bool use_first = (Rvvelt<uint64_t>(0, (i / 64)) >> (i % 64)) & 0x1;
5434 vd = use_first ? simm5 : vs2;
5435 USE(vs1);
5436 USE(rs1);
5437 });
5438 }
5439 break;
5440 case RO_V_VMSEQ_VI:
5441 RVV_VI_VI_LOOP_CMP({ res = simm5 == vs2; })
5442 break;
5443 case RO_V_VMSNE_VI:
5444 RVV_VI_VI_LOOP_CMP({ res = simm5 != vs2; })
5445 break;
5446 case RO_V_VMSLEU_VI:
5447 RVV_VI_VI_ULOOP_CMP({ res = vs2 <= uimm5; })
5448 break;
5449 case RO_V_VMSLE_VI:
5450 RVV_VI_VI_LOOP_CMP({ res = vs2 <= simm5; })
5451 break;
5452 case RO_V_VMSGT_VI:
5453 RVV_VI_VI_LOOP_CMP({ res = vs2 > simm5; })
5454 break;
5455 case RO_V_VSLIDEDOWN_VI: {
5456 RVV_VI_CHECK_SLIDE(false);
5457 const uint8_t sh = instr_.RvvUimm5();
5458 RVV_VI_GENERAL_LOOP_BASE
5459
5460 reg_t offset = 0;
5461 bool is_valid = (i + sh) < rvv_vlmax();
5462
5463 if (is_valid) {
5464 offset = sh;
5465 }
5466
5467 switch (rvv_vsew()) {
5468 case E8: {
5469 VI_XI_SLIDEDOWN_PARAMS(8, offset);
5470 vd = is_valid ? vs2 : 0;
5471 } break;
5472 case E16: {
5473 VI_XI_SLIDEDOWN_PARAMS(16, offset);
5474 vd = is_valid ? vs2 : 0;
5475 } break;
5476 case E32: {
5477 VI_XI_SLIDEDOWN_PARAMS(32, offset);
5478 vd = is_valid ? vs2 : 0;
5479 } break;
5480 default: {
5481 VI_XI_SLIDEDOWN_PARAMS(64, offset);
5482 vd = is_valid ? vs2 : 0;
5483 } break;
5484 }
5485 RVV_VI_LOOP_END
5486 rvv_trace_vd();
5487 } break;
5488 case RO_V_VSLIDEUP_VI: {
5489 RVV_VI_CHECK_SLIDE(true);
5490
5491 const uint8_t offset = instr_.RvvUimm5();
5492 RVV_VI_GENERAL_LOOP_BASE
5493 if (rvv_vstart() < offset && i < offset) continue;
5494
5495 switch (rvv_vsew()) {
5496 case E8: {
5497 VI_XI_SLIDEUP_PARAMS(8, offset);
5498 vd = vs2;
5499 } break;
5500 case E16: {
5501 VI_XI_SLIDEUP_PARAMS(16, offset);
5502 vd = vs2;
5503 } break;
5504 case E32: {
5505 VI_XI_SLIDEUP_PARAMS(32, offset);
5506 vd = vs2;
5507 } break;
5508 default: {
5509 VI_XI_SLIDEUP_PARAMS(64, offset);
5510 vd = vs2;
5511 } break;
5512 }
5513 RVV_VI_LOOP_END
5514 rvv_trace_vd();
5515 } break;
5516 case RO_V_VSRL_VI:
5517 RVV_VI_VI_ULOOP({ vd = vs2 >> uimm5; })
5518 break;
5519 case RO_V_VSRA_VI:
5520 RVV_VI_VI_LOOP({ vd = vs2 >> (simm5 & (rvv_sew() - 1) & 0x1f); })
5521 break;
5522 case RO_V_VSLL_VI:
5523 RVV_VI_VI_ULOOP({ vd = vs2 << uimm5; })
5524 break;
5525 case RO_V_VADC_VI:
5526 if (instr_.RvvVM()) {
5527 RVV_VI_XI_LOOP_WITH_CARRY({
5528 auto& v0 = Rvvelt<uint64_t>(0, midx);
5529 vd = simm5 + vs2 + (v0 >> mpos) & 0x1;
5530 USE(rs1);
5531 })
5532 } else {
5533 UNREACHABLE();
5534 }
5535 break;
5536 case RO_V_VNCLIP_WI:
5537 RVV_VN_CLIP_VI_LOOP()
5538 break;
5539 case RO_V_VNCLIPU_WI:
5540 RVV_VN_CLIPU_VI_LOOP()
5541 break;
5542 default:
5543 UNIMPLEMENTED_RISCV();
5544 break;
5545 }
5546 }
5547
DecodeRvvIVX()5548 void Simulator::DecodeRvvIVX() {
5549 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_IVX);
5550 switch (instr_.InstructionBits() & kVTypeMask) {
5551 case RO_V_VADD_VX: {
5552 RVV_VI_VX_LOOP({ vd = rs1 + vs2; })
5553 break;
5554 }
5555 case RO_V_VSADD_VX: {
5556 RVV_VI_GENERAL_LOOP_BASE
5557 bool sat = false;
5558 switch (rvv_vsew()) {
5559 case E8: {
5560 VX_PARAMS(8);
5561 vd = sat_add<int8_t, uint8_t>(vs2, rs1, sat);
5562 break;
5563 }
5564 case E16: {
5565 VX_PARAMS(16);
5566 vd = sat_add<int16_t, uint16_t>(vs2, rs1, sat);
5567 break;
5568 }
5569 case E32: {
5570 VX_PARAMS(32);
5571 vd = sat_add<int32_t, uint32_t>(vs2, rs1, sat);
5572 break;
5573 }
5574 default: {
5575 VX_PARAMS(64);
5576 vd = sat_add<int64_t, uint64_t>(vs2, rs1, sat);
5577 break;
5578 }
5579 }
5580 set_rvv_vxsat(sat);
5581 RVV_VI_LOOP_END
5582 break;
5583 }
5584 case RO_V_VSADDU_VX: {
5585 RVV_VI_VX_ULOOP({
5586 vd = vs2 + rs1;
5587 vd |= -(vd < vs2);
5588 })
5589 break;
5590 }
5591 case RO_V_VSUB_VX: {
5592 RVV_VI_VX_LOOP({ vd = vs2 - rs1; })
5593 break;
5594 }
5595 case RO_V_VSSUB_VX: {
5596 RVV_VI_GENERAL_LOOP_BASE
5597 bool sat = false;
5598 switch (rvv_vsew()) {
5599 case E8: {
5600 VX_PARAMS(8);
5601 vd = sat_sub<int8_t, uint8_t>(vs2, rs1, sat);
5602 break;
5603 }
5604 case E16: {
5605 VX_PARAMS(16);
5606 vd = sat_sub<int16_t, uint16_t>(vs2, rs1, sat);
5607 break;
5608 }
5609 case E32: {
5610 VX_PARAMS(32);
5611 vd = sat_sub<int32_t, uint32_t>(vs2, rs1, sat);
5612 break;
5613 }
5614 default: {
5615 VX_PARAMS(64);
5616 vd = sat_sub<int64_t, uint64_t>(vs2, rs1, sat);
5617 break;
5618 }
5619 }
5620 set_rvv_vxsat(sat);
5621 RVV_VI_LOOP_END
5622 break;
5623 }
5624 case RO_V_VRSUB_VX: {
5625 RVV_VI_VX_LOOP({ vd = rs1 - vs2; })
5626 break;
5627 }
5628 case RO_V_VAND_VX: {
5629 RVV_VI_VX_LOOP({ vd = rs1 & vs2; })
5630 break;
5631 }
5632 case RO_V_VOR_VX: {
5633 RVV_VI_VX_LOOP({ vd = rs1 | vs2; })
5634 break;
5635 }
5636 case RO_V_VXOR_VX: {
5637 RVV_VI_VX_LOOP({ vd = rs1 ^ vs2; })
5638 break;
5639 }
5640 case RO_V_VMAX_VX: {
5641 RVV_VI_VX_LOOP({
5642 if (rs1 <= vs2) {
5643 vd = vs2;
5644 } else {
5645 vd = rs1;
5646 }
5647 })
5648 break;
5649 }
5650 case RO_V_VMAXU_VX: {
5651 RVV_VI_VX_ULOOP({
5652 if (rs1 <= vs2) {
5653 vd = vs2;
5654 } else {
5655 vd = rs1;
5656 }
5657 })
5658 break;
5659 }
5660 case RO_V_VMINU_VX: {
5661 RVV_VI_VX_ULOOP({
5662 if (rs1 <= vs2) {
5663 vd = rs1;
5664 } else {
5665 vd = vs2;
5666 }
5667 })
5668 break;
5669 }
5670 case RO_V_VMIN_VX: {
5671 RVV_VI_VX_LOOP({
5672 if (rs1 <= vs2) {
5673 vd = rs1;
5674 } else {
5675 vd = vs2;
5676 }
5677 })
5678 break;
5679 }
5680 case RO_V_VMV_VX:
5681 if (instr_.RvvVM()) {
5682 RVV_VI_VVXI_MERGE_LOOP({
5683 vd = rs1;
5684 USE(vs1);
5685 USE(vs2);
5686 USE(simm5);
5687 });
5688 } else {
5689 RVV_VI_VVXI_MERGE_LOOP({
5690 bool use_first = (Rvvelt<uint64_t>(0, (i / 64)) >> (i % 64)) & 0x1;
5691 vd = use_first ? rs1 : vs2;
5692 USE(vs1);
5693 USE(simm5);
5694 });
5695 }
5696 break;
5697 case RO_V_VMSEQ_VX:
5698 RVV_VI_VX_LOOP_CMP({ res = vs2 == rs1; })
5699 break;
5700 case RO_V_VMSNE_VX:
5701 RVV_VI_VX_LOOP_CMP({ res = vs2 != rs1; })
5702 break;
5703 case RO_V_VMSLT_VX:
5704 RVV_VI_VX_LOOP_CMP({ res = vs2 < rs1; })
5705 break;
5706 case RO_V_VMSLTU_VX:
5707 RVV_VI_VX_ULOOP_CMP({ res = vs2 < rs1; })
5708 break;
5709 case RO_V_VMSLE_VX:
5710 RVV_VI_VX_LOOP_CMP({ res = vs2 <= rs1; })
5711 break;
5712 case RO_V_VMSLEU_VX:
5713 RVV_VI_VX_ULOOP_CMP({ res = vs2 <= rs1; })
5714 break;
5715 case RO_V_VMSGT_VX:
5716 RVV_VI_VX_LOOP_CMP({ res = vs2 > rs1; })
5717 break;
5718 case RO_V_VMSGTU_VX:
5719 RVV_VI_VX_ULOOP_CMP({ res = vs2 > rs1; })
5720 break;
5721 case RO_V_VSLIDEDOWN_VX:
5722 UNIMPLEMENTED_RISCV();
5723 break;
5724 case RO_V_VADC_VX:
5725 if (instr_.RvvVM()) {
5726 RVV_VI_XI_LOOP_WITH_CARRY({
5727 auto& v0 = Rvvelt<uint64_t>(0, midx);
5728 vd = rs1 + vs2 + (v0 >> mpos) & 0x1;
5729 USE(simm5);
5730 })
5731 } else {
5732 UNREACHABLE();
5733 }
5734 break;
5735 case RO_V_VSLL_VX: {
5736 RVV_VI_VX_LOOP({ vd = vs2 << rs1; })
5737 break;
5738 }
5739 case RO_V_VSRL_VX: {
5740 RVV_VI_VX_ULOOP({ vd = (vs2 >> (rs1 & (rvv_sew() - 1))); })
5741 break;
5742 }
5743 case RO_V_VSRA_VX: {
5744 RVV_VI_VX_LOOP({ vd = ((vs2) >> (rs1 & (rvv_sew() - 1))); })
5745 break;
5746 }
5747 default:
5748 UNIMPLEMENTED_RISCV();
5749 break;
5750 }
5751 }
5752
DecodeRvvMVV()5753 void Simulator::DecodeRvvMVV() {
5754 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_MVV);
5755 switch (instr_.InstructionBits() & kVTypeMask) {
5756 case RO_V_VMUNARY0: {
5757 if (instr_.Vs1Value() == VID_V) {
5758 CHECK(rvv_vsew() >= E8 && rvv_vsew() <= E64);
5759 uint8_t rd_num = rvv_vd_reg();
5760 require_align(rd_num, rvv_vflmul());
5761 require_vm;
5762 for (uint8_t i = rvv_vstart(); i < rvv_vl(); ++i) {
5763 RVV_VI_LOOP_MASK_SKIP();
5764 switch (rvv_vsew()) {
5765 case E8:
5766 Rvvelt<uint8_t>(rd_num, i, true) = i;
5767 break;
5768 case E16:
5769 Rvvelt<uint16_t>(rd_num, i, true) = i;
5770 break;
5771 case E32:
5772 Rvvelt<uint32_t>(rd_num, i, true) = i;
5773 break;
5774 default:
5775 Rvvelt<uint64_t>(rd_num, i, true) = i;
5776 break;
5777 }
5778 }
5779 set_rvv_vstart(0);
5780 } else {
5781 UNIMPLEMENTED_RISCV();
5782 }
5783 break;
5784 }
5785 case RO_V_VMUL_VV: {
5786 RVV_VI_VV_LOOP({ vd = vs2 * vs1; })
5787 break;
5788 }
5789 case RO_V_VWMUL_VV: {
5790 RVV_VI_CHECK_DSS(true);
5791 RVV_VI_VV_LOOP_WIDEN({
5792 VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, int);
5793 USE(vd);
5794 })
5795 break;
5796 }
5797 case RO_V_VWMULU_VV: {
5798 RVV_VI_CHECK_DSS(true);
5799 RVV_VI_VV_LOOP_WIDEN({
5800 VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, uint);
5801 USE(vd);
5802 })
5803 break;
5804 }
5805 case RO_V_VMULHU_VV: {
5806 RVV_VI_VV_LOOP({ vd = ((__uint128_t)vs2 * vs1) >> rvv_sew(); })
5807 break;
5808 }
5809 case RO_V_VMULH_VV: {
5810 RVV_VI_VV_LOOP({ vd = ((__int128_t)vs2 * vs1) >> rvv_sew(); })
5811 break;
5812 }
5813 case RO_V_VDIV_VV: {
5814 RVV_VI_VV_LOOP({ vd = vs2 / vs1; })
5815 break;
5816 }
5817 case RO_V_VDIVU_VV: {
5818 RVV_VI_VV_LOOP({ vd = vs2 / vs1; })
5819 break;
5820 }
5821 case RO_V_VWXUNARY0: {
5822 if (rvv_vs1_reg() == 0) {
5823 switch (rvv_vsew()) {
5824 case E8:
5825 set_rd(Rvvelt<type_sew_t<8>::type>(rvv_vs2_reg(), 0));
5826 break;
5827 case E16:
5828 set_rd(Rvvelt<type_sew_t<16>::type>(rvv_vs2_reg(), 0));
5829 break;
5830 case E32:
5831 set_rd(Rvvelt<type_sew_t<32>::type>(rvv_vs2_reg(), 0));
5832 break;
5833 case E64:
5834 set_rd(Rvvelt<type_sew_t<64>::type>(rvv_vs2_reg(), 0));
5835 break;
5836 default:
5837 UNREACHABLE();
5838 }
5839 set_rvv_vstart(0);
5840 rvv_trace_vd();
5841 } else if (rvv_vs1_reg() == 0b10000) {
5842 uint64_t cnt = 0;
5843 RVV_VI_GENERAL_LOOP_BASE
5844 RVV_VI_LOOP_MASK_SKIP()
5845 const uint8_t idx = i / 64;
5846 const uint8_t pos = i % 64;
5847 bool mask = (Rvvelt<uint64_t>(rvv_vs2_reg(), idx) >> pos) & 0x1;
5848 if (mask) cnt++;
5849 RVV_VI_LOOP_END
5850 set_register(rd_reg(), cnt);
5851 rvv_trace_vd();
5852 } else if (rvv_vs1_reg() == 0b10001) {
5853 int64_t index = -1;
5854 RVV_VI_GENERAL_LOOP_BASE
5855 RVV_VI_LOOP_MASK_SKIP()
5856 const uint8_t idx = i / 64;
5857 const uint8_t pos = i % 64;
5858 bool mask = (Rvvelt<uint64_t>(rvv_vs2_reg(), idx) >> pos) & 0x1;
5859 if (mask) {
5860 index = i;
5861 break;
5862 }
5863 RVV_VI_LOOP_END
5864 set_register(rd_reg(), index);
5865 rvv_trace_vd();
5866 } else {
5867 v8::base::EmbeddedVector<char, 256> buffer;
5868 disasm::NameConverter converter;
5869 disasm::Disassembler dasm(converter);
5870 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(&instr_));
5871 PrintF("EXECUTING 0x%08" PRIxPTR " %-44s\n",
5872 reinterpret_cast<intptr_t>(&instr_), buffer.begin());
5873 UNIMPLEMENTED_RISCV();
5874 }
5875 } break;
5876 case RO_V_VREDMAXU:
5877 RVV_VI_VV_ULOOP_REDUCTION(
5878 { vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; })
5879 break;
5880 case RO_V_VREDMAX:
5881 RVV_VI_VV_LOOP_REDUCTION(
5882 { vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; })
5883 break;
5884 case RO_V_VREDMINU:
5885 RVV_VI_VV_ULOOP_REDUCTION(
5886 { vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; })
5887 break;
5888 case RO_V_VREDMIN:
5889 RVV_VI_VV_LOOP_REDUCTION(
5890 { vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; })
5891 break;
5892 case RO_V_VXUNARY0:
5893 if (rvv_vs1_reg() == 0b00010) {
5894 RVV_VI_VIE_8_LOOP(false);
5895 } else if (rvv_vs1_reg() == 0b00011) {
5896 RVV_VI_VIE_8_LOOP(true);
5897 } else if (rvv_vs1_reg() == 0b00100) {
5898 RVV_VI_VIE_4_LOOP(false);
5899 } else if (rvv_vs1_reg() == 0b00101) {
5900 RVV_VI_VIE_4_LOOP(true);
5901 } else if (rvv_vs1_reg() == 0b00110) {
5902 RVV_VI_VIE_2_LOOP(false);
5903 } else if (rvv_vs1_reg() == 0b00111) {
5904 RVV_VI_VIE_2_LOOP(true);
5905 } else {
5906 UNSUPPORTED_RISCV();
5907 }
5908 break;
5909 case RO_V_VWADDU_VV:
5910 RVV_VI_CHECK_DSS(true);
5911 RVV_VI_VV_LOOP_WIDEN({
5912 VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, uint);
5913 USE(vd);
5914 })
5915 break;
5916 case RO_V_VWADD_VV:
5917 RVV_VI_CHECK_DSS(true);
5918 RVV_VI_VV_LOOP_WIDEN({
5919 VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, int);
5920 USE(vd);
5921 })
5922 break;
5923 case RO_V_VCOMPRESS_VV: {
5924 CHECK_EQ(rvv_vstart(), 0);
5925 require_align(rvv_vd_reg(), rvv_vflmul());
5926 require_align(rvv_vs2_reg(), rvv_vflmul());
5927 require(rvv_vd_reg() != rvv_vs2_reg());
5928 require_noover(rvv_vd_reg(), rvv_vflmul(), rvv_vs1_reg(), 1);
5929
5930 reg_t pos = 0;
5931
5932 RVV_VI_GENERAL_LOOP_BASE
5933 const uint64_t midx = i / 64;
5934 const uint64_t mpos = i % 64;
5935
5936 bool do_mask = (Rvvelt<uint64_t>(rvv_vs1_reg(), midx) >> mpos) & 0x1;
5937 if (do_mask) {
5938 switch (rvv_vsew()) {
5939 case E8:
5940 Rvvelt<uint8_t>(rvv_vd_reg(), pos, true) =
5941 Rvvelt<uint8_t>(rvv_vs2_reg(), i);
5942 break;
5943 case E16:
5944 Rvvelt<uint16_t>(rvv_vd_reg(), pos, true) =
5945 Rvvelt<uint16_t>(rvv_vs2_reg(), i);
5946 break;
5947 case E32:
5948 Rvvelt<uint32_t>(rvv_vd_reg(), pos, true) =
5949 Rvvelt<uint32_t>(rvv_vs2_reg(), i);
5950 break;
5951 default:
5952 Rvvelt<uint64_t>(rvv_vd_reg(), pos, true) =
5953 Rvvelt<uint64_t>(rvv_vs2_reg(), i);
5954 break;
5955 }
5956
5957 ++pos;
5958 }
5959 RVV_VI_LOOP_END;
5960 rvv_trace_vd();
5961 } break;
5962 default:
5963 v8::base::EmbeddedVector<char, 256> buffer;
5964 disasm::NameConverter converter;
5965 disasm::Disassembler dasm(converter);
5966 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(&instr_));
5967 PrintF("EXECUTING 0x%08" PRIxPTR " %-44s\n",
5968 reinterpret_cast<intptr_t>(&instr_), buffer.begin());
5969 UNIMPLEMENTED_RISCV();
5970 break;
5971 }
5972 }
5973
DecodeRvvMVX()5974 void Simulator::DecodeRvvMVX() {
5975 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_MVX);
5976 switch (instr_.InstructionBits() & kVTypeMask) {
5977 case RO_V_VRXUNARY0:
5978 if (instr_.Vs2Value() == 0x0) {
5979 if (rvv_vl() > 0 && rvv_vstart() < rvv_vl()) {
5980 switch (rvv_vsew()) {
5981 case E8:
5982 Rvvelt<uint8_t>(rvv_vd_reg(), 0, true) =
5983 (uint8_t)get_register(rs1_reg());
5984 break;
5985 case E16:
5986 Rvvelt<uint16_t>(rvv_vd_reg(), 0, true) =
5987 (uint16_t)get_register(rs1_reg());
5988 break;
5989 case E32:
5990 Rvvelt<uint32_t>(rvv_vd_reg(), 0, true) =
5991 (uint32_t)get_register(rs1_reg());
5992 break;
5993 case E64:
5994 Rvvelt<uint64_t>(rvv_vd_reg(), 0, true) =
5995 (uint64_t)get_register(rs1_reg());
5996 break;
5997 default:
5998 UNREACHABLE();
5999 }
6000 // set_rvv_vl(0);
6001 }
6002 set_rvv_vstart(0);
6003 rvv_trace_vd();
6004 } else {
6005 UNSUPPORTED_RISCV();
6006 }
6007 break;
6008 case RO_V_VDIV_VX: {
6009 RVV_VI_VX_LOOP({ vd = vs2 / rs1; })
6010 break;
6011 }
6012 case RO_V_VDIVU_VX: {
6013 RVV_VI_VX_ULOOP({ vd = vs2 / rs1; })
6014 break;
6015 }
6016 case RO_V_VMUL_VX: {
6017 RVV_VI_VX_LOOP({ vd = vs2 * rs1; })
6018 break;
6019 }
6020 case RO_V_VWADDUW_VX: {
6021 RVV_VI_CHECK_DDS(false);
6022 RVV_VI_VX_LOOP_WIDEN({
6023 VI_WIDE_WVX_OP(rs1, +, uint);
6024 USE(vd);
6025 USE(vs2);
6026 })
6027 break;
6028 }
6029 default:
6030 v8::base::EmbeddedVector<char, 256> buffer;
6031 disasm::NameConverter converter;
6032 disasm::Disassembler dasm(converter);
6033 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(&instr_));
6034 PrintF("EXECUTING 0x%08" PRIxPTR " %-44s\n",
6035 reinterpret_cast<intptr_t>(&instr_), buffer.begin());
6036 UNIMPLEMENTED_RISCV();
6037 break;
6038 }
6039 }
6040
DecodeRvvFVV()6041 void Simulator::DecodeRvvFVV() {
6042 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_FVV);
6043 switch (instr_.InstructionBits() & kVTypeMask) {
6044 case RO_V_VFDIV_VV: {
6045 RVV_VI_VFP_VV_LOOP(
6046 { UNIMPLEMENTED(); },
6047 {
6048 // TODO(riscv): use rm value (round mode)
6049 auto fn = [this](float vs1, float vs2) {
6050 if (is_invalid_fdiv(vs1, vs2)) {
6051 this->set_fflags(kInvalidOperation);
6052 return std::numeric_limits<float>::quiet_NaN();
6053 } else if (vs1 == 0.0f) {
6054 this->set_fflags(kDivideByZero);
6055 return (std::signbit(vs1) == std::signbit(vs2)
6056 ? std::numeric_limits<float>::infinity()
6057 : -std::numeric_limits<float>::infinity());
6058 } else {
6059 return vs2 / vs1;
6060 }
6061 };
6062 auto alu_out = fn(vs1, vs2);
6063 // if any input or result is NaN, the result is quiet_NaN
6064 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6065 // signaling_nan sets kInvalidOperation bit
6066 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6067 set_fflags(kInvalidOperation);
6068 alu_out = std::numeric_limits<float>::quiet_NaN();
6069 }
6070 vd = alu_out;
6071 },
6072 {
6073 // TODO(riscv): use rm value (round mode)
6074 auto fn = [this](double vs1, double vs2) {
6075 if (is_invalid_fdiv(vs1, vs2)) {
6076 this->set_fflags(kInvalidOperation);
6077 return std::numeric_limits<double>::quiet_NaN();
6078 } else if (vs1 == 0.0f) {
6079 this->set_fflags(kDivideByZero);
6080 return (std::signbit(vs1) == std::signbit(vs2)
6081 ? std::numeric_limits<double>::infinity()
6082 : -std::numeric_limits<double>::infinity());
6083 } else {
6084 return vs2 / vs1;
6085 }
6086 };
6087 auto alu_out = fn(vs1, vs2);
6088 // if any input or result is NaN, the result is quiet_NaN
6089 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6090 // signaling_nan sets kInvalidOperation bit
6091 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6092 set_fflags(kInvalidOperation);
6093 alu_out = std::numeric_limits<double>::quiet_NaN();
6094 }
6095 vd = alu_out;
6096 })
6097 break;
6098 }
6099 case RO_V_VFMUL_VV: {
6100 RVV_VI_VFP_VV_LOOP(
6101 { UNIMPLEMENTED(); },
6102 {
6103 // TODO(riscv): use rm value (round mode)
6104 auto fn = [this](double drs1, double drs2) {
6105 if (is_invalid_fmul(drs1, drs2)) {
6106 this->set_fflags(kInvalidOperation);
6107 return std::numeric_limits<double>::quiet_NaN();
6108 } else {
6109 return drs1 * drs2;
6110 }
6111 };
6112 auto alu_out = fn(vs1, vs2);
6113 // if any input or result is NaN, the result is quiet_NaN
6114 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6115 // signaling_nan sets kInvalidOperation bit
6116 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6117 set_fflags(kInvalidOperation);
6118 alu_out = std::numeric_limits<float>::quiet_NaN();
6119 }
6120 vd = alu_out;
6121 },
6122 {
6123 // TODO(riscv): use rm value (round mode)
6124 auto fn = [this](double drs1, double drs2) {
6125 if (is_invalid_fmul(drs1, drs2)) {
6126 this->set_fflags(kInvalidOperation);
6127 return std::numeric_limits<double>::quiet_NaN();
6128 } else {
6129 return drs1 * drs2;
6130 }
6131 };
6132 auto alu_out = fn(vs1, vs2);
6133 // if any input or result is NaN, the result is quiet_NaN
6134 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6135 // signaling_nan sets kInvalidOperation bit
6136 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6137 set_fflags(kInvalidOperation);
6138 alu_out = std::numeric_limits<double>::quiet_NaN();
6139 }
6140 vd = alu_out;
6141 })
6142 break;
6143 }
6144 case RO_V_VFUNARY0:
6145 switch (instr_.Vs1Value()) {
6146 case VFCVT_X_F_V:
6147 RVV_VI_VFP_VF_LOOP(
6148 { UNIMPLEMENTED(); },
6149 {
6150 Rvvelt<int32_t>(rvv_vd_reg(), i) =
6151 RoundF2IHelper<int32_t>(vs2, read_csr_value(csr_frm));
6152 USE(vd);
6153 USE(fs1);
6154 },
6155 {
6156 Rvvelt<int64_t>(rvv_vd_reg(), i) =
6157 RoundF2IHelper<int64_t>(vs2, read_csr_value(csr_frm));
6158 USE(vd);
6159 USE(fs1);
6160 })
6161 break;
6162 case VFCVT_XU_F_V:
6163 RVV_VI_VFP_VF_LOOP(
6164 { UNIMPLEMENTED(); },
6165 {
6166 Rvvelt<uint32_t>(rvv_vd_reg(), i) =
6167 RoundF2IHelper<uint32_t>(vs2, read_csr_value(csr_frm));
6168 USE(vd);
6169 USE(fs1);
6170 },
6171 {
6172 Rvvelt<uint64_t>(rvv_vd_reg(), i) =
6173 RoundF2IHelper<uint64_t>(vs2, read_csr_value(csr_frm));
6174 USE(vd);
6175 USE(fs1);
6176 })
6177 break;
6178 case VFCVT_F_XU_V:
6179 RVV_VI_VFP_VF_LOOP({ UNIMPLEMENTED(); },
6180 {
6181 auto vs2_i = Rvvelt<uint32_t>(rvv_vs2_reg(), i);
6182 vd = static_cast<float>(vs2_i);
6183 USE(vs2);
6184 USE(fs1);
6185 },
6186 {
6187 auto vs2_i = Rvvelt<uint64_t>(rvv_vs2_reg(), i);
6188 vd = static_cast<double>(vs2_i);
6189 USE(vs2);
6190 USE(fs1);
6191 })
6192 break;
6193 case VFCVT_F_X_V:
6194 RVV_VI_VFP_VF_LOOP({ UNIMPLEMENTED(); },
6195 {
6196 auto vs2_i = Rvvelt<int32_t>(rvv_vs2_reg(), i);
6197 vd = static_cast<float>(vs2_i);
6198 USE(vs2);
6199 USE(fs1);
6200 },
6201 {
6202 auto vs2_i = Rvvelt<int64_t>(rvv_vs2_reg(), i);
6203 vd = static_cast<double>(vs2_i);
6204 USE(vs2);
6205 USE(fs1);
6206 })
6207 break;
6208 case VFNCVT_F_F_W:
6209 RVV_VI_VFP_CVT_SCALE(
6210 { UNREACHABLE(); }, { UNREACHABLE(); },
6211 {
6212 auto vs2 = Rvvelt<double>(rvv_vs2_reg(), i);
6213 Rvvelt<float>(rvv_vd_reg(), i, true) =
6214 CanonicalizeDoubleToFloatOperation(
6215 [](double drs) { return static_cast<float>(drs); },
6216 vs2);
6217 },
6218 { ; }, { ; }, { ; }, false, (rvv_vsew() >= E16))
6219 break;
6220 case VFNCVT_X_F_W:
6221 RVV_VI_VFP_CVT_SCALE(
6222 { UNREACHABLE(); }, { UNREACHABLE(); },
6223 {
6224 auto vs2 = Rvvelt<double>(rvv_vs2_reg(), i);
6225 int32_t& vd = Rvvelt<int32_t>(rvv_vd_reg(), i, true);
6226 vd = RoundF2IHelper<int32_t>(vs2, read_csr_value(csr_frm));
6227 },
6228 { ; }, { ; }, { ; }, false, (rvv_vsew() <= E32))
6229 break;
6230 case VFNCVT_XU_F_W:
6231 RVV_VI_VFP_CVT_SCALE(
6232 { UNREACHABLE(); }, { UNREACHABLE(); },
6233 {
6234 auto vs2 = Rvvelt<double>(rvv_vs2_reg(), i);
6235 uint32_t& vd = Rvvelt<uint32_t>(rvv_vd_reg(), i, true);
6236 vd = RoundF2IHelper<uint32_t>(vs2, read_csr_value(csr_frm));
6237 },
6238 { ; }, { ; }, { ; }, false, (rvv_vsew() <= E32))
6239 break;
6240 case VFWCVT_F_X_V:
6241 RVV_VI_VFP_CVT_SCALE({ UNREACHABLE(); },
6242 {
6243 auto vs2 = Rvvelt<int16_t>(rvv_vs2_reg(), i);
6244 Rvvelt<float32_t>(rvv_vd_reg(), i, true) =
6245 static_cast<float>(vs2);
6246 },
6247 {
6248 auto vs2 = Rvvelt<int32_t>(rvv_vs2_reg(), i);
6249 Rvvelt<double>(rvv_vd_reg(), i, true) =
6250 static_cast<double>(vs2);
6251 },
6252 { ; }, { ; }, { ; }, true, (rvv_vsew() >= E8))
6253 break;
6254 case VFWCVT_F_XU_V:
6255 RVV_VI_VFP_CVT_SCALE({ UNREACHABLE(); },
6256 {
6257 auto vs2 = Rvvelt<uint16_t>(rvv_vs2_reg(), i);
6258 Rvvelt<float32_t>(rvv_vd_reg(), i, true) =
6259 static_cast<float>(vs2);
6260 },
6261 {
6262 auto vs2 = Rvvelt<uint32_t>(rvv_vs2_reg(), i);
6263 Rvvelt<double>(rvv_vd_reg(), i, true) =
6264 static_cast<double>(vs2);
6265 },
6266 { ; }, { ; }, { ; }, true, (rvv_vsew() >= E8))
6267 break;
6268 case VFWCVT_XU_F_V:
6269 RVV_VI_VFP_CVT_SCALE({ UNREACHABLE(); }, { UNREACHABLE(); },
6270 {
6271 auto vs2 = Rvvelt<float32_t>(rvv_vs2_reg(), i);
6272 Rvvelt<uint64_t>(rvv_vd_reg(), i, true) =
6273 static_cast<uint64_t>(vs2);
6274 },
6275 { ; }, { ; }, { ; }, true, (rvv_vsew() >= E16))
6276 break;
6277 case VFWCVT_X_F_V:
6278 RVV_VI_VFP_CVT_SCALE({ UNREACHABLE(); }, { UNREACHABLE(); },
6279 {
6280 auto vs2 = Rvvelt<float32_t>(rvv_vs2_reg(), i);
6281 Rvvelt<int64_t>(rvv_vd_reg(), i, true) =
6282 static_cast<int64_t>(vs2);
6283 },
6284 { ; }, { ; }, { ; }, true, (rvv_vsew() >= E16))
6285 break;
6286 case VFWCVT_F_F_V:
6287 RVV_VI_VFP_CVT_SCALE({ UNREACHABLE(); }, { UNREACHABLE(); },
6288 {
6289 auto vs2 = Rvvelt<float32_t>(rvv_vs2_reg(), i);
6290 Rvvelt<double>(rvv_vd_reg(), i, true) =
6291 static_cast<double>(vs2);
6292 },
6293 { ; }, { ; }, { ; }, true, (rvv_vsew() >= E16))
6294 break;
6295 default:
6296 UNSUPPORTED_RISCV();
6297 break;
6298 }
6299 break;
6300 case RO_V_VFUNARY1:
6301 switch (instr_.Vs1Value()) {
6302 case VFCLASS_V:
6303 RVV_VI_VFP_VF_LOOP(
6304 { UNIMPLEMENTED(); },
6305 {
6306 int32_t& vd_i = Rvvelt<int32_t>(rvv_vd_reg(), i, true);
6307 vd_i = int32_t(FclassHelper(vs2));
6308 USE(fs1);
6309 USE(vd);
6310 },
6311 {
6312 int64_t& vd_i = Rvvelt<int64_t>(rvv_vd_reg(), i, true);
6313 vd_i = FclassHelper(vs2);
6314 USE(fs1);
6315 USE(vd);
6316 })
6317 break;
6318 case VFSQRT_V:
6319 RVV_VI_VFP_VF_LOOP({ UNIMPLEMENTED(); },
6320 {
6321 vd = std::sqrt(vs2);
6322 USE(fs1);
6323 },
6324 {
6325 vd = std::sqrt(vs2);
6326 USE(fs1);
6327 })
6328 break;
6329 case VFRSQRT7_V:
6330 RVV_VI_VFP_VF_LOOP(
6331 {},
6332 {
6333 vd = base::RecipSqrt(vs2);
6334 USE(fs1);
6335 },
6336 {
6337 vd = base::RecipSqrt(vs2);
6338 USE(fs1);
6339 })
6340 break;
6341 case VFREC7_V:
6342 RVV_VI_VFP_VF_LOOP(
6343 {},
6344 {
6345 vd = base::Recip(vs2);
6346 USE(fs1);
6347 },
6348 {
6349 vd = base::Recip(vs2);
6350 USE(fs1);
6351 })
6352 break;
6353 default:
6354 break;
6355 }
6356 break;
6357 case RO_V_VMFEQ_VV: {
6358 RVV_VI_VFP_LOOP_CMP({ UNIMPLEMENTED(); },
6359 { res = CompareFHelper(vs2, vs1, EQ); },
6360 { res = CompareFHelper(vs2, vs1, EQ); }, true)
6361 } break;
6362 case RO_V_VMFNE_VV: {
6363 RVV_VI_VFP_LOOP_CMP({ UNIMPLEMENTED(); },
6364 { res = CompareFHelper(vs2, vs1, NE); },
6365 { res = CompareFHelper(vs2, vs1, NE); }, true)
6366 } break;
6367 case RO_V_VMFLT_VV: {
6368 RVV_VI_VFP_LOOP_CMP({ UNIMPLEMENTED(); },
6369 { res = CompareFHelper(vs2, vs1, LT); },
6370 { res = CompareFHelper(vs2, vs1, LT); }, true)
6371 } break;
6372 case RO_V_VMFLE_VV: {
6373 RVV_VI_VFP_LOOP_CMP({ UNIMPLEMENTED(); },
6374 { res = CompareFHelper(vs2, vs1, LE); },
6375 { res = CompareFHelper(vs2, vs1, LE); }, true)
6376 } break;
6377 case RO_V_VFMAX_VV: {
6378 RVV_VI_VFP_VV_LOOP({ UNIMPLEMENTED(); },
6379 { vd = FMaxMinHelper(vs2, vs1, MaxMinKind::kMax); },
6380 { vd = FMaxMinHelper(vs2, vs1, MaxMinKind::kMax); })
6381 break;
6382 }
6383 case RO_V_VFREDMAX_VV: {
6384 RVV_VI_VFP_VV_LOOP_REDUCTION(
6385 { UNIMPLEMENTED(); },
6386 { vd_0 = FMaxMinHelper(vd_0, vs2, MaxMinKind::kMax); },
6387 { vd_0 = FMaxMinHelper(vd_0, vs2, MaxMinKind::kMax); })
6388 break;
6389 }
6390 case RO_V_VFMIN_VV: {
6391 RVV_VI_VFP_VV_LOOP({ UNIMPLEMENTED(); },
6392 { vd = FMaxMinHelper(vs2, vs1, MaxMinKind::kMin); },
6393 { vd = FMaxMinHelper(vs2, vs1, MaxMinKind::kMin); })
6394 break;
6395 }
6396 case RO_V_VFSGNJ_VV:
6397 RVV_VI_VFP_VV_LOOP({ UNIMPLEMENTED(); },
6398 { vd = fsgnj32(vs2, vs1, false, false); },
6399 { vd = fsgnj64(vs2, vs1, false, false); })
6400 break;
6401 case RO_V_VFSGNJN_VV:
6402 RVV_VI_VFP_VV_LOOP({ UNIMPLEMENTED(); },
6403 { vd = fsgnj32(vs2, vs1, true, false); },
6404 { vd = fsgnj64(vs2, vs1, true, false); })
6405 break;
6406 case RO_V_VFSGNJX_VV:
6407 RVV_VI_VFP_VV_LOOP({ UNIMPLEMENTED(); },
6408 { vd = fsgnj32(vs2, vs1, false, true); },
6409 { vd = fsgnj64(vs2, vs1, false, true); })
6410 break;
6411 case RO_V_VFADD_VV:
6412 RVV_VI_VFP_VV_LOOP(
6413 { UNIMPLEMENTED(); },
6414 {
6415 auto fn = [this](float frs1, float frs2) {
6416 if (is_invalid_fadd(frs1, frs2)) {
6417 this->set_fflags(kInvalidOperation);
6418 return std::numeric_limits<float>::quiet_NaN();
6419 } else {
6420 return frs1 + frs2;
6421 }
6422 };
6423 auto alu_out = fn(vs1, vs2);
6424 // if any input or result is NaN, the result is quiet_NaN
6425 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6426 // signaling_nan sets kInvalidOperation bit
6427 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6428 set_fflags(kInvalidOperation);
6429 alu_out = std::numeric_limits<float>::quiet_NaN();
6430 }
6431 vd = alu_out;
6432 },
6433 {
6434 auto fn = [this](double frs1, double frs2) {
6435 if (is_invalid_fadd(frs1, frs2)) {
6436 this->set_fflags(kInvalidOperation);
6437 return std::numeric_limits<double>::quiet_NaN();
6438 } else {
6439 return frs1 + frs2;
6440 }
6441 };
6442 auto alu_out = fn(vs1, vs2);
6443 // if any input or result is NaN, the result is quiet_NaN
6444 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6445 // signaling_nan sets kInvalidOperation bit
6446 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6447 set_fflags(kInvalidOperation);
6448 alu_out = std::numeric_limits<double>::quiet_NaN();
6449 }
6450 vd = alu_out;
6451 })
6452 break;
6453 case RO_V_VFSUB_VV:
6454 RVV_VI_VFP_VV_LOOP(
6455 { UNIMPLEMENTED(); },
6456 {
6457 auto fn = [this](float frs1, float frs2) {
6458 if (is_invalid_fsub(frs1, frs2)) {
6459 this->set_fflags(kInvalidOperation);
6460 return std::numeric_limits<float>::quiet_NaN();
6461 } else {
6462 return frs2 - frs1;
6463 }
6464 };
6465 auto alu_out = fn(vs1, vs2);
6466 // if any input or result is NaN, the result is quiet_NaN
6467 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6468 // signaling_nan sets kInvalidOperation bit
6469 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6470 set_fflags(kInvalidOperation);
6471 alu_out = std::numeric_limits<float>::quiet_NaN();
6472 }
6473
6474 vd = alu_out;
6475 },
6476 {
6477 auto fn = [this](double frs1, double frs2) {
6478 if (is_invalid_fsub(frs1, frs2)) {
6479 this->set_fflags(kInvalidOperation);
6480 return std::numeric_limits<double>::quiet_NaN();
6481 } else {
6482 return frs2 - frs1;
6483 }
6484 };
6485 auto alu_out = fn(vs1, vs2);
6486 // if any input or result is NaN, the result is quiet_NaN
6487 if (std::isnan(alu_out) || std::isnan(vs1) || std::isnan(vs2)) {
6488 // signaling_nan sets kInvalidOperation bit
6489 if (isSnan(alu_out) || isSnan(vs1) || isSnan(vs2))
6490 set_fflags(kInvalidOperation);
6491 alu_out = std::numeric_limits<double>::quiet_NaN();
6492 }
6493 vd = alu_out;
6494 })
6495 break;
6496 case RO_V_VFWADD_VV:
6497 RVV_VI_CHECK_DSS(true);
6498 RVV_VI_VFP_VV_LOOP_WIDEN(
6499 {
6500 RVV_VI_VFP_VV_ARITH_CHECK_COMPUTE(double, is_invalid_fadd, +);
6501 USE(vs3);
6502 },
6503 false)
6504 break;
6505 case RO_V_VFWSUB_VV:
6506 RVV_VI_CHECK_DSS(true);
6507 RVV_VI_VFP_VV_LOOP_WIDEN(
6508 {
6509 RVV_VI_VFP_VV_ARITH_CHECK_COMPUTE(double, is_invalid_fsub, -);
6510 USE(vs3);
6511 },
6512 false)
6513 break;
6514 case RO_V_VFWADD_W_VV:
6515 RVV_VI_CHECK_DSS(true);
6516 RVV_VI_VFP_VV_LOOP_WIDEN(
6517 {
6518 RVV_VI_VFP_VV_ARITH_CHECK_COMPUTE(double, is_invalid_fadd, +);
6519 USE(vs3);
6520 },
6521 true)
6522 break;
6523 case RO_V_VFWSUB_W_VV:
6524 RVV_VI_CHECK_DSS(true);
6525 RVV_VI_VFP_VV_LOOP_WIDEN(
6526 {
6527 RVV_VI_VFP_VV_ARITH_CHECK_COMPUTE(double, is_invalid_fsub, -);
6528 USE(vs3);
6529 },
6530 true)
6531 break;
6532 case RO_V_VFWMUL_VV:
6533 RVV_VI_CHECK_DSS(true);
6534 RVV_VI_VFP_VV_LOOP_WIDEN(
6535 {
6536 RVV_VI_VFP_VV_ARITH_CHECK_COMPUTE(double, is_invalid_fmul, *);
6537 USE(vs3);
6538 },
6539 false)
6540 break;
6541 case RO_V_VFWREDUSUM_VV:
6542 case RO_V_VFWREDOSUM_VV:
6543 RVV_VI_CHECK_DSS(true);
6544 switch (rvv_vsew()) {
6545 case E16:
6546 case E64: {
6547 UNIMPLEMENTED();
6548 }
6549 case E32: {
6550 double& vd = Rvvelt<double>(rvv_vd_reg(), 0, true);
6551 float vs1 = Rvvelt<float>(rvv_vs1_reg(), 0);
6552 double alu_out = vs1;
6553 for (uint64_t i = rvv_vstart(); i < rvv_vl(); ++i) {
6554 double vs2 = static_cast<double>(Rvvelt<float>(rvv_vs2_reg(), i));
6555 if (is_invalid_fadd(alu_out, vs2)) {
6556 set_fflags(kInvalidOperation);
6557 alu_out = std::numeric_limits<float>::quiet_NaN();
6558 break;
6559 }
6560 alu_out = alu_out + vs2;
6561 if (std::isnan(alu_out) || std::isnan(vs2)) {
6562 // signaling_nan sets kInvalidOperation bit
6563 if (isSnan(alu_out) || isSnan(vs2)) set_fflags(kInvalidOperation);
6564 alu_out = std::numeric_limits<float>::quiet_NaN();
6565 break;
6566 }
6567 }
6568 vd = alu_out;
6569 break;
6570 }
6571 default:
6572 require(false);
6573 break;
6574 }
6575
6576 break;
6577 case RO_V_VFMADD_VV:
6578 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, vd, vs1, vs2)},
6579 {RVV_VI_VFP_FMA(double, vd, vs1, vs2)})
6580 break;
6581 case RO_V_VFNMADD_VV:
6582 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, -vd, vs1, -vs2)},
6583 {RVV_VI_VFP_FMA(double, -vd, vs1, -vs2)})
6584 break;
6585 case RO_V_VFMSUB_VV:
6586 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, vd, vs1, -vs2)},
6587 {RVV_VI_VFP_FMA(double, vd, vs1, -vs2)})
6588 break;
6589 case RO_V_VFNMSUB_VV:
6590 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, -vd, vs1, +vs2)},
6591 {RVV_VI_VFP_FMA(double, -vd, vs1, +vs2)})
6592 break;
6593 case RO_V_VFMACC_VV:
6594 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, vs2, vs1, vd)},
6595 {RVV_VI_VFP_FMA(double, vs2, vs1, vd)})
6596 break;
6597 case RO_V_VFNMACC_VV:
6598 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, -vs2, vs1, -vd)},
6599 {RVV_VI_VFP_FMA(double, -vs2, vs1, -vd)})
6600 break;
6601 case RO_V_VFMSAC_VV:
6602 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, vs2, vs1, -vd)},
6603 {RVV_VI_VFP_FMA(double, vs2, vs1, -vd)})
6604 break;
6605 case RO_V_VFNMSAC_VV:
6606 RVV_VI_VFP_FMA_VV_LOOP({RVV_VI_VFP_FMA(float, -vs2, vs1, +vd)},
6607 {RVV_VI_VFP_FMA(double, -vs2, vs1, +vd)})
6608 break;
6609 case RO_V_VFWMACC_VV:
6610 RVV_VI_CHECK_DSS(true);
6611 RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, vs1, vs3)}, false)
6612 break;
6613 case RO_V_VFWNMACC_VV:
6614 RVV_VI_CHECK_DSS(true);
6615 RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, vs1, -vs3)}, false)
6616 break;
6617 case RO_V_VFWMSAC_VV:
6618 RVV_VI_CHECK_DSS(true);
6619 RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, vs1, -vs3)}, false)
6620 break;
6621 case RO_V_VFWNMSAC_VV:
6622 RVV_VI_CHECK_DSS(true);
6623 RVV_VI_VFP_VV_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, vs1, +vs3)}, false)
6624 break;
6625 case RO_V_VFMV_FS:
6626 switch (rvv_vsew()) {
6627 case E16: {
6628 UNIMPLEMENTED();
6629 }
6630 case E32: {
6631 float fs2 = Rvvelt<float>(rvv_vs2_reg(), 0);
6632 set_fpu_register_float(rd_reg(), fs2);
6633 break;
6634 }
6635 case E64: {
6636 double fs2 = Rvvelt<double>(rvv_vs2_reg(), 0);
6637 set_fpu_register_double(rd_reg(), fs2);
6638 break;
6639 }
6640 default:
6641 require(0);
6642 break;
6643 }
6644 rvv_trace_vd();
6645 break;
6646 default:
6647 UNSUPPORTED_RISCV();
6648 break;
6649 }
6650 }
6651
DecodeRvvFVF()6652 void Simulator::DecodeRvvFVF() {
6653 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_FVF);
6654 switch (instr_.InstructionBits() & kVTypeMask) {
6655 case RO_V_VFSGNJ_VF:
6656 RVV_VI_VFP_VF_LOOP(
6657 {}, { vd = fsgnj32(vs2, fs1, false, false); },
6658 { vd = fsgnj64(vs2, fs1, false, false); })
6659 break;
6660 case RO_V_VFSGNJN_VF:
6661 RVV_VI_VFP_VF_LOOP(
6662 {}, { vd = fsgnj32(vs2, fs1, true, false); },
6663 { vd = fsgnj64(vs2, fs1, true, false); })
6664 break;
6665 case RO_V_VFSGNJX_VF:
6666 RVV_VI_VFP_VF_LOOP(
6667 {}, { vd = fsgnj32(vs2, fs1, false, true); },
6668 { vd = fsgnj64(vs2, fs1, false, true); })
6669 break;
6670 case RO_V_VFMV_VF:
6671 RVV_VI_VFP_VF_LOOP(
6672 {},
6673 {
6674 vd = fs1;
6675 USE(vs2);
6676 },
6677 {
6678 vd = fs1;
6679 USE(vs2);
6680 })
6681 break;
6682 case RO_V_VFWADD_VF:
6683 RVV_VI_CHECK_DSS(true);
6684 RVV_VI_VFP_VF_LOOP_WIDEN(
6685 {
6686 RVV_VI_VFP_VF_ARITH_CHECK_COMPUTE(double, is_invalid_fadd, +);
6687 USE(vs3);
6688 },
6689 false)
6690 break;
6691 case RO_V_VFWSUB_VF:
6692 RVV_VI_CHECK_DSS(true);
6693 RVV_VI_VFP_VF_LOOP_WIDEN(
6694 {
6695 RVV_VI_VFP_VF_ARITH_CHECK_COMPUTE(double, is_invalid_fsub, -);
6696 USE(vs3);
6697 },
6698 false)
6699 break;
6700 case RO_V_VFWADD_W_VF:
6701 RVV_VI_CHECK_DSS(true);
6702 RVV_VI_VFP_VF_LOOP_WIDEN(
6703 {
6704 RVV_VI_VFP_VF_ARITH_CHECK_COMPUTE(double, is_invalid_fadd, +);
6705 USE(vs3);
6706 },
6707 true)
6708 break;
6709 case RO_V_VFWSUB_W_VF:
6710 RVV_VI_CHECK_DSS(true);
6711 RVV_VI_VFP_VF_LOOP_WIDEN(
6712 {
6713 RVV_VI_VFP_VF_ARITH_CHECK_COMPUTE(double, is_invalid_fsub, -);
6714 USE(vs3);
6715 },
6716 true)
6717 break;
6718 case RO_V_VFWMUL_VF:
6719 RVV_VI_CHECK_DSS(true);
6720 RVV_VI_VFP_VF_LOOP_WIDEN(
6721 {
6722 RVV_VI_VFP_VF_ARITH_CHECK_COMPUTE(double, is_invalid_fmul, *);
6723 USE(vs3);
6724 },
6725 false)
6726 break;
6727 case RO_V_VFMADD_VF:
6728 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, vd, fs1, vs2)},
6729 {RVV_VI_VFP_FMA(double, vd, fs1, vs2)})
6730 break;
6731 case RO_V_VFNMADD_VF:
6732 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, -vd, fs1, -vs2)},
6733 {RVV_VI_VFP_FMA(double, -vd, fs1, -vs2)})
6734 break;
6735 case RO_V_VFMSUB_VF:
6736 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, vd, fs1, -vs2)},
6737 {RVV_VI_VFP_FMA(double, vd, fs1, -vs2)})
6738 break;
6739 case RO_V_VFNMSUB_VF:
6740 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, -vd, fs1, vs2)},
6741 {RVV_VI_VFP_FMA(double, -vd, fs1, vs2)})
6742 break;
6743 case RO_V_VFMACC_VF:
6744 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, vs2, fs1, vd)},
6745 {RVV_VI_VFP_FMA(double, vs2, fs1, vd)})
6746 break;
6747 case RO_V_VFNMACC_VF:
6748 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, -vs2, fs1, -vd)},
6749 {RVV_VI_VFP_FMA(double, -vs2, fs1, -vd)})
6750 break;
6751 case RO_V_VFMSAC_VF:
6752 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, vs2, fs1, -vd)},
6753 {RVV_VI_VFP_FMA(double, vs2, fs1, -vd)})
6754 break;
6755 case RO_V_VFNMSAC_VF:
6756 RVV_VI_VFP_FMA_VF_LOOP({RVV_VI_VFP_FMA(float, -vs2, fs1, vd)},
6757 {RVV_VI_VFP_FMA(double, -vs2, fs1, vd)})
6758 break;
6759 case RO_V_VFWMACC_VF:
6760 RVV_VI_CHECK_DSS(true);
6761 RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, fs1, vs3)}, false)
6762 break;
6763 case RO_V_VFWNMACC_VF:
6764 RVV_VI_CHECK_DSS(true);
6765 RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, fs1, -vs3)}, false)
6766 break;
6767 case RO_V_VFWMSAC_VF:
6768 RVV_VI_CHECK_DSS(true);
6769 RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, vs2, fs1, -vs3)}, false)
6770 break;
6771 case RO_V_VFWNMSAC_VF:
6772 RVV_VI_CHECK_DSS(true);
6773 RVV_VI_VFP_VF_LOOP_WIDEN({RVV_VI_VFP_FMA(float, -vs2, fs1, vs3)}, false)
6774 break;
6775 default:
6776 UNSUPPORTED_RISCV();
6777 break;
6778 }
6779 }
DecodeVType()6780 void Simulator::DecodeVType() {
6781 switch (instr_.InstructionBits() & (kFunct3Mask | kBaseOpcodeMask)) {
6782 case OP_IVV:
6783 DecodeRvvIVV();
6784 return;
6785 case OP_FVV:
6786 DecodeRvvFVV();
6787 return;
6788 case OP_MVV:
6789 DecodeRvvMVV();
6790 return;
6791 case OP_IVI:
6792 DecodeRvvIVI();
6793 return;
6794 case OP_IVX:
6795 DecodeRvvIVX();
6796 return;
6797 case OP_FVF:
6798 DecodeRvvFVF();
6799 return;
6800 case OP_MVX:
6801 DecodeRvvMVX();
6802 return;
6803 }
6804 switch (instr_.InstructionBits() &
6805 (kBaseOpcodeMask | kFunct3Mask | 0x80000000)) {
6806 case RO_V_VSETVLI: {
6807 uint64_t avl;
6808 set_rvv_vtype(rvv_zimm());
6809 CHECK_GE(rvv_vsew(), E8);
6810 CHECK_LE(rvv_vsew(), E64);
6811 if (rs1_reg() != zero_reg) {
6812 avl = rs1();
6813 } else if (rd_reg() != zero_reg) {
6814 avl = ~0;
6815 } else {
6816 avl = rvv_vl();
6817 }
6818 avl = avl <= rvv_vlmax() ? avl : rvv_vlmax();
6819 set_rvv_vl(avl);
6820 set_rd(rvv_vl());
6821 rvv_trace_status();
6822 break;
6823 }
6824 case RO_V_VSETVL: {
6825 if (!(instr_.InstructionBits() & 0x40000000)) {
6826 uint64_t avl;
6827 set_rvv_vtype(rs2());
6828 CHECK_GE(rvv_sew(), E8);
6829 CHECK_LE(rvv_sew(), E64);
6830 if (rs1_reg() != zero_reg) {
6831 avl = rs1();
6832 } else if (rd_reg() != zero_reg) {
6833 avl = ~0;
6834 } else {
6835 avl = rvv_vl();
6836 }
6837 avl = avl <= rvv_vlmax()
6838 ? avl
6839 : avl < (rvv_vlmax() * 2) ? avl / 2 : rvv_vlmax();
6840 set_rvv_vl(avl);
6841 set_rd(rvv_vl());
6842 rvv_trace_status();
6843 } else {
6844 DCHECK_EQ(instr_.InstructionBits() &
6845 (kBaseOpcodeMask | kFunct3Mask | 0xC0000000),
6846 RO_V_VSETIVLI);
6847 uint64_t avl;
6848 set_rvv_vtype(rvv_zimm());
6849 avl = instr_.Rvvuimm();
6850 avl = avl <= rvv_vlmax()
6851 ? avl
6852 : avl < (rvv_vlmax() * 2) ? avl / 2 : rvv_vlmax();
6853 set_rvv_vl(avl);
6854 set_rd(rvv_vl());
6855 rvv_trace_status();
6856 break;
6857 }
6858 break;
6859 }
6860 default:
6861 FATAL("Error: Unsupport on FILE:%s:%d.", __FILE__, __LINE__);
6862 }
6863 }
6864 #endif
6865
6866 // Executes the current instruction.
InstructionDecode(Instruction * instr)6867 void Simulator::InstructionDecode(Instruction* instr) {
6868 if (v8::internal::FLAG_check_icache) {
6869 CheckICache(i_cache(), instr);
6870 }
6871 pc_modified_ = false;
6872
6873 v8::base::EmbeddedVector<char, 256> buffer;
6874
6875 if (::v8::internal::FLAG_trace_sim) {
6876 SNPrintF(trace_buf_, " ");
6877 disasm::NameConverter converter;
6878 disasm::Disassembler dasm(converter);
6879 // Use a reasonably large buffer.
6880 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(instr));
6881
6882 // PrintF("EXECUTING 0x%08" PRIxPTR " %-44s\n",
6883 // reinterpret_cast<intptr_t>(instr), buffer.begin());
6884 }
6885
6886 instr_ = instr;
6887 switch (instr_.InstructionType()) {
6888 case Instruction::kRType:
6889 DecodeRVRType();
6890 break;
6891 case Instruction::kR4Type:
6892 DecodeRVR4Type();
6893 break;
6894 case Instruction::kIType:
6895 DecodeRVIType();
6896 break;
6897 case Instruction::kSType:
6898 DecodeRVSType();
6899 break;
6900 case Instruction::kBType:
6901 DecodeRVBType();
6902 break;
6903 case Instruction::kUType:
6904 DecodeRVUType();
6905 break;
6906 case Instruction::kJType:
6907 DecodeRVJType();
6908 break;
6909 case Instruction::kCRType:
6910 DecodeCRType();
6911 break;
6912 case Instruction::kCAType:
6913 DecodeCAType();
6914 break;
6915 case Instruction::kCJType:
6916 DecodeCJType();
6917 break;
6918 case Instruction::kCBType:
6919 DecodeCBType();
6920 break;
6921 case Instruction::kCIType:
6922 DecodeCIType();
6923 break;
6924 case Instruction::kCIWType:
6925 DecodeCIWType();
6926 break;
6927 case Instruction::kCSSType:
6928 DecodeCSSType();
6929 break;
6930 case Instruction::kCLType:
6931 DecodeCLType();
6932 break;
6933 case Instruction::kCSType:
6934 DecodeCSType();
6935 break;
6936 #ifdef CAN_USE_RVV_INSTRUCTIONS
6937 case Instruction::kVType:
6938 DecodeVType();
6939 break;
6940 #endif
6941 default:
6942 if (1) {
6943 std::cout << "Unrecognized instruction [@pc=0x" << std::hex
6944 << registers_[pc] << "]: 0x" << instr->InstructionBits()
6945 << std::endl;
6946 }
6947 UNSUPPORTED();
6948 }
6949
6950 if (::v8::internal::FLAG_trace_sim) {
6951 PrintF(" 0x%012" PRIxPTR " %-44s\t%s\n",
6952 reinterpret_cast<intptr_t>(instr), buffer.begin(),
6953 trace_buf_.begin());
6954 }
6955
6956 if (!pc_modified_) {
6957 set_register(pc,
6958 reinterpret_cast<int64_t>(instr) + instr->InstructionSize());
6959 }
6960 }
6961
Execute()6962 void Simulator::Execute() {
6963 // Get the PC to simulate. Cannot use the accessor here as we need the
6964 // raw PC value and not the one used as input to arithmetic instructions.
6965 int64_t program_counter = get_pc();
6966 while (program_counter != end_sim_pc) {
6967 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
6968 icount_++;
6969 if (icount_ == static_cast<int64_t>(::v8::internal::FLAG_stop_sim_at)) {
6970 RiscvDebugger dbg(this);
6971 dbg.Debug();
6972 } else {
6973 InstructionDecode(instr);
6974 }
6975 CheckBreakpoints();
6976 program_counter = get_pc();
6977 }
6978 }
6979
CallInternal(Address entry)6980 void Simulator::CallInternal(Address entry) {
6981 // Adjust JS-based stack limit to C-based stack limit.
6982 isolate_->stack_guard()->AdjustStackLimitForSimulator();
6983
6984 // Prepare to execute the code at entry.
6985 set_register(pc, static_cast<int64_t>(entry));
6986 // Put down marker for end of simulation. The simulator will stop simulation
6987 // when the PC reaches this value. By saving the "end simulation" value into
6988 // the LR the simulation stops when returning to this call point.
6989 set_register(ra, end_sim_pc);
6990
6991 // Remember the values of callee-saved registers.
6992 int64_t s0_val = get_register(s0);
6993 int64_t s1_val = get_register(s1);
6994 int64_t s2_val = get_register(s2);
6995 int64_t s3_val = get_register(s3);
6996 int64_t s4_val = get_register(s4);
6997 int64_t s5_val = get_register(s5);
6998 int64_t s6_val = get_register(s6);
6999 int64_t s7_val = get_register(s7);
7000 int64_t s8_val = get_register(s8);
7001 int64_t s9_val = get_register(s9);
7002 int64_t s10_val = get_register(s10);
7003 int64_t s11_val = get_register(s11);
7004 int64_t gp_val = get_register(gp);
7005 int64_t sp_val = get_register(sp);
7006
7007 // Set up the callee-saved registers with a known value. To be able to check
7008 // that they are preserved properly across JS execution.
7009 int64_t callee_saved_value = icount_;
7010 set_register(s0, callee_saved_value);
7011 set_register(s1, callee_saved_value);
7012 set_register(s2, callee_saved_value);
7013 set_register(s3, callee_saved_value);
7014 set_register(s4, callee_saved_value);
7015 set_register(s5, callee_saved_value);
7016 set_register(s6, callee_saved_value);
7017 set_register(s7, callee_saved_value);
7018 set_register(s8, callee_saved_value);
7019 set_register(s9, callee_saved_value);
7020 set_register(s10, callee_saved_value);
7021 set_register(s11, callee_saved_value);
7022 set_register(gp, callee_saved_value);
7023
7024 // Start the simulation.
7025 Execute();
7026
7027 // Check that the callee-saved registers have been preserved.
7028 CHECK_EQ(callee_saved_value, get_register(s0));
7029 CHECK_EQ(callee_saved_value, get_register(s1));
7030 CHECK_EQ(callee_saved_value, get_register(s2));
7031 CHECK_EQ(callee_saved_value, get_register(s3));
7032 CHECK_EQ(callee_saved_value, get_register(s4));
7033 CHECK_EQ(callee_saved_value, get_register(s5));
7034 CHECK_EQ(callee_saved_value, get_register(s6));
7035 CHECK_EQ(callee_saved_value, get_register(s7));
7036 CHECK_EQ(callee_saved_value, get_register(s8));
7037 CHECK_EQ(callee_saved_value, get_register(s9));
7038 CHECK_EQ(callee_saved_value, get_register(s10));
7039 CHECK_EQ(callee_saved_value, get_register(s11));
7040 CHECK_EQ(callee_saved_value, get_register(gp));
7041
7042 // Restore callee-saved registers with the original value.
7043 set_register(s0, s0_val);
7044 set_register(s1, s1_val);
7045 set_register(s2, s2_val);
7046 set_register(s3, s3_val);
7047 set_register(s4, s4_val);
7048 set_register(s5, s5_val);
7049 set_register(s6, s6_val);
7050 set_register(s7, s7_val);
7051 set_register(s8, s8_val);
7052 set_register(s9, s9_val);
7053 set_register(s10, s10_val);
7054 set_register(s11, s11_val);
7055 set_register(gp, gp_val);
7056 set_register(sp, sp_val);
7057 }
7058
CallImpl(Address entry,int argument_count,const intptr_t * arguments)7059 intptr_t Simulator::CallImpl(Address entry, int argument_count,
7060 const intptr_t* arguments) {
7061 constexpr int kRegisterPassedArguments = 8;
7062 // Set up arguments.
7063
7064 // RISC-V 64G ISA has a0-a7 for passing arguments
7065 int reg_arg_count = std::min(kRegisterPassedArguments, argument_count);
7066 if (reg_arg_count > 0) set_register(a0, arguments[0]);
7067 if (reg_arg_count > 1) set_register(a1, arguments[1]);
7068 if (reg_arg_count > 2) set_register(a2, arguments[2]);
7069 if (reg_arg_count > 3) set_register(a3, arguments[3]);
7070 if (reg_arg_count > 4) set_register(a4, arguments[4]);
7071 if (reg_arg_count > 5) set_register(a5, arguments[5]);
7072 if (reg_arg_count > 6) set_register(a6, arguments[6]);
7073 if (reg_arg_count > 7) set_register(a7, arguments[7]);
7074
7075 if (::v8::internal::FLAG_trace_sim) {
7076 std::cout << "CallImpl: reg_arg_count = " << reg_arg_count << std::hex
7077 << " entry-pc (JSEntry) = 0x" << entry
7078 << " a0 (Isolate-root) = 0x" << get_register(a0)
7079 << " a1 (orig_func/new_target) = 0x" << get_register(a1)
7080 << " a2 (func/target) = 0x" << get_register(a2)
7081 << " a3 (receiver) = 0x" << get_register(a3) << " a4 (argc) = 0x"
7082 << get_register(a4) << " a5 (argv) = 0x" << get_register(a5)
7083 << std::endl;
7084 }
7085
7086 // Remaining arguments passed on stack.
7087 int64_t original_stack = get_register(sp);
7088 // Compute position of stack on entry to generated code.
7089 int stack_args_count = argument_count - reg_arg_count;
7090 int stack_args_size = stack_args_count * sizeof(*arguments) + kCArgsSlotsSize;
7091 int64_t entry_stack = original_stack - stack_args_size;
7092
7093 if (base::OS::ActivationFrameAlignment() != 0) {
7094 entry_stack &= -base::OS::ActivationFrameAlignment();
7095 }
7096 // Store remaining arguments on stack, from low to high memory.
7097 intptr_t* stack_argument = reinterpret_cast<intptr_t*>(entry_stack);
7098 memcpy(stack_argument + kCArgSlotCount, arguments + reg_arg_count,
7099 stack_args_count * sizeof(*arguments));
7100 set_register(sp, entry_stack);
7101
7102 CallInternal(entry);
7103
7104 // Pop stack passed arguments.
7105 CHECK_EQ(entry_stack, get_register(sp));
7106 set_register(sp, original_stack);
7107
7108 // return get_register(a0);
7109 // RISCV uses a0 to return result
7110 return get_register(a0);
7111 }
7112
CallFP(Address entry,double d0,double d1)7113 double Simulator::CallFP(Address entry, double d0, double d1) {
7114 set_fpu_register_double(fa0, d0);
7115 set_fpu_register_double(fa1, d1);
7116 CallInternal(entry);
7117 return get_fpu_register_double(fa0);
7118 }
7119
PushAddress(uintptr_t address)7120 uintptr_t Simulator::PushAddress(uintptr_t address) {
7121 int64_t new_sp = get_register(sp) - sizeof(uintptr_t);
7122 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp);
7123 *stack_slot = address;
7124 set_register(sp, new_sp);
7125 return new_sp;
7126 }
7127
PopAddress()7128 uintptr_t Simulator::PopAddress() {
7129 int64_t current_sp = get_register(sp);
7130 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
7131 uintptr_t address = *stack_slot;
7132 set_register(sp, current_sp + sizeof(uintptr_t));
7133 return address;
7134 }
7135
LocalMonitor()7136 Simulator::LocalMonitor::LocalMonitor()
7137 : access_state_(MonitorAccess::Open),
7138 tagged_addr_(0),
7139 size_(TransactionSize::None) {}
7140
Clear()7141 void Simulator::LocalMonitor::Clear() {
7142 access_state_ = MonitorAccess::Open;
7143 tagged_addr_ = 0;
7144 size_ = TransactionSize::None;
7145 }
7146
NotifyLoad()7147 void Simulator::LocalMonitor::NotifyLoad() {
7148 if (access_state_ == MonitorAccess::RMW) {
7149 // A non linked load could clear the local monitor. As a result, it's
7150 // most strict to unconditionally clear the local monitor on load.
7151 Clear();
7152 }
7153 }
7154
NotifyLoadLinked(uintptr_t addr,TransactionSize size)7155 void Simulator::LocalMonitor::NotifyLoadLinked(uintptr_t addr,
7156 TransactionSize size) {
7157 access_state_ = MonitorAccess::RMW;
7158 tagged_addr_ = addr;
7159 size_ = size;
7160 }
7161
NotifyStore()7162 void Simulator::LocalMonitor::NotifyStore() {
7163 if (access_state_ == MonitorAccess::RMW) {
7164 // A non exclusive store could clear the local monitor. As a result, it's
7165 // most strict to unconditionally clear the local monitor on store.
7166 Clear();
7167 }
7168 }
7169
NotifyStoreConditional(uintptr_t addr,TransactionSize size)7170 bool Simulator::LocalMonitor::NotifyStoreConditional(uintptr_t addr,
7171 TransactionSize size) {
7172 if (access_state_ == MonitorAccess::RMW) {
7173 if (addr == tagged_addr_ && size_ == size) {
7174 Clear();
7175 return true;
7176 } else {
7177 return false;
7178 }
7179 } else {
7180 DCHECK(access_state_ == MonitorAccess::Open);
7181 return false;
7182 }
7183 }
7184
LinkedAddress()7185 Simulator::GlobalMonitor::LinkedAddress::LinkedAddress()
7186 : access_state_(MonitorAccess::Open),
7187 tagged_addr_(0),
7188 next_(nullptr),
7189 prev_(nullptr),
7190 failure_counter_(0) {}
7191
Clear_Locked()7192 void Simulator::GlobalMonitor::LinkedAddress::Clear_Locked() {
7193 access_state_ = MonitorAccess::Open;
7194 tagged_addr_ = 0;
7195 }
7196
NotifyLoadLinked_Locked(uintptr_t addr)7197 void Simulator::GlobalMonitor::LinkedAddress::NotifyLoadLinked_Locked(
7198 uintptr_t addr) {
7199 access_state_ = MonitorAccess::RMW;
7200 tagged_addr_ = addr;
7201 }
7202
NotifyStore_Locked()7203 void Simulator::GlobalMonitor::LinkedAddress::NotifyStore_Locked() {
7204 if (access_state_ == MonitorAccess::RMW) {
7205 // A non exclusive store could clear the global monitor. As a result, it's
7206 // most strict to unconditionally clear global monitors on store.
7207 Clear_Locked();
7208 }
7209 }
7210
NotifyStoreConditional_Locked(uintptr_t addr,bool is_requesting_thread)7211 bool Simulator::GlobalMonitor::LinkedAddress::NotifyStoreConditional_Locked(
7212 uintptr_t addr, bool is_requesting_thread) {
7213 if (access_state_ == MonitorAccess::RMW) {
7214 if (is_requesting_thread) {
7215 if (addr == tagged_addr_) {
7216 Clear_Locked();
7217 // Introduce occasional sc/scd failures. This is to simulate the
7218 // behavior of hardware, which can randomly fail due to background
7219 // cache evictions.
7220 if (failure_counter_++ >= kMaxFailureCounter) {
7221 failure_counter_ = 0;
7222 return false;
7223 } else {
7224 return true;
7225 }
7226 }
7227 } else if ((addr & kExclusiveTaggedAddrMask) ==
7228 (tagged_addr_ & kExclusiveTaggedAddrMask)) {
7229 // Check the masked addresses when responding to a successful lock by
7230 // another thread so the implementation is more conservative (i.e. the
7231 // granularity of locking is as large as possible.)
7232 Clear_Locked();
7233 return false;
7234 }
7235 }
7236 return false;
7237 }
7238
NotifyLoadLinked_Locked(uintptr_t addr,LinkedAddress * linked_address)7239 void Simulator::GlobalMonitor::NotifyLoadLinked_Locked(
7240 uintptr_t addr, LinkedAddress* linked_address) {
7241 linked_address->NotifyLoadLinked_Locked(addr);
7242 PrependProcessor_Locked(linked_address);
7243 }
7244
NotifyStore_Locked(LinkedAddress * linked_address)7245 void Simulator::GlobalMonitor::NotifyStore_Locked(
7246 LinkedAddress* linked_address) {
7247 // Notify each thread of the store operation.
7248 for (LinkedAddress* iter = head_; iter; iter = iter->next_) {
7249 iter->NotifyStore_Locked();
7250 }
7251 }
7252
NotifyStoreConditional_Locked(uintptr_t addr,LinkedAddress * linked_address)7253 bool Simulator::GlobalMonitor::NotifyStoreConditional_Locked(
7254 uintptr_t addr, LinkedAddress* linked_address) {
7255 DCHECK(IsProcessorInLinkedList_Locked(linked_address));
7256 if (linked_address->NotifyStoreConditional_Locked(addr, true)) {
7257 // Notify the other processors that this StoreConditional succeeded.
7258 for (LinkedAddress* iter = head_; iter; iter = iter->next_) {
7259 if (iter != linked_address) {
7260 iter->NotifyStoreConditional_Locked(addr, false);
7261 }
7262 }
7263 return true;
7264 } else {
7265 return false;
7266 }
7267 }
7268
IsProcessorInLinkedList_Locked(LinkedAddress * linked_address) const7269 bool Simulator::GlobalMonitor::IsProcessorInLinkedList_Locked(
7270 LinkedAddress* linked_address) const {
7271 return head_ == linked_address || linked_address->next_ ||
7272 linked_address->prev_;
7273 }
7274
PrependProcessor_Locked(LinkedAddress * linked_address)7275 void Simulator::GlobalMonitor::PrependProcessor_Locked(
7276 LinkedAddress* linked_address) {
7277 if (IsProcessorInLinkedList_Locked(linked_address)) {
7278 return;
7279 }
7280
7281 if (head_) {
7282 head_->prev_ = linked_address;
7283 }
7284 linked_address->prev_ = nullptr;
7285 linked_address->next_ = head_;
7286 head_ = linked_address;
7287 }
7288
RemoveLinkedAddress(LinkedAddress * linked_address)7289 void Simulator::GlobalMonitor::RemoveLinkedAddress(
7290 LinkedAddress* linked_address) {
7291 base::MutexGuard lock_guard(&mutex);
7292 if (!IsProcessorInLinkedList_Locked(linked_address)) {
7293 return;
7294 }
7295
7296 if (linked_address->prev_) {
7297 linked_address->prev_->next_ = linked_address->next_;
7298 } else {
7299 head_ = linked_address->next_;
7300 }
7301 if (linked_address->next_) {
7302 linked_address->next_->prev_ = linked_address->prev_;
7303 }
7304 linked_address->prev_ = nullptr;
7305 linked_address->next_ = nullptr;
7306 }
7307
7308 #undef SScanF
7309
7310 } // namespace internal
7311 } // namespace v8
7312
7313 #endif // USE_SIMULATOR
7314