Searched refs:OP_MVV (Results 1 – 4 of 4) sorted by relevance
/third_party/node/deps/v8/src/codegen/riscv64/ |
D | constants-riscv64.h | 637 OP_MVV = OP_V | (0b010 << kFunct3Shift), enumerator 717 RO_V_VDIVU_VV = OP_MVV | (VDIVU_FUNCT6 << kRvvFunct6Shift), 721 RO_V_VDIV_VV = OP_MVV | (VDIV_FUNCT6 << kRvvFunct6Shift), 725 RO_V_VREMU_VV = OP_MVV | (VREMU_FUNCT6 << kRvvFunct6Shift), 729 RO_V_VREM_VV = OP_MVV | (VREM_FUNCT6 << kRvvFunct6Shift), 733 RO_V_VMULHU_VV = OP_MVV | (VMULHU_FUNCT6 << kRvvFunct6Shift), 737 RO_V_VMUL_VV = OP_MVV | (VMUL_FUNCT6 << kRvvFunct6Shift), 741 RO_V_VWMUL_VV = OP_MVV | (VWMUL_FUNCT6 << kRvvFunct6Shift), 745 RO_V_VWMULU_VV = OP_MVV | (VWMULU_FUNCT6 << kRvvFunct6Shift), 749 RO_V_VMULHSU_VV = OP_MVV | (VMULHSU_FUNCT6 << kRvvFunct6Shift), [all …]
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D | assembler-riscv64.cc | 1148 DCHECK(opcode == OP_MVV || opcode == OP_FVV || opcode == OP_IVV); in GenInstrV() 1158 DCHECK(opcode == OP_MVV || opcode == OP_FVV || opcode == OP_IVV); in GenInstrV() 1168 DCHECK(opcode == OP_MVV || opcode == OP_FVV); in GenInstrV() 1276 DCHECK(opcode == OP_MVV); in GenInstrV() 2478 GenInstrV(VREDMAXU_FUNCT6, OP_MVV, vd, vs1, vs2, mask); in vredmaxu_vs() 2483 GenInstrV(VREDMAX_FUNCT6, OP_MVV, vd, vs1, vs2, mask); in vredmax_vs() 2488 GenInstrV(VREDMIN_FUNCT6, OP_MVV, vd, vs1, vs2, mask); in vredmin_vs() 2493 GenInstrV(VREDMINU_FUNCT6, OP_MVV, vd, vs1, vs2, mask); in vredminu_vs() 2509 GenInstrV(VWXUNARY0_FUNCT6, OP_MVV, rd, 0b00000, vs2, NoMask); in vmv_xs() 2577 GenInstrV(VMUNARY0_FUNCT6, OP_MVV, vd, VID_V, v0, mask); in vid_v() [all …]
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/third_party/node/deps/v8/src/diagnostics/riscv64/ |
D | disasm-riscv64.cc | 2227 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_MVV); in DecodeRvvMVV() 2617 case OP_MVV: in DecodeVType()
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/third_party/node/deps/v8/src/execution/riscv64/ |
D | simulator-riscv64.cc | 5754 DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_MVV); in DecodeRvvMVV() 6788 case OP_MVV: in DecodeVType()
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