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Searched refs:cu_mask (Results 1 – 13 of 13) sorted by relevance

/third_party/mesa3d/src/amd/common/
Dac_shader_util.c658 bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask) in ac_compute_late_alloc() argument
661 *cu_mask = 0xffff; in ac_compute_late_alloc()
695 *cu_mask &= info->gfx_level == GFX10 ? ~BITFIELD_RANGE(2, 2) : in ac_compute_late_alloc()
713 *cu_mask = 0xfffe; /* 1 CU disabled */ in ac_compute_late_alloc()
Dac_gpu_info.c1145 info->cu_mask[i][j] = device_info.cu_bitmap[i % 4][(i / 4) * 2 + j]; in ac_query_gpu_info()
1159 info->cu_mask[i][0] = device_info.cu_bitmap[i % 4][i / 4]; in ac_query_gpu_info()
1161 info->cu_mask[i][j] = device_info.cu_bitmap[i][j]; in ac_query_gpu_info()
1163 info->num_cu += util_bitcount(info->cu_mask[i][j]); in ac_query_gpu_info()
1173 if (info->cu_mask[se][sa]) { in ac_query_gpu_info()
1552 info->cu_mask[i][j], util_bitcount(info->cu_mask[i][j]), in ac_print_gpu_info()
1553 info->spi_cu_en & BITFIELD_MASK(util_bitcount(info->cu_mask[i][j]))); in ac_print_gpu_info()
Dac_shader_util.h119 bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask);
Dac_gpu_info.h199 uint32_t cu_mask[AMD_MAX_SE][AMD_MAX_SA_PER_SE]; member
Dac_rgp.c357 uint16_t cu_mask[SQTT_MAX_NUM_SE][SQTT_SA_PER_SE]; member
517 chunk->cu_mask[se][sa] = rad_info->cu_mask[se][sa]; in ac_sqtt_fill_asic_info()
/third_party/mesa3d/src/amd/vulkan/
Dradv_sqtt.c42 return device->physical_device->rad_info.cu_mask[se][0] == 0; in radv_se_is_disabled()
90 int first_active_cu = ffs(device->physical_device->rad_info.cu_mask[se][0]); in radv_emit_thread_trace_start()
676 int first_active_cu = ffs(device->physical_device->rad_info.cu_mask[se][0]); in radv_get_thread_trace()
Dradv_pipeline.c5703 unsigned late_alloc_wave64, cu_mask; in radv_pipeline_emit_hw_vs() local
5705 &late_alloc_wave64, &cu_mask); in radv_pipeline_emit_hw_vs()
5710 S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F), in radv_pipeline_emit_hw_vs()
5715 S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F)); in radv_pipeline_emit_hw_vs()
5894 unsigned late_alloc_wave64, cu_mask; in radv_pipeline_emit_hw_ngg() local
5896 shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask); in radv_pipeline_emit_hw_ngg()
5901 S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F)); in radv_pipeline_emit_hw_ngg()
5907 S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F), in radv_pipeline_emit_hw_ngg()
5916 S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F)); in radv_pipeline_emit_hw_ngg()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_sqtt.c74 return sctx->screen->info.cu_mask[se][0] == 0; in si_se_is_disabled()
104 int first_active_cu = ffs(sctx->screen->info.cu_mask[se][0]); in si_emit_thread_trace_start()
576 int first_active_cu = ffs(sctx->screen->info.cu_mask[se][0]); in si_get_thread_trace()
Dsi_state_shaders.cpp1413 unsigned late_alloc_wave64, cu_mask; in gfx10_shader_ngg() local
1417 &late_alloc_wave64, &cu_mask); in gfx10_shader_ngg()
1437 shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(cu_mask) | in gfx10_shader_ngg()
1711 unsigned late_alloc_wave64, cu_mask; in si_shader_vs() local
1714 &late_alloc_wave64, &cu_mask); in si_shader_vs()
1724 S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F), in si_shader_vs()
/third_party/ntfs-3g/ntfsprogs/
Dntfswipe.c661 s64 cu_mask = na->compression_block_clusters - 1; in wipe_compressed_attribute() local
666 if ((cur_vcn & cu_mask) || in wipe_compressed_attribute()
676 if (offset == (offset & (~cu_mask))) { in wipe_compressed_attribute()
681 offset = (offset & (~cu_mask)) in wipe_compressed_attribute()
/third_party/mesa3d/docs/relnotes/
D20.1.0.rst3885 - ac: add ac_gpu_info::cu_mask to store bitmask of compute units
3886 - radv/rgp: report correct cu_mask info
D22.0.0.rst2952 - ac/gpu_info: set cu_mask correctly for Arcturus
D22.2.0.rst3912 - ac/gpu_info: set cu_mask correctly for gfx11