| /third_party/elfutils/tests/ |
| D | run-varlocs.sh | 59 [400500,400504) {reg4}
67 [400510,40051c) {reg4}
69 [40052a,400531) {GNU_entry_value(1) {reg4}, stack_value}
82 [400400,400403) {reg4}
83 [400403,40040b) {GNU_entry_value(1) {reg4}, stack_value}
110 [400400,400408) {reg4}
111 [400408,400423) {GNU_entry_value(1) {reg4}, stack_value}
147 [401050,401066) {reg4}
148 [401066,401067) {entry_value(1) {reg4}, stack_value}
159 [401150,401160) {reg4}
[all …]
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| D | run-dwarfcfi.sh | 42 reg4: location expression: call_frame_cfa stack_value
59 reg4: undefined
76 reg4: undefined
93 reg4: undefined
110 reg4: same_value
127 reg4: undefined
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| D | run-readelf-loc.sh | 297 [ 0] reg4
302 [ 0] reg4
453 [ 0] reg4
458 [ 0] reg4
659 [ 0] reg4
664 [ 0] reg4
817 [ 0] reg4
822 [ 0] reg4
1114 [ 0] reg4
1119 [ 0] reg4
[all …]
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| D | run-readelf-zdebug-rel.sh | 87 [ 0] reg4
192 [ 0] reg4
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| D | run-readelf-dw-form-indirect.sh | 559 [ 0] reg4
579 [ 0] reg4
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| D | run-addrcfi.sh | 37 integer reg4 (%esp): location expression: call_frame_cfa stack_value
84 integer reg4 (%esp): location expression: call_frame_cfa stack_value
136 integer reg4 (%rsi): undefined
202 integer reg4 (%rsi): undefined
306 integer reg4 (r4): undefined
1328 integer reg4 (r4): undefined
2356 integer reg4 (r4): undefined
3382 integer reg4 (%r4): undefined
3459 integer reg4 (%r4): undefined
3537 integer reg4 (r4): same_value
[all …]
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| /third_party/ffmpeg/libavcodec/loongarch/ |
| D | vp9_idct_lsx.c | 376 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_lsx() local
385 reg4, reg5, reg6, reg7); in vp9_idct16_1d_columns_addblk_lsx()
413 VP9_DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vp9_idct16_1d_columns_addblk_lsx()
414 LSX_BUTTERFLY_4_H(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_lsx()
420 reg4 = __lsx_vsub_h(reg6, loc3); in vp9_idct16_1d_columns_addblk_lsx()
462 loc1 = __lsx_vadd_h(reg4, loc0); in vp9_idct16_1d_columns_addblk_lsx()
463 loc2 = __lsx_vsub_h(reg4, loc0); in vp9_idct16_1d_columns_addblk_lsx()
467 LSX_BUTTERFLY_4_H(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vp9_idct16_1d_columns_addblk_lsx()
481 DUP4_ARG2(__lsx_vsrari_h, reg0, 6, reg2, 6, reg4, 6, reg6, 6, in vp9_idct16_1d_columns_addblk_lsx()
482 reg0, reg2, reg4, reg6); in vp9_idct16_1d_columns_addblk_lsx()
[all …]
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| D | h264_intrapred_lasx.c | 30 __m256i reg0, reg1, reg2, reg3, reg4; \
75 reg4 = __lasx_xvslli_w(reg0, 3); \
76 reg4 = __lasx_xvadd_w(reg4, reg3); \
79 tmp1 = __lasx_xvadd_w(reg2, reg4); \
84 tmp3 = __lasx_xvadd_w(reg2, reg4); \
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| D | vp9_mc_lsx.c | 457 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_4w_lsx() local
486 DUP2_ARG2(__lsx_vilvl_d, tmp1, tmp0, tmp3, tmp2, reg3, reg4); in common_vt_8t_4w_lsx()
487 DUP2_ARG2(__lsx_vxori_b, reg3, 128, reg4, 128, reg3, reg4); in common_vt_8t_4w_lsx()
490 out1 = FILT_8TAP_DPADD_S_H(reg1, reg2, reg3, reg4, filter0, filter1, in common_vt_8t_4w_lsx()
505 reg2 = reg4; in common_vt_8t_4w_lsx()
517 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
542 DUP2_ARG2(__lsx_vilvl_b, src4, src3, src6, src5, reg4, reg5); in common_vt_8t_8w_lsx()
555 out1 = FILT_8TAP_DPADD_S_H(reg3, reg4, reg5, tmp1, filter0, filter1, in common_vt_8t_8w_lsx()
559 out3 = FILT_8TAP_DPADD_S_H(reg4, reg5, tmp1, tmp3, filter0, filter1, in common_vt_8t_8w_lsx()
576 reg4 = tmp1; in common_vt_8t_8w_lsx()
[all …]
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| /third_party/vixl/src/aarch64/ |
| D | registers-aarch64.h | 973 const CPURegister& reg4 = NoReg,
986 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1029 const CPURegister& reg4 = NoCPUReg,
1038 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
1053 const CPURegister& reg4 = NoReg,
1062 even &= !reg4.IsValid() || ((reg4.GetCode() % 2) == 0);
1078 const CPURegister& reg4 = NoCPUReg) {
1095 if (!reg4.IsValid()) {
1097 } else if (reg4.GetCode() !=
1112 const CPURegister& reg4 = NoCPUReg) {
[all …]
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| D | macro-assembler-aarch64.cc | 3038 const Register& reg4) { in Emit() argument
3041 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3052 const VRegister& reg4) { in Emit() argument
3054 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3062 const CPURegister& reg4) { in Emit() argument
3067 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Emit()
3102 const Register& reg4) { in Emit() argument
3104 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3112 const VRegister& reg4) { in Emit() argument
3114 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
[all …]
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| D | operands-aarch64.h | 45 CPURegister reg4 = NoCPUReg)
46 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
49 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
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| /third_party/node/deps/v8/src/interpreter/ |
| D | bytecode-register.cc | 106 Register reg4, Register reg5) { in AreContiguous() argument
113 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) { in AreContiguous()
116 if (reg5.is_valid() && reg4.index() + 1 != reg5.index()) { in AreContiguous()
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| D | bytecode-register.h | 87 Register reg4 = invalid_value(),
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| /third_party/ffmpeg/libavcodec/mips/ |
| D | vp9_idct_msa.c | 967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
986 VP9_DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vp9_idct16_1d_columns_addblk_msa()
987 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_msa()
993 reg4 = reg6 - loc3; in vp9_idct16_1d_columns_addblk_msa()
1035 loc1 = reg4 + loc0; in vp9_idct16_1d_columns_addblk_msa()
1036 loc2 = reg4 - loc0; in vp9_idct16_1d_columns_addblk_msa()
1040 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vp9_idct16_1d_columns_addblk_msa()
1054 SRARI_H4_SH(reg0, reg2, reg4, reg6, 6); in vp9_idct16_1d_columns_addblk_msa()
1055 VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg0, reg2, reg4, reg6); in vp9_idct16_1d_columns_addblk_msa()
[all …]
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| D | vp9mc_16bpp_neon.S | 326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
330 sqrshrun \reg4\().4h, \reg4\().4s, #7
340 umin \reg4\().4h, \reg4\().4h, \minreg\().4h
345 urhadd \reg4\().4h, \reg4\().4h, \tmp4\().4h
350 st1 {\reg4\().4h}, [x0], x1
355 .macro do_store8 reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, minreg, type
359 sqrshrun2 \reg2\().8h, \reg4\().4s, #7
362 sqrshrun \reg4\().4h, \reg7\().4s, #7
363 sqrshrun2 \reg4\().8h, \reg8\().4s, #7
373 umin \reg4\().8h, \reg4\().8h, \minreg\().8h
[all …]
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| D | vp9mc_neon.S | 407 .macro do_store reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, type
411 sqrshrun \reg4\().8b, \reg4\().8h, #7
420 urhadd \reg4\().8b, \reg4\().8b, \tmp4\().8b
425 st1 {\reg4\().8b}, [x0], x1
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_optimizer.cpp | 506 void replace_src(Instr *instr, RegisterVec4& reg4);
553 void SimplifySourceVecVisitor::replace_src(Instr *instr, RegisterVec4& reg4) in replace_src() argument
556 auto s = reg4[i]; in replace_src()
571 ReplaceConstSource visitor(instr, reg4, i); in replace_src()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | register-arm64.h | 515 const CPURegister& reg3 = NoReg, const CPURegister& reg4 = NoReg,
525 const CPURegister& reg3 = NoCPUReg, const CPURegister& reg4 = NoCPUReg,
534 const VRegister& reg4 = NoVReg);
543 const VRegister& reg4 = NoVReg);
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| D | assembler-arm64.cc | 225 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
234 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
261 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
268 match &= !reg4.is_valid() || reg4.IsSameSizeAndType(reg1); in AreSameSizeAndType()
277 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat() argument
281 (!reg4.is_valid() || reg4.IsSameFormat(reg1)); in AreSameFormat()
285 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive() argument
288 DCHECK(!reg3.is_valid() && !reg4.is_valid()); in AreConsecutive()
295 DCHECK(!reg4.is_valid()); in AreConsecutive()
301 if (!reg4.is_valid()) { in AreConsecutive()
[all …]
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| /third_party/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 454 CPURegister reg4) { in Printf() argument
462 PushRegister(reg4); in Printf()
476 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) | in Printf()
481 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() + in Printf()
505 if (reg4.GetType() == CPURegister::kRRegister) { in Printf()
506 available_registers.Remove(Register(reg4.GetCode())); in Printf()
516 PushRegister(reg4); in Printf()
529 PreparePrintfArgument(reg4, &core_count, &vfp_count, &printf_type); in Printf()
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| D | instructions-aarch32.h | 468 constexpr RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
470 RegisterToList(reg3) | RegisterToList(reg4)) {}
559 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList() argument
561 RegisterToList(reg3) | RegisterToList(reg4)) {} in VRegisterList()
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| /third_party/skia/third_party/externals/opengl-registry/extensions/ATI/ |
| D | ATI_text_fragment_shader.txt | 1107 DOT3 r4, r1, r4.2x.bias; # reg4 = N.L
1125 MUL r4, r0, r4; # reg4 = diff * env map
1144 DOT3 r4, r1.2x.bias, r4.2x.bias; # reg4 = N.L
1172 MUL r4, r0, r4; # reg4 = diffuse * basemap
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| /third_party/openGLES/extensions/ATI/ |
| D | ATI_text_fragment_shader.txt | 1107 DOT3 r4, r1, r4.2x.bias; # reg4 = N.L
1125 MUL r4, r0, r4; # reg4 = diff * env map
1144 DOT3 r4, r1.2x.bias, r4.2x.bias; # reg4 = N.L
1172 MUL r4, r0, r4; # reg4 = diffuse * basemap
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | macro-assembler-arm.h | 36 Register reg4 = no_reg,
|