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/third_party/rust/crates/libc/ci/docker/riscv64gc-unknown-linux-gnu/
DDockerfile5 gcc-riscv64-linux-gnu libc6-dev-riscv64-cross \
6 qemu-system-riscv64 linux-headers-generic
8 ENV CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER=riscv64-linux-gnu-gcc \
9 CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER="qemu-riscv64 -L /usr/riscv64-linux-gnu" \
10 CC_riscv64gc_unknown_linux_gnu=riscv64-linux-gnu-gcc \
/third_party/node/deps/openssl/config/archs/linux64-riscv64/no-asm/
Dopenssl-cl.gypi3 'openssl_defines_linux64-riscv64': [
9 'openssl_cflags_linux64-riscv64': [
14 'openssl_ex_libs_linux64-riscv64': [
17 'openssl_cli_srcs_linux64-riscv64': [
54 './config/archs/linux64-riscv64/no-asm/apps/progs.c',
92 'defines': ['<@(openssl_defines_linux64-riscv64)'],
96 'cflags' : ['<@(openssl_cflags_linux64-riscv64)'],
97 'libraries': ['<@(openssl_ex_libs_linux64-riscv64)'],
98 'sources': ['<@(openssl_cli_srcs_linux64-riscv64)'],
Dopenssl-fips.gypi274 'openssl_sources_linux64-riscv64': [
275 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_sm2_gen.c',
276 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_digests_gen.c',
277 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_dsa_gen.c',
278 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_ec_gen.c',
279 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_ecx_gen.c',
280 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_rsa_gen.c',
281 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_wrap_gen.c',
282 './config/archs/linux64-riscv64/no-asm/providers/legacy.ld',
283 './config/archs/linux64-riscv64/no-asm/providers/fips.ld',
[all …]
Dopenssl.gypi955 'openssl_sources_linux64-riscv64': [
956 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_sm2_gen.c',
957 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_digests_gen.c',
958 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_dsa_gen.c',
959 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_ec_gen.c',
960 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_ecx_gen.c',
961 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_rsa_gen.c',
962 './config/archs/linux64-riscv64/no-asm/providers/common/der/der_wrap_gen.c',
963 './config/archs/linux64-riscv64/no-asm/providers/legacy.ld',
964 './config/archs/linux64-riscv64/no-asm/providers/fips.ld',
[all …]
/third_party/rust/crates/linux-raw-sys/gen/ioctl/
Dgenerate.sh41 riscv64-linux-gnu-gcc -Iinclude -c list.c $cflags
42 riscv64-linux-gnu-gcc main.c list.o -o main.exe $cflags
43 qemu-riscv64 -L /usr/riscv64-linux-gnu ./main.exe >> "$out"
/third_party/elfutils/tests/
Drun-disasm-riscv64.sh20 testfiles testfile-riscv64-dis1.o testfile-riscv64-dis1.expect
21 testrun_compare ${abs_top_builddir}/src/objdump -d testfile-riscv64-dis1.o < testfile-riscv64-dis1.…
26 cat <<EOF | riscv64-linux-gnu-as -c -o testfile-riscv64-dis1.o -
Drun-strip-test12.sh1 original=testfile-riscv64
2 stripped=testfile-riscv64-s
/third_party/rust/crates/rustix/src/backend/linux_raw/arch/outline/
Driscv64.s1 # Assembly code for making riscv64 syscalls.
3 # riscv64 syscall argument register ordering is the same as the riscv64
/third_party/node/deps/v8/infra/mb/
Dmb_config.pyl37 'riscv64.debug': 'default_debug_riscv64',
38 'riscv64.optdebug': 'default_optdebug_riscv64',
39 'riscv64.release': 'default_release_riscv64',
40 'riscv64.debug.sim': 'default_debug_riscv64_sim',
41 'riscv64.optdebug.sim': 'default_optdebug_riscv64_sim',
42 'riscv64.release.sim': 'default_release_riscv64_sim',
200 'V8 Linux - riscv64 - sim - builder': 'release_simulate_riscv64',
340 'debug', 'riscv64', 'gcc', 'v8_enable_slow_dchecks', 'v8_full_debug'],
342 'debug', 'riscv64', 'gcc', 'v8_enable_slow_dchecks'],
344 'release', 'riscv64', 'gcc'],
[all …]
/third_party/rust/crates/libc/src/unix/linux_like/linux/gnu/b64/
Dmod.rs118 mod riscv64;
119 pub use self::riscv64::*;
/third_party/node/deps/v8/
DBUILD.bazel351 # NOTE: Bazel rules for riscv64 weren't tested on a real system.
2327 "src/baseline/riscv64/baseline-assembler-riscv64-inl.h",
2328 "src/baseline/riscv64/baseline-compiler-riscv64-inl.h",
2329 "src/codegen/riscv64/assembler-riscv64.cc",
2330 "src/codegen/riscv64/assembler-riscv64.h",
2331 "src/codegen/riscv64/assembler-riscv64-inl.h",
2332 "src/codegen/riscv64/constants-riscv64.cc",
2333 "src/codegen/riscv64/constants-riscv64.h",
2334 "src/codegen/riscv64/cpu-riscv64.cc",
2335 "src/codegen/riscv64/interface-descriptors-riscv64-inl.h",
[all …]
DBUILD.gn559 v8_current_cpu == "arm64" || v8_current_cpu == "riscv64",
560 "Sharing a pointer compression cage is only supported on x64,arm64 and riscv64")
623 if (v8_current_cpu == "riscv64") {
695 if (current_cpu == "riscv64") {
1190 if (v8_current_cpu == "riscv64") {
1294 v8_current_cpu == "mips64el" || v8_current_cpu == "riscv64") {
2474 } else if (v8_current_cpu == "riscv64") {
2476 ### gcmole(arch:riscv64) ###
2477 "src/builtins/riscv64/builtins-riscv64.cc",
3861 } else if (v8_current_cpu == "riscv64") {
[all …]
/third_party/musl/
Dmusl_src.gni163 } else if (musl_arch == "riscv64") {
165 "src/fenv/riscv64/fenv-sf.c",
166 "src/fenv/riscv64/fenv.S",
167 "src/ldso/riscv64/dlsym.s",
168 "src/math/riscv64/copysign.c",
169 "src/math/riscv64/copysignf.c",
170 "src/math/riscv64/fabs.c",
171 "src/math/riscv64/fabsf.c",
172 "src/math/riscv64/fma.c",
173 "src/math/riscv64/fmaf.c",
[all …]
Dmusl_config.gni15 } else if (current_cpu == "riscv64") {
16 musl_arch = "riscv64"
/third_party/rust/crates/libc/src/unix/linux_like/linux/musl/b64/
Dmod.rs161 mod riscv64;
162 pub use self::riscv64::*;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/
DTriple.cpp56 case riscv64: return "riscv64"; in getArchTypeName()
147 case riscv64: return "riscv"; in getArchTypePrefix()
289 .Case("riscv64", riscv64) in getArchTypeForLLVMName()
422 .Case("riscv64", Triple::riscv64) in parseArch()
696 case Triple::riscv64: in getDefaultFormat()
1286 case llvm::Triple::riscv64: in getArchPointerBitWidth()
1366 case Triple::riscv64: T.setArch(Triple::riscv32); break; in get32BitArchVariant()
1408 case Triple::riscv64: in get64BitArchVariant()
1429 case Triple::riscv32: T.setArch(Triple::riscv64); break; in get64BitArchVariant()
1464 case Triple::riscv64: in getBigEndianArchVariant()
[all …]
/third_party/lzma/
DBUILD.gn126 } else if (target_cpu == "riscv64") {
153 } else if (current_cpu == "riscv64") {
/third_party/node/deps/openssl/
Dopenssl_no_asm.gypi43 }, 'target_arch=="riscv64" and OS=="linux"', {
44 'includes': ['config/archs/linux64-riscv64/no-asm/openssl.gypi'],
Dopenssl-fips_no_asm.gypi43 }, 'target_arch=="riscv64" and OS=="linux"', {
44 'includes': ['config/archs/linux64-riscv64/no-asm/openssl-fips.gypi'],
Dopenssl-cl_no_asm.gypi42 }, 'target_arch=="riscv64" and OS=="linux"', {
43 'includes': ['config/archs/linux64-riscv64/no-asm/openssl-cl.gypi'],
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/TargetInfo/
DRISCVTargetInfo.cpp26 RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64", in LLVMInitializeRISCVTargetInfo()
/third_party/node/deps/v8/src/base/
Dbuild_config.h177 #error Target architecture riscv64 is only supported on riscv64 and x64 host
/third_party/node/deps/v8/bazel/config/
DBUILD.bazel59 constraint_values = ["@platforms//cpu:riscv64"],
105 name = "riscv64",
/third_party/rust/crates/rustix/
DCargo.toml41 … target_pointer_width = "64"), target_arch = "powerpc64", target_arch = "riscv64", target_arch = "…
50 … target_pointer_width = "64"), target_arch = "powerpc64", target_arch = "riscv64", target_arch = "…
58 … target_pointer_width = "64"), target_arch = "powerpc64", target_arch = "riscv64", target_arch = "…
/third_party/node/tools/v8_gypfiles/
Dv8.gyp290 ['v8_target_arch=="riscv64" or v8_target_arch=="riscv64"', {
292 '<(V8_ROOT)/src/builtins/riscv64/builtins-riscv64.cc',
660 ['v8_target_arch=="riscv64"', {
662 …ILD.gn" "v8_header_set.\\"v8_internal_headers\\".*?v8_current_cpu == \\"riscv64\\".*?sources \\+=…
905 ['v8_target_arch=="riscv64"', {
907 …(V8_ROOT)/BUILD.gn" "\\"v8_base_without_compiler.*?v8_current_cpu == \\"riscv64\\".*?sources \\+=…
980 …#['v8_current_cpu in ["mips", "mipsel", "mips64", "mips64el", "ppc", "arm", "riscv64", "loong64"]'…
1679 …['_toolset == "host" and host_arch == "riscv64" or _toolset == "target" and target_arch=="riscv64"…
1681 '<(V8_ROOT)/src/heap/base/asm/riscv64/push_registers_asm.cc',

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