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Searched refs:scalarize (Results 1 – 10 of 10) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp268 .scalarize(0); in AMDGPULegalizerInfo()
273 .scalarize(0); in AMDGPULegalizerInfo()
281 .scalarize(0); in AMDGPULegalizerInfo()
286 .scalarize(0); in AMDGPULegalizerInfo()
296 .scalarize(0); in AMDGPULegalizerInfo()
302 .scalarize(0); // TODO: Implement. in AMDGPULegalizerInfo()
368 .scalarize(0); in AMDGPULegalizerInfo()
372 .scalarize(0); in AMDGPULegalizerInfo()
376 .scalarize(0); in AMDGPULegalizerInfo()
383 .scalarize(0) in AMDGPULegalizerInfo()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64LegalizerInfo.cpp118 .scalarize(0); in AArch64LegalizerInfo()
178 .scalarize(0) in AArch64LegalizerInfo()
412 .scalarize(0); in AArch64LegalizerInfo()
494 scalarize(0)) in AArch64LegalizerInfo()
497 scalarize(1)) in AArch64LegalizerInfo()
538 .scalarize(0) in AArch64LegalizerInfo()
539 .scalarize(1); in AArch64LegalizerInfo()
580 .scalarize(1); in AArch64LegalizerInfo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizeMutations.cpp67 LegalizeMutation LegalizeMutations::scalarize(unsigned TypeIdx) { in scalarize() function in LegalizeMutations
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizerInfo.h286 LegalizeMutation scalarize(unsigned TypeIdx);
735 LegalizeRuleSet &scalarize(unsigned TypeIdx) { in scalarize() function
738 LegalizeMutations::scalarize(TypeIdx)); in scalarize()
/third_party/mesa3d/docs/relnotes/
D22.1.2.rst145 - zink: scalarize when rewriting explicit 64bit io
D22.2.0.rst1848 - mesa/st: Only scalarize for doubles lowering if we're lowering doubles.
3823 - radeonsi: scalarize IO instructions
4587 - zink: always scalarize pack/unpack alu ops
4597 - zink: scalarize when rewriting explicit 64bit io
D20.3.0.rst3440 - radeonsi: don't scalarize 16-bit vec2 ALU opcodes
4119 - nir: scalarize fdot in reverse
D22.1.0.rst2247 - nir: scalarize transform feedback info in nir_lower_io_to_scalar
D22.0.0.rst1697 - broadcom/compiler: add lowering pass to scalarize non 32-bit general load/store
D21.2.0.rst1558 - radv,aco: scalarize all phis via nir_lower_phis_to_scalar()