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Searched refs:slti (Results 1 – 25 of 26) sorted by relevance

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/third_party/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz2 ... sp,3 66 f4: 13 20 00 00 slti zero,zero,0 67 f8: 93 20 ...
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td439 // op2 can be cmpi or slti/sltiu
657 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
684 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
1066 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1121 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1166 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIM16Alu> {
1176 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIM16Alu> {
1180 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
DMipsSchedule.td329 def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu
DMipsScheduleP5600.td39 // and, lui, nor, or, slti, sltiu, sub, subu, xor
DMips64InstrInfo.td128 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
DMicroMipsInstrInfo.td726 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
DMipsScheduleGeneric.td45 // rotr, rotrv, seb, seh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl,
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.h265 void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
DIceInstMIPS32.cpp1031 Asm->slti(getDest(), getSrc(0), Imm); in emitIAS()
DIceAssemblerMIPS32.cpp1002 void AssemblerMIPS32::slti(const Operand *OpRt, const Operand *OpRs, in slti() function in Ice::MIPS32::AssemblerMIPS32
/third_party/node/deps/v8/src/codegen/loong64/
Dassembler-loong64.h390 void slti(Register rd, Register rj, int32_t si12);
Dassembler-loong64.cc1087 void Assembler::slti(Register rd, Register rj, int32_t si12) { in slti() function in v8::internal::Assembler
Dmacro-assembler-loong64.cc698 slti(rd, rj, static_cast<int32_t>(rk.immediate())); in CallRecordWriteStub()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td412 def SLTI : ALU_ri<0b010, "slti">;
/third_party/node/deps/v8/src/codegen/riscv64/
Dassembler-riscv64.h432 void slti(Register rd, Register rs1, int16_t imm12);
Dassembler-riscv64.cc1601 void Assembler::slti(Register rd, Register rs1, int16_t imm12) { in slti() function in v8::internal::Assembler
Dmacro-assembler-riscv64.cc785 slti(rd, rs, static_cast<int32_t>(rt.immediate())); in Slt()
/third_party/node/deps/v8/src/codegen/mips/
Dassembler-mips.h593 void slti(Register rd, Register rs, int32_t j);
Dassembler-mips.cc2304 void Assembler::slti(Register rt, Register rs, int32_t j) { in slti() function in v8::internal::Assembler
Dmacro-assembler-mips.cc774 slti(rd, rs, rt.immediate()); in CallRecordWriteStub()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5088 "slli.h\006slli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei"
7728 …{ 8459 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16…
7729 …{ 8459 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc…
7730 …{ 8459 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicr…
7731 …{ 8459 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16R…
11236 { 8459 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11237 { 8459 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
/third_party/node/deps/v8/src/codegen/mips64/
Dassembler-mips64.h637 void slti(Register rd, Register rs, int32_t j);
Dassembler-mips64.cc2443 void Assembler::slti(Register rt, Register rs, int32_t j) { in slti() function in v8::internal::Assembler
Dmacro-assembler-mips64.cc907 slti(rd, rs, static_cast<int32_t>(rt.immediate())); in CallRecordWriteStub()
/third_party/node/deps/v8/src/builtins/mips/
Dbuiltins-mips.cc3350 __ slti(t2, a2, 2 * loadstore_chunk); in Generate_MemCopyUint8Uint8() local

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