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Searched refs:tg4 (Results 1 – 14 of 14) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_emit.c203 unsigned num_textures = tex->num_textures + v->astc_srgb.count + v->tg4.count; in emit_textures()
261 for (i = 0; i < v->tg4.count; i++) { in emit_textures()
264 unsigned idx = v->tg4.orig_idx[i]; in emit_textures()
343 assert(v->tg4.count == 0); in emit_textures()
929 cp->tg4.count; in fd4_emit_cs_state()
/third_party/mesa3d/docs/relnotes/
D17.2.6.rst61 - nir/spirv: tg4 requires a sampler
D22.1.0.rst1608 - freedreno/ir3: remove bogus tg4 -> tex lowering pass
1611 - freedreno/a4xx: add swizzles to shader keys for tg4 workaround
1612 - freedreno/a4xx: fix integer tg4
1617 - freedreno/a4xx: extend astc and tg4 workarounds to compute shaders
3073 - ac/llvm: remove deref chasing for tg4 integer workaround
3104 - radv: fix clearing of TRUNC_COORD with tg4 and immutable samplers
D22.2.0.rst1807 - nir: Don't assert on tg4 offset range.
2609 - radeonsi: r600: d3d12: st: Use NIR lowering for tg4 offset arrays instead of GLSL lowering
4747 - zink: allow multiple tex components for depth tg4
5179 - radv: fix clearing of TRUNC_COORD with tg4 and immutable samplers
D19.1.0.rst2188 - spirv: Drop inline tg4 lowering
2466 - nir/lower_tex: Add support for tg4 offsets lowering
D22.0.0.rst2334 - intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHP
3661 - intel/compiler: Assert that unsupported tg4 offsets were lowered for XeHP
D19.0.0.rst799 - v3d: Force sampling from base level for tg4.
D19.3.0.rst915 - llvmpipe: add support for tg4 component selection.
D21.0.0.rst2513 - zink: handle non-const offsets for txf/tg4 ops
D20.3.0.rst1277 - gallivm/nir: lower tg4 offsets.
D21.1.0.rst4814 - aco: fix integer tg4 workaround with unnormalized coordinates
/third_party/mesa3d/src/freedreno/ir3/
Dir3_shader.h713 } tg4; member
Dir3_compiler_nir.c3217 array_insert(ctx->ir, ctx->ir->tg4, sam); in emit_tex()
4469 so->tg4.base = tex_idx; in fixup_tg4()
4472 struct ir3_instruction *sam = ctx->ir->tg4[i]; in fixup_tg4()
4479 so->tg4.orig_idx[idx++] = sam->cat5.tex; in fixup_tg4()
4480 so->tg4.count++; in fixup_tg4()
Dir3.h540 DECLARE_ARRAY(struct ir3_instruction *, tg4);