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Searched refs:u_bit_consecutive (Results 1 – 25 of 48) sorted by relevance

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/third_party/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_util.c271 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
273 read_mask = u_bit_consecutive(0, dim_layer_shadow) & 0xf; in tgsi_util_get_src_usage_mask()
287 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
297 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
308 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
315 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
336 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_src_usage_mask()
/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
Dnir.c45 dest->write_mask = u_bit_consecutive(0, ssa->num_components); in ppir_node_create_ssa()
113 u_bit_consecutive(0, 4)); in ppir_node_add_src()
246 &instr->src[0], u_bit_consecutive(0, instr->num_components)); in ppir_emit_discard_if()
271 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
292 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
320 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
383 dest->write_mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
392 u_bit_consecutive(0, instr->num_components)); in ppir_emit_intrinsic()
481 mask = u_bit_consecutive(0, nir_tex_instr_dest_size(instr)); in ppir_emit_tex()
516 u_bit_consecutive(0, instr->coord_components)); in ppir_emit_tex()
Dregalloc.c214 ld_dest->write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_src()
249 alu_dest->write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_src()
298 load->dest.write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_dest_load()
321 move_alu->dest.write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_dest_load()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shaderlib_tgsi.c158 ureg_writemask(ureg_dst(values[i]), u_bit_consecutive(0, inst_dwords[i])); in si_create_dma_compute_shader()
170 struct ureg_dst dst = ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d])); in si_create_dma_compute_shader()
Dsi_blit.c298 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); in si_decompress_depth()
450 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); in si_blit_decompress_color()
733 u_bit_consecutive(0, info->base.num_images)); in si_check_render_feedback()
820 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) { in si_decompress_textures()
1267 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1, last_level - base_level); in si_generate_mipmap()
Dsi_descriptors.c2047 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, SI_NUM_SHADER_DESCS); in si_mark_shader_pointers_dirty()
2066 sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS); in si_shader_pointers_mark_dirty()
2244 sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_INTERNAL, SI_DESCS_FIRST_COMPUTE); in si_emit_graphics_shader_pointers()
2780 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS); in si_init_all_descriptors()
2843 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE); in si_upload_graphics_shader_descriptors()
2853 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE); in si_upload_compute_shader_descriptors()
2895 … u_bit_consecutive(0, current_shader->cso->info.base.num_images)); in si_gfx_resources_check_encrypted()
2974 …si_image_views_check_encrypted(sctx, &sctx->images[sh], u_bit_consecutive(0, info->base.num_images… in si_compute_resources_check_encrypted()
Dsi_debug.c758 enabled_constbuf = u_bit_consecutive(0, info->base.num_ubos); in si_dump_descriptors()
759 enabled_shaderbuf = u_bit_consecutive(0, info->base.num_ssbos); in si_dump_descriptors()
761 enabled_images = u_bit_consecutive(0, info->base.num_images); in si_dump_descriptors()
Dsi_shader_info.c810 u_bit_consecutive(0, info->base.clip_distance_array_size); in si_nir_scan_shader()
811 info->culldist_mask = u_bit_consecutive(0, info->base.cull_distance_array_size) << in si_nir_scan_shader()
Dsi_compute.c153 unsigned non_fmask_images = u_bit_consecutive(0, sel->info.base.num_images); in si_create_compute_state_async()
916 mask = u_bit_consecutive(0, info->base.num_images) & images->enabled_mask; in si_check_needs_implicit_sync()
Dsi_gfx_cs.c465 u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs); in si_begin_new_gfx_cs()
469 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8); in si_begin_new_gfx_cs()
Dsi_state.h410 u_bit_consecutive(SI_DESCS_FIRST_SHADER + PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
Dsi_clear.c231 int max = u_bit_consecutive(0, desc->channel[i].size - 1); in gfx8_get_dcc_clear_parameters()
239 unsigned max = u_bit_consecutive(0, desc->channel[i].size); in gfx8_get_dcc_clear_parameters()
/third_party/mesa3d/src/compiler/nir/
Dnir_lower_clip_disable.c125 if (clip_plane_enable == u_bit_consecutive(0, shader->info.clip_distance_array_size)) in nir_lower_clip_disable()
/third_party/mesa3d/src/util/
Dbitscan.h280 u_bit_consecutive(unsigned start, unsigned count) in u_bit_consecutive() function
/third_party/mesa3d/src/mesa/state_tracker/
Dst_atom.c147 if (ctx->Scissor.EnableFlags & u_bit_consecutive(0, num_viewports)) in check_program_state()
Dst_atom_blend.c133 GLbitfield cb_mask = u_bit_consecutive(0, num_cb); in blend_per_rt()
/third_party/mesa3d/src/gallium/auxiliary/nir/
Dnir_to_tgsi_info.c798 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance); in nir_tgsi_scan_shader()
799 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance); in nir_tgsi_scan_shader()
/third_party/mesa3d/src/gallium/auxiliary/util/
Du_helpers.c58 *enabled_buffers &= ~u_bit_consecutive(start_slot, count); in util_set_vertex_buffers_mask()
/third_party/mesa3d/src/amd/compiler/
Daco_insert_NOPs.cpp223 writemask |= u_bit_consecutive(start, end - start); in handle_raw_hazard_instr()
282 state, state.block, min_states, op.physReg(), u_bit_consecutive(0, op.size()), false); in handle_raw_hazard()
/third_party/mesa3d/src/gallium/drivers/virgl/
Dvirgl_context.c1241 vctx->atomic_buffer_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_hw_atomic_buffers()
1271 binding->ssbo_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_shader_buffers()
1327 binding->image_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_shader_images()
/third_party/mesa3d/src/gallium/drivers/lima/
Dlima_job.c755 wb[wb_idx].mrt_bits = u_bit_consecutive(0, nr_samples); in lima_pack_wb_zsbuf_reg()
790 wb[wb_idx].mrt_bits = u_bit_consecutive(0, nr_samples); in lima_pack_wb_cbuf_reg()
/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_state.c1088 unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots); in nv50_set_vertex_buffers()
1094 clear_mask = ~u_bit_consecutive(start_slot, count); in nv50_set_vertex_buffers()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c438 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.max_render_backends); in do_winsys_init()
/third_party/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_state.c151 const unsigned modified_bits = u_bit_consecutive(start, count); in fd_set_shader_buffers()
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_state.c1032 unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots); in nvc0_set_vertex_buffers()
1038 clear_mask = ~u_bit_consecutive(start_slot, count); in nvc0_set_vertex_buffers()

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