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Searched refs:VOP1 (Results 1 – 19 of 19) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td28 field bit VOP1 = 0;
140 let TSFlags{7} = VOP1;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
DVOP1Instructions.td10 // VOP1 Classes
51 let VOP1 = 1;
142 // VOP1 Instructions
170 let VOP1 = 1;
811 let VOP1 = 1;
821 let VOP1 = 1;
DSIInstrInfo.td1439 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
1459 VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst
1594 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1607 // VOP1 without input operands (V_NOP, V_CLREXCP)
1612 // VOP1 with modifiers
1616 // VOP1 without modifiers
1747 // VOP1 without input operands (V_NOP)
1791 // VOP1 without input operands (V_NOP)
1823 // VOP1 without input operands (V_NOP)
1826 // VOP1
[all …]
DSIDefines.h32 VOP1 = 1 << 7, enumerator
DSIInstrInfo.h406 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
410 return get(Opcode).TSFlags & SIInstrFlags::VOP1; in isVOP1()
DSIInstructions.td680 // VOP1 Patterns
/third_party/mesa3d/src/amd/compiler/
Daco_opcodes.py72 VOP1 = 1 << 8 variable in Format
762 VOP1 = { variable
858 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, in_mod, out_mod, cls) in default_class(VOP1, InstrClass.V…
859 opcode(name, gfx7, gfx9, gfx10, Format.VOP1, cls, in_mod, out_mod)
Daco_validate.cpp121 if ((uint32_t)base_format & (uint32_t)Format::VOP1) in validate_ir()
122 base_format = Format::VOP1; in validate_ir()
145 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
152 check(base_format == Format::VOP2 || base_format == Format::VOP1 || in validate_ir()
Daco_ir.h98 VOP1 = 1 << 8, enumerator
291 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
1258 constexpr bool isVOP1() const noexcept { return (uint16_t)format & (uint16_t)Format::VOP1; } in isVOP1()
DREADME-ISA.md97 ## VOP1 instructions encoded as VOP3
Daco_insert_NOPs.cpp713 create_instruction<VOP1_instruction>(aco_opcode::v_mov_b32, Format::VOP1, 1, 1)}; in handle_instruction_gfx10()
Daco_assembler.cpp282 case Format::VOP1: { in emit_instruction()
Daco_lower_to_hw_instr.cpp516 aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)}; in emit_reduction()
539 aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)}; in emit_reduction()
Daco_spill.cpp290 if (instr->format != Format::VOP1 && instr->format != Format::SOP1 && in should_rematerialize()
Daco_register_allocation.cpp3057 Format::VOP1, 1, 1)); in register_allocation()
Daco_instruction_selection.cpp9342 create_instruction<VOP3_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)}; in prepare_cube_coords()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2820 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
3260 if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0) in validateLdsDirect()
6851 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1); in cvtSdwaVOP1()
6922 case SIInstrFlags::VOP1: in cvtSDWA()
/third_party/mesa3d/docs/relnotes/
D19.3.0.rst3292 - aco: Support GFX10 VOP3 and VOP1 as VOP3 in aco_assembler.
D20.3.0.rst1183 - aco: propagate SGPRs into VOP1 instructions early.