1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI DaVinci clocksource driver
4 *
5 * Copyright (C) 2019 Texas Instruments
6 * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
7 * (with tiny parts adopted from code by Kevin Hilman <khilman@baylibre.com>)
8 */
9
10 #include <linux/clk.h>
11 #include <linux/clockchips.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/sched_clock.h>
17
18 #include <clocksource/timer-davinci.h>
19
20 #undef pr_fmt
21 #define pr_fmt(fmt) "%s: " fmt, __func__
22
23 #define DAVINCI_TIMER_REG_TIM12 0x10
24 #define DAVINCI_TIMER_REG_TIM34 0x14
25 #define DAVINCI_TIMER_REG_PRD12 0x18
26 #define DAVINCI_TIMER_REG_PRD34 0x1c
27 #define DAVINCI_TIMER_REG_TCR 0x20
28 #define DAVINCI_TIMER_REG_TGCR 0x24
29
30 #define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2)
31 #define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0)
32 #define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2)
33 #define DAVINCI_TIMER_UNRESET GENMASK(1, 0)
34
35 #define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0)
36 #define DAVINCI_TIMER_ENAMODE_DISABLED 0x00
37 #define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0)
38 #define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1)
39
40 #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6
41 #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22
42
43 #define DAVINCI_TIMER_MIN_DELTA 0x01
44 #define DAVINCI_TIMER_MAX_DELTA 0xfffffffe
45
46 #define DAVINCI_TIMER_CLKSRC_BITS 32
47
48 #define DAVINCI_TIMER_TGCR_DEFAULT \
49 (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET)
50
51 struct davinci_clockevent {
52 struct clock_event_device dev;
53 void __iomem *base;
54 unsigned int cmp_off;
55 };
56
57 /*
58 * This must be globally accessible by davinci_timer_read_sched_clock(), so
59 * let's keep it here.
60 */
61 static struct {
62 struct clocksource dev;
63 void __iomem *base;
64 unsigned int tim_off;
65 } davinci_clocksource;
66
67 static struct davinci_clockevent *
to_davinci_clockevent(struct clock_event_device * clockevent)68 to_davinci_clockevent(struct clock_event_device *clockevent)
69 {
70 return container_of(clockevent, struct davinci_clockevent, dev);
71 }
72
73 static unsigned int
davinci_clockevent_read(struct davinci_clockevent * clockevent,unsigned int reg)74 davinci_clockevent_read(struct davinci_clockevent *clockevent,
75 unsigned int reg)
76 {
77 return readl_relaxed(clockevent->base + reg);
78 }
79
davinci_clockevent_write(struct davinci_clockevent * clockevent,unsigned int reg,unsigned int val)80 static void davinci_clockevent_write(struct davinci_clockevent *clockevent,
81 unsigned int reg, unsigned int val)
82 {
83 writel_relaxed(val, clockevent->base + reg);
84 }
85
davinci_tim12_shutdown(void __iomem * base)86 static void davinci_tim12_shutdown(void __iomem *base)
87 {
88 unsigned int tcr;
89
90 tcr = DAVINCI_TIMER_ENAMODE_DISABLED <<
91 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
92 /*
93 * This function is only ever called if we're using both timer
94 * halves. In this case TIM34 runs in periodic mode and we must
95 * not modify it.
96 */
97 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
98 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
99
100 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
101 }
102
davinci_tim12_set_oneshot(void __iomem * base)103 static void davinci_tim12_set_oneshot(void __iomem *base)
104 {
105 unsigned int tcr;
106
107 tcr = DAVINCI_TIMER_ENAMODE_ONESHOT <<
108 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
109 /* Same as above. */
110 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
111 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
112
113 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
114 }
115
davinci_clockevent_shutdown(struct clock_event_device * dev)116 static int davinci_clockevent_shutdown(struct clock_event_device *dev)
117 {
118 struct davinci_clockevent *clockevent;
119
120 clockevent = to_davinci_clockevent(dev);
121
122 davinci_tim12_shutdown(clockevent->base);
123
124 return 0;
125 }
126
davinci_clockevent_set_oneshot(struct clock_event_device * dev)127 static int davinci_clockevent_set_oneshot(struct clock_event_device *dev)
128 {
129 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
130
131 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
132
133 davinci_tim12_set_oneshot(clockevent->base);
134
135 return 0;
136 }
137
138 static int
davinci_clockevent_set_next_event_std(unsigned long cycles,struct clock_event_device * dev)139 davinci_clockevent_set_next_event_std(unsigned long cycles,
140 struct clock_event_device *dev)
141 {
142 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
143
144 davinci_clockevent_shutdown(dev);
145
146 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
147 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles);
148
149 davinci_clockevent_set_oneshot(dev);
150
151 return 0;
152 }
153
154 static int
davinci_clockevent_set_next_event_cmp(unsigned long cycles,struct clock_event_device * dev)155 davinci_clockevent_set_next_event_cmp(unsigned long cycles,
156 struct clock_event_device *dev)
157 {
158 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
159 unsigned int curr_time;
160
161 curr_time = davinci_clockevent_read(clockevent,
162 DAVINCI_TIMER_REG_TIM12);
163 davinci_clockevent_write(clockevent,
164 clockevent->cmp_off, curr_time + cycles);
165
166 return 0;
167 }
168
davinci_timer_irq_timer(int irq,void * data)169 static irqreturn_t davinci_timer_irq_timer(int irq, void *data)
170 {
171 struct davinci_clockevent *clockevent = data;
172
173 if (!clockevent_state_oneshot(&clockevent->dev))
174 davinci_tim12_shutdown(clockevent->base);
175
176 clockevent->dev.event_handler(&clockevent->dev);
177
178 return IRQ_HANDLED;
179 }
180
davinci_timer_read_sched_clock(void)181 static u64 notrace davinci_timer_read_sched_clock(void)
182 {
183 return readl_relaxed(davinci_clocksource.base +
184 davinci_clocksource.tim_off);
185 }
186
davinci_clocksource_read(struct clocksource * dev)187 static u64 davinci_clocksource_read(struct clocksource *dev)
188 {
189 return davinci_timer_read_sched_clock();
190 }
191
192 /*
193 * Standard use-case: we're using tim12 for clockevent and tim34 for
194 * clocksource. The default is making the former run in oneshot mode
195 * and the latter in periodic mode.
196 */
davinci_clocksource_init_tim34(void __iomem * base)197 static void davinci_clocksource_init_tim34(void __iomem *base)
198 {
199 int tcr;
200
201 tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
202 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
203 tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT <<
204 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
205
206 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
207 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34);
208 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
209 }
210
211 /*
212 * Special use-case on da830: the DSP may use tim34. We're using tim12 for
213 * both clocksource and clockevent. We set tim12 to periodic and don't touch
214 * tim34.
215 */
davinci_clocksource_init_tim12(void __iomem * base)216 static void davinci_clocksource_init_tim12(void __iomem *base)
217 {
218 unsigned int tcr;
219
220 tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
221 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
222
223 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
224 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12);
225 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
226 }
227
davinci_timer_init(void __iomem * base)228 static void davinci_timer_init(void __iomem *base)
229 {
230 /* Set clock to internal mode and disable it. */
231 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR);
232 /*
233 * Reset both 32-bit timers, set no prescaler for timer 34, set the
234 * timer to dual 32-bit unchained mode, unreset both 32-bit timers.
235 */
236 writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT,
237 base + DAVINCI_TIMER_REG_TGCR);
238 /* Init both counters to zero. */
239 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
240 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
241 }
242
davinci_timer_register(struct clk * clk,const struct davinci_timer_cfg * timer_cfg)243 int __init davinci_timer_register(struct clk *clk,
244 const struct davinci_timer_cfg *timer_cfg)
245 {
246 struct davinci_clockevent *clockevent;
247 unsigned int tick_rate;
248 void __iomem *base;
249 int rv;
250
251 rv = clk_prepare_enable(clk);
252 if (rv) {
253 pr_err("Unable to prepare and enable the timer clock\n");
254 return rv;
255 }
256
257 if (!request_mem_region(timer_cfg->reg.start,
258 resource_size(&timer_cfg->reg),
259 "davinci-timer")) {
260 pr_err("Unable to request memory region\n");
261 rv = -EBUSY;
262 goto exit_clk_disable;
263 }
264
265 base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg));
266 if (!base) {
267 pr_err("Unable to map the register range\n");
268 rv = -ENOMEM;
269 goto exit_mem_region;
270 }
271
272 davinci_timer_init(base);
273 tick_rate = clk_get_rate(clk);
274
275 clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL);
276 if (!clockevent) {
277 rv = -ENOMEM;
278 goto exit_iounmap_base;
279 }
280
281 clockevent->dev.name = "tim12";
282 clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT;
283 clockevent->dev.cpumask = cpumask_of(0);
284 clockevent->base = base;
285
286 if (timer_cfg->cmp_off) {
287 clockevent->cmp_off = timer_cfg->cmp_off;
288 clockevent->dev.set_next_event =
289 davinci_clockevent_set_next_event_cmp;
290 } else {
291 clockevent->dev.set_next_event =
292 davinci_clockevent_set_next_event_std;
293 clockevent->dev.set_state_oneshot =
294 davinci_clockevent_set_oneshot;
295 clockevent->dev.set_state_shutdown =
296 davinci_clockevent_shutdown;
297 }
298
299 rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start,
300 davinci_timer_irq_timer, IRQF_TIMER,
301 "clockevent/tim12", clockevent);
302 if (rv) {
303 pr_err("Unable to request the clockevent interrupt\n");
304 goto exit_free_clockevent;
305 }
306
307 davinci_clocksource.dev.rating = 300;
308 davinci_clocksource.dev.read = davinci_clocksource_read;
309 davinci_clocksource.dev.mask =
310 CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS);
311 davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS;
312 davinci_clocksource.base = base;
313
314 if (timer_cfg->cmp_off) {
315 davinci_clocksource.dev.name = "tim12";
316 davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12;
317 davinci_clocksource_init_tim12(base);
318 } else {
319 davinci_clocksource.dev.name = "tim34";
320 davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34;
321 davinci_clocksource_init_tim34(base);
322 }
323
324 clockevents_config_and_register(&clockevent->dev, tick_rate,
325 DAVINCI_TIMER_MIN_DELTA,
326 DAVINCI_TIMER_MAX_DELTA);
327
328 rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
329 if (rv) {
330 pr_err("Unable to register clocksource\n");
331 goto exit_free_irq;
332 }
333
334 sched_clock_register(davinci_timer_read_sched_clock,
335 DAVINCI_TIMER_CLKSRC_BITS, tick_rate);
336
337 return 0;
338
339 exit_free_irq:
340 free_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start,
341 clockevent);
342 exit_free_clockevent:
343 kfree(clockevent);
344 exit_iounmap_base:
345 iounmap(base);
346 exit_mem_region:
347 release_mem_region(timer_cfg->reg.start,
348 resource_size(&timer_cfg->reg));
349 exit_clk_disable:
350 clk_disable_unprepare(clk);
351 return rv;
352 }
353
of_davinci_timer_register(struct device_node * np)354 static int __init of_davinci_timer_register(struct device_node *np)
355 {
356 struct davinci_timer_cfg timer_cfg = { };
357 struct clk *clk;
358 int rv;
359
360 rv = of_address_to_resource(np, 0, &timer_cfg.reg);
361 if (rv) {
362 pr_err("Unable to get the register range for timer\n");
363 return rv;
364 }
365
366 rv = of_irq_to_resource_table(np, timer_cfg.irq,
367 DAVINCI_TIMER_NUM_IRQS);
368 if (rv != DAVINCI_TIMER_NUM_IRQS) {
369 pr_err("Unable to get the interrupts for timer\n");
370 return rv;
371 }
372
373 clk = of_clk_get(np, 0);
374 if (IS_ERR(clk)) {
375 pr_err("Unable to get the timer clock\n");
376 return PTR_ERR(clk);
377 }
378
379 rv = davinci_timer_register(clk, &timer_cfg);
380 if (rv)
381 clk_put(clk);
382
383 return rv;
384 }
385 TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register);
386