1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/drm_cache.h>
29 #include "amdgpu.h"
30 #include "gmc_v8_0.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_amdkfd.h"
33 #include "amdgpu_gem.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40
41 #include "oss/oss_3_0_d.h"
42 #include "oss/oss_3_0_sh_mask.h"
43
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46
47 #include "vid.h"
48 #include "vi.h"
49
50 #include "amdgpu_atombios.h"
51
52 #include "ivsrcid/ivsrcid_vislands30.h"
53
54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56 static int gmc_v8_0_wait_for_idle(void *handle);
57
58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
63 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
64 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
65
66 static const u32 golden_settings_tonga_a11[] =
67 {
68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
75 };
76
77 static const u32 tonga_mgcg_cgcg_init[] =
78 {
79 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
80 };
81
82 static const u32 golden_settings_fiji_a10[] =
83 {
84 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
85 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
86 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
87 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
88 };
89
90 static const u32 fiji_mgcg_cgcg_init[] =
91 {
92 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
93 };
94
95 static const u32 golden_settings_polaris11_a11[] =
96 {
97 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
98 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
99 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
100 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
101 };
102
103 static const u32 golden_settings_polaris10_a11[] =
104 {
105 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
106 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
107 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
108 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
109 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
110 };
111
112 static const u32 cz_mgcg_cgcg_init[] =
113 {
114 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
115 };
116
117 static const u32 stoney_mgcg_cgcg_init[] =
118 {
119 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
120 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
121 };
122
123 static const u32 golden_settings_stoney_common[] =
124 {
125 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
126 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
127 };
128
gmc_v8_0_init_golden_registers(struct amdgpu_device * adev)129 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
130 {
131 switch (adev->asic_type) {
132 case CHIP_FIJI:
133 amdgpu_device_program_register_sequence(adev,
134 fiji_mgcg_cgcg_init,
135 ARRAY_SIZE(fiji_mgcg_cgcg_init));
136 amdgpu_device_program_register_sequence(adev,
137 golden_settings_fiji_a10,
138 ARRAY_SIZE(golden_settings_fiji_a10));
139 break;
140 case CHIP_TONGA:
141 amdgpu_device_program_register_sequence(adev,
142 tonga_mgcg_cgcg_init,
143 ARRAY_SIZE(tonga_mgcg_cgcg_init));
144 amdgpu_device_program_register_sequence(adev,
145 golden_settings_tonga_a11,
146 ARRAY_SIZE(golden_settings_tonga_a11));
147 break;
148 case CHIP_POLARIS11:
149 case CHIP_POLARIS12:
150 case CHIP_VEGAM:
151 amdgpu_device_program_register_sequence(adev,
152 golden_settings_polaris11_a11,
153 ARRAY_SIZE(golden_settings_polaris11_a11));
154 break;
155 case CHIP_POLARIS10:
156 amdgpu_device_program_register_sequence(adev,
157 golden_settings_polaris10_a11,
158 ARRAY_SIZE(golden_settings_polaris10_a11));
159 break;
160 case CHIP_CARRIZO:
161 amdgpu_device_program_register_sequence(adev,
162 cz_mgcg_cgcg_init,
163 ARRAY_SIZE(cz_mgcg_cgcg_init));
164 break;
165 case CHIP_STONEY:
166 amdgpu_device_program_register_sequence(adev,
167 stoney_mgcg_cgcg_init,
168 ARRAY_SIZE(stoney_mgcg_cgcg_init));
169 amdgpu_device_program_register_sequence(adev,
170 golden_settings_stoney_common,
171 ARRAY_SIZE(golden_settings_stoney_common));
172 break;
173 default:
174 break;
175 }
176 }
177
gmc_v8_0_mc_stop(struct amdgpu_device * adev)178 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
179 {
180 u32 blackout;
181
182 gmc_v8_0_wait_for_idle(adev);
183
184 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
185 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
186 /* Block CPU access */
187 WREG32(mmBIF_FB_EN, 0);
188 /* blackout the MC */
189 blackout = REG_SET_FIELD(blackout,
190 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
191 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
192 }
193 /* wait for the MC to settle */
194 udelay(100);
195 }
196
gmc_v8_0_mc_resume(struct amdgpu_device * adev)197 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
198 {
199 u32 tmp;
200
201 /* unblackout the MC */
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
205 /* allow CPU access */
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
208 WREG32(mmBIF_FB_EN, tmp);
209 }
210
211 /**
212 * gmc_v8_0_init_microcode - load ucode images from disk
213 *
214 * @adev: amdgpu_device pointer
215 *
216 * Use the firmware interface to load the ucode images into
217 * the driver (not loaded into hw).
218 * Returns 0 on success, error on failure.
219 */
gmc_v8_0_init_microcode(struct amdgpu_device * adev)220 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
221 {
222 const char *chip_name;
223 char fw_name[30];
224 int err;
225
226 DRM_DEBUG("\n");
227
228 switch (adev->asic_type) {
229 case CHIP_TONGA:
230 chip_name = "tonga";
231 break;
232 case CHIP_POLARIS11:
233 if (((adev->pdev->device == 0x67ef) &&
234 ((adev->pdev->revision == 0xe0) ||
235 (adev->pdev->revision == 0xe5))) ||
236 ((adev->pdev->device == 0x67ff) &&
237 ((adev->pdev->revision == 0xcf) ||
238 (adev->pdev->revision == 0xef) ||
239 (adev->pdev->revision == 0xff))))
240 chip_name = "polaris11_k";
241 else if ((adev->pdev->device == 0x67ef) &&
242 (adev->pdev->revision == 0xe2))
243 chip_name = "polaris11_k";
244 else
245 chip_name = "polaris11";
246 break;
247 case CHIP_POLARIS10:
248 if ((adev->pdev->device == 0x67df) &&
249 ((adev->pdev->revision == 0xe1) ||
250 (adev->pdev->revision == 0xf7)))
251 chip_name = "polaris10_k";
252 else
253 chip_name = "polaris10";
254 break;
255 case CHIP_POLARIS12:
256 if (((adev->pdev->device == 0x6987) &&
257 ((adev->pdev->revision == 0xc0) ||
258 (adev->pdev->revision == 0xc3))) ||
259 ((adev->pdev->device == 0x6981) &&
260 ((adev->pdev->revision == 0x00) ||
261 (adev->pdev->revision == 0x01) ||
262 (adev->pdev->revision == 0x10))))
263 chip_name = "polaris12_k";
264 else
265 chip_name = "polaris12";
266 break;
267 case CHIP_FIJI:
268 case CHIP_CARRIZO:
269 case CHIP_STONEY:
270 case CHIP_VEGAM:
271 return 0;
272 default: BUG();
273 }
274
275 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
276 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
277 if (err)
278 goto out;
279 err = amdgpu_ucode_validate(adev->gmc.fw);
280
281 out:
282 if (err) {
283 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
284 release_firmware(adev->gmc.fw);
285 adev->gmc.fw = NULL;
286 }
287 return err;
288 }
289
290 /**
291 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
292 *
293 * @adev: amdgpu_device pointer
294 *
295 * Load the GDDR MC ucode into the hw (VI).
296 * Returns 0 on success, error on failure.
297 */
gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device * adev)298 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
299 {
300 const struct mc_firmware_header_v1_0 *hdr;
301 const __le32 *fw_data = NULL;
302 const __le32 *io_mc_regs = NULL;
303 u32 running;
304 int i, ucode_size, regs_size;
305
306 /* Skip MC ucode loading on SR-IOV capable boards.
307 * vbios does this for us in asic_init in that case.
308 * Skip MC ucode loading on VF, because hypervisor will do that
309 * for this adaptor.
310 */
311 if (amdgpu_sriov_bios(adev))
312 return 0;
313
314 if (!adev->gmc.fw)
315 return -EINVAL;
316
317 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
318 amdgpu_ucode_print_mc_hdr(&hdr->header);
319
320 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
321 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
322 io_mc_regs = (const __le32 *)
323 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
324 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
325 fw_data = (const __le32 *)
326 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
327
328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
329
330 if (running == 0) {
331 /* reset the engine and set to writable */
332 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
333 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
334
335 /* load mc io regs */
336 for (i = 0; i < regs_size; i++) {
337 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
338 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
339 }
340 /* load the MC ucode */
341 for (i = 0; i < ucode_size; i++)
342 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
343
344 /* put the engine back into the active state */
345 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
346 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
347 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
348
349 /* wait for training to complete */
350 for (i = 0; i < adev->usec_timeout; i++) {
351 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
352 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
353 break;
354 udelay(1);
355 }
356 for (i = 0; i < adev->usec_timeout; i++) {
357 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
358 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
359 break;
360 udelay(1);
361 }
362 }
363
364 return 0;
365 }
366
gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device * adev)367 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
368 {
369 const struct mc_firmware_header_v1_0 *hdr;
370 const __le32 *fw_data = NULL;
371 const __le32 *io_mc_regs = NULL;
372 u32 data;
373 int i, ucode_size, regs_size;
374
375 /* Skip MC ucode loading on SR-IOV capable boards.
376 * vbios does this for us in asic_init in that case.
377 * Skip MC ucode loading on VF, because hypervisor will do that
378 * for this adaptor.
379 */
380 if (amdgpu_sriov_bios(adev))
381 return 0;
382
383 if (!adev->gmc.fw)
384 return -EINVAL;
385
386 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
387 amdgpu_ucode_print_mc_hdr(&hdr->header);
388
389 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
390 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
391 io_mc_regs = (const __le32 *)
392 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
393 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
394 fw_data = (const __le32 *)
395 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
396
397 data = RREG32(mmMC_SEQ_MISC0);
398 data &= ~(0x40);
399 WREG32(mmMC_SEQ_MISC0, data);
400
401 /* load mc io regs */
402 for (i = 0; i < regs_size; i++) {
403 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
404 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
405 }
406
407 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
408 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
409
410 /* load the MC ucode */
411 for (i = 0; i < ucode_size; i++)
412 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
413
414 /* put the engine back into the active state */
415 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
416 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
417 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
418
419 /* wait for training to complete */
420 for (i = 0; i < adev->usec_timeout; i++) {
421 data = RREG32(mmMC_SEQ_MISC0);
422 if (data & 0x80)
423 break;
424 udelay(1);
425 }
426
427 return 0;
428 }
429
gmc_v8_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)430 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
431 struct amdgpu_gmc *mc)
432 {
433 u64 base = 0;
434
435 if (!amdgpu_sriov_vf(adev))
436 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
437 base <<= 24;
438
439 amdgpu_gmc_vram_location(adev, mc, base);
440 amdgpu_gmc_gart_location(adev, mc);
441 }
442
443 /**
444 * gmc_v8_0_mc_program - program the GPU memory controller
445 *
446 * @adev: amdgpu_device pointer
447 *
448 * Set the location of vram, gart, and AGP in the GPU's
449 * physical address space (VI).
450 */
gmc_v8_0_mc_program(struct amdgpu_device * adev)451 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
452 {
453 u32 tmp;
454 int i, j;
455
456 /* Initialize HDP */
457 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
458 WREG32((0xb05 + j), 0x00000000);
459 WREG32((0xb06 + j), 0x00000000);
460 WREG32((0xb07 + j), 0x00000000);
461 WREG32((0xb08 + j), 0x00000000);
462 WREG32((0xb09 + j), 0x00000000);
463 }
464 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
465
466 if (gmc_v8_0_wait_for_idle((void *)adev)) {
467 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
468 }
469 if (adev->mode_info.num_crtc) {
470 /* Lockout access through VGA aperture*/
471 tmp = RREG32(mmVGA_HDP_CONTROL);
472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
473 WREG32(mmVGA_HDP_CONTROL, tmp);
474
475 /* disable VGA render */
476 tmp = RREG32(mmVGA_RENDER_CONTROL);
477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
478 WREG32(mmVGA_RENDER_CONTROL, tmp);
479 }
480 /* Update configuration */
481 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
482 adev->gmc.vram_start >> 12);
483 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
484 adev->gmc.vram_end >> 12);
485 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
486 adev->vram_scratch.gpu_addr >> 12);
487
488 if (amdgpu_sriov_vf(adev)) {
489 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
490 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
491 WREG32(mmMC_VM_FB_LOCATION, tmp);
492 /* XXX double check these! */
493 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
494 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
495 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
496 }
497
498 WREG32(mmMC_VM_AGP_BASE, 0);
499 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
500 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
501 if (gmc_v8_0_wait_for_idle((void *)adev)) {
502 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
503 }
504
505 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
506
507 tmp = RREG32(mmHDP_MISC_CNTL);
508 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
509 WREG32(mmHDP_MISC_CNTL, tmp);
510
511 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
512 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
513 }
514
515 /**
516 * gmc_v8_0_mc_init - initialize the memory controller driver params
517 *
518 * @adev: amdgpu_device pointer
519 *
520 * Look up the amount of vram, vram width, and decide how to place
521 * vram and gart within the GPU's physical address space (VI).
522 * Returns 0 for success.
523 */
gmc_v8_0_mc_init(struct amdgpu_device * adev)524 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
525 {
526 int r;
527 u32 tmp;
528
529 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
530 if (!adev->gmc.vram_width) {
531 int chansize, numchan;
532
533 /* Get VRAM informations */
534 tmp = RREG32(mmMC_ARB_RAMCFG);
535 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
536 chansize = 64;
537 } else {
538 chansize = 32;
539 }
540 tmp = RREG32(mmMC_SHARED_CHMAP);
541 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
542 case 0:
543 default:
544 numchan = 1;
545 break;
546 case 1:
547 numchan = 2;
548 break;
549 case 2:
550 numchan = 4;
551 break;
552 case 3:
553 numchan = 8;
554 break;
555 case 4:
556 numchan = 3;
557 break;
558 case 5:
559 numchan = 6;
560 break;
561 case 6:
562 numchan = 10;
563 break;
564 case 7:
565 numchan = 12;
566 break;
567 case 8:
568 numchan = 16;
569 break;
570 }
571 adev->gmc.vram_width = numchan * chansize;
572 }
573 /* size in MB on si */
574 tmp = RREG32(mmCONFIG_MEMSIZE);
575 /* some boards may have garbage in the upper 16 bits */
576 if (tmp & 0xffff0000) {
577 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
578 if (tmp & 0xffff)
579 tmp &= 0xffff;
580 }
581 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
582 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
583
584 if (!(adev->flags & AMD_IS_APU)) {
585 r = amdgpu_device_resize_fb_bar(adev);
586 if (r)
587 return r;
588 }
589 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
590 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
591
592 #ifdef CONFIG_X86_64
593 if (adev->flags & AMD_IS_APU) {
594 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
595 adev->gmc.aper_size = adev->gmc.real_vram_size;
596 }
597 #endif
598
599 /* In case the PCI BAR is larger than the actual amount of vram */
600 adev->gmc.visible_vram_size = adev->gmc.aper_size;
601 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
602 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
603
604 /* set the gart size */
605 if (amdgpu_gart_size == -1) {
606 switch (adev->asic_type) {
607 case CHIP_POLARIS10: /* all engines support GPUVM */
608 case CHIP_POLARIS11: /* all engines support GPUVM */
609 case CHIP_POLARIS12: /* all engines support GPUVM */
610 case CHIP_VEGAM: /* all engines support GPUVM */
611 default:
612 adev->gmc.gart_size = 256ULL << 20;
613 break;
614 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
615 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
616 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
617 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
618 adev->gmc.gart_size = 1024ULL << 20;
619 break;
620 }
621 } else {
622 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
623 }
624
625 gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
626
627 return 0;
628 }
629
630 /**
631 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
632 *
633 * @adev: amdgpu_device pointer
634 * @pasid: pasid to be flush
635 *
636 * Flush the TLB for the requested pasid.
637 */
gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub)638 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
639 uint16_t pasid, uint32_t flush_type,
640 bool all_hub)
641 {
642 int vmid;
643 unsigned int tmp;
644
645 if (amdgpu_in_reset(adev))
646 return -EIO;
647
648 for (vmid = 1; vmid < 16; vmid++) {
649
650 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
651 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
652 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
653 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
654 RREG32(mmVM_INVALIDATE_RESPONSE);
655 break;
656 }
657 }
658
659 return 0;
660
661 }
662
663 /*
664 * GART
665 * VMID 0 is the physical GPU addresses as used by the kernel.
666 * VMIDs 1-15 are used for userspace clients and are handled
667 * by the amdgpu vm/hsa code.
668 */
669
670 /**
671 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
672 *
673 * @adev: amdgpu_device pointer
674 * @vmid: vm instance to flush
675 *
676 * Flush the TLB for the requested page table (VI).
677 */
gmc_v8_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)678 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
679 uint32_t vmhub, uint32_t flush_type)
680 {
681 /* bits 0-15 are the VM contexts0-15 */
682 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
683 }
684
gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)685 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
686 unsigned vmid, uint64_t pd_addr)
687 {
688 uint32_t reg;
689
690 if (vmid < 8)
691 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
692 else
693 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
694 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
695
696 /* bits 0-15 are the VM contexts0-15 */
697 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
698
699 return pd_addr;
700 }
701
gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned vmid,unsigned pasid)702 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
703 unsigned pasid)
704 {
705 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
706 }
707
708 /*
709 * PTE format on VI:
710 * 63:40 reserved
711 * 39:12 4k physical page base address
712 * 11:7 fragment
713 * 6 write
714 * 5 read
715 * 4 exe
716 * 3 reserved
717 * 2 snooped
718 * 1 system
719 * 0 valid
720 *
721 * PDE format on VI:
722 * 63:59 block fragment size
723 * 58:40 reserved
724 * 39:1 physical base address of PTE
725 * bits 5:1 must be 0.
726 * 0 valid
727 */
728
gmc_v8_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)729 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
730 uint64_t *addr, uint64_t *flags)
731 {
732 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
733 }
734
gmc_v8_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)735 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
736 struct amdgpu_bo_va_mapping *mapping,
737 uint64_t *flags)
738 {
739 *flags &= ~AMDGPU_PTE_EXECUTABLE;
740 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
741 *flags &= ~AMDGPU_PTE_PRT;
742 }
743
744 /**
745 * gmc_v8_0_set_fault_enable_default - update VM fault handling
746 *
747 * @adev: amdgpu_device pointer
748 * @value: true redirects VM faults to the default page
749 */
gmc_v8_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)750 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
751 bool value)
752 {
753 u32 tmp;
754
755 tmp = RREG32(mmVM_CONTEXT1_CNTL);
756 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
757 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
758 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
759 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
760 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
761 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
762 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
763 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
764 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
765 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
766 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
767 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
768 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
769 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
770 WREG32(mmVM_CONTEXT1_CNTL, tmp);
771 }
772
773 /**
774 * gmc_v8_0_set_prt - set PRT VM fault
775 *
776 * @adev: amdgpu_device pointer
777 * @enable: enable/disable VM fault handling for PRT
778 */
gmc_v8_0_set_prt(struct amdgpu_device * adev,bool enable)779 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
780 {
781 u32 tmp;
782
783 if (enable && !adev->gmc.prt_warning) {
784 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
785 adev->gmc.prt_warning = true;
786 }
787
788 tmp = RREG32(mmVM_PRT_CNTL);
789 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
790 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
791 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
792 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
793 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
794 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
795 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
796 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
797 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
798 L2_CACHE_STORE_INVALID_ENTRIES, enable);
799 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
800 L1_TLB_STORE_INVALID_ENTRIES, enable);
801 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
802 MASK_PDE0_FAULT, enable);
803 WREG32(mmVM_PRT_CNTL, tmp);
804
805 if (enable) {
806 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
807 uint32_t high = adev->vm_manager.max_pfn -
808 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
809
810 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
811 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
812 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
813 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
814 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
815 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
816 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
817 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
818 } else {
819 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
820 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
821 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
822 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
823 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
824 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
825 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
826 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
827 }
828 }
829
830 /**
831 * gmc_v8_0_gart_enable - gart enable
832 *
833 * @adev: amdgpu_device pointer
834 *
835 * This sets up the TLBs, programs the page tables for VMID0,
836 * sets up the hw for VMIDs 1-15 which are allocated on
837 * demand, and sets up the global locations for the LDS, GDS,
838 * and GPUVM for FSA64 clients (VI).
839 * Returns 0 for success, errors for failure.
840 */
gmc_v8_0_gart_enable(struct amdgpu_device * adev)841 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
842 {
843 uint64_t table_addr;
844 int r, i;
845 u32 tmp, field;
846
847 if (adev->gart.bo == NULL) {
848 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
849 return -EINVAL;
850 }
851 r = amdgpu_gart_table_vram_pin(adev);
852 if (r)
853 return r;
854
855 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
856
857 /* Setup TLB control */
858 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
859 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
860 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
861 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
862 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
863 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
864 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
865 /* Setup L2 cache */
866 tmp = RREG32(mmVM_L2_CNTL);
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
871 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
874 WREG32(mmVM_L2_CNTL, tmp);
875 tmp = RREG32(mmVM_L2_CNTL2);
876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
878 WREG32(mmVM_L2_CNTL2, tmp);
879
880 field = adev->vm_manager.fragment_size;
881 tmp = RREG32(mmVM_L2_CNTL3);
882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
885 WREG32(mmVM_L2_CNTL3, tmp);
886 /* XXX: set to enable PTE/PDE in system memory */
887 tmp = RREG32(mmVM_L2_CNTL4);
888 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
889 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
890 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
891 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
892 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
893 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
894 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
895 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
896 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
897 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
898 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
899 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
900 WREG32(mmVM_L2_CNTL4, tmp);
901 /* setup context0 */
902 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
903 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
904 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
905 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
906 (u32)(adev->dummy_page_addr >> 12));
907 WREG32(mmVM_CONTEXT0_CNTL2, 0);
908 tmp = RREG32(mmVM_CONTEXT0_CNTL);
909 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
910 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
911 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
912 WREG32(mmVM_CONTEXT0_CNTL, tmp);
913
914 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
915 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
916 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
917
918 /* empty context1-15 */
919 /* FIXME start with 4G, once using 2 level pt switch to full
920 * vm size space
921 */
922 /* set vm size, must be a multiple of 4 */
923 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
924 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
925 for (i = 1; i < 16; i++) {
926 if (i < 8)
927 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
928 table_addr >> 12);
929 else
930 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
931 table_addr >> 12);
932 }
933
934 /* enable context1-15 */
935 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
936 (u32)(adev->dummy_page_addr >> 12));
937 WREG32(mmVM_CONTEXT1_CNTL2, 4);
938 tmp = RREG32(mmVM_CONTEXT1_CNTL);
939 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
940 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
941 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
942 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
943 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
944 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
945 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
946 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
947 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
948 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
949 adev->vm_manager.block_size - 9);
950 WREG32(mmVM_CONTEXT1_CNTL, tmp);
951 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
952 gmc_v8_0_set_fault_enable_default(adev, false);
953 else
954 gmc_v8_0_set_fault_enable_default(adev, true);
955
956 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
957 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
958 (unsigned)(adev->gmc.gart_size >> 20),
959 (unsigned long long)table_addr);
960 adev->gart.ready = true;
961 return 0;
962 }
963
gmc_v8_0_gart_init(struct amdgpu_device * adev)964 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
965 {
966 int r;
967
968 if (adev->gart.bo) {
969 WARN(1, "R600 PCIE GART already initialized\n");
970 return 0;
971 }
972 /* Initialize common gart structure */
973 r = amdgpu_gart_init(adev);
974 if (r)
975 return r;
976 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
977 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
978 return amdgpu_gart_table_vram_alloc(adev);
979 }
980
981 /**
982 * gmc_v8_0_gart_disable - gart disable
983 *
984 * @adev: amdgpu_device pointer
985 *
986 * This disables all VM page table (VI).
987 */
gmc_v8_0_gart_disable(struct amdgpu_device * adev)988 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
989 {
990 u32 tmp;
991
992 /* Disable all tables */
993 WREG32(mmVM_CONTEXT0_CNTL, 0);
994 WREG32(mmVM_CONTEXT1_CNTL, 0);
995 /* Setup TLB control */
996 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
997 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
998 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
999 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
1000 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
1001 /* Setup L2 cache */
1002 tmp = RREG32(mmVM_L2_CNTL);
1003 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
1004 WREG32(mmVM_L2_CNTL, tmp);
1005 WREG32(mmVM_L2_CNTL2, 0);
1006 amdgpu_gart_table_vram_unpin(adev);
1007 }
1008
1009 /**
1010 * gmc_v8_0_vm_decode_fault - print human readable fault info
1011 *
1012 * @adev: amdgpu_device pointer
1013 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
1014 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
1015 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
1016 *
1017 * Print human readable fault information (VI).
1018 */
gmc_v8_0_vm_decode_fault(struct amdgpu_device * adev,u32 status,u32 addr,u32 mc_client,unsigned pasid)1019 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1020 u32 addr, u32 mc_client, unsigned pasid)
1021 {
1022 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1023 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1024 PROTECTIONS);
1025 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1026 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1027 u32 mc_id;
1028
1029 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1030 MEMORY_CLIENT_ID);
1031
1032 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1033 protections, vmid, pasid, addr,
1034 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1035 MEMORY_CLIENT_RW) ?
1036 "write" : "read", block, mc_client, mc_id);
1037 }
1038
gmc_v8_0_convert_vram_type(int mc_seq_vram_type)1039 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1040 {
1041 switch (mc_seq_vram_type) {
1042 case MC_SEQ_MISC0__MT__GDDR1:
1043 return AMDGPU_VRAM_TYPE_GDDR1;
1044 case MC_SEQ_MISC0__MT__DDR2:
1045 return AMDGPU_VRAM_TYPE_DDR2;
1046 case MC_SEQ_MISC0__MT__GDDR3:
1047 return AMDGPU_VRAM_TYPE_GDDR3;
1048 case MC_SEQ_MISC0__MT__GDDR4:
1049 return AMDGPU_VRAM_TYPE_GDDR4;
1050 case MC_SEQ_MISC0__MT__GDDR5:
1051 return AMDGPU_VRAM_TYPE_GDDR5;
1052 case MC_SEQ_MISC0__MT__HBM:
1053 return AMDGPU_VRAM_TYPE_HBM;
1054 case MC_SEQ_MISC0__MT__DDR3:
1055 return AMDGPU_VRAM_TYPE_DDR3;
1056 default:
1057 return AMDGPU_VRAM_TYPE_UNKNOWN;
1058 }
1059 }
1060
gmc_v8_0_early_init(void * handle)1061 static int gmc_v8_0_early_init(void *handle)
1062 {
1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1064
1065 gmc_v8_0_set_gmc_funcs(adev);
1066 gmc_v8_0_set_irq_funcs(adev);
1067
1068 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1069 adev->gmc.shared_aperture_end =
1070 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1071 adev->gmc.private_aperture_start =
1072 adev->gmc.shared_aperture_end + 1;
1073 adev->gmc.private_aperture_end =
1074 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1075
1076 return 0;
1077 }
1078
gmc_v8_0_late_init(void * handle)1079 static int gmc_v8_0_late_init(void *handle)
1080 {
1081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1082
1083 amdgpu_bo_late_init(adev);
1084
1085 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1086 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1087 else
1088 return 0;
1089 }
1090
gmc_v8_0_get_vbios_fb_size(struct amdgpu_device * adev)1091 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1092 {
1093 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1094 unsigned size;
1095
1096 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1097 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1098 } else {
1099 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1100 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1101 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1102 4);
1103 }
1104
1105 return size;
1106 }
1107
1108 #define mmMC_SEQ_MISC0_FIJI 0xA71
1109
gmc_v8_0_sw_init(void * handle)1110 static int gmc_v8_0_sw_init(void *handle)
1111 {
1112 int r;
1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115 adev->num_vmhubs = 1;
1116
1117 if (adev->flags & AMD_IS_APU) {
1118 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1119 } else {
1120 u32 tmp;
1121
1122 if ((adev->asic_type == CHIP_FIJI) ||
1123 (adev->asic_type == CHIP_VEGAM))
1124 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1125 else
1126 tmp = RREG32(mmMC_SEQ_MISC0);
1127 tmp &= MC_SEQ_MISC0__MT__MASK;
1128 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1129 }
1130
1131 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1132 if (r)
1133 return r;
1134
1135 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1136 if (r)
1137 return r;
1138
1139 /* Adjust VM size here.
1140 * Currently set to 4GB ((1 << 20) 4k pages).
1141 * Max GPUVM size for cayman and SI is 40 bits.
1142 */
1143 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1144
1145 /* Set the internal MC address mask
1146 * This is the max address of the GPU's
1147 * internal address space.
1148 */
1149 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1150
1151 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1152 if (r) {
1153 pr_warn("No suitable DMA available\n");
1154 return r;
1155 }
1156 adev->need_swiotlb = drm_need_swiotlb(40);
1157
1158 r = gmc_v8_0_init_microcode(adev);
1159 if (r) {
1160 DRM_ERROR("Failed to load mc firmware!\n");
1161 return r;
1162 }
1163
1164 r = gmc_v8_0_mc_init(adev);
1165 if (r)
1166 return r;
1167
1168 amdgpu_gmc_get_vbios_allocations(adev);
1169
1170 /* Memory manager */
1171 r = amdgpu_bo_init(adev);
1172 if (r)
1173 return r;
1174
1175 r = gmc_v8_0_gart_init(adev);
1176 if (r)
1177 return r;
1178
1179 /*
1180 * number of VMs
1181 * VMID 0 is reserved for System
1182 * amdgpu graphics/compute will use VMIDs 1-7
1183 * amdkfd will use VMIDs 8-15
1184 */
1185 adev->vm_manager.first_kfd_vmid = 8;
1186 amdgpu_vm_manager_init(adev);
1187
1188 /* base offset of vram pages */
1189 if (adev->flags & AMD_IS_APU) {
1190 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1191
1192 tmp <<= 22;
1193 adev->vm_manager.vram_base_offset = tmp;
1194 } else {
1195 adev->vm_manager.vram_base_offset = 0;
1196 }
1197
1198 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1199 GFP_KERNEL);
1200 if (!adev->gmc.vm_fault_info)
1201 return -ENOMEM;
1202 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1203
1204 return 0;
1205 }
1206
gmc_v8_0_sw_fini(void * handle)1207 static int gmc_v8_0_sw_fini(void *handle)
1208 {
1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210
1211 amdgpu_gem_force_release(adev);
1212 amdgpu_vm_manager_fini(adev);
1213 kfree(adev->gmc.vm_fault_info);
1214 amdgpu_gart_table_vram_free(adev);
1215 amdgpu_bo_fini(adev);
1216 amdgpu_gart_fini(adev);
1217 release_firmware(adev->gmc.fw);
1218 adev->gmc.fw = NULL;
1219
1220 return 0;
1221 }
1222
gmc_v8_0_hw_init(void * handle)1223 static int gmc_v8_0_hw_init(void *handle)
1224 {
1225 int r;
1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
1228 gmc_v8_0_init_golden_registers(adev);
1229
1230 gmc_v8_0_mc_program(adev);
1231
1232 if (adev->asic_type == CHIP_TONGA) {
1233 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1234 if (r) {
1235 DRM_ERROR("Failed to load MC firmware!\n");
1236 return r;
1237 }
1238 } else if (adev->asic_type == CHIP_POLARIS11 ||
1239 adev->asic_type == CHIP_POLARIS10 ||
1240 adev->asic_type == CHIP_POLARIS12) {
1241 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1242 if (r) {
1243 DRM_ERROR("Failed to load MC firmware!\n");
1244 return r;
1245 }
1246 }
1247
1248 r = gmc_v8_0_gart_enable(adev);
1249 if (r)
1250 return r;
1251
1252 return r;
1253 }
1254
gmc_v8_0_hw_fini(void * handle)1255 static int gmc_v8_0_hw_fini(void *handle)
1256 {
1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258
1259 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1260 gmc_v8_0_gart_disable(adev);
1261
1262 return 0;
1263 }
1264
gmc_v8_0_suspend(void * handle)1265 static int gmc_v8_0_suspend(void *handle)
1266 {
1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268
1269 gmc_v8_0_hw_fini(adev);
1270
1271 return 0;
1272 }
1273
gmc_v8_0_resume(void * handle)1274 static int gmc_v8_0_resume(void *handle)
1275 {
1276 int r;
1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278
1279 r = gmc_v8_0_hw_init(adev);
1280 if (r)
1281 return r;
1282
1283 amdgpu_vmid_reset_all(adev);
1284
1285 return 0;
1286 }
1287
gmc_v8_0_is_idle(void * handle)1288 static bool gmc_v8_0_is_idle(void *handle)
1289 {
1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291 u32 tmp = RREG32(mmSRBM_STATUS);
1292
1293 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1294 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1295 return false;
1296
1297 return true;
1298 }
1299
gmc_v8_0_wait_for_idle(void * handle)1300 static int gmc_v8_0_wait_for_idle(void *handle)
1301 {
1302 unsigned i;
1303 u32 tmp;
1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305
1306 for (i = 0; i < adev->usec_timeout; i++) {
1307 /* read MC_STATUS */
1308 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1309 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1310 SRBM_STATUS__MCC_BUSY_MASK |
1311 SRBM_STATUS__MCD_BUSY_MASK |
1312 SRBM_STATUS__VMC_BUSY_MASK |
1313 SRBM_STATUS__VMC1_BUSY_MASK);
1314 if (!tmp)
1315 return 0;
1316 udelay(1);
1317 }
1318 return -ETIMEDOUT;
1319
1320 }
1321
gmc_v8_0_check_soft_reset(void * handle)1322 static bool gmc_v8_0_check_soft_reset(void *handle)
1323 {
1324 u32 srbm_soft_reset = 0;
1325 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326 u32 tmp = RREG32(mmSRBM_STATUS);
1327
1328 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1329 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1330 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1331
1332 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1333 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1334 if (!(adev->flags & AMD_IS_APU))
1335 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1336 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1337 }
1338 if (srbm_soft_reset) {
1339 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1340 return true;
1341 } else {
1342 adev->gmc.srbm_soft_reset = 0;
1343 return false;
1344 }
1345 }
1346
gmc_v8_0_pre_soft_reset(void * handle)1347 static int gmc_v8_0_pre_soft_reset(void *handle)
1348 {
1349 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350
1351 if (!adev->gmc.srbm_soft_reset)
1352 return 0;
1353
1354 gmc_v8_0_mc_stop(adev);
1355 if (gmc_v8_0_wait_for_idle(adev)) {
1356 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1357 }
1358
1359 return 0;
1360 }
1361
gmc_v8_0_soft_reset(void * handle)1362 static int gmc_v8_0_soft_reset(void *handle)
1363 {
1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1365 u32 srbm_soft_reset;
1366
1367 if (!adev->gmc.srbm_soft_reset)
1368 return 0;
1369 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1370
1371 if (srbm_soft_reset) {
1372 u32 tmp;
1373
1374 tmp = RREG32(mmSRBM_SOFT_RESET);
1375 tmp |= srbm_soft_reset;
1376 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1377 WREG32(mmSRBM_SOFT_RESET, tmp);
1378 tmp = RREG32(mmSRBM_SOFT_RESET);
1379
1380 udelay(50);
1381
1382 tmp &= ~srbm_soft_reset;
1383 WREG32(mmSRBM_SOFT_RESET, tmp);
1384 tmp = RREG32(mmSRBM_SOFT_RESET);
1385
1386 /* Wait a little for things to settle down */
1387 udelay(50);
1388 }
1389
1390 return 0;
1391 }
1392
gmc_v8_0_post_soft_reset(void * handle)1393 static int gmc_v8_0_post_soft_reset(void *handle)
1394 {
1395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1396
1397 if (!adev->gmc.srbm_soft_reset)
1398 return 0;
1399
1400 gmc_v8_0_mc_resume(adev);
1401 return 0;
1402 }
1403
gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)1404 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1405 struct amdgpu_irq_src *src,
1406 unsigned type,
1407 enum amdgpu_interrupt_state state)
1408 {
1409 u32 tmp;
1410 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1411 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1412 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1413 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1414 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1415 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1416 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1417
1418 switch (state) {
1419 case AMDGPU_IRQ_STATE_DISABLE:
1420 /* system context */
1421 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1422 tmp &= ~bits;
1423 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1424 /* VMs */
1425 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1426 tmp &= ~bits;
1427 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1428 break;
1429 case AMDGPU_IRQ_STATE_ENABLE:
1430 /* system context */
1431 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1432 tmp |= bits;
1433 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1434 /* VMs */
1435 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1436 tmp |= bits;
1437 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1438 break;
1439 default:
1440 break;
1441 }
1442
1443 return 0;
1444 }
1445
gmc_v8_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1446 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1447 struct amdgpu_irq_src *source,
1448 struct amdgpu_iv_entry *entry)
1449 {
1450 u32 addr, status, mc_client, vmid;
1451
1452 if (amdgpu_sriov_vf(adev)) {
1453 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1454 entry->src_id, entry->src_data[0]);
1455 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1456 return 0;
1457 }
1458
1459 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1460 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1461 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1462 /* reset addr and status */
1463 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1464
1465 if (!addr && !status)
1466 return 0;
1467
1468 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1469 gmc_v8_0_set_fault_enable_default(adev, false);
1470
1471 if (printk_ratelimit()) {
1472 struct amdgpu_task_info task_info;
1473
1474 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1475 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1476
1477 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1478 entry->src_id, entry->src_data[0], task_info.process_name,
1479 task_info.tgid, task_info.task_name, task_info.pid);
1480 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1481 addr);
1482 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1483 status);
1484 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1485 entry->pasid);
1486 }
1487
1488 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1489 VMID);
1490 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1491 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1492 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1493 u32 protections = REG_GET_FIELD(status,
1494 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1495 PROTECTIONS);
1496
1497 info->vmid = vmid;
1498 info->mc_id = REG_GET_FIELD(status,
1499 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1500 MEMORY_CLIENT_ID);
1501 info->status = status;
1502 info->page_addr = addr;
1503 info->prot_valid = protections & 0x7 ? true : false;
1504 info->prot_read = protections & 0x8 ? true : false;
1505 info->prot_write = protections & 0x10 ? true : false;
1506 info->prot_exec = protections & 0x20 ? true : false;
1507 mb();
1508 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1509 }
1510
1511 return 0;
1512 }
1513
fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1514 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1515 bool enable)
1516 {
1517 uint32_t data;
1518
1519 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1520 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1521 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1522 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1523
1524 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1525 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1526 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1527
1528 data = RREG32(mmMC_HUB_MISC_VM_CG);
1529 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1530 WREG32(mmMC_HUB_MISC_VM_CG, data);
1531
1532 data = RREG32(mmMC_XPB_CLK_GAT);
1533 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1534 WREG32(mmMC_XPB_CLK_GAT, data);
1535
1536 data = RREG32(mmATC_MISC_CG);
1537 data |= ATC_MISC_CG__ENABLE_MASK;
1538 WREG32(mmATC_MISC_CG, data);
1539
1540 data = RREG32(mmMC_CITF_MISC_WR_CG);
1541 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1542 WREG32(mmMC_CITF_MISC_WR_CG, data);
1543
1544 data = RREG32(mmMC_CITF_MISC_RD_CG);
1545 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1546 WREG32(mmMC_CITF_MISC_RD_CG, data);
1547
1548 data = RREG32(mmMC_CITF_MISC_VM_CG);
1549 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1550 WREG32(mmMC_CITF_MISC_VM_CG, data);
1551
1552 data = RREG32(mmVM_L2_CG);
1553 data |= VM_L2_CG__ENABLE_MASK;
1554 WREG32(mmVM_L2_CG, data);
1555 } else {
1556 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1557 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1558 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1559
1560 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1561 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1562 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1563
1564 data = RREG32(mmMC_HUB_MISC_VM_CG);
1565 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1566 WREG32(mmMC_HUB_MISC_VM_CG, data);
1567
1568 data = RREG32(mmMC_XPB_CLK_GAT);
1569 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1570 WREG32(mmMC_XPB_CLK_GAT, data);
1571
1572 data = RREG32(mmATC_MISC_CG);
1573 data &= ~ATC_MISC_CG__ENABLE_MASK;
1574 WREG32(mmATC_MISC_CG, data);
1575
1576 data = RREG32(mmMC_CITF_MISC_WR_CG);
1577 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1578 WREG32(mmMC_CITF_MISC_WR_CG, data);
1579
1580 data = RREG32(mmMC_CITF_MISC_RD_CG);
1581 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1582 WREG32(mmMC_CITF_MISC_RD_CG, data);
1583
1584 data = RREG32(mmMC_CITF_MISC_VM_CG);
1585 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1586 WREG32(mmMC_CITF_MISC_VM_CG, data);
1587
1588 data = RREG32(mmVM_L2_CG);
1589 data &= ~VM_L2_CG__ENABLE_MASK;
1590 WREG32(mmVM_L2_CG, data);
1591 }
1592 }
1593
fiji_update_mc_light_sleep(struct amdgpu_device * adev,bool enable)1594 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1595 bool enable)
1596 {
1597 uint32_t data;
1598
1599 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1600 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1601 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1602 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1603
1604 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1605 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1606 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1607
1608 data = RREG32(mmMC_HUB_MISC_VM_CG);
1609 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1610 WREG32(mmMC_HUB_MISC_VM_CG, data);
1611
1612 data = RREG32(mmMC_XPB_CLK_GAT);
1613 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1614 WREG32(mmMC_XPB_CLK_GAT, data);
1615
1616 data = RREG32(mmATC_MISC_CG);
1617 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1618 WREG32(mmATC_MISC_CG, data);
1619
1620 data = RREG32(mmMC_CITF_MISC_WR_CG);
1621 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1622 WREG32(mmMC_CITF_MISC_WR_CG, data);
1623
1624 data = RREG32(mmMC_CITF_MISC_RD_CG);
1625 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1626 WREG32(mmMC_CITF_MISC_RD_CG, data);
1627
1628 data = RREG32(mmMC_CITF_MISC_VM_CG);
1629 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1630 WREG32(mmMC_CITF_MISC_VM_CG, data);
1631
1632 data = RREG32(mmVM_L2_CG);
1633 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1634 WREG32(mmVM_L2_CG, data);
1635 } else {
1636 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1637 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1638 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1639
1640 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1641 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1642 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1643
1644 data = RREG32(mmMC_HUB_MISC_VM_CG);
1645 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1646 WREG32(mmMC_HUB_MISC_VM_CG, data);
1647
1648 data = RREG32(mmMC_XPB_CLK_GAT);
1649 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1650 WREG32(mmMC_XPB_CLK_GAT, data);
1651
1652 data = RREG32(mmATC_MISC_CG);
1653 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1654 WREG32(mmATC_MISC_CG, data);
1655
1656 data = RREG32(mmMC_CITF_MISC_WR_CG);
1657 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1658 WREG32(mmMC_CITF_MISC_WR_CG, data);
1659
1660 data = RREG32(mmMC_CITF_MISC_RD_CG);
1661 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1662 WREG32(mmMC_CITF_MISC_RD_CG, data);
1663
1664 data = RREG32(mmMC_CITF_MISC_VM_CG);
1665 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1666 WREG32(mmMC_CITF_MISC_VM_CG, data);
1667
1668 data = RREG32(mmVM_L2_CG);
1669 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1670 WREG32(mmVM_L2_CG, data);
1671 }
1672 }
1673
gmc_v8_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1674 static int gmc_v8_0_set_clockgating_state(void *handle,
1675 enum amd_clockgating_state state)
1676 {
1677 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1678
1679 if (amdgpu_sriov_vf(adev))
1680 return 0;
1681
1682 switch (adev->asic_type) {
1683 case CHIP_FIJI:
1684 fiji_update_mc_medium_grain_clock_gating(adev,
1685 state == AMD_CG_STATE_GATE);
1686 fiji_update_mc_light_sleep(adev,
1687 state == AMD_CG_STATE_GATE);
1688 break;
1689 default:
1690 break;
1691 }
1692 return 0;
1693 }
1694
gmc_v8_0_set_powergating_state(void * handle,enum amd_powergating_state state)1695 static int gmc_v8_0_set_powergating_state(void *handle,
1696 enum amd_powergating_state state)
1697 {
1698 return 0;
1699 }
1700
gmc_v8_0_get_clockgating_state(void * handle,u32 * flags)1701 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1702 {
1703 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1704 int data;
1705
1706 if (amdgpu_sriov_vf(adev))
1707 *flags = 0;
1708
1709 /* AMD_CG_SUPPORT_MC_MGCG */
1710 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1711 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1712 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1713
1714 /* AMD_CG_SUPPORT_MC_LS */
1715 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1716 *flags |= AMD_CG_SUPPORT_MC_LS;
1717 }
1718
1719 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1720 .name = "gmc_v8_0",
1721 .early_init = gmc_v8_0_early_init,
1722 .late_init = gmc_v8_0_late_init,
1723 .sw_init = gmc_v8_0_sw_init,
1724 .sw_fini = gmc_v8_0_sw_fini,
1725 .hw_init = gmc_v8_0_hw_init,
1726 .hw_fini = gmc_v8_0_hw_fini,
1727 .suspend = gmc_v8_0_suspend,
1728 .resume = gmc_v8_0_resume,
1729 .is_idle = gmc_v8_0_is_idle,
1730 .wait_for_idle = gmc_v8_0_wait_for_idle,
1731 .check_soft_reset = gmc_v8_0_check_soft_reset,
1732 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1733 .soft_reset = gmc_v8_0_soft_reset,
1734 .post_soft_reset = gmc_v8_0_post_soft_reset,
1735 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1736 .set_powergating_state = gmc_v8_0_set_powergating_state,
1737 .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1738 };
1739
1740 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1741 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1742 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1743 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1744 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1745 .set_prt = gmc_v8_0_set_prt,
1746 .get_vm_pde = gmc_v8_0_get_vm_pde,
1747 .get_vm_pte = gmc_v8_0_get_vm_pte,
1748 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size,
1749 };
1750
1751 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1752 .set = gmc_v8_0_vm_fault_interrupt_state,
1753 .process = gmc_v8_0_process_interrupt,
1754 };
1755
gmc_v8_0_set_gmc_funcs(struct amdgpu_device * adev)1756 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1757 {
1758 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1759 }
1760
gmc_v8_0_set_irq_funcs(struct amdgpu_device * adev)1761 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1762 {
1763 adev->gmc.vm_fault.num_types = 1;
1764 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1765 }
1766
1767 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1768 {
1769 .type = AMD_IP_BLOCK_TYPE_GMC,
1770 .major = 8,
1771 .minor = 0,
1772 .rev = 0,
1773 .funcs = &gmc_v8_0_ip_funcs,
1774 };
1775
1776 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1777 {
1778 .type = AMD_IP_BLOCK_TYPE_GMC,
1779 .major = 8,
1780 .minor = 1,
1781 .rev = 0,
1782 .funcs = &gmc_v8_0_ip_funcs,
1783 };
1784
1785 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1786 {
1787 .type = AMD_IP_BLOCK_TYPE_GMC,
1788 .major = 8,
1789 .minor = 5,
1790 .rev = 0,
1791 .funcs = &gmc_v8_0_ip_funcs,
1792 };
1793