1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/log2.h>
35 #include <linux/etherdevice.h>
36 #include <net/ip.h>
37 #include <linux/slab.h>
38 #include <linux/netdevice.h>
39
40 #include <rdma/ib_cache.h>
41 #include <rdma/ib_pack.h>
42 #include <rdma/ib_addr.h>
43 #include <rdma/ib_mad.h>
44 #include <rdma/uverbs_ioctl.h>
45
46 #include <linux/mlx4/driver.h>
47 #include <linux/mlx4/qp.h>
48
49 #include "mlx4_ib.h"
50 #include <rdma/mlx4-abi.h>
51
52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
56 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
57 struct ib_udata *udata);
58
59 enum {
60 MLX4_IB_ACK_REQ_FREQ = 8,
61 };
62
63 enum {
64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
66 MLX4_IB_LINK_TYPE_IB = 0,
67 MLX4_IB_LINK_TYPE_ETH = 1
68 };
69
70 enum {
71 MLX4_IB_MIN_SQ_STRIDE = 6,
72 MLX4_IB_CACHE_LINE_SIZE = 64,
73 };
74
75 enum {
76 MLX4_RAW_QP_MTU = 7,
77 MLX4_RAW_QP_MSGMAX = 31,
78 };
79
80 #ifndef ETH_ALEN
81 #define ETH_ALEN 6
82 #endif
83
84 static const __be32 mlx4_ib_opcode[] = {
85 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
86 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
87 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
88 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
89 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
90 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
91 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
92 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
93 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
94 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
95 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
96 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
97 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
98 };
99
100 enum mlx4_ib_source_type {
101 MLX4_IB_QP_SRC = 0,
102 MLX4_IB_RWQ_SRC = 1,
103 };
104
is_tunnel_qp(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)105 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
106 {
107 if (!mlx4_is_master(dev->dev))
108 return 0;
109
110 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
111 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
112 8 * MLX4_MFUNC_MAX;
113 }
114
is_sqp(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)115 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
116 {
117 int proxy_sqp = 0;
118 int real_sqp = 0;
119 int i;
120 /* PPF or Native -- real SQP */
121 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
122 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
123 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
124 if (real_sqp)
125 return 1;
126 /* VF or PF -- proxy SQP */
127 if (mlx4_is_mfunc(dev->dev)) {
128 for (i = 0; i < dev->dev->caps.num_ports; i++) {
129 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
130 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
131 proxy_sqp = 1;
132 break;
133 }
134 }
135 }
136 if (proxy_sqp)
137 return 1;
138
139 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
140 }
141
142 /* used for INIT/CLOSE port logic */
is_qp0(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)143 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
144 {
145 int proxy_qp0 = 0;
146 int real_qp0 = 0;
147 int i;
148 /* PPF or Native -- real QP0 */
149 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
150 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
151 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
152 if (real_qp0)
153 return 1;
154 /* VF or PF -- proxy QP0 */
155 if (mlx4_is_mfunc(dev->dev)) {
156 for (i = 0; i < dev->dev->caps.num_ports; i++) {
157 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
158 proxy_qp0 = 1;
159 break;
160 }
161 }
162 }
163 return proxy_qp0;
164 }
165
get_wqe(struct mlx4_ib_qp * qp,int offset)166 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
167 {
168 return mlx4_buf_offset(&qp->buf, offset);
169 }
170
get_recv_wqe(struct mlx4_ib_qp * qp,int n)171 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
172 {
173 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
174 }
175
get_send_wqe(struct mlx4_ib_qp * qp,int n)176 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
177 {
178 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
179 }
180
181 /*
182 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
183 * first four bytes of every 64 byte chunk with 0xffffffff, except for
184 * the very first chunk of the WQE.
185 */
stamp_send_wqe(struct mlx4_ib_qp * qp,int n)186 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
187 {
188 __be32 *wqe;
189 int i;
190 int s;
191 void *buf;
192 struct mlx4_wqe_ctrl_seg *ctrl;
193
194 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
195 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
196 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
197 for (i = 64; i < s; i += 64) {
198 wqe = buf + i;
199 *wqe = cpu_to_be32(0xffffffff);
200 }
201 }
202
mlx4_ib_qp_event(struct mlx4_qp * qp,enum mlx4_event type)203 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
204 {
205 struct ib_event event;
206 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
207
208 if (type == MLX4_EVENT_TYPE_PATH_MIG)
209 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
210
211 if (ibqp->event_handler) {
212 event.device = ibqp->device;
213 event.element.qp = ibqp;
214 switch (type) {
215 case MLX4_EVENT_TYPE_PATH_MIG:
216 event.event = IB_EVENT_PATH_MIG;
217 break;
218 case MLX4_EVENT_TYPE_COMM_EST:
219 event.event = IB_EVENT_COMM_EST;
220 break;
221 case MLX4_EVENT_TYPE_SQ_DRAINED:
222 event.event = IB_EVENT_SQ_DRAINED;
223 break;
224 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
225 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
226 break;
227 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
228 event.event = IB_EVENT_QP_FATAL;
229 break;
230 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
231 event.event = IB_EVENT_PATH_MIG_ERR;
232 break;
233 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
234 event.event = IB_EVENT_QP_REQ_ERR;
235 break;
236 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
237 event.event = IB_EVENT_QP_ACCESS_ERR;
238 break;
239 default:
240 pr_warn("Unexpected event type %d "
241 "on QP %06x\n", type, qp->qpn);
242 return;
243 }
244
245 ibqp->event_handler(&event, ibqp->qp_context);
246 }
247 }
248
mlx4_ib_wq_event(struct mlx4_qp * qp,enum mlx4_event type)249 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
250 {
251 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
252 type, qp->qpn);
253 }
254
send_wqe_overhead(enum mlx4_ib_qp_type type,u32 flags)255 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
256 {
257 /*
258 * UD WQEs must have a datagram segment.
259 * RC and UC WQEs might have a remote address segment.
260 * MLX WQEs need two extra inline data segments (for the UD
261 * header and space for the ICRC).
262 */
263 switch (type) {
264 case MLX4_IB_QPT_UD:
265 return sizeof (struct mlx4_wqe_ctrl_seg) +
266 sizeof (struct mlx4_wqe_datagram_seg) +
267 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
268 case MLX4_IB_QPT_PROXY_SMI_OWNER:
269 case MLX4_IB_QPT_PROXY_SMI:
270 case MLX4_IB_QPT_PROXY_GSI:
271 return sizeof (struct mlx4_wqe_ctrl_seg) +
272 sizeof (struct mlx4_wqe_datagram_seg) + 64;
273 case MLX4_IB_QPT_TUN_SMI_OWNER:
274 case MLX4_IB_QPT_TUN_GSI:
275 return sizeof (struct mlx4_wqe_ctrl_seg) +
276 sizeof (struct mlx4_wqe_datagram_seg);
277
278 case MLX4_IB_QPT_UC:
279 return sizeof (struct mlx4_wqe_ctrl_seg) +
280 sizeof (struct mlx4_wqe_raddr_seg);
281 case MLX4_IB_QPT_RC:
282 return sizeof (struct mlx4_wqe_ctrl_seg) +
283 sizeof (struct mlx4_wqe_masked_atomic_seg) +
284 sizeof (struct mlx4_wqe_raddr_seg);
285 case MLX4_IB_QPT_SMI:
286 case MLX4_IB_QPT_GSI:
287 return sizeof (struct mlx4_wqe_ctrl_seg) +
288 ALIGN(MLX4_IB_UD_HEADER_SIZE +
289 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
290 MLX4_INLINE_ALIGN) *
291 sizeof (struct mlx4_wqe_inline_seg),
292 sizeof (struct mlx4_wqe_data_seg)) +
293 ALIGN(4 +
294 sizeof (struct mlx4_wqe_inline_seg),
295 sizeof (struct mlx4_wqe_data_seg));
296 default:
297 return sizeof (struct mlx4_wqe_ctrl_seg);
298 }
299 }
300
set_rq_size(struct mlx4_ib_dev * dev,struct ib_qp_cap * cap,bool is_user,bool has_rq,struct mlx4_ib_qp * qp,u32 inl_recv_sz)301 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
302 bool is_user, bool has_rq, struct mlx4_ib_qp *qp,
303 u32 inl_recv_sz)
304 {
305 /* Sanity check RQ size before proceeding */
306 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
307 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
308 return -EINVAL;
309
310 if (!has_rq) {
311 if (cap->max_recv_wr || inl_recv_sz)
312 return -EINVAL;
313
314 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
315 } else {
316 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
317 sizeof(struct mlx4_wqe_data_seg);
318 u32 wqe_size;
319
320 /* HW requires >= 1 RQ entry with >= 1 gather entry */
321 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
322 inl_recv_sz > max_inl_recv_sz))
323 return -EINVAL;
324
325 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
326 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
327 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
328 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
329 }
330
331 /* leave userspace return values as they were, so as not to break ABI */
332 if (is_user) {
333 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
334 cap->max_recv_sge = qp->rq.max_gs;
335 } else {
336 cap->max_recv_wr = qp->rq.max_post =
337 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
338 cap->max_recv_sge = min(qp->rq.max_gs,
339 min(dev->dev->caps.max_sq_sg,
340 dev->dev->caps.max_rq_sg));
341 }
342
343 return 0;
344 }
345
set_kernel_sq_size(struct mlx4_ib_dev * dev,struct ib_qp_cap * cap,enum mlx4_ib_qp_type type,struct mlx4_ib_qp * qp)346 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
347 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
348 {
349 int s;
350
351 /* Sanity check SQ size before proceeding */
352 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
353 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
354 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
355 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
356 return -EINVAL;
357
358 /*
359 * For MLX transport we need 2 extra S/G entries:
360 * one for the header and one for the checksum at the end
361 */
362 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
363 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
364 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
365 return -EINVAL;
366
367 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
368 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
369 send_wqe_overhead(type, qp->flags);
370
371 if (s > dev->dev->caps.max_sq_desc_sz)
372 return -EINVAL;
373
374 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
375
376 /*
377 * We need to leave 2 KB + 1 WR of headroom in the SQ to
378 * allow HW to prefetch.
379 */
380 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
381 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
382 qp->sq_spare_wqes);
383
384 qp->sq.max_gs =
385 (min(dev->dev->caps.max_sq_desc_sz,
386 (1 << qp->sq.wqe_shift)) -
387 send_wqe_overhead(type, qp->flags)) /
388 sizeof (struct mlx4_wqe_data_seg);
389
390 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
391 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
392 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
393 qp->rq.offset = 0;
394 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
395 } else {
396 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
397 qp->sq.offset = 0;
398 }
399
400 cap->max_send_wr = qp->sq.max_post =
401 qp->sq.wqe_cnt - qp->sq_spare_wqes;
402 cap->max_send_sge = min(qp->sq.max_gs,
403 min(dev->dev->caps.max_sq_sg,
404 dev->dev->caps.max_rq_sg));
405 /* We don't support inline sends for kernel QPs (yet) */
406 cap->max_inline_data = 0;
407
408 return 0;
409 }
410
set_user_sq_size(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,struct mlx4_ib_create_qp * ucmd)411 static int set_user_sq_size(struct mlx4_ib_dev *dev,
412 struct mlx4_ib_qp *qp,
413 struct mlx4_ib_create_qp *ucmd)
414 {
415 u32 cnt;
416
417 /* Sanity check SQ size before proceeding */
418 if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) ||
419 cnt > dev->dev->caps.max_wqes)
420 return -EINVAL;
421 if (ucmd->log_sq_stride >
422 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
423 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
424 return -EINVAL;
425
426 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
427 qp->sq.wqe_shift = ucmd->log_sq_stride;
428
429 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
430 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
431
432 return 0;
433 }
434
alloc_proxy_bufs(struct ib_device * dev,struct mlx4_ib_qp * qp)435 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
436 {
437 int i;
438
439 qp->sqp_proxy_rcv =
440 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
441 GFP_KERNEL);
442 if (!qp->sqp_proxy_rcv)
443 return -ENOMEM;
444 for (i = 0; i < qp->rq.wqe_cnt; i++) {
445 qp->sqp_proxy_rcv[i].addr =
446 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
447 GFP_KERNEL);
448 if (!qp->sqp_proxy_rcv[i].addr)
449 goto err;
450 qp->sqp_proxy_rcv[i].map =
451 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
452 sizeof (struct mlx4_ib_proxy_sqp_hdr),
453 DMA_FROM_DEVICE);
454 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
455 kfree(qp->sqp_proxy_rcv[i].addr);
456 goto err;
457 }
458 }
459 return 0;
460
461 err:
462 while (i > 0) {
463 --i;
464 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
465 sizeof (struct mlx4_ib_proxy_sqp_hdr),
466 DMA_FROM_DEVICE);
467 kfree(qp->sqp_proxy_rcv[i].addr);
468 }
469 kfree(qp->sqp_proxy_rcv);
470 qp->sqp_proxy_rcv = NULL;
471 return -ENOMEM;
472 }
473
free_proxy_bufs(struct ib_device * dev,struct mlx4_ib_qp * qp)474 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
475 {
476 int i;
477
478 for (i = 0; i < qp->rq.wqe_cnt; i++) {
479 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
480 sizeof (struct mlx4_ib_proxy_sqp_hdr),
481 DMA_FROM_DEVICE);
482 kfree(qp->sqp_proxy_rcv[i].addr);
483 }
484 kfree(qp->sqp_proxy_rcv);
485 }
486
qp_has_rq(struct ib_qp_init_attr * attr)487 static bool qp_has_rq(struct ib_qp_init_attr *attr)
488 {
489 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
490 return false;
491
492 return !attr->srq;
493 }
494
qp0_enabled_vf(struct mlx4_dev * dev,int qpn)495 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
496 {
497 int i;
498 for (i = 0; i < dev->caps.num_ports; i++) {
499 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
500 return !!dev->caps.spec_qps[i].qp0_qkey;
501 }
502 return 0;
503 }
504
mlx4_ib_free_qp_counter(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)505 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
506 struct mlx4_ib_qp *qp)
507 {
508 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
509 mlx4_counter_free(dev->dev, qp->counter_index->index);
510 list_del(&qp->counter_index->list);
511 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
512
513 kfree(qp->counter_index);
514 qp->counter_index = NULL;
515 }
516
set_qp_rss(struct mlx4_ib_dev * dev,struct mlx4_ib_rss * rss_ctx,struct ib_qp_init_attr * init_attr,struct mlx4_ib_create_qp_rss * ucmd)517 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
518 struct ib_qp_init_attr *init_attr,
519 struct mlx4_ib_create_qp_rss *ucmd)
520 {
521 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
522 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
523
524 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
525 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
526 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
527 MLX4_EN_RSS_KEY_SIZE);
528 } else {
529 pr_debug("RX Hash function is not supported\n");
530 return (-EOPNOTSUPP);
531 }
532
533 if (ucmd->rx_hash_fields_mask & ~(u64)(MLX4_IB_RX_HASH_SRC_IPV4 |
534 MLX4_IB_RX_HASH_DST_IPV4 |
535 MLX4_IB_RX_HASH_SRC_IPV6 |
536 MLX4_IB_RX_HASH_DST_IPV6 |
537 MLX4_IB_RX_HASH_SRC_PORT_TCP |
538 MLX4_IB_RX_HASH_DST_PORT_TCP |
539 MLX4_IB_RX_HASH_SRC_PORT_UDP |
540 MLX4_IB_RX_HASH_DST_PORT_UDP |
541 MLX4_IB_RX_HASH_INNER)) {
542 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
543 ucmd->rx_hash_fields_mask);
544 return (-EOPNOTSUPP);
545 }
546
547 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
548 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
549 rss_ctx->flags = MLX4_RSS_IPV4;
550 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
551 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
552 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
553 return (-EOPNOTSUPP);
554 }
555
556 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
557 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
558 rss_ctx->flags |= MLX4_RSS_IPV6;
559 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
560 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
561 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
562 return (-EOPNOTSUPP);
563 }
564
565 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
566 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
567 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
568 pr_debug("RX Hash fields_mask for UDP is not supported\n");
569 return (-EOPNOTSUPP);
570 }
571
572 if (rss_ctx->flags & MLX4_RSS_IPV4)
573 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
574 if (rss_ctx->flags & MLX4_RSS_IPV6)
575 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
576 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
577 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
578 return (-EOPNOTSUPP);
579 }
580 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
581 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
582 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
583 return (-EOPNOTSUPP);
584 }
585
586 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
587 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
588 if (rss_ctx->flags & MLX4_RSS_IPV4)
589 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
590 if (rss_ctx->flags & MLX4_RSS_IPV6)
591 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
592 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
593 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
594 return (-EOPNOTSUPP);
595 }
596 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
597 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
598 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
599 return (-EOPNOTSUPP);
600 }
601
602 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
603 if (dev->dev->caps.tunnel_offload_mode ==
604 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
605 /*
606 * Hash according to inner headers if exist, otherwise
607 * according to outer headers.
608 */
609 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
610 } else {
611 pr_debug("RSS Hash for inner headers isn't supported\n");
612 return (-EOPNOTSUPP);
613 }
614 }
615
616 return 0;
617 }
618
create_qp_rss(struct mlx4_ib_dev * dev,struct ib_qp_init_attr * init_attr,struct mlx4_ib_create_qp_rss * ucmd,struct mlx4_ib_qp * qp)619 static int create_qp_rss(struct mlx4_ib_dev *dev,
620 struct ib_qp_init_attr *init_attr,
621 struct mlx4_ib_create_qp_rss *ucmd,
622 struct mlx4_ib_qp *qp)
623 {
624 int qpn;
625 int err;
626
627 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
628
629 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
630 if (err)
631 return err;
632
633 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
634 if (err)
635 goto err_qpn;
636
637 INIT_LIST_HEAD(&qp->gid_list);
638 INIT_LIST_HEAD(&qp->steering_rules);
639
640 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
641 qp->state = IB_QPS_RESET;
642
643 /* Set dummy send resources to be compatible with HV and PRM */
644 qp->sq_no_prefetch = 1;
645 qp->sq.wqe_cnt = 1;
646 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
647 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
648 qp->mtt = (to_mqp(
649 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
650
651 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
652 if (!qp->rss_ctx) {
653 err = -ENOMEM;
654 goto err_qp_alloc;
655 }
656
657 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
658 if (err)
659 goto err;
660
661 return 0;
662
663 err:
664 kfree(qp->rss_ctx);
665
666 err_qp_alloc:
667 mlx4_qp_remove(dev->dev, &qp->mqp);
668 mlx4_qp_free(dev->dev, &qp->mqp);
669
670 err_qpn:
671 mlx4_qp_release_range(dev->dev, qpn, 1);
672 return err;
673 }
674
_mlx4_ib_create_qp_rss(struct ib_pd * pd,struct mlx4_ib_qp * qp,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)675 static int _mlx4_ib_create_qp_rss(struct ib_pd *pd, struct mlx4_ib_qp *qp,
676 struct ib_qp_init_attr *init_attr,
677 struct ib_udata *udata)
678 {
679 struct mlx4_ib_create_qp_rss ucmd = {};
680 size_t required_cmd_sz;
681 int err;
682
683 if (!udata) {
684 pr_debug("RSS QP with NULL udata\n");
685 return -EINVAL;
686 }
687
688 if (udata->outlen)
689 return -EOPNOTSUPP;
690
691 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
692 sizeof(ucmd.reserved1);
693 if (udata->inlen < required_cmd_sz) {
694 pr_debug("invalid inlen\n");
695 return -EINVAL;
696 }
697
698 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
699 pr_debug("copy failed\n");
700 return -EFAULT;
701 }
702
703 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
704 return -EOPNOTSUPP;
705
706 if (ucmd.comp_mask || ucmd.reserved1)
707 return -EOPNOTSUPP;
708
709 if (udata->inlen > sizeof(ucmd) &&
710 !ib_is_udata_cleared(udata, sizeof(ucmd),
711 udata->inlen - sizeof(ucmd))) {
712 pr_debug("inlen is not supported\n");
713 return -EOPNOTSUPP;
714 }
715
716 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
717 pr_debug("RSS QP with unsupported QP type %d\n",
718 init_attr->qp_type);
719 return -EOPNOTSUPP;
720 }
721
722 if (init_attr->create_flags) {
723 pr_debug("RSS QP doesn't support create flags\n");
724 return -EOPNOTSUPP;
725 }
726
727 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
728 pr_debug("RSS QP with unsupported send attributes\n");
729 return -EOPNOTSUPP;
730 }
731
732 qp->pri.vid = 0xFFFF;
733 qp->alt.vid = 0xFFFF;
734
735 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
736 if (err)
737 return err;
738
739 qp->ibqp.qp_num = qp->mqp.qpn;
740 return 0;
741 }
742
743 /*
744 * This function allocates a WQN from a range which is consecutive and aligned
745 * to its size. In case the range is full, then it creates a new range and
746 * allocates WQN from it. The new range will be used for following allocations.
747 */
mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext * context,struct mlx4_ib_qp * qp,int range_size,int * wqn)748 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
749 struct mlx4_ib_qp *qp, int range_size, int *wqn)
750 {
751 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
752 struct mlx4_wqn_range *range;
753 int err = 0;
754
755 mutex_lock(&context->wqn_ranges_mutex);
756
757 range = list_first_entry_or_null(&context->wqn_ranges_list,
758 struct mlx4_wqn_range, list);
759
760 if (!range || (range->refcount == range->size) || range->dirty) {
761 range = kzalloc(sizeof(*range), GFP_KERNEL);
762 if (!range) {
763 err = -ENOMEM;
764 goto out;
765 }
766
767 err = mlx4_qp_reserve_range(dev->dev, range_size,
768 range_size, &range->base_wqn, 0,
769 qp->mqp.usage);
770 if (err) {
771 kfree(range);
772 goto out;
773 }
774
775 range->size = range_size;
776 list_add(&range->list, &context->wqn_ranges_list);
777 } else if (range_size != 1) {
778 /*
779 * Requesting a new range (>1) when last range is still open, is
780 * not valid.
781 */
782 err = -EINVAL;
783 goto out;
784 }
785
786 qp->wqn_range = range;
787
788 *wqn = range->base_wqn + range->refcount;
789
790 range->refcount++;
791
792 out:
793 mutex_unlock(&context->wqn_ranges_mutex);
794
795 return err;
796 }
797
mlx4_ib_release_wqn(struct mlx4_ib_ucontext * context,struct mlx4_ib_qp * qp,bool dirty_release)798 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
799 struct mlx4_ib_qp *qp, bool dirty_release)
800 {
801 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
802 struct mlx4_wqn_range *range;
803
804 mutex_lock(&context->wqn_ranges_mutex);
805
806 range = qp->wqn_range;
807
808 range->refcount--;
809 if (!range->refcount) {
810 mlx4_qp_release_range(dev->dev, range->base_wqn,
811 range->size);
812 list_del(&range->list);
813 kfree(range);
814 } else if (dirty_release) {
815 /*
816 * A range which one of its WQNs is destroyed, won't be able to be
817 * reused for further WQN allocations.
818 * The next created WQ will allocate a new range.
819 */
820 range->dirty = true;
821 }
822
823 mutex_unlock(&context->wqn_ranges_mutex);
824 }
825
create_rq(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata,struct mlx4_ib_qp * qp)826 static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
827 struct ib_udata *udata, struct mlx4_ib_qp *qp)
828 {
829 struct mlx4_ib_dev *dev = to_mdev(pd->device);
830 int qpn;
831 int err;
832 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
833 udata, struct mlx4_ib_ucontext, ibucontext);
834 struct mlx4_ib_cq *mcq;
835 unsigned long flags;
836 int range_size;
837 struct mlx4_ib_create_wq wq;
838 size_t copy_len;
839 int shift;
840 int n;
841
842 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
843
844 spin_lock_init(&qp->sq.lock);
845 spin_lock_init(&qp->rq.lock);
846 INIT_LIST_HEAD(&qp->gid_list);
847 INIT_LIST_HEAD(&qp->steering_rules);
848
849 qp->state = IB_QPS_RESET;
850
851 copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
852
853 if (ib_copy_from_udata(&wq, udata, copy_len)) {
854 err = -EFAULT;
855 goto err;
856 }
857
858 if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] ||
859 wq.reserved[2]) {
860 pr_debug("user command isn't supported\n");
861 err = -EOPNOTSUPP;
862 goto err;
863 }
864
865 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) {
866 pr_debug("WQN range size must be equal or smaller than %d\n",
867 dev->dev->caps.max_rss_tbl_sz);
868 err = -EOPNOTSUPP;
869 goto err;
870 }
871 range_size = 1 << wq.log_range_size;
872
873 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS)
874 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
875
876 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz);
877 if (err)
878 goto err;
879
880 qp->sq_no_prefetch = 1;
881 qp->sq.wqe_cnt = 1;
882 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
883 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
884 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
885
886 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0);
887 if (IS_ERR(qp->umem)) {
888 err = PTR_ERR(qp->umem);
889 goto err;
890 }
891
892 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
893 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
894
895 if (err)
896 goto err_buf;
897
898 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
899 if (err)
900 goto err_mtt;
901
902 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db);
903 if (err)
904 goto err_mtt;
905 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
906
907 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn);
908 if (err)
909 goto err_wrid;
910
911 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
912 if (err)
913 goto err_qpn;
914
915 /*
916 * Hardware wants QPN written in big-endian order (after
917 * shifting) for send doorbell. Precompute this value to save
918 * a little bit when posting sends.
919 */
920 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
921
922 qp->mqp.event = mlx4_ib_wq_event;
923
924 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
925 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
926 to_mcq(init_attr->recv_cq));
927 /* Maintain device to QPs access, needed for further handling
928 * via reset flow
929 */
930 list_add_tail(&qp->qps_list, &dev->qp_list);
931 /* Maintain CQ to QPs access, needed for further handling
932 * via reset flow
933 */
934 mcq = to_mcq(init_attr->send_cq);
935 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
936 mcq = to_mcq(init_attr->recv_cq);
937 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
938 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
939 to_mcq(init_attr->recv_cq));
940 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
941 return 0;
942
943 err_qpn:
944 mlx4_ib_release_wqn(context, qp, 0);
945 err_wrid:
946 mlx4_ib_db_unmap_user(context, &qp->db);
947
948 err_mtt:
949 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
950 err_buf:
951 ib_umem_release(qp->umem);
952 err:
953 return err;
954 }
955
create_qp_common(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata,int sqpn,struct mlx4_ib_qp * qp)956 static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
957 struct ib_udata *udata, int sqpn,
958 struct mlx4_ib_qp *qp)
959 {
960 struct mlx4_ib_dev *dev = to_mdev(pd->device);
961 int qpn;
962 int err;
963 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
964 udata, struct mlx4_ib_ucontext, ibucontext);
965 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
966 struct mlx4_ib_cq *mcq;
967 unsigned long flags;
968
969 /* When tunneling special qps, we use a plain UD qp */
970 if (sqpn) {
971 if (mlx4_is_mfunc(dev->dev) &&
972 (!mlx4_is_master(dev->dev) ||
973 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
974 if (init_attr->qp_type == IB_QPT_GSI)
975 qp_type = MLX4_IB_QPT_PROXY_GSI;
976 else {
977 if (mlx4_is_master(dev->dev) ||
978 qp0_enabled_vf(dev->dev, sqpn))
979 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
980 else
981 qp_type = MLX4_IB_QPT_PROXY_SMI;
982 }
983 }
984 qpn = sqpn;
985 /* add extra sg entry for tunneling */
986 init_attr->cap.max_recv_sge++;
987 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
988 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
989 container_of(init_attr,
990 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
991 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
992 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
993 !mlx4_is_master(dev->dev))
994 return -EINVAL;
995 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
996 qp_type = MLX4_IB_QPT_TUN_GSI;
997 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
998 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
999 tnl_init->port))
1000 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1001 else
1002 qp_type = MLX4_IB_QPT_TUN_SMI;
1003 /* we are definitely in the PPF here, since we are creating
1004 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1005 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1006 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1007 sqpn = qpn;
1008 }
1009
1010 if (init_attr->qp_type == IB_QPT_SMI ||
1011 init_attr->qp_type == IB_QPT_GSI || qp_type == MLX4_IB_QPT_SMI ||
1012 qp_type == MLX4_IB_QPT_GSI ||
1013 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1014 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1015 qp->sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1016 if (!qp->sqp)
1017 return -ENOMEM;
1018 }
1019
1020 qp->mlx4_ib_qp_type = qp_type;
1021
1022 spin_lock_init(&qp->sq.lock);
1023 spin_lock_init(&qp->rq.lock);
1024 INIT_LIST_HEAD(&qp->gid_list);
1025 INIT_LIST_HEAD(&qp->steering_rules);
1026
1027 qp->state = IB_QPS_RESET;
1028 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1029 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1030
1031 if (udata) {
1032 struct mlx4_ib_create_qp ucmd;
1033 size_t copy_len;
1034 int shift;
1035 int n;
1036
1037 copy_len = sizeof(struct mlx4_ib_create_qp);
1038
1039 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
1040 err = -EFAULT;
1041 goto err;
1042 }
1043
1044 qp->inl_recv_sz = ucmd.inl_recv_sz;
1045
1046 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1047 if (!(dev->dev->caps.flags &
1048 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1049 pr_debug("scatter FCS is unsupported\n");
1050 err = -EOPNOTSUPP;
1051 goto err;
1052 }
1053
1054 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1055 }
1056
1057 err = set_rq_size(dev, &init_attr->cap, udata,
1058 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
1059 if (err)
1060 goto err;
1061
1062 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
1063
1064 err = set_user_sq_size(dev, qp, &ucmd);
1065 if (err)
1066 goto err;
1067
1068 qp->umem =
1069 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0);
1070 if (IS_ERR(qp->umem)) {
1071 err = PTR_ERR(qp->umem);
1072 goto err;
1073 }
1074
1075 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1076 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1077
1078 if (err)
1079 goto err_buf;
1080
1081 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1082 if (err)
1083 goto err_mtt;
1084
1085 if (qp_has_rq(init_attr)) {
1086 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db);
1087 if (err)
1088 goto err_mtt;
1089 }
1090 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1091 } else {
1092 err = set_rq_size(dev, &init_attr->cap, udata,
1093 qp_has_rq(init_attr), qp, 0);
1094 if (err)
1095 goto err;
1096
1097 qp->sq_no_prefetch = 0;
1098
1099 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1100 qp->flags |= MLX4_IB_QP_LSO;
1101
1102 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1103 if (dev->steering_support ==
1104 MLX4_STEERING_MODE_DEVICE_MANAGED)
1105 qp->flags |= MLX4_IB_QP_NETIF;
1106 else {
1107 err = -EINVAL;
1108 goto err;
1109 }
1110 }
1111
1112 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
1113 if (err)
1114 goto err;
1115
1116 if (qp_has_rq(init_attr)) {
1117 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1118 if (err)
1119 goto err;
1120
1121 *qp->db.db = 0;
1122 }
1123
1124 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
1125 &qp->buf)) {
1126 err = -ENOMEM;
1127 goto err_db;
1128 }
1129
1130 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1131 &qp->mtt);
1132 if (err)
1133 goto err_buf;
1134
1135 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1136 if (err)
1137 goto err_mtt;
1138
1139 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1140 sizeof(u64), GFP_KERNEL);
1141 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1142 sizeof(u64), GFP_KERNEL);
1143 if (!qp->sq.wrid || !qp->rq.wrid) {
1144 err = -ENOMEM;
1145 goto err_wrid;
1146 }
1147 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1148 }
1149
1150 if (sqpn) {
1151 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1152 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1153 if (alloc_proxy_bufs(pd->device, qp)) {
1154 err = -ENOMEM;
1155 goto err_wrid;
1156 }
1157 }
1158 } else {
1159 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1160 * otherwise, the WQE BlueFlame setup flow wrongly causes
1161 * VLAN insertion. */
1162 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1163 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1164 (init_attr->cap.max_send_wr ?
1165 MLX4_RESERVE_ETH_BF_QP : 0) |
1166 (init_attr->cap.max_recv_wr ?
1167 MLX4_RESERVE_A0_QP : 0),
1168 qp->mqp.usage);
1169 else
1170 if (qp->flags & MLX4_IB_QP_NETIF)
1171 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1172 else
1173 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1174 &qpn, 0, qp->mqp.usage);
1175 if (err)
1176 goto err_proxy;
1177 }
1178
1179 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1180 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1181
1182 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1183 if (err)
1184 goto err_qpn;
1185
1186 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1187 qp->mqp.qpn |= (1 << 23);
1188
1189 /*
1190 * Hardware wants QPN written in big-endian order (after
1191 * shifting) for send doorbell. Precompute this value to save
1192 * a little bit when posting sends.
1193 */
1194 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1195
1196 qp->mqp.event = mlx4_ib_qp_event;
1197
1198 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1199 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1200 to_mcq(init_attr->recv_cq));
1201 /* Maintain device to QPs access, needed for further handling
1202 * via reset flow
1203 */
1204 list_add_tail(&qp->qps_list, &dev->qp_list);
1205 /* Maintain CQ to QPs access, needed for further handling
1206 * via reset flow
1207 */
1208 mcq = to_mcq(init_attr->send_cq);
1209 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1210 mcq = to_mcq(init_attr->recv_cq);
1211 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1212 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1213 to_mcq(init_attr->recv_cq));
1214 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1215 return 0;
1216
1217 err_qpn:
1218 if (!sqpn) {
1219 if (qp->flags & MLX4_IB_QP_NETIF)
1220 mlx4_ib_steer_qp_free(dev, qpn, 1);
1221 else
1222 mlx4_qp_release_range(dev->dev, qpn, 1);
1223 }
1224 err_proxy:
1225 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1226 free_proxy_bufs(pd->device, qp);
1227 err_wrid:
1228 if (udata) {
1229 if (qp_has_rq(init_attr))
1230 mlx4_ib_db_unmap_user(context, &qp->db);
1231 } else {
1232 kvfree(qp->sq.wrid);
1233 kvfree(qp->rq.wrid);
1234 }
1235
1236 err_mtt:
1237 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1238
1239 err_buf:
1240 if (!qp->umem)
1241 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1242 ib_umem_release(qp->umem);
1243
1244 err_db:
1245 if (!udata && qp_has_rq(init_attr))
1246 mlx4_db_free(dev->dev, &qp->db);
1247
1248 err:
1249 kfree(qp->sqp);
1250 return err;
1251 }
1252
to_mlx4_state(enum ib_qp_state state)1253 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1254 {
1255 switch (state) {
1256 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1257 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1258 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1259 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1260 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1261 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1262 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1263 default: return -1;
1264 }
1265 }
1266
mlx4_ib_lock_cqs(struct mlx4_ib_cq * send_cq,struct mlx4_ib_cq * recv_cq)1267 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1268 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1269 {
1270 if (send_cq == recv_cq) {
1271 spin_lock(&send_cq->lock);
1272 __acquire(&recv_cq->lock);
1273 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1274 spin_lock(&send_cq->lock);
1275 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1276 } else {
1277 spin_lock(&recv_cq->lock);
1278 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1279 }
1280 }
1281
mlx4_ib_unlock_cqs(struct mlx4_ib_cq * send_cq,struct mlx4_ib_cq * recv_cq)1282 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1283 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1284 {
1285 if (send_cq == recv_cq) {
1286 __release(&recv_cq->lock);
1287 spin_unlock(&send_cq->lock);
1288 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1289 spin_unlock(&recv_cq->lock);
1290 spin_unlock(&send_cq->lock);
1291 } else {
1292 spin_unlock(&send_cq->lock);
1293 spin_unlock(&recv_cq->lock);
1294 }
1295 }
1296
del_gid_entries(struct mlx4_ib_qp * qp)1297 static void del_gid_entries(struct mlx4_ib_qp *qp)
1298 {
1299 struct mlx4_ib_gid_entry *ge, *tmp;
1300
1301 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1302 list_del(&ge->list);
1303 kfree(ge);
1304 }
1305 }
1306
get_pd(struct mlx4_ib_qp * qp)1307 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1308 {
1309 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1310 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1311 else
1312 return to_mpd(qp->ibqp.pd);
1313 }
1314
get_cqs(struct mlx4_ib_qp * qp,enum mlx4_ib_source_type src,struct mlx4_ib_cq ** send_cq,struct mlx4_ib_cq ** recv_cq)1315 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1316 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1317 {
1318 switch (qp->ibqp.qp_type) {
1319 case IB_QPT_XRC_TGT:
1320 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1321 *recv_cq = *send_cq;
1322 break;
1323 case IB_QPT_XRC_INI:
1324 *send_cq = to_mcq(qp->ibqp.send_cq);
1325 *recv_cq = *send_cq;
1326 break;
1327 default:
1328 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1329 to_mcq(qp->ibwq.cq);
1330 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1331 *recv_cq;
1332 break;
1333 }
1334 }
1335
destroy_qp_rss(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1336 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1337 {
1338 if (qp->state != IB_QPS_RESET) {
1339 int i;
1340
1341 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1342 i++) {
1343 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1344 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1345
1346 mutex_lock(&wq->mutex);
1347
1348 wq->rss_usecnt--;
1349
1350 mutex_unlock(&wq->mutex);
1351 }
1352
1353 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1354 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1355 pr_warn("modify QP %06x to RESET failed.\n",
1356 qp->mqp.qpn);
1357 }
1358
1359 mlx4_qp_remove(dev->dev, &qp->mqp);
1360 mlx4_qp_free(dev->dev, &qp->mqp);
1361 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1362 del_gid_entries(qp);
1363 }
1364
destroy_qp_common(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,enum mlx4_ib_source_type src,struct ib_udata * udata)1365 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1366 enum mlx4_ib_source_type src,
1367 struct ib_udata *udata)
1368 {
1369 struct mlx4_ib_cq *send_cq, *recv_cq;
1370 unsigned long flags;
1371
1372 if (qp->state != IB_QPS_RESET) {
1373 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1374 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1375 pr_warn("modify QP %06x to RESET failed.\n",
1376 qp->mqp.qpn);
1377 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1378 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1379 qp->pri.smac = 0;
1380 qp->pri.smac_port = 0;
1381 }
1382 if (qp->alt.smac) {
1383 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1384 qp->alt.smac = 0;
1385 }
1386 if (qp->pri.vid < 0x1000) {
1387 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1388 qp->pri.vid = 0xFFFF;
1389 qp->pri.candidate_vid = 0xFFFF;
1390 qp->pri.update_vid = 0;
1391 }
1392 if (qp->alt.vid < 0x1000) {
1393 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1394 qp->alt.vid = 0xFFFF;
1395 qp->alt.candidate_vid = 0xFFFF;
1396 qp->alt.update_vid = 0;
1397 }
1398 }
1399
1400 get_cqs(qp, src, &send_cq, &recv_cq);
1401
1402 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1403 mlx4_ib_lock_cqs(send_cq, recv_cq);
1404
1405 /* del from lists under both locks above to protect reset flow paths */
1406 list_del(&qp->qps_list);
1407 list_del(&qp->cq_send_list);
1408 list_del(&qp->cq_recv_list);
1409 if (!udata) {
1410 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1411 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1412 if (send_cq != recv_cq)
1413 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1414 }
1415
1416 mlx4_qp_remove(dev->dev, &qp->mqp);
1417
1418 mlx4_ib_unlock_cqs(send_cq, recv_cq);
1419 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1420
1421 mlx4_qp_free(dev->dev, &qp->mqp);
1422
1423 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1424 if (qp->flags & MLX4_IB_QP_NETIF)
1425 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1426 else if (src == MLX4_IB_RWQ_SRC)
1427 mlx4_ib_release_wqn(
1428 rdma_udata_to_drv_context(
1429 udata,
1430 struct mlx4_ib_ucontext,
1431 ibucontext),
1432 qp, 1);
1433 else
1434 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1435 }
1436
1437 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1438
1439 if (udata) {
1440 if (qp->rq.wqe_cnt) {
1441 struct mlx4_ib_ucontext *mcontext =
1442 rdma_udata_to_drv_context(
1443 udata,
1444 struct mlx4_ib_ucontext,
1445 ibucontext);
1446
1447 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1448 }
1449 } else {
1450 kvfree(qp->sq.wrid);
1451 kvfree(qp->rq.wrid);
1452 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1453 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1454 free_proxy_bufs(&dev->ib_dev, qp);
1455 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1456 if (qp->rq.wqe_cnt)
1457 mlx4_db_free(dev->dev, &qp->db);
1458 }
1459 ib_umem_release(qp->umem);
1460
1461 del_gid_entries(qp);
1462 }
1463
get_sqp_num(struct mlx4_ib_dev * dev,struct ib_qp_init_attr * attr)1464 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1465 {
1466 /* Native or PPF */
1467 if (!mlx4_is_mfunc(dev->dev) ||
1468 (mlx4_is_master(dev->dev) &&
1469 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1470 return dev->dev->phys_caps.base_sqpn +
1471 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1472 attr->port_num - 1;
1473 }
1474 /* PF or VF -- creating proxies */
1475 if (attr->qp_type == IB_QPT_SMI)
1476 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1477 else
1478 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1479 }
1480
_mlx4_ib_create_qp(struct ib_pd * pd,struct mlx4_ib_qp * qp,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1481 static int _mlx4_ib_create_qp(struct ib_pd *pd, struct mlx4_ib_qp *qp,
1482 struct ib_qp_init_attr *init_attr,
1483 struct ib_udata *udata)
1484 {
1485 int err;
1486 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1487 u16 xrcdn = 0;
1488
1489 if (init_attr->rwq_ind_tbl)
1490 return _mlx4_ib_create_qp_rss(pd, qp, init_attr, udata);
1491
1492 /*
1493 * We only support LSO, vendor flag1, and multicast loopback blocking,
1494 * and only for kernel UD QPs.
1495 */
1496 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1497 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1498 MLX4_IB_SRIOV_TUNNEL_QP |
1499 MLX4_IB_SRIOV_SQP |
1500 MLX4_IB_QP_NETIF |
1501 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1502 return -EINVAL;
1503
1504 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1505 if (init_attr->qp_type != IB_QPT_UD)
1506 return -EINVAL;
1507 }
1508
1509 if (init_attr->create_flags) {
1510 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1511 return -EINVAL;
1512
1513 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1514 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1515 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1516 init_attr->qp_type != IB_QPT_UD) ||
1517 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1518 init_attr->qp_type > IB_QPT_GSI) ||
1519 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1520 init_attr->qp_type != IB_QPT_GSI))
1521 return -EINVAL;
1522 }
1523
1524 switch (init_attr->qp_type) {
1525 case IB_QPT_XRC_TGT:
1526 pd = to_mxrcd(init_attr->xrcd)->pd;
1527 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1528 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1529 fallthrough;
1530 case IB_QPT_XRC_INI:
1531 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1532 return -ENOSYS;
1533 init_attr->recv_cq = init_attr->send_cq;
1534 fallthrough;
1535 case IB_QPT_RC:
1536 case IB_QPT_UC:
1537 case IB_QPT_RAW_PACKET:
1538 case IB_QPT_UD:
1539 qp->pri.vid = 0xFFFF;
1540 qp->alt.vid = 0xFFFF;
1541 err = create_qp_common(pd, init_attr, udata, 0, qp);
1542 if (err)
1543 return err;
1544
1545 qp->ibqp.qp_num = qp->mqp.qpn;
1546 qp->xrcdn = xrcdn;
1547 break;
1548 case IB_QPT_SMI:
1549 case IB_QPT_GSI:
1550 {
1551 int sqpn;
1552
1553 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1554 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1555 1, 1, &sqpn, 0,
1556 MLX4_RES_USAGE_DRIVER);
1557
1558 if (res)
1559 return res;
1560 } else {
1561 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1562 }
1563
1564 qp->pri.vid = 0xFFFF;
1565 qp->alt.vid = 0xFFFF;
1566 err = create_qp_common(pd, init_attr, udata, sqpn, qp);
1567 if (err)
1568 return err;
1569
1570 qp->port = init_attr->port_num;
1571 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1572 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1573 break;
1574 }
1575 default:
1576 /* Don't support raw QPs */
1577 return -EOPNOTSUPP;
1578 }
1579 return 0;
1580 }
1581
mlx4_ib_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1582 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1583 struct ib_qp_init_attr *init_attr,
1584 struct ib_udata *udata) {
1585 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1586 struct mlx4_ib_dev *dev = to_mdev(device);
1587 struct mlx4_ib_qp *qp;
1588 int ret;
1589
1590 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1591 if (!qp)
1592 return ERR_PTR(-ENOMEM);
1593
1594 mutex_init(&qp->mutex);
1595 ret = _mlx4_ib_create_qp(pd, qp, init_attr, udata);
1596 if (ret) {
1597 kfree(qp);
1598 return ERR_PTR(ret);
1599 }
1600
1601 if (init_attr->qp_type == IB_QPT_GSI &&
1602 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1603 struct mlx4_ib_sqp *sqp = qp->sqp;
1604 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1605
1606 if (is_eth &&
1607 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1608 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1609 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1610
1611 if (IS_ERR(sqp->roce_v2_gsi)) {
1612 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1613 sqp->roce_v2_gsi = NULL;
1614 } else {
1615 to_mqp(sqp->roce_v2_gsi)->flags |=
1616 MLX4_IB_ROCE_V2_GSI_QP;
1617 }
1618
1619 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1620 }
1621 }
1622 return &qp->ibqp;
1623 }
1624
_mlx4_ib_destroy_qp(struct ib_qp * qp,struct ib_udata * udata)1625 static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
1626 {
1627 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1628 struct mlx4_ib_qp *mqp = to_mqp(qp);
1629
1630 if (is_qp0(dev, mqp))
1631 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1632
1633 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1634 dev->qp1_proxy[mqp->port - 1] == mqp) {
1635 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1636 dev->qp1_proxy[mqp->port - 1] = NULL;
1637 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1638 }
1639
1640 if (mqp->counter_index)
1641 mlx4_ib_free_qp_counter(dev, mqp);
1642
1643 if (qp->rwq_ind_tbl) {
1644 destroy_qp_rss(dev, mqp);
1645 } else {
1646 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata);
1647 }
1648
1649 kfree(mqp->sqp);
1650 kfree(mqp);
1651
1652 return 0;
1653 }
1654
mlx4_ib_destroy_qp(struct ib_qp * qp,struct ib_udata * udata)1655 int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
1656 {
1657 struct mlx4_ib_qp *mqp = to_mqp(qp);
1658
1659 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1660 struct mlx4_ib_sqp *sqp = mqp->sqp;
1661
1662 if (sqp->roce_v2_gsi)
1663 ib_destroy_qp(sqp->roce_v2_gsi);
1664 }
1665
1666 return _mlx4_ib_destroy_qp(qp, udata);
1667 }
1668
to_mlx4_st(struct mlx4_ib_dev * dev,enum mlx4_ib_qp_type type)1669 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1670 {
1671 switch (type) {
1672 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1673 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1674 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1675 case MLX4_IB_QPT_XRC_INI:
1676 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1677 case MLX4_IB_QPT_SMI:
1678 case MLX4_IB_QPT_GSI:
1679 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1680
1681 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1682 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1683 MLX4_QP_ST_MLX : -1);
1684 case MLX4_IB_QPT_PROXY_SMI:
1685 case MLX4_IB_QPT_TUN_SMI:
1686 case MLX4_IB_QPT_PROXY_GSI:
1687 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1688 MLX4_QP_ST_UD : -1);
1689 default: return -1;
1690 }
1691 }
1692
to_mlx4_access_flags(struct mlx4_ib_qp * qp,const struct ib_qp_attr * attr,int attr_mask)1693 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1694 int attr_mask)
1695 {
1696 u8 dest_rd_atomic;
1697 u32 access_flags;
1698 u32 hw_access_flags = 0;
1699
1700 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1701 dest_rd_atomic = attr->max_dest_rd_atomic;
1702 else
1703 dest_rd_atomic = qp->resp_depth;
1704
1705 if (attr_mask & IB_QP_ACCESS_FLAGS)
1706 access_flags = attr->qp_access_flags;
1707 else
1708 access_flags = qp->atomic_rd_en;
1709
1710 if (!dest_rd_atomic)
1711 access_flags &= IB_ACCESS_REMOTE_WRITE;
1712
1713 if (access_flags & IB_ACCESS_REMOTE_READ)
1714 hw_access_flags |= MLX4_QP_BIT_RRE;
1715 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1716 hw_access_flags |= MLX4_QP_BIT_RAE;
1717 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1718 hw_access_flags |= MLX4_QP_BIT_RWE;
1719
1720 return cpu_to_be32(hw_access_flags);
1721 }
1722
store_sqp_attrs(struct mlx4_ib_sqp * sqp,const struct ib_qp_attr * attr,int attr_mask)1723 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1724 int attr_mask)
1725 {
1726 if (attr_mask & IB_QP_PKEY_INDEX)
1727 sqp->pkey_index = attr->pkey_index;
1728 if (attr_mask & IB_QP_QKEY)
1729 sqp->qkey = attr->qkey;
1730 if (attr_mask & IB_QP_SQ_PSN)
1731 sqp->send_psn = attr->sq_psn;
1732 }
1733
mlx4_set_sched(struct mlx4_qp_path * path,u8 port)1734 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1735 {
1736 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1737 }
1738
_mlx4_set_path(struct mlx4_ib_dev * dev,const struct rdma_ah_attr * ah,u64 smac,u16 vlan_tag,struct mlx4_qp_path * path,struct mlx4_roce_smac_vlan_info * smac_info,u8 port)1739 static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1740 const struct rdma_ah_attr *ah,
1741 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1742 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1743 {
1744 int vidx;
1745 int smac_index;
1746 int err;
1747
1748 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1749 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1750 if (rdma_ah_get_static_rate(ah)) {
1751 path->static_rate = rdma_ah_get_static_rate(ah) +
1752 MLX4_STAT_RATE_OFFSET;
1753 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1754 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1755 --path->static_rate;
1756 } else
1757 path->static_rate = 0;
1758
1759 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1760 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1761 int real_sgid_index =
1762 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
1763
1764 if (real_sgid_index < 0)
1765 return real_sgid_index;
1766 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1767 pr_err("sgid_index (%u) too large. max is %d\n",
1768 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1769 return -1;
1770 }
1771
1772 path->grh_mylmc |= 1 << 7;
1773 path->mgid_index = real_sgid_index;
1774 path->hop_limit = grh->hop_limit;
1775 path->tclass_flowlabel =
1776 cpu_to_be32((grh->traffic_class << 20) |
1777 (grh->flow_label));
1778 memcpy(path->rgid, grh->dgid.raw, 16);
1779 }
1780
1781 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1782 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1783 return -1;
1784
1785 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1786 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1787
1788 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1789 if (vlan_tag < 0x1000) {
1790 if (smac_info->vid < 0x1000) {
1791 /* both valid vlan ids */
1792 if (smac_info->vid != vlan_tag) {
1793 /* different VIDs. unreg old and reg new */
1794 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1795 if (err)
1796 return err;
1797 smac_info->candidate_vid = vlan_tag;
1798 smac_info->candidate_vlan_index = vidx;
1799 smac_info->candidate_vlan_port = port;
1800 smac_info->update_vid = 1;
1801 path->vlan_index = vidx;
1802 } else {
1803 path->vlan_index = smac_info->vlan_index;
1804 }
1805 } else {
1806 /* no current vlan tag in qp */
1807 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1808 if (err)
1809 return err;
1810 smac_info->candidate_vid = vlan_tag;
1811 smac_info->candidate_vlan_index = vidx;
1812 smac_info->candidate_vlan_port = port;
1813 smac_info->update_vid = 1;
1814 path->vlan_index = vidx;
1815 }
1816 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1817 path->fl = 1 << 6;
1818 } else {
1819 /* have current vlan tag. unregister it at modify-qp success */
1820 if (smac_info->vid < 0x1000) {
1821 smac_info->candidate_vid = 0xFFFF;
1822 smac_info->update_vid = 1;
1823 }
1824 }
1825
1826 /* get smac_index for RoCE use.
1827 * If no smac was yet assigned, register one.
1828 * If one was already assigned, but the new mac differs,
1829 * unregister the old one and register the new one.
1830 */
1831 if ((!smac_info->smac && !smac_info->smac_port) ||
1832 smac_info->smac != smac) {
1833 /* register candidate now, unreg if needed, after success */
1834 smac_index = mlx4_register_mac(dev->dev, port, smac);
1835 if (smac_index >= 0) {
1836 smac_info->candidate_smac_index = smac_index;
1837 smac_info->candidate_smac = smac;
1838 smac_info->candidate_smac_port = port;
1839 } else {
1840 return -EINVAL;
1841 }
1842 } else {
1843 smac_index = smac_info->smac_index;
1844 }
1845 memcpy(path->dmac, ah->roce.dmac, 6);
1846 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1847 /* put MAC table smac index for IBoE */
1848 path->grh_mylmc = (u8) (smac_index) | 0x80;
1849 } else {
1850 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1851 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1852 }
1853
1854 return 0;
1855 }
1856
mlx4_set_path(struct mlx4_ib_dev * dev,const struct ib_qp_attr * qp,enum ib_qp_attr_mask qp_attr_mask,struct mlx4_ib_qp * mqp,struct mlx4_qp_path * path,u8 port,u16 vlan_id,u8 * smac)1857 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1858 enum ib_qp_attr_mask qp_attr_mask,
1859 struct mlx4_ib_qp *mqp,
1860 struct mlx4_qp_path *path, u8 port,
1861 u16 vlan_id, u8 *smac)
1862 {
1863 return _mlx4_set_path(dev, &qp->ah_attr,
1864 mlx4_mac_to_u64(smac),
1865 vlan_id,
1866 path, &mqp->pri, port);
1867 }
1868
mlx4_set_alt_path(struct mlx4_ib_dev * dev,const struct ib_qp_attr * qp,enum ib_qp_attr_mask qp_attr_mask,struct mlx4_ib_qp * mqp,struct mlx4_qp_path * path,u8 port)1869 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1870 const struct ib_qp_attr *qp,
1871 enum ib_qp_attr_mask qp_attr_mask,
1872 struct mlx4_ib_qp *mqp,
1873 struct mlx4_qp_path *path, u8 port)
1874 {
1875 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1876 0,
1877 0xffff,
1878 path, &mqp->alt, port);
1879 }
1880
update_mcg_macs(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1881 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1882 {
1883 struct mlx4_ib_gid_entry *ge, *tmp;
1884
1885 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1886 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1887 ge->added = 1;
1888 ge->port = qp->port;
1889 }
1890 }
1891 }
1892
handle_eth_ud_smac_index(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,struct mlx4_qp_context * context)1893 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1894 struct mlx4_ib_qp *qp,
1895 struct mlx4_qp_context *context)
1896 {
1897 u64 u64_mac;
1898 int smac_index;
1899
1900 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1901
1902 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1903 if (!qp->pri.smac && !qp->pri.smac_port) {
1904 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1905 if (smac_index >= 0) {
1906 qp->pri.candidate_smac_index = smac_index;
1907 qp->pri.candidate_smac = u64_mac;
1908 qp->pri.candidate_smac_port = qp->port;
1909 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1910 } else {
1911 return -ENOENT;
1912 }
1913 }
1914 return 0;
1915 }
1916
create_qp_lb_counter(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1917 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1918 {
1919 struct counter_index *new_counter_index;
1920 int err;
1921 u32 tmp_idx;
1922
1923 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1924 IB_LINK_LAYER_ETHERNET ||
1925 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1926 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1927 return 0;
1928
1929 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
1930 if (err)
1931 return err;
1932
1933 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1934 if (!new_counter_index) {
1935 mlx4_counter_free(dev->dev, tmp_idx);
1936 return -ENOMEM;
1937 }
1938
1939 new_counter_index->index = tmp_idx;
1940 new_counter_index->allocated = 1;
1941 qp->counter_index = new_counter_index;
1942
1943 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1944 list_add_tail(&new_counter_index->list,
1945 &dev->counters_table[qp->port - 1].counters_list);
1946 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1947
1948 return 0;
1949 }
1950
1951 enum {
1952 MLX4_QPC_ROCE_MODE_1 = 0,
1953 MLX4_QPC_ROCE_MODE_2 = 2,
1954 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1955 };
1956
gid_type_to_qpc(enum ib_gid_type gid_type)1957 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1958 {
1959 switch (gid_type) {
1960 case IB_GID_TYPE_ROCE:
1961 return MLX4_QPC_ROCE_MODE_1;
1962 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1963 return MLX4_QPC_ROCE_MODE_2;
1964 default:
1965 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1966 }
1967 }
1968
1969 /*
1970 * Go over all RSS QP's childes (WQs) and apply their HW state according to
1971 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
1972 */
bringup_rss_rwqs(struct ib_rwq_ind_table * ind_tbl,u8 port_num,struct ib_udata * udata)1973 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num,
1974 struct ib_udata *udata)
1975 {
1976 int err = 0;
1977 int i;
1978
1979 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
1980 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
1981 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1982
1983 mutex_lock(&wq->mutex);
1984
1985 /* Mlx4_ib restrictions:
1986 * WQ's is associated to a port according to the RSS QP it is
1987 * associates to.
1988 * In case the WQ is associated to a different port by another
1989 * RSS QP, return a failure.
1990 */
1991 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
1992 err = -EINVAL;
1993 mutex_unlock(&wq->mutex);
1994 break;
1995 }
1996 wq->port = port_num;
1997 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
1998 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata);
1999 if (err) {
2000 mutex_unlock(&wq->mutex);
2001 break;
2002 }
2003 }
2004 wq->rss_usecnt++;
2005
2006 mutex_unlock(&wq->mutex);
2007 }
2008
2009 if (i && err) {
2010 int j;
2011
2012 for (j = (i - 1); j >= 0; j--) {
2013 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2014 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2015
2016 mutex_lock(&wq->mutex);
2017
2018 if ((wq->rss_usecnt == 1) &&
2019 (ibwq->state == IB_WQS_RDY))
2020 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET,
2021 udata))
2022 pr_warn("failed to reverse WQN=0x%06x\n",
2023 ibwq->wq_num);
2024 wq->rss_usecnt--;
2025
2026 mutex_unlock(&wq->mutex);
2027 }
2028 }
2029
2030 return err;
2031 }
2032
bring_down_rss_rwqs(struct ib_rwq_ind_table * ind_tbl,struct ib_udata * udata)2033 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl,
2034 struct ib_udata *udata)
2035 {
2036 int i;
2037
2038 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2039 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2040 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2041
2042 mutex_lock(&wq->mutex);
2043
2044 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2045 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata))
2046 pr_warn("failed to reverse WQN=%x\n",
2047 ibwq->wq_num);
2048 wq->rss_usecnt--;
2049
2050 mutex_unlock(&wq->mutex);
2051 }
2052 }
2053
fill_qp_rss_context(struct mlx4_qp_context * context,struct mlx4_ib_qp * qp)2054 static void fill_qp_rss_context(struct mlx4_qp_context *context,
2055 struct mlx4_ib_qp *qp)
2056 {
2057 struct mlx4_rss_context *rss_context;
2058
2059 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2060 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2061
2062 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2063 rss_context->default_qpn =
2064 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2065 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2066 rss_context->base_qpn_udp = rss_context->default_qpn;
2067 rss_context->flags = qp->rss_ctx->flags;
2068 /* Currently support just toeplitz */
2069 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2070
2071 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2072 MLX4_EN_RSS_KEY_SIZE);
2073 }
2074
__mlx4_ib_modify_qp(void * src,enum mlx4_ib_source_type src_type,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct ib_udata * udata)2075 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2076 const struct ib_qp_attr *attr, int attr_mask,
2077 enum ib_qp_state cur_state,
2078 enum ib_qp_state new_state,
2079 struct ib_udata *udata)
2080 {
2081 struct ib_srq *ibsrq;
2082 const struct ib_gid_attr *gid_attr = NULL;
2083 struct ib_rwq_ind_table *rwq_ind_tbl;
2084 enum ib_qp_type qp_type;
2085 struct mlx4_ib_dev *dev;
2086 struct mlx4_ib_qp *qp;
2087 struct mlx4_ib_pd *pd;
2088 struct mlx4_ib_cq *send_cq, *recv_cq;
2089 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2090 udata, struct mlx4_ib_ucontext, ibucontext);
2091 struct mlx4_qp_context *context;
2092 enum mlx4_qp_optpar optpar = 0;
2093 int sqd_event;
2094 int steer_qp = 0;
2095 int err = -EINVAL;
2096 int counter_index;
2097
2098 if (src_type == MLX4_IB_RWQ_SRC) {
2099 struct ib_wq *ibwq;
2100
2101 ibwq = (struct ib_wq *)src;
2102 ibsrq = NULL;
2103 rwq_ind_tbl = NULL;
2104 qp_type = IB_QPT_RAW_PACKET;
2105 qp = to_mqp((struct ib_qp *)ibwq);
2106 dev = to_mdev(ibwq->device);
2107 pd = to_mpd(ibwq->pd);
2108 } else {
2109 struct ib_qp *ibqp;
2110
2111 ibqp = (struct ib_qp *)src;
2112 ibsrq = ibqp->srq;
2113 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2114 qp_type = ibqp->qp_type;
2115 qp = to_mqp(ibqp);
2116 dev = to_mdev(ibqp->device);
2117 pd = get_pd(qp);
2118 }
2119
2120 /* APM is not supported under RoCE */
2121 if (attr_mask & IB_QP_ALT_PATH &&
2122 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2123 IB_LINK_LAYER_ETHERNET)
2124 return -ENOTSUPP;
2125
2126 context = kzalloc(sizeof *context, GFP_KERNEL);
2127 if (!context)
2128 return -ENOMEM;
2129
2130 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2131 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2132
2133 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2134 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2135 else {
2136 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2137 switch (attr->path_mig_state) {
2138 case IB_MIG_MIGRATED:
2139 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2140 break;
2141 case IB_MIG_REARM:
2142 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2143 break;
2144 case IB_MIG_ARMED:
2145 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2146 break;
2147 }
2148 }
2149
2150 if (qp->inl_recv_sz)
2151 context->param3 |= cpu_to_be32(1 << 25);
2152
2153 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2154 context->param3 |= cpu_to_be32(1 << 29);
2155
2156 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2157 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2158 else if (qp_type == IB_QPT_RAW_PACKET)
2159 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2160 else if (qp_type == IB_QPT_UD) {
2161 if (qp->flags & MLX4_IB_QP_LSO)
2162 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2163 ilog2(dev->dev->caps.max_gso_sz);
2164 else
2165 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2166 } else if (attr_mask & IB_QP_PATH_MTU) {
2167 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2168 pr_err("path MTU (%u) is invalid\n",
2169 attr->path_mtu);
2170 goto out;
2171 }
2172 context->mtu_msgmax = (attr->path_mtu << 5) |
2173 ilog2(dev->dev->caps.max_msg_sz);
2174 }
2175
2176 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2177 if (qp->rq.wqe_cnt)
2178 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2179 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2180 }
2181
2182 if (qp->sq.wqe_cnt)
2183 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2184 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2185
2186 if (new_state == IB_QPS_RESET && qp->counter_index)
2187 mlx4_ib_free_qp_counter(dev, qp);
2188
2189 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2190 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2191 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2192 if (qp_type == IB_QPT_RAW_PACKET)
2193 context->param3 |= cpu_to_be32(1 << 30);
2194 }
2195
2196 if (ucontext)
2197 context->usr_page = cpu_to_be32(
2198 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index));
2199 else
2200 context->usr_page = cpu_to_be32(
2201 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2202
2203 if (attr_mask & IB_QP_DEST_QPN)
2204 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2205
2206 if (attr_mask & IB_QP_PORT) {
2207 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2208 !(attr_mask & IB_QP_AV)) {
2209 mlx4_set_sched(&context->pri_path, attr->port_num);
2210 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2211 }
2212 }
2213
2214 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2215 err = create_qp_lb_counter(dev, qp);
2216 if (err)
2217 goto out;
2218
2219 counter_index =
2220 dev->counters_table[qp->port - 1].default_counter;
2221 if (qp->counter_index)
2222 counter_index = qp->counter_index->index;
2223
2224 if (counter_index != -1) {
2225 context->pri_path.counter_index = counter_index;
2226 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2227 if (qp->counter_index) {
2228 context->pri_path.fl |=
2229 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2230 context->pri_path.vlan_control |=
2231 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2232 }
2233 } else
2234 context->pri_path.counter_index =
2235 MLX4_SINK_COUNTER_INDEX(dev->dev);
2236
2237 if (qp->flags & MLX4_IB_QP_NETIF) {
2238 mlx4_ib_steer_qp_reg(dev, qp, 1);
2239 steer_qp = 1;
2240 }
2241
2242 if (qp_type == IB_QPT_GSI) {
2243 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2244 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2245 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2246
2247 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2248 }
2249 }
2250
2251 if (attr_mask & IB_QP_PKEY_INDEX) {
2252 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2253 context->pri_path.disable_pkey_check = 0x40;
2254 context->pri_path.pkey_index = attr->pkey_index;
2255 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2256 }
2257
2258 if (attr_mask & IB_QP_AV) {
2259 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2260 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2261 u16 vlan = 0xffff;
2262 u8 smac[ETH_ALEN];
2263 int is_eth =
2264 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2265 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2266
2267 if (is_eth) {
2268 gid_attr = attr->ah_attr.grh.sgid_attr;
2269 err = rdma_read_gid_l2_fields(gid_attr, &vlan,
2270 &smac[0]);
2271 if (err)
2272 goto out;
2273 }
2274
2275 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2276 port_num, vlan, smac))
2277 goto out;
2278
2279 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2280 MLX4_QP_OPTPAR_SCHED_QUEUE);
2281
2282 if (is_eth &&
2283 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2284 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
2285
2286 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2287 err = -EINVAL;
2288 goto out;
2289 }
2290 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2291 }
2292
2293 }
2294
2295 if (attr_mask & IB_QP_TIMEOUT) {
2296 context->pri_path.ackto |= attr->timeout << 3;
2297 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2298 }
2299
2300 if (attr_mask & IB_QP_ALT_PATH) {
2301 if (attr->alt_port_num == 0 ||
2302 attr->alt_port_num > dev->dev->caps.num_ports)
2303 goto out;
2304
2305 if (attr->alt_pkey_index >=
2306 dev->dev->caps.pkey_table_len[attr->alt_port_num])
2307 goto out;
2308
2309 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2310 &context->alt_path,
2311 attr->alt_port_num))
2312 goto out;
2313
2314 context->alt_path.pkey_index = attr->alt_pkey_index;
2315 context->alt_path.ackto = attr->alt_timeout << 3;
2316 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2317 }
2318
2319 context->pd = cpu_to_be32(pd->pdn);
2320
2321 if (!rwq_ind_tbl) {
2322 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2323 get_cqs(qp, src_type, &send_cq, &recv_cq);
2324 } else { /* Set dummy CQs to be compatible with HV and PRM */
2325 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2326 recv_cq = send_cq;
2327 }
2328 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2329 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2330
2331 /* Set "fast registration enabled" for all kernel QPs */
2332 if (!ucontext)
2333 context->params1 |= cpu_to_be32(1 << 11);
2334
2335 if (attr_mask & IB_QP_RNR_RETRY) {
2336 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2337 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2338 }
2339
2340 if (attr_mask & IB_QP_RETRY_CNT) {
2341 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2342 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2343 }
2344
2345 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2346 if (attr->max_rd_atomic)
2347 context->params1 |=
2348 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2349 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2350 }
2351
2352 if (attr_mask & IB_QP_SQ_PSN)
2353 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2354
2355 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2356 if (attr->max_dest_rd_atomic)
2357 context->params2 |=
2358 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2359 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2360 }
2361
2362 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2363 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2364 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2365 }
2366
2367 if (ibsrq)
2368 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2369
2370 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2371 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2372 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2373 }
2374 if (attr_mask & IB_QP_RQ_PSN)
2375 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2376
2377 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2378 if (attr_mask & IB_QP_QKEY) {
2379 if (qp->mlx4_ib_qp_type &
2380 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2381 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2382 else {
2383 if (mlx4_is_mfunc(dev->dev) &&
2384 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2385 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2386 MLX4_RESERVED_QKEY_BASE) {
2387 pr_err("Cannot use reserved QKEY"
2388 " 0x%x (range 0xffff0000..0xffffffff"
2389 " is reserved)\n", attr->qkey);
2390 err = -EINVAL;
2391 goto out;
2392 }
2393 context->qkey = cpu_to_be32(attr->qkey);
2394 }
2395 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2396 }
2397
2398 if (ibsrq)
2399 context->srqn = cpu_to_be32(1 << 24 |
2400 to_msrq(ibsrq)->msrq.srqn);
2401
2402 if (qp->rq.wqe_cnt &&
2403 cur_state == IB_QPS_RESET &&
2404 new_state == IB_QPS_INIT)
2405 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2406
2407 if (cur_state == IB_QPS_INIT &&
2408 new_state == IB_QPS_RTR &&
2409 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2410 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2411 context->pri_path.sched_queue = (qp->port - 1) << 6;
2412 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2413 qp->mlx4_ib_qp_type &
2414 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2415 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2416 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2417 context->pri_path.fl = 0x80;
2418 } else {
2419 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2420 context->pri_path.fl = 0x80;
2421 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2422 }
2423 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2424 IB_LINK_LAYER_ETHERNET) {
2425 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2426 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2427 context->pri_path.feup = 1 << 7; /* don't fsm */
2428 /* handle smac_index */
2429 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2430 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2431 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2432 err = handle_eth_ud_smac_index(dev, qp, context);
2433 if (err) {
2434 err = -EINVAL;
2435 goto out;
2436 }
2437 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2438 dev->qp1_proxy[qp->port - 1] = qp;
2439 }
2440 }
2441 }
2442
2443 if (qp_type == IB_QPT_RAW_PACKET) {
2444 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2445 MLX4_IB_LINK_TYPE_ETH;
2446 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2447 /* set QP to receive both tunneled & non-tunneled packets */
2448 if (!rwq_ind_tbl)
2449 context->srqn = cpu_to_be32(7 << 28);
2450 }
2451 }
2452
2453 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2454 int is_eth = rdma_port_get_link_layer(
2455 &dev->ib_dev, qp->port) ==
2456 IB_LINK_LAYER_ETHERNET;
2457 if (is_eth) {
2458 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2459 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2460 }
2461 }
2462
2463 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2464 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2465 sqd_event = 1;
2466 else
2467 sqd_event = 0;
2468
2469 if (!ucontext &&
2470 cur_state == IB_QPS_RESET &&
2471 new_state == IB_QPS_INIT)
2472 context->rlkey_roce_mode |= (1 << 4);
2473
2474 /*
2475 * Before passing a kernel QP to the HW, make sure that the
2476 * ownership bits of the send queue are set and the SQ
2477 * headroom is stamped so that the hardware doesn't start
2478 * processing stale work requests.
2479 */
2480 if (!ucontext &&
2481 cur_state == IB_QPS_RESET &&
2482 new_state == IB_QPS_INIT) {
2483 struct mlx4_wqe_ctrl_seg *ctrl;
2484 int i;
2485
2486 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2487 ctrl = get_send_wqe(qp, i);
2488 ctrl->owner_opcode = cpu_to_be32(1 << 31);
2489 ctrl->qpn_vlan.fence_size =
2490 1 << (qp->sq.wqe_shift - 4);
2491 stamp_send_wqe(qp, i);
2492 }
2493 }
2494
2495 if (rwq_ind_tbl &&
2496 cur_state == IB_QPS_RESET &&
2497 new_state == IB_QPS_INIT) {
2498 fill_qp_rss_context(context, qp);
2499 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2500 }
2501
2502 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2503 to_mlx4_state(new_state), context, optpar,
2504 sqd_event, &qp->mqp);
2505 if (err)
2506 goto out;
2507
2508 qp->state = new_state;
2509
2510 if (attr_mask & IB_QP_ACCESS_FLAGS)
2511 qp->atomic_rd_en = attr->qp_access_flags;
2512 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2513 qp->resp_depth = attr->max_dest_rd_atomic;
2514 if (attr_mask & IB_QP_PORT) {
2515 qp->port = attr->port_num;
2516 update_mcg_macs(dev, qp);
2517 }
2518 if (attr_mask & IB_QP_ALT_PATH)
2519 qp->alt_port = attr->alt_port_num;
2520
2521 if (is_sqp(dev, qp))
2522 store_sqp_attrs(qp->sqp, attr, attr_mask);
2523
2524 /*
2525 * If we moved QP0 to RTR, bring the IB link up; if we moved
2526 * QP0 to RESET or ERROR, bring the link back down.
2527 */
2528 if (is_qp0(dev, qp)) {
2529 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2530 if (mlx4_INIT_PORT(dev->dev, qp->port))
2531 pr_warn("INIT_PORT failed for port %d\n",
2532 qp->port);
2533
2534 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2535 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2536 mlx4_CLOSE_PORT(dev->dev, qp->port);
2537 }
2538
2539 /*
2540 * If we moved a kernel QP to RESET, clean up all old CQ
2541 * entries and reinitialize the QP.
2542 */
2543 if (new_state == IB_QPS_RESET) {
2544 if (!ucontext) {
2545 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2546 ibsrq ? to_msrq(ibsrq) : NULL);
2547 if (send_cq != recv_cq)
2548 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2549
2550 qp->rq.head = 0;
2551 qp->rq.tail = 0;
2552 qp->sq.head = 0;
2553 qp->sq.tail = 0;
2554 qp->sq_next_wqe = 0;
2555 if (qp->rq.wqe_cnt)
2556 *qp->db.db = 0;
2557
2558 if (qp->flags & MLX4_IB_QP_NETIF)
2559 mlx4_ib_steer_qp_reg(dev, qp, 0);
2560 }
2561 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2562 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2563 qp->pri.smac = 0;
2564 qp->pri.smac_port = 0;
2565 }
2566 if (qp->alt.smac) {
2567 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2568 qp->alt.smac = 0;
2569 }
2570 if (qp->pri.vid < 0x1000) {
2571 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2572 qp->pri.vid = 0xFFFF;
2573 qp->pri.candidate_vid = 0xFFFF;
2574 qp->pri.update_vid = 0;
2575 }
2576
2577 if (qp->alt.vid < 0x1000) {
2578 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2579 qp->alt.vid = 0xFFFF;
2580 qp->alt.candidate_vid = 0xFFFF;
2581 qp->alt.update_vid = 0;
2582 }
2583 }
2584 out:
2585 if (err && qp->counter_index)
2586 mlx4_ib_free_qp_counter(dev, qp);
2587 if (err && steer_qp)
2588 mlx4_ib_steer_qp_reg(dev, qp, 0);
2589 kfree(context);
2590 if (qp->pri.candidate_smac ||
2591 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2592 if (err) {
2593 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2594 } else {
2595 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2596 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2597 qp->pri.smac = qp->pri.candidate_smac;
2598 qp->pri.smac_index = qp->pri.candidate_smac_index;
2599 qp->pri.smac_port = qp->pri.candidate_smac_port;
2600 }
2601 qp->pri.candidate_smac = 0;
2602 qp->pri.candidate_smac_index = 0;
2603 qp->pri.candidate_smac_port = 0;
2604 }
2605 if (qp->alt.candidate_smac) {
2606 if (err) {
2607 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2608 } else {
2609 if (qp->alt.smac)
2610 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2611 qp->alt.smac = qp->alt.candidate_smac;
2612 qp->alt.smac_index = qp->alt.candidate_smac_index;
2613 qp->alt.smac_port = qp->alt.candidate_smac_port;
2614 }
2615 qp->alt.candidate_smac = 0;
2616 qp->alt.candidate_smac_index = 0;
2617 qp->alt.candidate_smac_port = 0;
2618 }
2619
2620 if (qp->pri.update_vid) {
2621 if (err) {
2622 if (qp->pri.candidate_vid < 0x1000)
2623 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2624 qp->pri.candidate_vid);
2625 } else {
2626 if (qp->pri.vid < 0x1000)
2627 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2628 qp->pri.vid);
2629 qp->pri.vid = qp->pri.candidate_vid;
2630 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2631 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2632 }
2633 qp->pri.candidate_vid = 0xFFFF;
2634 qp->pri.update_vid = 0;
2635 }
2636
2637 if (qp->alt.update_vid) {
2638 if (err) {
2639 if (qp->alt.candidate_vid < 0x1000)
2640 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2641 qp->alt.candidate_vid);
2642 } else {
2643 if (qp->alt.vid < 0x1000)
2644 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2645 qp->alt.vid);
2646 qp->alt.vid = qp->alt.candidate_vid;
2647 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2648 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2649 }
2650 qp->alt.candidate_vid = 0xFFFF;
2651 qp->alt.update_vid = 0;
2652 }
2653
2654 return err;
2655 }
2656
2657 enum {
2658 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2659 IB_QP_PORT),
2660 };
2661
_mlx4_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)2662 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2663 int attr_mask, struct ib_udata *udata)
2664 {
2665 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2666 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2667 enum ib_qp_state cur_state, new_state;
2668 int err = -EINVAL;
2669 mutex_lock(&qp->mutex);
2670
2671 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2672 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2673
2674 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2675 attr_mask)) {
2676 pr_debug("qpn 0x%x: invalid attribute mask specified "
2677 "for transition %d to %d. qp_type %d,"
2678 " attr_mask 0x%x\n",
2679 ibqp->qp_num, cur_state, new_state,
2680 ibqp->qp_type, attr_mask);
2681 goto out;
2682 }
2683
2684 if (ibqp->rwq_ind_tbl) {
2685 if (!(((cur_state == IB_QPS_RESET) &&
2686 (new_state == IB_QPS_INIT)) ||
2687 ((cur_state == IB_QPS_INIT) &&
2688 (new_state == IB_QPS_RTR)))) {
2689 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2690 ibqp->qp_num, cur_state, new_state);
2691
2692 err = -EOPNOTSUPP;
2693 goto out;
2694 }
2695
2696 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2697 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2698 ibqp->qp_num, attr_mask, cur_state, new_state);
2699
2700 err = -EOPNOTSUPP;
2701 goto out;
2702 }
2703 }
2704
2705 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2706 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2707 if ((ibqp->qp_type == IB_QPT_RC) ||
2708 (ibqp->qp_type == IB_QPT_UD) ||
2709 (ibqp->qp_type == IB_QPT_UC) ||
2710 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2711 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2712 attr->port_num = mlx4_ib_bond_next_port(dev);
2713 }
2714 } else {
2715 /* no sense in changing port_num
2716 * when ports are bonded */
2717 attr_mask &= ~IB_QP_PORT;
2718 }
2719 }
2720
2721 if ((attr_mask & IB_QP_PORT) &&
2722 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2723 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2724 "for transition %d to %d. qp_type %d\n",
2725 ibqp->qp_num, attr->port_num, cur_state,
2726 new_state, ibqp->qp_type);
2727 goto out;
2728 }
2729
2730 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2731 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2732 IB_LINK_LAYER_ETHERNET))
2733 goto out;
2734
2735 if (attr_mask & IB_QP_PKEY_INDEX) {
2736 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2737 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2738 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2739 "for transition %d to %d. qp_type %d\n",
2740 ibqp->qp_num, attr->pkey_index, cur_state,
2741 new_state, ibqp->qp_type);
2742 goto out;
2743 }
2744 }
2745
2746 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2747 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2748 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2749 "Transition %d to %d. qp_type %d\n",
2750 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2751 new_state, ibqp->qp_type);
2752 goto out;
2753 }
2754
2755 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2756 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2757 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2758 "Transition %d to %d. qp_type %d\n",
2759 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2760 new_state, ibqp->qp_type);
2761 goto out;
2762 }
2763
2764 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2765 err = 0;
2766 goto out;
2767 }
2768
2769 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2770 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num,
2771 udata);
2772 if (err)
2773 goto out;
2774 }
2775
2776 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2777 cur_state, new_state, udata);
2778
2779 if (ibqp->rwq_ind_tbl && err)
2780 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata);
2781
2782 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2783 attr->port_num = 1;
2784
2785 out:
2786 mutex_unlock(&qp->mutex);
2787 return err;
2788 }
2789
mlx4_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)2790 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2791 int attr_mask, struct ib_udata *udata)
2792 {
2793 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2794 int ret;
2795
2796 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2797
2798 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2799 struct mlx4_ib_sqp *sqp = mqp->sqp;
2800 int err = 0;
2801
2802 if (sqp->roce_v2_gsi)
2803 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2804 if (err)
2805 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2806 err);
2807 }
2808 return ret;
2809 }
2810
vf_get_qp0_qkey(struct mlx4_dev * dev,int qpn,u32 * qkey)2811 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2812 {
2813 int i;
2814 for (i = 0; i < dev->caps.num_ports; i++) {
2815 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2816 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2817 *qkey = dev->caps.spec_qps[i].qp0_qkey;
2818 return 0;
2819 }
2820 }
2821 return -EINVAL;
2822 }
2823
build_sriov_qp0_header(struct mlx4_ib_qp * qp,const struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)2824 static int build_sriov_qp0_header(struct mlx4_ib_qp *qp,
2825 const struct ib_ud_wr *wr,
2826 void *wqe, unsigned *mlx_seg_len)
2827 {
2828 struct mlx4_ib_dev *mdev = to_mdev(qp->ibqp.device);
2829 struct mlx4_ib_sqp *sqp = qp->sqp;
2830 struct ib_device *ib_dev = qp->ibqp.device;
2831 struct mlx4_wqe_mlx_seg *mlx = wqe;
2832 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2833 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2834 u16 pkey;
2835 u32 qkey;
2836 int send_size;
2837 int header_size;
2838 int spc;
2839 int err;
2840 int i;
2841
2842 if (wr->wr.opcode != IB_WR_SEND)
2843 return -EINVAL;
2844
2845 send_size = 0;
2846
2847 for (i = 0; i < wr->wr.num_sge; ++i)
2848 send_size += wr->wr.sg_list[i].length;
2849
2850 /* for proxy-qp0 sends, need to add in size of tunnel header */
2851 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2852 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2853 send_size += sizeof (struct mlx4_ib_tunnel_header);
2854
2855 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2856
2857 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2858 sqp->ud_header.lrh.service_level =
2859 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2860 sqp->ud_header.lrh.destination_lid =
2861 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2862 sqp->ud_header.lrh.source_lid =
2863 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2864 }
2865
2866 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2867
2868 /* force loopback */
2869 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2870 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2871
2872 sqp->ud_header.lrh.virtual_lane = 0;
2873 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2874 err = ib_get_cached_pkey(ib_dev, qp->port, 0, &pkey);
2875 if (err)
2876 return err;
2877 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2878 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2879 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2880 else
2881 sqp->ud_header.bth.destination_qpn =
2882 cpu_to_be32(mdev->dev->caps.spec_qps[qp->port - 1].qp0_tunnel);
2883
2884 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2885 if (mlx4_is_master(mdev->dev)) {
2886 if (mlx4_get_parav_qkey(mdev->dev, qp->mqp.qpn, &qkey))
2887 return -EINVAL;
2888 } else {
2889 if (vf_get_qp0_qkey(mdev->dev, qp->mqp.qpn, &qkey))
2890 return -EINVAL;
2891 }
2892 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2893 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->mqp.qpn);
2894
2895 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2896 sqp->ud_header.immediate_present = 0;
2897
2898 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2899
2900 /*
2901 * Inline data segments may not cross a 64 byte boundary. If
2902 * our UD header is bigger than the space available up to the
2903 * next 64 byte boundary in the WQE, use two inline data
2904 * segments to hold the UD header.
2905 */
2906 spc = MLX4_INLINE_ALIGN -
2907 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2908 if (header_size <= spc) {
2909 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2910 memcpy(inl + 1, sqp->header_buf, header_size);
2911 i = 1;
2912 } else {
2913 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2914 memcpy(inl + 1, sqp->header_buf, spc);
2915
2916 inl = (void *) (inl + 1) + spc;
2917 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2918 /*
2919 * Need a barrier here to make sure all the data is
2920 * visible before the byte_count field is set.
2921 * Otherwise the HCA prefetcher could grab the 64-byte
2922 * chunk with this inline segment and get a valid (!=
2923 * 0xffffffff) byte count but stale data, and end up
2924 * generating a packet with bad headers.
2925 *
2926 * The first inline segment's byte_count field doesn't
2927 * need a barrier, because it comes after a
2928 * control/MLX segment and therefore is at an offset
2929 * of 16 mod 64.
2930 */
2931 wmb();
2932 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2933 i = 2;
2934 }
2935
2936 *mlx_seg_len =
2937 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2938 return 0;
2939 }
2940
sl_to_vl(struct mlx4_ib_dev * dev,u8 sl,int port_num)2941 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2942 {
2943 union sl2vl_tbl_to_u64 tmp_vltab;
2944 u8 vl;
2945
2946 if (sl > 15)
2947 return 0xf;
2948 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2949 vl = tmp_vltab.sl8[sl >> 1];
2950 if (sl & 1)
2951 vl &= 0x0f;
2952 else
2953 vl >>= 4;
2954 return vl;
2955 }
2956
fill_gid_by_hw_index(struct mlx4_ib_dev * ibdev,u8 port_num,int index,union ib_gid * gid,enum ib_gid_type * gid_type)2957 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2958 int index, union ib_gid *gid,
2959 enum ib_gid_type *gid_type)
2960 {
2961 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2962 struct mlx4_port_gid_table *port_gid_table;
2963 unsigned long flags;
2964
2965 port_gid_table = &iboe->gids[port_num - 1];
2966 spin_lock_irqsave(&iboe->lock, flags);
2967 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2968 *gid_type = port_gid_table->gids[index].gid_type;
2969 spin_unlock_irqrestore(&iboe->lock, flags);
2970 if (rdma_is_zero_gid(gid))
2971 return -ENOENT;
2972
2973 return 0;
2974 }
2975
2976 #define MLX4_ROCEV2_QP1_SPORT 0xC000
build_mlx_header(struct mlx4_ib_qp * qp,const struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)2977 static int build_mlx_header(struct mlx4_ib_qp *qp, const struct ib_ud_wr *wr,
2978 void *wqe, unsigned *mlx_seg_len)
2979 {
2980 struct mlx4_ib_sqp *sqp = qp->sqp;
2981 struct ib_device *ib_dev = qp->ibqp.device;
2982 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
2983 struct mlx4_wqe_mlx_seg *mlx = wqe;
2984 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2985 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2986 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2987 union ib_gid sgid;
2988 u16 pkey;
2989 int send_size;
2990 int header_size;
2991 int spc;
2992 int i;
2993 int err = 0;
2994 u16 vlan = 0xffff;
2995 bool is_eth;
2996 bool is_vlan = false;
2997 bool is_grh;
2998 bool is_udp = false;
2999 int ip_version = 0;
3000
3001 send_size = 0;
3002 for (i = 0; i < wr->wr.num_sge; ++i)
3003 send_size += wr->wr.sg_list[i].length;
3004
3005 is_eth = rdma_port_get_link_layer(qp->ibqp.device, qp->port) == IB_LINK_LAYER_ETHERNET;
3006 is_grh = mlx4_ib_ah_grh_present(ah);
3007 if (is_eth) {
3008 enum ib_gid_type gid_type;
3009 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3010 /* When multi-function is enabled, the ib_core gid
3011 * indexes don't necessarily match the hw ones, so
3012 * we must use our own cache */
3013 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3014 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3015 ah->av.ib.gid_index, &sgid.raw[0]);
3016 if (err)
3017 return err;
3018 } else {
3019 err = fill_gid_by_hw_index(ibdev, qp->port,
3020 ah->av.ib.gid_index, &sgid,
3021 &gid_type);
3022 if (!err) {
3023 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3024 if (is_udp) {
3025 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3026 ip_version = 4;
3027 else
3028 ip_version = 6;
3029 is_grh = false;
3030 }
3031 } else {
3032 return err;
3033 }
3034 }
3035 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3036 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3037 is_vlan = true;
3038 }
3039 }
3040 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3041 ip_version, is_udp, 0, &sqp->ud_header);
3042 if (err)
3043 return err;
3044
3045 if (!is_eth) {
3046 sqp->ud_header.lrh.service_level =
3047 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3048 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3049 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3050 }
3051
3052 if (is_grh || (ip_version == 6)) {
3053 sqp->ud_header.grh.traffic_class =
3054 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3055 sqp->ud_header.grh.flow_label =
3056 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3057 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
3058 if (is_eth) {
3059 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3060 } else {
3061 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3062 /* When multi-function is enabled, the ib_core gid
3063 * indexes don't necessarily match the hw ones, so
3064 * we must use our own cache
3065 */
3066 sqp->ud_header.grh.source_gid.global
3067 .subnet_prefix =
3068 cpu_to_be64(atomic64_read(
3069 &(to_mdev(ib_dev)
3070 ->sriov
3071 .demux[qp->port - 1]
3072 .subnet_prefix)));
3073 sqp->ud_header.grh.source_gid.global
3074 .interface_id =
3075 to_mdev(ib_dev)
3076 ->sriov.demux[qp->port - 1]
3077 .guid_cache[ah->av.ib.gid_index];
3078 } else {
3079 sqp->ud_header.grh.source_gid =
3080 ah->ibah.sgid_attr->gid;
3081 }
3082 }
3083 memcpy(sqp->ud_header.grh.destination_gid.raw,
3084 ah->av.ib.dgid, 16);
3085 }
3086
3087 if (ip_version == 4) {
3088 sqp->ud_header.ip4.tos =
3089 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3090 sqp->ud_header.ip4.id = 0;
3091 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3092 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3093
3094 memcpy(&sqp->ud_header.ip4.saddr,
3095 sgid.raw + 12, 4);
3096 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3097 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3098 }
3099
3100 if (is_udp) {
3101 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3102 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3103 sqp->ud_header.udp.csum = 0;
3104 }
3105
3106 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3107
3108 if (!is_eth) {
3109 mlx->flags |=
3110 cpu_to_be32((!qp->ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3111 (sqp->ud_header.lrh.destination_lid ==
3112 IB_LID_PERMISSIVE ?
3113 MLX4_WQE_MLX_SLR :
3114 0) |
3115 (sqp->ud_header.lrh.service_level << 8));
3116 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3117 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3118 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3119 }
3120
3121 switch (wr->wr.opcode) {
3122 case IB_WR_SEND:
3123 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3124 sqp->ud_header.immediate_present = 0;
3125 break;
3126 case IB_WR_SEND_WITH_IMM:
3127 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3128 sqp->ud_header.immediate_present = 1;
3129 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
3130 break;
3131 default:
3132 return -EINVAL;
3133 }
3134
3135 if (is_eth) {
3136 struct in6_addr in6;
3137 u16 ether_type;
3138 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3139
3140 ether_type = (!is_udp) ? ETH_P_IBOE:
3141 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3142
3143 mlx->sched_prio = cpu_to_be16(pcp);
3144
3145 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3146 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
3147 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3148 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3149 memcpy(&in6, sgid.raw, sizeof(in6));
3150
3151
3152 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3153 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3154 if (!is_vlan) {
3155 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3156 } else {
3157 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3158 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3159 }
3160 } else {
3161 sqp->ud_header.lrh.virtual_lane =
3162 !qp->ibqp.qp_num ?
3163 15 :
3164 sl_to_vl(to_mdev(ib_dev),
3165 sqp->ud_header.lrh.service_level,
3166 qp->port);
3167 if (qp->ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3168 return -EINVAL;
3169 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3170 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3171 }
3172 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3173 if (!qp->ibqp.qp_num)
3174 err = ib_get_cached_pkey(ib_dev, qp->port, sqp->pkey_index,
3175 &pkey);
3176 else
3177 err = ib_get_cached_pkey(ib_dev, qp->port, wr->pkey_index,
3178 &pkey);
3179 if (err)
3180 return err;
3181
3182 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3183 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3184 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3185 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3186 sqp->qkey : wr->remote_qkey);
3187 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->ibqp.qp_num);
3188
3189 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3190
3191 if (0) {
3192 pr_err("built UD header of size %d:\n", header_size);
3193 for (i = 0; i < header_size / 4; ++i) {
3194 if (i % 8 == 0)
3195 pr_err(" [%02x] ", i * 4);
3196 pr_cont(" %08x",
3197 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3198 if ((i + 1) % 8 == 0)
3199 pr_cont("\n");
3200 }
3201 pr_err("\n");
3202 }
3203
3204 /*
3205 * Inline data segments may not cross a 64 byte boundary. If
3206 * our UD header is bigger than the space available up to the
3207 * next 64 byte boundary in the WQE, use two inline data
3208 * segments to hold the UD header.
3209 */
3210 spc = MLX4_INLINE_ALIGN -
3211 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3212 if (header_size <= spc) {
3213 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3214 memcpy(inl + 1, sqp->header_buf, header_size);
3215 i = 1;
3216 } else {
3217 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3218 memcpy(inl + 1, sqp->header_buf, spc);
3219
3220 inl = (void *) (inl + 1) + spc;
3221 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3222 /*
3223 * Need a barrier here to make sure all the data is
3224 * visible before the byte_count field is set.
3225 * Otherwise the HCA prefetcher could grab the 64-byte
3226 * chunk with this inline segment and get a valid (!=
3227 * 0xffffffff) byte count but stale data, and end up
3228 * generating a packet with bad headers.
3229 *
3230 * The first inline segment's byte_count field doesn't
3231 * need a barrier, because it comes after a
3232 * control/MLX segment and therefore is at an offset
3233 * of 16 mod 64.
3234 */
3235 wmb();
3236 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3237 i = 2;
3238 }
3239
3240 *mlx_seg_len =
3241 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3242 return 0;
3243 }
3244
mlx4_wq_overflow(struct mlx4_ib_wq * wq,int nreq,struct ib_cq * ib_cq)3245 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3246 {
3247 unsigned cur;
3248 struct mlx4_ib_cq *cq;
3249
3250 cur = wq->head - wq->tail;
3251 if (likely(cur + nreq < wq->max_post))
3252 return 0;
3253
3254 cq = to_mcq(ib_cq);
3255 spin_lock(&cq->lock);
3256 cur = wq->head - wq->tail;
3257 spin_unlock(&cq->lock);
3258
3259 return cur + nreq >= wq->max_post;
3260 }
3261
convert_access(int acc)3262 static __be32 convert_access(int acc)
3263 {
3264 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3265 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3266 (acc & IB_ACCESS_REMOTE_WRITE ?
3267 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3268 (acc & IB_ACCESS_REMOTE_READ ?
3269 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
3270 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3271 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3272 }
3273
set_reg_seg(struct mlx4_wqe_fmr_seg * fseg,const struct ib_reg_wr * wr)3274 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3275 const struct ib_reg_wr *wr)
3276 {
3277 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3278
3279 fseg->flags = convert_access(wr->access);
3280 fseg->mem_key = cpu_to_be32(wr->key);
3281 fseg->buf_list = cpu_to_be64(mr->page_map);
3282 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3283 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3284 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3285 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3286 fseg->reserved[0] = 0;
3287 fseg->reserved[1] = 0;
3288 }
3289
set_local_inv_seg(struct mlx4_wqe_local_inval_seg * iseg,u32 rkey)3290 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3291 {
3292 memset(iseg, 0, sizeof(*iseg));
3293 iseg->mem_key = cpu_to_be32(rkey);
3294 }
3295
set_raddr_seg(struct mlx4_wqe_raddr_seg * rseg,u64 remote_addr,u32 rkey)3296 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3297 u64 remote_addr, u32 rkey)
3298 {
3299 rseg->raddr = cpu_to_be64(remote_addr);
3300 rseg->rkey = cpu_to_be32(rkey);
3301 rseg->reserved = 0;
3302 }
3303
set_atomic_seg(struct mlx4_wqe_atomic_seg * aseg,const struct ib_atomic_wr * wr)3304 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3305 const struct ib_atomic_wr *wr)
3306 {
3307 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3308 aseg->swap_add = cpu_to_be64(wr->swap);
3309 aseg->compare = cpu_to_be64(wr->compare_add);
3310 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3311 aseg->swap_add = cpu_to_be64(wr->compare_add);
3312 aseg->compare = cpu_to_be64(wr->compare_add_mask);
3313 } else {
3314 aseg->swap_add = cpu_to_be64(wr->compare_add);
3315 aseg->compare = 0;
3316 }
3317
3318 }
3319
set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg * aseg,const struct ib_atomic_wr * wr)3320 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3321 const struct ib_atomic_wr *wr)
3322 {
3323 aseg->swap_add = cpu_to_be64(wr->swap);
3324 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3325 aseg->compare = cpu_to_be64(wr->compare_add);
3326 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
3327 }
3328
set_datagram_seg(struct mlx4_wqe_datagram_seg * dseg,const struct ib_ud_wr * wr)3329 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3330 const struct ib_ud_wr *wr)
3331 {
3332 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3333 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3334 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3335 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3336 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3337 }
3338
set_tunnel_datagram_seg(struct mlx4_ib_dev * dev,struct mlx4_wqe_datagram_seg * dseg,const struct ib_ud_wr * wr,enum mlx4_ib_qp_type qpt)3339 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3340 struct mlx4_wqe_datagram_seg *dseg,
3341 const struct ib_ud_wr *wr,
3342 enum mlx4_ib_qp_type qpt)
3343 {
3344 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3345 struct mlx4_av sqp_av = {0};
3346 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3347
3348 /* force loopback */
3349 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3350 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3351 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3352 cpu_to_be32(0xf0000000);
3353
3354 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3355 if (qpt == MLX4_IB_QPT_PROXY_GSI)
3356 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3357 else
3358 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3359 /* Use QKEY from the QP context, which is set by master */
3360 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3361 }
3362
build_tunnel_header(const struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)3363 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3364 unsigned *mlx_seg_len)
3365 {
3366 struct mlx4_wqe_inline_seg *inl = wqe;
3367 struct mlx4_ib_tunnel_header hdr;
3368 struct mlx4_ib_ah *ah = to_mah(wr->ah);
3369 int spc;
3370 int i;
3371
3372 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3373 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3374 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3375 hdr.qkey = cpu_to_be32(wr->remote_qkey);
3376 memcpy(hdr.mac, ah->av.eth.mac, 6);
3377 hdr.vlan = ah->av.eth.vlan;
3378
3379 spc = MLX4_INLINE_ALIGN -
3380 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3381 if (sizeof (hdr) <= spc) {
3382 memcpy(inl + 1, &hdr, sizeof (hdr));
3383 wmb();
3384 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3385 i = 1;
3386 } else {
3387 memcpy(inl + 1, &hdr, spc);
3388 wmb();
3389 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3390
3391 inl = (void *) (inl + 1) + spc;
3392 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3393 wmb();
3394 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3395 i = 2;
3396 }
3397
3398 *mlx_seg_len =
3399 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3400 }
3401
set_mlx_icrc_seg(void * dseg)3402 static void set_mlx_icrc_seg(void *dseg)
3403 {
3404 u32 *t = dseg;
3405 struct mlx4_wqe_inline_seg *iseg = dseg;
3406
3407 t[1] = 0;
3408
3409 /*
3410 * Need a barrier here before writing the byte_count field to
3411 * make sure that all the data is visible before the
3412 * byte_count field is set. Otherwise, if the segment begins
3413 * a new cacheline, the HCA prefetcher could grab the 64-byte
3414 * chunk and get a valid (!= * 0xffffffff) byte count but
3415 * stale data, and end up sending the wrong data.
3416 */
3417 wmb();
3418
3419 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3420 }
3421
set_data_seg(struct mlx4_wqe_data_seg * dseg,struct ib_sge * sg)3422 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3423 {
3424 dseg->lkey = cpu_to_be32(sg->lkey);
3425 dseg->addr = cpu_to_be64(sg->addr);
3426
3427 /*
3428 * Need a barrier here before writing the byte_count field to
3429 * make sure that all the data is visible before the
3430 * byte_count field is set. Otherwise, if the segment begins
3431 * a new cacheline, the HCA prefetcher could grab the 64-byte
3432 * chunk and get a valid (!= * 0xffffffff) byte count but
3433 * stale data, and end up sending the wrong data.
3434 */
3435 wmb();
3436
3437 dseg->byte_count = cpu_to_be32(sg->length);
3438 }
3439
__set_data_seg(struct mlx4_wqe_data_seg * dseg,struct ib_sge * sg)3440 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3441 {
3442 dseg->byte_count = cpu_to_be32(sg->length);
3443 dseg->lkey = cpu_to_be32(sg->lkey);
3444 dseg->addr = cpu_to_be64(sg->addr);
3445 }
3446
build_lso_seg(struct mlx4_wqe_lso_seg * wqe,const struct ib_ud_wr * wr,struct mlx4_ib_qp * qp,unsigned * lso_seg_len,__be32 * lso_hdr_sz,__be32 * blh)3447 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3448 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3449 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
3450 {
3451 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3452
3453 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3454 *blh = cpu_to_be32(1 << 6);
3455
3456 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3457 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3458 return -EINVAL;
3459
3460 memcpy(wqe->header, wr->header, wr->hlen);
3461
3462 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
3463 *lso_seg_len = halign;
3464 return 0;
3465 }
3466
send_ieth(const struct ib_send_wr * wr)3467 static __be32 send_ieth(const struct ib_send_wr *wr)
3468 {
3469 switch (wr->opcode) {
3470 case IB_WR_SEND_WITH_IMM:
3471 case IB_WR_RDMA_WRITE_WITH_IMM:
3472 return wr->ex.imm_data;
3473
3474 case IB_WR_SEND_WITH_INV:
3475 return cpu_to_be32(wr->ex.invalidate_rkey);
3476
3477 default:
3478 return 0;
3479 }
3480 }
3481
add_zero_len_inline(void * wqe)3482 static void add_zero_len_inline(void *wqe)
3483 {
3484 struct mlx4_wqe_inline_seg *inl = wqe;
3485 memset(wqe, 0, 16);
3486 inl->byte_count = cpu_to_be32(1 << 31);
3487 }
3488
_mlx4_ib_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr,bool drain)3489 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3490 const struct ib_send_wr **bad_wr, bool drain)
3491 {
3492 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3493 void *wqe;
3494 struct mlx4_wqe_ctrl_seg *ctrl;
3495 struct mlx4_wqe_data_seg *dseg;
3496 unsigned long flags;
3497 int nreq;
3498 int err = 0;
3499 unsigned ind;
3500 int size;
3501 unsigned seglen;
3502 __be32 dummy;
3503 __be32 *lso_wqe;
3504 __be32 lso_hdr_sz;
3505 __be32 blh;
3506 int i;
3507 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3508
3509 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3510 struct mlx4_ib_sqp *sqp = qp->sqp;
3511
3512 if (sqp->roce_v2_gsi) {
3513 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3514 enum ib_gid_type gid_type;
3515 union ib_gid gid;
3516
3517 if (!fill_gid_by_hw_index(mdev, qp->port,
3518 ah->av.ib.gid_index,
3519 &gid, &gid_type))
3520 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3521 to_mqp(sqp->roce_v2_gsi) : qp;
3522 else
3523 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3524 ah->av.ib.gid_index);
3525 }
3526 }
3527
3528 spin_lock_irqsave(&qp->sq.lock, flags);
3529 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3530 !drain) {
3531 err = -EIO;
3532 *bad_wr = wr;
3533 nreq = 0;
3534 goto out;
3535 }
3536
3537 ind = qp->sq_next_wqe;
3538
3539 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3540 lso_wqe = &dummy;
3541 blh = 0;
3542
3543 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3544 err = -ENOMEM;
3545 *bad_wr = wr;
3546 goto out;
3547 }
3548
3549 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3550 err = -EINVAL;
3551 *bad_wr = wr;
3552 goto out;
3553 }
3554
3555 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3556 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3557
3558 ctrl->srcrb_flags =
3559 (wr->send_flags & IB_SEND_SIGNALED ?
3560 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3561 (wr->send_flags & IB_SEND_SOLICITED ?
3562 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3563 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3564 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3565 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3566 qp->sq_signal_bits;
3567
3568 ctrl->imm = send_ieth(wr);
3569
3570 wqe += sizeof *ctrl;
3571 size = sizeof *ctrl / 16;
3572
3573 switch (qp->mlx4_ib_qp_type) {
3574 case MLX4_IB_QPT_RC:
3575 case MLX4_IB_QPT_UC:
3576 switch (wr->opcode) {
3577 case IB_WR_ATOMIC_CMP_AND_SWP:
3578 case IB_WR_ATOMIC_FETCH_AND_ADD:
3579 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3580 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3581 atomic_wr(wr)->rkey);
3582 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3583
3584 set_atomic_seg(wqe, atomic_wr(wr));
3585 wqe += sizeof (struct mlx4_wqe_atomic_seg);
3586
3587 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3588 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3589
3590 break;
3591
3592 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3593 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3594 atomic_wr(wr)->rkey);
3595 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3596
3597 set_masked_atomic_seg(wqe, atomic_wr(wr));
3598 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3599
3600 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3601 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3602
3603 break;
3604
3605 case IB_WR_RDMA_READ:
3606 case IB_WR_RDMA_WRITE:
3607 case IB_WR_RDMA_WRITE_WITH_IMM:
3608 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3609 rdma_wr(wr)->rkey);
3610 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3611 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3612 break;
3613
3614 case IB_WR_LOCAL_INV:
3615 ctrl->srcrb_flags |=
3616 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3617 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3618 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3619 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3620 break;
3621
3622 case IB_WR_REG_MR:
3623 ctrl->srcrb_flags |=
3624 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3625 set_reg_seg(wqe, reg_wr(wr));
3626 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3627 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3628 break;
3629
3630 default:
3631 /* No extra segments required for sends */
3632 break;
3633 }
3634 break;
3635
3636 case MLX4_IB_QPT_TUN_SMI_OWNER:
3637 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3638 &seglen);
3639 if (unlikely(err)) {
3640 *bad_wr = wr;
3641 goto out;
3642 }
3643 wqe += seglen;
3644 size += seglen / 16;
3645 break;
3646 case MLX4_IB_QPT_TUN_SMI:
3647 case MLX4_IB_QPT_TUN_GSI:
3648 /* this is a UD qp used in MAD responses to slaves. */
3649 set_datagram_seg(wqe, ud_wr(wr));
3650 /* set the forced-loopback bit in the data seg av */
3651 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3652 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3653 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3654 break;
3655 case MLX4_IB_QPT_UD:
3656 set_datagram_seg(wqe, ud_wr(wr));
3657 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3658 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3659
3660 if (wr->opcode == IB_WR_LSO) {
3661 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3662 &lso_hdr_sz, &blh);
3663 if (unlikely(err)) {
3664 *bad_wr = wr;
3665 goto out;
3666 }
3667 lso_wqe = (__be32 *) wqe;
3668 wqe += seglen;
3669 size += seglen / 16;
3670 }
3671 break;
3672
3673 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3674 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3675 &seglen);
3676 if (unlikely(err)) {
3677 *bad_wr = wr;
3678 goto out;
3679 }
3680 wqe += seglen;
3681 size += seglen / 16;
3682 /* to start tunnel header on a cache-line boundary */
3683 add_zero_len_inline(wqe);
3684 wqe += 16;
3685 size++;
3686 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3687 wqe += seglen;
3688 size += seglen / 16;
3689 break;
3690 case MLX4_IB_QPT_PROXY_SMI:
3691 case MLX4_IB_QPT_PROXY_GSI:
3692 /* If we are tunneling special qps, this is a UD qp.
3693 * In this case we first add a UD segment targeting
3694 * the tunnel qp, and then add a header with address
3695 * information */
3696 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3697 ud_wr(wr),
3698 qp->mlx4_ib_qp_type);
3699 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3700 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3701 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3702 wqe += seglen;
3703 size += seglen / 16;
3704 break;
3705
3706 case MLX4_IB_QPT_SMI:
3707 case MLX4_IB_QPT_GSI:
3708 err = build_mlx_header(qp, ud_wr(wr), ctrl, &seglen);
3709 if (unlikely(err)) {
3710 *bad_wr = wr;
3711 goto out;
3712 }
3713 wqe += seglen;
3714 size += seglen / 16;
3715 break;
3716
3717 default:
3718 break;
3719 }
3720
3721 /*
3722 * Write data segments in reverse order, so as to
3723 * overwrite cacheline stamp last within each
3724 * cacheline. This avoids issues with WQE
3725 * prefetching.
3726 */
3727
3728 dseg = wqe;
3729 dseg += wr->num_sge - 1;
3730 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3731
3732 /* Add one more inline data segment for ICRC for MLX sends */
3733 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3734 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3735 qp->mlx4_ib_qp_type &
3736 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3737 set_mlx_icrc_seg(dseg + 1);
3738 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3739 }
3740
3741 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3742 set_data_seg(dseg, wr->sg_list + i);
3743
3744 /*
3745 * Possibly overwrite stamping in cacheline with LSO
3746 * segment only after making sure all data segments
3747 * are written.
3748 */
3749 wmb();
3750 *lso_wqe = lso_hdr_sz;
3751
3752 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3753 MLX4_WQE_CTRL_FENCE : 0) | size;
3754
3755 /*
3756 * Make sure descriptor is fully written before
3757 * setting ownership bit (because HW can start
3758 * executing as soon as we do).
3759 */
3760 wmb();
3761
3762 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3763 *bad_wr = wr;
3764 err = -EINVAL;
3765 goto out;
3766 }
3767
3768 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3769 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3770
3771 /*
3772 * We can improve latency by not stamping the last
3773 * send queue WQE until after ringing the doorbell, so
3774 * only stamp here if there are still more WQEs to post.
3775 */
3776 if (wr->next)
3777 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3778 ind++;
3779 }
3780
3781 out:
3782 if (likely(nreq)) {
3783 qp->sq.head += nreq;
3784
3785 /*
3786 * Make sure that descriptors are written before
3787 * doorbell record.
3788 */
3789 wmb();
3790
3791 writel_relaxed(qp->doorbell_qpn,
3792 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3793
3794 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
3795
3796 qp->sq_next_wqe = ind;
3797 }
3798
3799 spin_unlock_irqrestore(&qp->sq.lock, flags);
3800
3801 return err;
3802 }
3803
mlx4_ib_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)3804 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3805 const struct ib_send_wr **bad_wr)
3806 {
3807 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3808 }
3809
_mlx4_ib_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr,bool drain)3810 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3811 const struct ib_recv_wr **bad_wr, bool drain)
3812 {
3813 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3814 struct mlx4_wqe_data_seg *scat;
3815 unsigned long flags;
3816 int err = 0;
3817 int nreq;
3818 int ind;
3819 int max_gs;
3820 int i;
3821 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3822
3823 max_gs = qp->rq.max_gs;
3824 spin_lock_irqsave(&qp->rq.lock, flags);
3825
3826 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3827 !drain) {
3828 err = -EIO;
3829 *bad_wr = wr;
3830 nreq = 0;
3831 goto out;
3832 }
3833
3834 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3835
3836 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3837 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3838 err = -ENOMEM;
3839 *bad_wr = wr;
3840 goto out;
3841 }
3842
3843 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3844 err = -EINVAL;
3845 *bad_wr = wr;
3846 goto out;
3847 }
3848
3849 scat = get_recv_wqe(qp, ind);
3850
3851 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3852 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3853 ib_dma_sync_single_for_device(ibqp->device,
3854 qp->sqp_proxy_rcv[ind].map,
3855 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3856 DMA_FROM_DEVICE);
3857 scat->byte_count =
3858 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3859 /* use dma lkey from upper layer entry */
3860 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3861 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3862 scat++;
3863 max_gs--;
3864 }
3865
3866 for (i = 0; i < wr->num_sge; ++i)
3867 __set_data_seg(scat + i, wr->sg_list + i);
3868
3869 if (i < max_gs) {
3870 scat[i].byte_count = 0;
3871 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3872 scat[i].addr = 0;
3873 }
3874
3875 qp->rq.wrid[ind] = wr->wr_id;
3876
3877 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3878 }
3879
3880 out:
3881 if (likely(nreq)) {
3882 qp->rq.head += nreq;
3883
3884 /*
3885 * Make sure that descriptors are written before
3886 * doorbell record.
3887 */
3888 wmb();
3889
3890 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3891 }
3892
3893 spin_unlock_irqrestore(&qp->rq.lock, flags);
3894
3895 return err;
3896 }
3897
mlx4_ib_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)3898 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3899 const struct ib_recv_wr **bad_wr)
3900 {
3901 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3902 }
3903
to_ib_qp_state(enum mlx4_qp_state mlx4_state)3904 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3905 {
3906 switch (mlx4_state) {
3907 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3908 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3909 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3910 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3911 case MLX4_QP_STATE_SQ_DRAINING:
3912 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3913 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3914 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3915 default: return -1;
3916 }
3917 }
3918
to_ib_mig_state(int mlx4_mig_state)3919 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3920 {
3921 switch (mlx4_mig_state) {
3922 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3923 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3924 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3925 default: return -1;
3926 }
3927 }
3928
to_ib_qp_access_flags(int mlx4_flags)3929 static int to_ib_qp_access_flags(int mlx4_flags)
3930 {
3931 int ib_flags = 0;
3932
3933 if (mlx4_flags & MLX4_QP_BIT_RRE)
3934 ib_flags |= IB_ACCESS_REMOTE_READ;
3935 if (mlx4_flags & MLX4_QP_BIT_RWE)
3936 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3937 if (mlx4_flags & MLX4_QP_BIT_RAE)
3938 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3939
3940 return ib_flags;
3941 }
3942
to_rdma_ah_attr(struct mlx4_ib_dev * ibdev,struct rdma_ah_attr * ah_attr,struct mlx4_qp_path * path)3943 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
3944 struct rdma_ah_attr *ah_attr,
3945 struct mlx4_qp_path *path)
3946 {
3947 struct mlx4_dev *dev = ibdev->dev;
3948 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
3949
3950 memset(ah_attr, 0, sizeof(*ah_attr));
3951 if (port_num == 0 || port_num > dev->caps.num_ports)
3952 return;
3953 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
3954
3955 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
3956 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3957 ((path->sched_queue & 4) << 1));
3958 else
3959 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
3960 rdma_ah_set_port_num(ah_attr, port_num);
3961
3962 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3963 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3964 rdma_ah_set_static_rate(ah_attr,
3965 path->static_rate ? path->static_rate - 5 : 0);
3966 if (path->grh_mylmc & (1 << 7)) {
3967 rdma_ah_set_grh(ah_attr, NULL,
3968 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3969 path->mgid_index,
3970 path->hop_limit,
3971 (be32_to_cpu(path->tclass_flowlabel)
3972 >> 20) & 0xff);
3973 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
3974 }
3975 }
3976
mlx4_ib_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3977 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3978 struct ib_qp_init_attr *qp_init_attr)
3979 {
3980 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3981 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3982 struct mlx4_qp_context context;
3983 int mlx4_state;
3984 int err = 0;
3985
3986 if (ibqp->rwq_ind_tbl)
3987 return -EOPNOTSUPP;
3988
3989 mutex_lock(&qp->mutex);
3990
3991 if (qp->state == IB_QPS_RESET) {
3992 qp_attr->qp_state = IB_QPS_RESET;
3993 goto done;
3994 }
3995
3996 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3997 if (err) {
3998 err = -EINVAL;
3999 goto out;
4000 }
4001
4002 mlx4_state = be32_to_cpu(context.flags) >> 28;
4003
4004 qp->state = to_ib_qp_state(mlx4_state);
4005 qp_attr->qp_state = qp->state;
4006 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4007 qp_attr->path_mig_state =
4008 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4009 qp_attr->qkey = be32_to_cpu(context.qkey);
4010 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4011 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4012 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4013 qp_attr->qp_access_flags =
4014 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4015
4016 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4017 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4018 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
4019 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
4020 qp_attr->alt_port_num =
4021 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4022 }
4023
4024 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
4025 if (qp_attr->qp_state == IB_QPS_INIT)
4026 qp_attr->port_num = qp->port;
4027 else
4028 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
4029
4030 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4031 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4032
4033 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4034
4035 qp_attr->max_dest_rd_atomic =
4036 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4037 qp_attr->min_rnr_timer =
4038 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4039 qp_attr->timeout = context.pri_path.ackto >> 3;
4040 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4041 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4042 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4043
4044 done:
4045 qp_attr->cur_qp_state = qp_attr->qp_state;
4046 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4047 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4048
4049 if (!ibqp->uobject) {
4050 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4051 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4052 } else {
4053 qp_attr->cap.max_send_wr = 0;
4054 qp_attr->cap.max_send_sge = 0;
4055 }
4056
4057 /*
4058 * We don't support inline sends for kernel QPs (yet), and we
4059 * don't know what userspace's value should be.
4060 */
4061 qp_attr->cap.max_inline_data = 0;
4062
4063 qp_init_attr->cap = qp_attr->cap;
4064
4065 qp_init_attr->create_flags = 0;
4066 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4067 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4068
4069 if (qp->flags & MLX4_IB_QP_LSO)
4070 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4071
4072 if (qp->flags & MLX4_IB_QP_NETIF)
4073 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4074
4075 qp_init_attr->sq_sig_type =
4076 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4077 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4078
4079 out:
4080 mutex_unlock(&qp->mutex);
4081 return err;
4082 }
4083
mlx4_ib_create_wq(struct ib_pd * pd,struct ib_wq_init_attr * init_attr,struct ib_udata * udata)4084 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4085 struct ib_wq_init_attr *init_attr,
4086 struct ib_udata *udata)
4087 {
4088 struct mlx4_dev *dev = to_mdev(pd->device)->dev;
4089 struct ib_qp_init_attr ib_qp_init_attr = {};
4090 struct mlx4_ib_qp *qp;
4091 struct mlx4_ib_create_wq ucmd;
4092 int err, required_cmd_sz;
4093
4094 if (!udata)
4095 return ERR_PTR(-EINVAL);
4096
4097 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4098 sizeof(ucmd.comp_mask);
4099 if (udata->inlen < required_cmd_sz) {
4100 pr_debug("invalid inlen\n");
4101 return ERR_PTR(-EINVAL);
4102 }
4103
4104 if (udata->inlen > sizeof(ucmd) &&
4105 !ib_is_udata_cleared(udata, sizeof(ucmd),
4106 udata->inlen - sizeof(ucmd))) {
4107 pr_debug("inlen is not supported\n");
4108 return ERR_PTR(-EOPNOTSUPP);
4109 }
4110
4111 if (udata->outlen)
4112 return ERR_PTR(-EOPNOTSUPP);
4113
4114 if (init_attr->wq_type != IB_WQT_RQ) {
4115 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4116 return ERR_PTR(-EOPNOTSUPP);
4117 }
4118
4119 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS ||
4120 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
4121 pr_debug("unsupported create_flags %u\n",
4122 init_attr->create_flags);
4123 return ERR_PTR(-EOPNOTSUPP);
4124 }
4125
4126 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4127 if (!qp)
4128 return ERR_PTR(-ENOMEM);
4129
4130 mutex_init(&qp->mutex);
4131 qp->pri.vid = 0xFFFF;
4132 qp->alt.vid = 0xFFFF;
4133
4134 ib_qp_init_attr.qp_context = init_attr->wq_context;
4135 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4136 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4137 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4138 ib_qp_init_attr.recv_cq = init_attr->cq;
4139 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4140
4141 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4142 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4143
4144 err = create_rq(pd, &ib_qp_init_attr, udata, qp);
4145 if (err) {
4146 kfree(qp);
4147 return ERR_PTR(err);
4148 }
4149
4150 qp->ibwq.event_handler = init_attr->event_handler;
4151 qp->ibwq.wq_num = qp->mqp.qpn;
4152 qp->ibwq.state = IB_WQS_RESET;
4153
4154 return &qp->ibwq;
4155 }
4156
ib_wq2qp_state(enum ib_wq_state state)4157 static int ib_wq2qp_state(enum ib_wq_state state)
4158 {
4159 switch (state) {
4160 case IB_WQS_RESET:
4161 return IB_QPS_RESET;
4162 case IB_WQS_RDY:
4163 return IB_QPS_RTR;
4164 default:
4165 return IB_QPS_ERR;
4166 }
4167 }
4168
_mlx4_ib_modify_wq(struct ib_wq * ibwq,enum ib_wq_state new_state,struct ib_udata * udata)4169 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
4170 struct ib_udata *udata)
4171 {
4172 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4173 enum ib_qp_state qp_cur_state;
4174 enum ib_qp_state qp_new_state;
4175 int attr_mask;
4176 int err;
4177
4178 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4179 * the WQ logic state.
4180 */
4181 qp_cur_state = qp->state;
4182 qp_new_state = ib_wq2qp_state(new_state);
4183
4184 if (ib_wq2qp_state(new_state) == qp_cur_state)
4185 return 0;
4186
4187 if (new_state == IB_WQS_RDY) {
4188 struct ib_qp_attr attr = {};
4189
4190 attr.port_num = qp->port;
4191 attr_mask = IB_QP_PORT;
4192
4193 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4194 attr_mask, IB_QPS_RESET, IB_QPS_INIT,
4195 udata);
4196 if (err) {
4197 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4198 ibwq->wq_num);
4199 return err;
4200 }
4201
4202 qp_cur_state = IB_QPS_INIT;
4203 }
4204
4205 attr_mask = 0;
4206 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4207 qp_cur_state, qp_new_state, udata);
4208
4209 if (err && (qp_cur_state == IB_QPS_INIT)) {
4210 qp_new_state = IB_QPS_RESET;
4211 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4212 attr_mask, IB_QPS_INIT, IB_QPS_RESET,
4213 udata)) {
4214 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4215 ibwq->wq_num);
4216 qp_new_state = IB_QPS_INIT;
4217 }
4218 }
4219
4220 qp->state = qp_new_state;
4221
4222 return err;
4223 }
4224
mlx4_ib_modify_wq(struct ib_wq * ibwq,struct ib_wq_attr * wq_attr,u32 wq_attr_mask,struct ib_udata * udata)4225 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4226 u32 wq_attr_mask, struct ib_udata *udata)
4227 {
4228 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4229 struct mlx4_ib_modify_wq ucmd = {};
4230 size_t required_cmd_sz;
4231 enum ib_wq_state cur_state, new_state;
4232 int err = 0;
4233
4234 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4235 sizeof(ucmd.reserved);
4236 if (udata->inlen < required_cmd_sz)
4237 return -EINVAL;
4238
4239 if (udata->inlen > sizeof(ucmd) &&
4240 !ib_is_udata_cleared(udata, sizeof(ucmd),
4241 udata->inlen - sizeof(ucmd)))
4242 return -EOPNOTSUPP;
4243
4244 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4245 return -EFAULT;
4246
4247 if (ucmd.comp_mask || ucmd.reserved)
4248 return -EOPNOTSUPP;
4249
4250 if (wq_attr_mask & IB_WQ_FLAGS)
4251 return -EOPNOTSUPP;
4252
4253 cur_state = wq_attr->curr_wq_state;
4254 new_state = wq_attr->wq_state;
4255
4256 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4257 return -EINVAL;
4258
4259 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4260 return -EINVAL;
4261
4262 /* Need to protect against the parent RSS which also may modify WQ
4263 * state.
4264 */
4265 mutex_lock(&qp->mutex);
4266
4267 /* Can update HW state only if a RSS QP has already associated to this
4268 * WQ, so we can apply its port on the WQ.
4269 */
4270 if (qp->rss_usecnt)
4271 err = _mlx4_ib_modify_wq(ibwq, new_state, udata);
4272
4273 if (!err)
4274 ibwq->state = new_state;
4275
4276 mutex_unlock(&qp->mutex);
4277
4278 return err;
4279 }
4280
mlx4_ib_destroy_wq(struct ib_wq * ibwq,struct ib_udata * udata)4281 int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata)
4282 {
4283 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4284 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4285
4286 if (qp->counter_index)
4287 mlx4_ib_free_qp_counter(dev, qp);
4288
4289 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata);
4290
4291 kfree(qp);
4292 return 0;
4293 }
4294
mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table * rwq_ind_table,struct ib_rwq_ind_table_init_attr * init_attr,struct ib_udata * udata)4295 int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table,
4296 struct ib_rwq_ind_table_init_attr *init_attr,
4297 struct ib_udata *udata)
4298 {
4299 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4300 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4301 struct ib_device *device = rwq_ind_table->device;
4302 unsigned int base_wqn;
4303 size_t min_resp_len;
4304 int i, err = 0;
4305
4306 if (udata->inlen > 0 &&
4307 !ib_is_udata_cleared(udata, 0,
4308 udata->inlen))
4309 return -EOPNOTSUPP;
4310
4311 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4312 if (udata->outlen && udata->outlen < min_resp_len)
4313 return -EINVAL;
4314
4315 if (ind_tbl_size >
4316 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4317 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4318 ind_tbl_size,
4319 device->attrs.rss_caps.max_rwq_indirection_table_size);
4320 return -EINVAL;
4321 }
4322
4323 base_wqn = init_attr->ind_tbl[0]->wq_num;
4324
4325 if (base_wqn % ind_tbl_size) {
4326 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4327 base_wqn);
4328 return -EINVAL;
4329 }
4330
4331 for (i = 1; i < ind_tbl_size; i++) {
4332 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4333 pr_debug("indirection table's WQNs aren't consecutive\n");
4334 return -EINVAL;
4335 }
4336 }
4337
4338 if (udata->outlen) {
4339 resp.response_length = offsetof(typeof(resp), response_length) +
4340 sizeof(resp.response_length);
4341 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4342 }
4343
4344 return err;
4345 }
4346
4347 struct mlx4_ib_drain_cqe {
4348 struct ib_cqe cqe;
4349 struct completion done;
4350 };
4351
mlx4_ib_drain_qp_done(struct ib_cq * cq,struct ib_wc * wc)4352 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4353 {
4354 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4355 struct mlx4_ib_drain_cqe,
4356 cqe);
4357
4358 complete(&cqe->done);
4359 }
4360
4361 /* This function returns only once the drained WR was completed */
handle_drain_completion(struct ib_cq * cq,struct mlx4_ib_drain_cqe * sdrain,struct mlx4_ib_dev * dev)4362 static void handle_drain_completion(struct ib_cq *cq,
4363 struct mlx4_ib_drain_cqe *sdrain,
4364 struct mlx4_ib_dev *dev)
4365 {
4366 struct mlx4_dev *mdev = dev->dev;
4367
4368 if (cq->poll_ctx == IB_POLL_DIRECT) {
4369 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4370 ib_process_cq_direct(cq, -1);
4371 return;
4372 }
4373
4374 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4375 struct mlx4_ib_cq *mcq = to_mcq(cq);
4376 bool triggered = false;
4377 unsigned long flags;
4378
4379 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4380 /* Make sure that the CQ handler won't run if wasn't run yet */
4381 if (!mcq->mcq.reset_notify_added)
4382 mcq->mcq.reset_notify_added = 1;
4383 else
4384 triggered = true;
4385 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4386
4387 if (triggered) {
4388 /* Wait for any scheduled/running task to be ended */
4389 switch (cq->poll_ctx) {
4390 case IB_POLL_SOFTIRQ:
4391 irq_poll_disable(&cq->iop);
4392 irq_poll_enable(&cq->iop);
4393 break;
4394 case IB_POLL_WORKQUEUE:
4395 cancel_work_sync(&cq->work);
4396 break;
4397 default:
4398 WARN_ON_ONCE(1);
4399 }
4400 }
4401
4402 /* Run the CQ handler - this makes sure that the drain WR will
4403 * be processed if wasn't processed yet.
4404 */
4405 mcq->mcq.comp(&mcq->mcq);
4406 }
4407
4408 wait_for_completion(&sdrain->done);
4409 }
4410
mlx4_ib_drain_sq(struct ib_qp * qp)4411 void mlx4_ib_drain_sq(struct ib_qp *qp)
4412 {
4413 struct ib_cq *cq = qp->send_cq;
4414 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4415 struct mlx4_ib_drain_cqe sdrain;
4416 const struct ib_send_wr *bad_swr;
4417 struct ib_rdma_wr swr = {
4418 .wr = {
4419 .next = NULL,
4420 { .wr_cqe = &sdrain.cqe, },
4421 .opcode = IB_WR_RDMA_WRITE,
4422 },
4423 };
4424 int ret;
4425 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4426 struct mlx4_dev *mdev = dev->dev;
4427
4428 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4429 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4430 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4431 return;
4432 }
4433
4434 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4435 init_completion(&sdrain.done);
4436
4437 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4438 if (ret) {
4439 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4440 return;
4441 }
4442
4443 handle_drain_completion(cq, &sdrain, dev);
4444 }
4445
mlx4_ib_drain_rq(struct ib_qp * qp)4446 void mlx4_ib_drain_rq(struct ib_qp *qp)
4447 {
4448 struct ib_cq *cq = qp->recv_cq;
4449 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4450 struct mlx4_ib_drain_cqe rdrain;
4451 struct ib_recv_wr rwr = {};
4452 const struct ib_recv_wr *bad_rwr;
4453 int ret;
4454 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4455 struct mlx4_dev *mdev = dev->dev;
4456
4457 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4458 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4459 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4460 return;
4461 }
4462
4463 rwr.wr_cqe = &rdrain.cqe;
4464 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4465 init_completion(&rdrain.done);
4466
4467 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4468 if (ret) {
4469 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4470 return;
4471 }
4472
4473 handle_drain_completion(cq, &rdrain, dev);
4474 }
4475