1 // SPDX-License-Identifier: GPL-2.0
2 /* SuperH Ethernet device driver
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/etherdevice.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/mdio-bitbang.h>
20 #include <linux/netdevice.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_net.h>
25 #include <linux/phy.h>
26 #include <linux/cache.h>
27 #include <linux/io.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/ethtool.h>
31 #include <linux/if_vlan.h>
32 #include <linux/sh_eth.h>
33 #include <linux/of_mdio.h>
34
35 #include "sh_eth.h"
36
37 #define SH_ETH_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR| \
41 NETIF_MSG_TX_ERR)
42
43 #define SH_ETH_OFFSET_INVALID ((u16)~0)
44
45 #define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
47
48 /* use some intentionally tricky logic here to initialize the whole struct to
49 * 0xffff, but then override certain fields, requiring us to indicate that we
50 * "know" that there are overrides in this structure, and we'll need to disable
51 * that warning from W=1 builds. GCC has supported this option since 4.2.X, but
52 * the macros available to do this only define GCC 8.
53 */
54 __diag_push();
55 __diag_ignore(GCC, 8, "-Woverride-init",
56 "logic to initialize all and then override some is OK");
57 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
58 SH_ETH_OFFSET_DEFAULTS,
59
60 [EDSR] = 0x0000,
61 [EDMR] = 0x0400,
62 [EDTRR] = 0x0408,
63 [EDRRR] = 0x0410,
64 [EESR] = 0x0428,
65 [EESIPR] = 0x0430,
66 [TDLAR] = 0x0010,
67 [TDFAR] = 0x0014,
68 [TDFXR] = 0x0018,
69 [TDFFR] = 0x001c,
70 [RDLAR] = 0x0030,
71 [RDFAR] = 0x0034,
72 [RDFXR] = 0x0038,
73 [RDFFR] = 0x003c,
74 [TRSCER] = 0x0438,
75 [RMFCR] = 0x0440,
76 [TFTR] = 0x0448,
77 [FDR] = 0x0450,
78 [RMCR] = 0x0458,
79 [RPADIR] = 0x0460,
80 [FCFTR] = 0x0468,
81 [CSMR] = 0x04E4,
82
83 [ECMR] = 0x0500,
84 [ECSR] = 0x0510,
85 [ECSIPR] = 0x0518,
86 [PIR] = 0x0520,
87 [PSR] = 0x0528,
88 [PIPR] = 0x052c,
89 [RFLR] = 0x0508,
90 [APR] = 0x0554,
91 [MPR] = 0x0558,
92 [PFTCR] = 0x055c,
93 [PFRCR] = 0x0560,
94 [TPAUSER] = 0x0564,
95 [GECMR] = 0x05b0,
96 [BCULR] = 0x05b4,
97 [MAHR] = 0x05c0,
98 [MALR] = 0x05c8,
99 [TROCR] = 0x0700,
100 [CDCR] = 0x0708,
101 [LCCR] = 0x0710,
102 [CEFCR] = 0x0740,
103 [FRECR] = 0x0748,
104 [TSFRCR] = 0x0750,
105 [TLFRCR] = 0x0758,
106 [RFCR] = 0x0760,
107 [CERCR] = 0x0768,
108 [CEECR] = 0x0770,
109 [MAFCR] = 0x0778,
110 [RMII_MII] = 0x0790,
111
112 [ARSTR] = 0x0000,
113 [TSU_CTRST] = 0x0004,
114 [TSU_FWEN0] = 0x0010,
115 [TSU_FWEN1] = 0x0014,
116 [TSU_FCM] = 0x0018,
117 [TSU_BSYSL0] = 0x0020,
118 [TSU_BSYSL1] = 0x0024,
119 [TSU_PRISL0] = 0x0028,
120 [TSU_PRISL1] = 0x002c,
121 [TSU_FWSL0] = 0x0030,
122 [TSU_FWSL1] = 0x0034,
123 [TSU_FWSLC] = 0x0038,
124 [TSU_QTAGM0] = 0x0040,
125 [TSU_QTAGM1] = 0x0044,
126 [TSU_FWSR] = 0x0050,
127 [TSU_FWINMK] = 0x0054,
128 [TSU_ADQT0] = 0x0048,
129 [TSU_ADQT1] = 0x004c,
130 [TSU_VTAG0] = 0x0058,
131 [TSU_VTAG1] = 0x005c,
132 [TSU_ADSBSY] = 0x0060,
133 [TSU_TEN] = 0x0064,
134 [TSU_POST1] = 0x0070,
135 [TSU_POST2] = 0x0074,
136 [TSU_POST3] = 0x0078,
137 [TSU_POST4] = 0x007c,
138 [TSU_ADRH0] = 0x0100,
139
140 [TXNLCR0] = 0x0080,
141 [TXALCR0] = 0x0084,
142 [RXNLCR0] = 0x0088,
143 [RXALCR0] = 0x008c,
144 [FWNLCR0] = 0x0090,
145 [FWALCR0] = 0x0094,
146 [TXNLCR1] = 0x00a0,
147 [TXALCR1] = 0x00a4,
148 [RXNLCR1] = 0x00a8,
149 [RXALCR1] = 0x00ac,
150 [FWNLCR1] = 0x00b0,
151 [FWALCR1] = 0x00b4,
152 };
153
154 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
155 SH_ETH_OFFSET_DEFAULTS,
156
157 [ECMR] = 0x0300,
158 [RFLR] = 0x0308,
159 [ECSR] = 0x0310,
160 [ECSIPR] = 0x0318,
161 [PIR] = 0x0320,
162 [PSR] = 0x0328,
163 [RDMLR] = 0x0340,
164 [IPGR] = 0x0350,
165 [APR] = 0x0354,
166 [MPR] = 0x0358,
167 [RFCF] = 0x0360,
168 [TPAUSER] = 0x0364,
169 [TPAUSECR] = 0x0368,
170 [MAHR] = 0x03c0,
171 [MALR] = 0x03c8,
172 [TROCR] = 0x03d0,
173 [CDCR] = 0x03d4,
174 [LCCR] = 0x03d8,
175 [CNDCR] = 0x03dc,
176 [CEFCR] = 0x03e4,
177 [FRECR] = 0x03e8,
178 [TSFRCR] = 0x03ec,
179 [TLFRCR] = 0x03f0,
180 [RFCR] = 0x03f4,
181 [MAFCR] = 0x03f8,
182
183 [EDMR] = 0x0200,
184 [EDTRR] = 0x0208,
185 [EDRRR] = 0x0210,
186 [TDLAR] = 0x0218,
187 [RDLAR] = 0x0220,
188 [EESR] = 0x0228,
189 [EESIPR] = 0x0230,
190 [TRSCER] = 0x0238,
191 [RMFCR] = 0x0240,
192 [TFTR] = 0x0248,
193 [FDR] = 0x0250,
194 [RMCR] = 0x0258,
195 [TFUCR] = 0x0264,
196 [RFOCR] = 0x0268,
197 [RMIIMODE] = 0x026c,
198 [FCFTR] = 0x0270,
199 [TRIMD] = 0x027c,
200 };
201
202 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
203 SH_ETH_OFFSET_DEFAULTS,
204
205 [ECMR] = 0x0100,
206 [RFLR] = 0x0108,
207 [ECSR] = 0x0110,
208 [ECSIPR] = 0x0118,
209 [PIR] = 0x0120,
210 [PSR] = 0x0128,
211 [RDMLR] = 0x0140,
212 [IPGR] = 0x0150,
213 [APR] = 0x0154,
214 [MPR] = 0x0158,
215 [TPAUSER] = 0x0164,
216 [RFCF] = 0x0160,
217 [TPAUSECR] = 0x0168,
218 [BCFRR] = 0x016c,
219 [MAHR] = 0x01c0,
220 [MALR] = 0x01c8,
221 [TROCR] = 0x01d0,
222 [CDCR] = 0x01d4,
223 [LCCR] = 0x01d8,
224 [CNDCR] = 0x01dc,
225 [CEFCR] = 0x01e4,
226 [FRECR] = 0x01e8,
227 [TSFRCR] = 0x01ec,
228 [TLFRCR] = 0x01f0,
229 [RFCR] = 0x01f4,
230 [MAFCR] = 0x01f8,
231 [RTRATE] = 0x01fc,
232
233 [EDMR] = 0x0000,
234 [EDTRR] = 0x0008,
235 [EDRRR] = 0x0010,
236 [TDLAR] = 0x0018,
237 [RDLAR] = 0x0020,
238 [EESR] = 0x0028,
239 [EESIPR] = 0x0030,
240 [TRSCER] = 0x0038,
241 [RMFCR] = 0x0040,
242 [TFTR] = 0x0048,
243 [FDR] = 0x0050,
244 [RMCR] = 0x0058,
245 [TFUCR] = 0x0064,
246 [RFOCR] = 0x0068,
247 [FCFTR] = 0x0070,
248 [RPADIR] = 0x0078,
249 [TRIMD] = 0x007c,
250 [RBWAR] = 0x00c8,
251 [RDFAR] = 0x00cc,
252 [TBRAR] = 0x00d4,
253 [TDFAR] = 0x00d8,
254 };
255
256 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
257 SH_ETH_OFFSET_DEFAULTS,
258
259 [EDMR] = 0x0000,
260 [EDTRR] = 0x0004,
261 [EDRRR] = 0x0008,
262 [TDLAR] = 0x000c,
263 [RDLAR] = 0x0010,
264 [EESR] = 0x0014,
265 [EESIPR] = 0x0018,
266 [TRSCER] = 0x001c,
267 [RMFCR] = 0x0020,
268 [TFTR] = 0x0024,
269 [FDR] = 0x0028,
270 [RMCR] = 0x002c,
271 [EDOCR] = 0x0030,
272 [FCFTR] = 0x0034,
273 [RPADIR] = 0x0038,
274 [TRIMD] = 0x003c,
275 [RBWAR] = 0x0040,
276 [RDFAR] = 0x0044,
277 [TBRAR] = 0x004c,
278 [TDFAR] = 0x0050,
279
280 [ECMR] = 0x0160,
281 [ECSR] = 0x0164,
282 [ECSIPR] = 0x0168,
283 [PIR] = 0x016c,
284 [MAHR] = 0x0170,
285 [MALR] = 0x0174,
286 [RFLR] = 0x0178,
287 [PSR] = 0x017c,
288 [TROCR] = 0x0180,
289 [CDCR] = 0x0184,
290 [LCCR] = 0x0188,
291 [CNDCR] = 0x018c,
292 [CEFCR] = 0x0194,
293 [FRECR] = 0x0198,
294 [TSFRCR] = 0x019c,
295 [TLFRCR] = 0x01a0,
296 [RFCR] = 0x01a4,
297 [MAFCR] = 0x01a8,
298 [IPGR] = 0x01b4,
299 [APR] = 0x01b8,
300 [MPR] = 0x01bc,
301 [TPAUSER] = 0x01c4,
302 [BCFR] = 0x01cc,
303
304 [ARSTR] = 0x0000,
305 [TSU_CTRST] = 0x0004,
306 [TSU_FWEN0] = 0x0010,
307 [TSU_FWEN1] = 0x0014,
308 [TSU_FCM] = 0x0018,
309 [TSU_BSYSL0] = 0x0020,
310 [TSU_BSYSL1] = 0x0024,
311 [TSU_PRISL0] = 0x0028,
312 [TSU_PRISL1] = 0x002c,
313 [TSU_FWSL0] = 0x0030,
314 [TSU_FWSL1] = 0x0034,
315 [TSU_FWSLC] = 0x0038,
316 [TSU_QTAGM0] = 0x0040,
317 [TSU_QTAGM1] = 0x0044,
318 [TSU_ADQT0] = 0x0048,
319 [TSU_ADQT1] = 0x004c,
320 [TSU_FWSR] = 0x0050,
321 [TSU_FWINMK] = 0x0054,
322 [TSU_ADSBSY] = 0x0060,
323 [TSU_TEN] = 0x0064,
324 [TSU_POST1] = 0x0070,
325 [TSU_POST2] = 0x0074,
326 [TSU_POST3] = 0x0078,
327 [TSU_POST4] = 0x007c,
328
329 [TXNLCR0] = 0x0080,
330 [TXALCR0] = 0x0084,
331 [RXNLCR0] = 0x0088,
332 [RXALCR0] = 0x008c,
333 [FWNLCR0] = 0x0090,
334 [FWALCR0] = 0x0094,
335 [TXNLCR1] = 0x00a0,
336 [TXALCR1] = 0x00a4,
337 [RXNLCR1] = 0x00a8,
338 [RXALCR1] = 0x00ac,
339 [FWNLCR1] = 0x00b0,
340 [FWALCR1] = 0x00b4,
341
342 [TSU_ADRH0] = 0x0100,
343 };
344 __diag_pop();
345
346 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
347 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
348
sh_eth_write(struct net_device * ndev,u32 data,int enum_index)349 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
350 {
351 struct sh_eth_private *mdp = netdev_priv(ndev);
352 u16 offset = mdp->reg_offset[enum_index];
353
354 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
355 return;
356
357 iowrite32(data, mdp->addr + offset);
358 }
359
sh_eth_read(struct net_device * ndev,int enum_index)360 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
361 {
362 struct sh_eth_private *mdp = netdev_priv(ndev);
363 u16 offset = mdp->reg_offset[enum_index];
364
365 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
366 return ~0U;
367
368 return ioread32(mdp->addr + offset);
369 }
370
sh_eth_modify(struct net_device * ndev,int enum_index,u32 clear,u32 set)371 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
372 u32 set)
373 {
374 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
375 enum_index);
376 }
377
sh_eth_tsu_get_offset(struct sh_eth_private * mdp,int enum_index)378 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
379 {
380 return mdp->reg_offset[enum_index];
381 }
382
sh_eth_tsu_write(struct sh_eth_private * mdp,u32 data,int enum_index)383 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
384 int enum_index)
385 {
386 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
387
388 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
389 return;
390
391 iowrite32(data, mdp->tsu_addr + offset);
392 }
393
sh_eth_tsu_read(struct sh_eth_private * mdp,int enum_index)394 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
395 {
396 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
397
398 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
399 return ~0U;
400
401 return ioread32(mdp->tsu_addr + offset);
402 }
403
sh_eth_soft_swap(char * src,int len)404 static void sh_eth_soft_swap(char *src, int len)
405 {
406 #ifdef __LITTLE_ENDIAN
407 u32 *p = (u32 *)src;
408 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
409
410 for (; p < maxp; p++)
411 *p = swab32(*p);
412 #endif
413 }
414
sh_eth_select_mii(struct net_device * ndev)415 static void sh_eth_select_mii(struct net_device *ndev)
416 {
417 struct sh_eth_private *mdp = netdev_priv(ndev);
418 u32 value;
419
420 switch (mdp->phy_interface) {
421 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
422 value = 0x3;
423 break;
424 case PHY_INTERFACE_MODE_GMII:
425 value = 0x2;
426 break;
427 case PHY_INTERFACE_MODE_MII:
428 value = 0x1;
429 break;
430 case PHY_INTERFACE_MODE_RMII:
431 value = 0x0;
432 break;
433 default:
434 netdev_warn(ndev,
435 "PHY interface mode was not setup. Set to MII.\n");
436 value = 0x1;
437 break;
438 }
439
440 sh_eth_write(ndev, value, RMII_MII);
441 }
442
sh_eth_set_duplex(struct net_device * ndev)443 static void sh_eth_set_duplex(struct net_device *ndev)
444 {
445 struct sh_eth_private *mdp = netdev_priv(ndev);
446
447 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
448 }
449
sh_eth_chip_reset(struct net_device * ndev)450 static void sh_eth_chip_reset(struct net_device *ndev)
451 {
452 struct sh_eth_private *mdp = netdev_priv(ndev);
453
454 /* reset device */
455 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
456 mdelay(1);
457 }
458
sh_eth_soft_reset(struct net_device * ndev)459 static int sh_eth_soft_reset(struct net_device *ndev)
460 {
461 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
462 mdelay(3);
463 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
464
465 return 0;
466 }
467
sh_eth_check_soft_reset(struct net_device * ndev)468 static int sh_eth_check_soft_reset(struct net_device *ndev)
469 {
470 int cnt;
471
472 for (cnt = 100; cnt > 0; cnt--) {
473 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
474 return 0;
475 mdelay(1);
476 }
477
478 netdev_err(ndev, "Device reset failed\n");
479 return -ETIMEDOUT;
480 }
481
sh_eth_soft_reset_gether(struct net_device * ndev)482 static int sh_eth_soft_reset_gether(struct net_device *ndev)
483 {
484 struct sh_eth_private *mdp = netdev_priv(ndev);
485 int ret;
486
487 sh_eth_write(ndev, EDSR_ENALL, EDSR);
488 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
489
490 ret = sh_eth_check_soft_reset(ndev);
491 if (ret)
492 return ret;
493
494 /* Table Init */
495 sh_eth_write(ndev, 0, TDLAR);
496 sh_eth_write(ndev, 0, TDFAR);
497 sh_eth_write(ndev, 0, TDFXR);
498 sh_eth_write(ndev, 0, TDFFR);
499 sh_eth_write(ndev, 0, RDLAR);
500 sh_eth_write(ndev, 0, RDFAR);
501 sh_eth_write(ndev, 0, RDFXR);
502 sh_eth_write(ndev, 0, RDFFR);
503
504 /* Reset HW CRC register */
505 if (mdp->cd->csmr)
506 sh_eth_write(ndev, 0, CSMR);
507
508 /* Select MII mode */
509 if (mdp->cd->select_mii)
510 sh_eth_select_mii(ndev);
511
512 return ret;
513 }
514
sh_eth_set_rate_gether(struct net_device * ndev)515 static void sh_eth_set_rate_gether(struct net_device *ndev)
516 {
517 struct sh_eth_private *mdp = netdev_priv(ndev);
518
519 if (WARN_ON(!mdp->cd->gecmr))
520 return;
521
522 switch (mdp->speed) {
523 case 10: /* 10BASE */
524 sh_eth_write(ndev, GECMR_10, GECMR);
525 break;
526 case 100:/* 100BASE */
527 sh_eth_write(ndev, GECMR_100, GECMR);
528 break;
529 case 1000: /* 1000BASE */
530 sh_eth_write(ndev, GECMR_1000, GECMR);
531 break;
532 }
533 }
534
535 #ifdef CONFIG_OF
536 /* R7S72100 */
537 static struct sh_eth_cpu_data r7s72100_data = {
538 .soft_reset = sh_eth_soft_reset_gether,
539
540 .chip_reset = sh_eth_chip_reset,
541 .set_duplex = sh_eth_set_duplex,
542
543 .register_type = SH_ETH_REG_GIGABIT,
544
545 .edtrr_trns = EDTRR_TRNS_GETHER,
546 .ecsr_value = ECSR_ICD,
547 .ecsipr_value = ECSIPR_ICDIP,
548 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
549 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
550 EESIPR_ECIIP |
551 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
552 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
553 EESIPR_RMAFIP | EESIPR_RRFIP |
554 EESIPR_RTLFIP | EESIPR_RTSFIP |
555 EESIPR_PREIP | EESIPR_CERFIP,
556
557 .tx_check = EESR_TC1 | EESR_FTC,
558 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
559 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
560 EESR_TDE,
561 .fdr_value = 0x0000070f,
562
563 .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
564
565 .no_psr = 1,
566 .apr = 1,
567 .mpr = 1,
568 .tpauser = 1,
569 .hw_swap = 1,
570 .rpadir = 1,
571 .no_trimd = 1,
572 .no_ade = 1,
573 .xdfar_rw = 1,
574 .csmr = 1,
575 .rx_csum = 1,
576 .tsu = 1,
577 .no_tx_cntrs = 1,
578 };
579
sh_eth_chip_reset_r8a7740(struct net_device * ndev)580 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
581 {
582 sh_eth_chip_reset(ndev);
583
584 sh_eth_select_mii(ndev);
585 }
586
587 /* R8A7740 */
588 static struct sh_eth_cpu_data r8a7740_data = {
589 .soft_reset = sh_eth_soft_reset_gether,
590
591 .chip_reset = sh_eth_chip_reset_r8a7740,
592 .set_duplex = sh_eth_set_duplex,
593 .set_rate = sh_eth_set_rate_gether,
594
595 .register_type = SH_ETH_REG_GIGABIT,
596
597 .edtrr_trns = EDTRR_TRNS_GETHER,
598 .ecsr_value = ECSR_ICD | ECSR_MPD,
599 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
600 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
603 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
604 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
605 EESIPR_CEEFIP | EESIPR_CELFIP |
606 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
607 EESIPR_PREIP | EESIPR_CERFIP,
608
609 .tx_check = EESR_TC1 | EESR_FTC,
610 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
611 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
612 EESR_TDE,
613 .fdr_value = 0x0000070f,
614
615 .apr = 1,
616 .mpr = 1,
617 .tpauser = 1,
618 .gecmr = 1,
619 .bculr = 1,
620 .hw_swap = 1,
621 .rpadir = 1,
622 .no_trimd = 1,
623 .no_ade = 1,
624 .xdfar_rw = 1,
625 .csmr = 1,
626 .rx_csum = 1,
627 .tsu = 1,
628 .select_mii = 1,
629 .magic = 1,
630 .cexcr = 1,
631 };
632
633 /* There is CPU dependent code */
sh_eth_set_rate_rcar(struct net_device * ndev)634 static void sh_eth_set_rate_rcar(struct net_device *ndev)
635 {
636 struct sh_eth_private *mdp = netdev_priv(ndev);
637
638 switch (mdp->speed) {
639 case 10: /* 10BASE */
640 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
641 break;
642 case 100:/* 100BASE */
643 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
644 break;
645 }
646 }
647
648 /* R-Car Gen1 */
649 static struct sh_eth_cpu_data rcar_gen1_data = {
650 .soft_reset = sh_eth_soft_reset,
651
652 .set_duplex = sh_eth_set_duplex,
653 .set_rate = sh_eth_set_rate_rcar,
654
655 .register_type = SH_ETH_REG_FAST_RCAR,
656
657 .edtrr_trns = EDTRR_TRNS_ETHER,
658 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
659 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
660 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
661 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
662 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
663 EESIPR_RMAFIP | EESIPR_RRFIP |
664 EESIPR_RTLFIP | EESIPR_RTSFIP |
665 EESIPR_PREIP | EESIPR_CERFIP,
666
667 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
668 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
669 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
670 .fdr_value = 0x00000f0f,
671
672 .apr = 1,
673 .mpr = 1,
674 .tpauser = 1,
675 .hw_swap = 1,
676 .no_xdfar = 1,
677 };
678
679 /* R-Car Gen2 and RZ/G1 */
680 static struct sh_eth_cpu_data rcar_gen2_data = {
681 .soft_reset = sh_eth_soft_reset,
682
683 .set_duplex = sh_eth_set_duplex,
684 .set_rate = sh_eth_set_rate_rcar,
685
686 .register_type = SH_ETH_REG_FAST_RCAR,
687
688 .edtrr_trns = EDTRR_TRNS_ETHER,
689 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
690 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
691 ECSIPR_MPDIP,
692 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
693 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
694 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
695 EESIPR_RMAFIP | EESIPR_RRFIP |
696 EESIPR_RTLFIP | EESIPR_RTSFIP |
697 EESIPR_PREIP | EESIPR_CERFIP,
698
699 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
700 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
701 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
702 .fdr_value = 0x00000f0f,
703
704 .trscer_err_mask = DESC_I_RINT8,
705
706 .apr = 1,
707 .mpr = 1,
708 .tpauser = 1,
709 .hw_swap = 1,
710 .no_xdfar = 1,
711 .rmiimode = 1,
712 .magic = 1,
713 };
714
715 /* R8A77980 */
716 static struct sh_eth_cpu_data r8a77980_data = {
717 .soft_reset = sh_eth_soft_reset_gether,
718
719 .set_duplex = sh_eth_set_duplex,
720 .set_rate = sh_eth_set_rate_gether,
721
722 .register_type = SH_ETH_REG_GIGABIT,
723
724 .edtrr_trns = EDTRR_TRNS_GETHER,
725 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
726 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
727 ECSIPR_MPDIP,
728 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
729 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
730 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
731 EESIPR_RMAFIP | EESIPR_RRFIP |
732 EESIPR_RTLFIP | EESIPR_RTSFIP |
733 EESIPR_PREIP | EESIPR_CERFIP,
734
735 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
736 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
737 EESR_RFE | EESR_RDE | EESR_RFRMER |
738 EESR_TFE | EESR_TDE | EESR_ECI,
739 .fdr_value = 0x0000070f,
740
741 .apr = 1,
742 .mpr = 1,
743 .tpauser = 1,
744 .gecmr = 1,
745 .bculr = 1,
746 .hw_swap = 1,
747 .nbst = 1,
748 .rpadir = 1,
749 .no_trimd = 1,
750 .no_ade = 1,
751 .xdfar_rw = 1,
752 .csmr = 1,
753 .rx_csum = 1,
754 .select_mii = 1,
755 .magic = 1,
756 .cexcr = 1,
757 };
758
759 /* R7S9210 */
760 static struct sh_eth_cpu_data r7s9210_data = {
761 .soft_reset = sh_eth_soft_reset,
762
763 .set_duplex = sh_eth_set_duplex,
764 .set_rate = sh_eth_set_rate_rcar,
765
766 .register_type = SH_ETH_REG_FAST_SH4,
767
768 .edtrr_trns = EDTRR_TRNS_ETHER,
769 .ecsr_value = ECSR_ICD,
770 .ecsipr_value = ECSIPR_ICDIP,
771 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
772 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
773 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
774 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
775 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
776 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
777 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
778
779 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
780 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
781 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
782
783 .fdr_value = 0x0000070f,
784
785 .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
786
787 .apr = 1,
788 .mpr = 1,
789 .tpauser = 1,
790 .hw_swap = 1,
791 .rpadir = 1,
792 .no_ade = 1,
793 .xdfar_rw = 1,
794 };
795 #endif /* CONFIG_OF */
796
sh_eth_set_rate_sh7724(struct net_device * ndev)797 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
798 {
799 struct sh_eth_private *mdp = netdev_priv(ndev);
800
801 switch (mdp->speed) {
802 case 10: /* 10BASE */
803 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
804 break;
805 case 100:/* 100BASE */
806 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
807 break;
808 }
809 }
810
811 /* SH7724 */
812 static struct sh_eth_cpu_data sh7724_data = {
813 .soft_reset = sh_eth_soft_reset,
814
815 .set_duplex = sh_eth_set_duplex,
816 .set_rate = sh_eth_set_rate_sh7724,
817
818 .register_type = SH_ETH_REG_FAST_SH4,
819
820 .edtrr_trns = EDTRR_TRNS_ETHER,
821 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
822 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
823 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
824 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
825 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
826 EESIPR_RMAFIP | EESIPR_RRFIP |
827 EESIPR_RTLFIP | EESIPR_RTSFIP |
828 EESIPR_PREIP | EESIPR_CERFIP,
829
830 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
831 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
832 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
833
834 .apr = 1,
835 .mpr = 1,
836 .tpauser = 1,
837 .hw_swap = 1,
838 .rpadir = 1,
839 };
840
sh_eth_set_rate_sh7757(struct net_device * ndev)841 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
842 {
843 struct sh_eth_private *mdp = netdev_priv(ndev);
844
845 switch (mdp->speed) {
846 case 10: /* 10BASE */
847 sh_eth_write(ndev, 0, RTRATE);
848 break;
849 case 100:/* 100BASE */
850 sh_eth_write(ndev, 1, RTRATE);
851 break;
852 }
853 }
854
855 /* SH7757 */
856 static struct sh_eth_cpu_data sh7757_data = {
857 .soft_reset = sh_eth_soft_reset,
858
859 .set_duplex = sh_eth_set_duplex,
860 .set_rate = sh_eth_set_rate_sh7757,
861
862 .register_type = SH_ETH_REG_FAST_SH4,
863
864 .edtrr_trns = EDTRR_TRNS_ETHER,
865 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
866 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
867 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
868 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
869 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
870 EESIPR_CEEFIP | EESIPR_CELFIP |
871 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
872 EESIPR_PREIP | EESIPR_CERFIP,
873
874 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
875 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
876 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
877
878 .irq_flags = IRQF_SHARED,
879 .apr = 1,
880 .mpr = 1,
881 .tpauser = 1,
882 .hw_swap = 1,
883 .no_ade = 1,
884 .rpadir = 1,
885 .rtrate = 1,
886 .dual_port = 1,
887 };
888
889 #define SH_GIGA_ETH_BASE 0xfee00000UL
890 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
891 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
sh_eth_chip_reset_giga(struct net_device * ndev)892 static void sh_eth_chip_reset_giga(struct net_device *ndev)
893 {
894 u32 mahr[2], malr[2];
895 int i;
896
897 /* save MAHR and MALR */
898 for (i = 0; i < 2; i++) {
899 malr[i] = ioread32((void *)GIGA_MALR(i));
900 mahr[i] = ioread32((void *)GIGA_MAHR(i));
901 }
902
903 sh_eth_chip_reset(ndev);
904
905 /* restore MAHR and MALR */
906 for (i = 0; i < 2; i++) {
907 iowrite32(malr[i], (void *)GIGA_MALR(i));
908 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
909 }
910 }
911
sh_eth_set_rate_giga(struct net_device * ndev)912 static void sh_eth_set_rate_giga(struct net_device *ndev)
913 {
914 struct sh_eth_private *mdp = netdev_priv(ndev);
915
916 if (WARN_ON(!mdp->cd->gecmr))
917 return;
918
919 switch (mdp->speed) {
920 case 10: /* 10BASE */
921 sh_eth_write(ndev, 0x00000000, GECMR);
922 break;
923 case 100:/* 100BASE */
924 sh_eth_write(ndev, 0x00000010, GECMR);
925 break;
926 case 1000: /* 1000BASE */
927 sh_eth_write(ndev, 0x00000020, GECMR);
928 break;
929 }
930 }
931
932 /* SH7757(GETHERC) */
933 static struct sh_eth_cpu_data sh7757_data_giga = {
934 .soft_reset = sh_eth_soft_reset_gether,
935
936 .chip_reset = sh_eth_chip_reset_giga,
937 .set_duplex = sh_eth_set_duplex,
938 .set_rate = sh_eth_set_rate_giga,
939
940 .register_type = SH_ETH_REG_GIGABIT,
941
942 .edtrr_trns = EDTRR_TRNS_GETHER,
943 .ecsr_value = ECSR_ICD | ECSR_MPD,
944 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
945 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
946 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
947 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
948 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
949 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
950 EESIPR_CEEFIP | EESIPR_CELFIP |
951 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
952 EESIPR_PREIP | EESIPR_CERFIP,
953
954 .tx_check = EESR_TC1 | EESR_FTC,
955 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
956 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
957 EESR_TDE,
958 .fdr_value = 0x0000072f,
959
960 .irq_flags = IRQF_SHARED,
961 .apr = 1,
962 .mpr = 1,
963 .tpauser = 1,
964 .gecmr = 1,
965 .bculr = 1,
966 .hw_swap = 1,
967 .rpadir = 1,
968 .no_trimd = 1,
969 .no_ade = 1,
970 .xdfar_rw = 1,
971 .tsu = 1,
972 .cexcr = 1,
973 .dual_port = 1,
974 };
975
976 /* SH7734 */
977 static struct sh_eth_cpu_data sh7734_data = {
978 .soft_reset = sh_eth_soft_reset_gether,
979
980 .chip_reset = sh_eth_chip_reset,
981 .set_duplex = sh_eth_set_duplex,
982 .set_rate = sh_eth_set_rate_gether,
983
984 .register_type = SH_ETH_REG_GIGABIT,
985
986 .edtrr_trns = EDTRR_TRNS_GETHER,
987 .ecsr_value = ECSR_ICD | ECSR_MPD,
988 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
989 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
990 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
991 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
992 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
993 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
994 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
995 EESIPR_PREIP | EESIPR_CERFIP,
996
997 .tx_check = EESR_TC1 | EESR_FTC,
998 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
999 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1000 EESR_TDE,
1001
1002 .apr = 1,
1003 .mpr = 1,
1004 .tpauser = 1,
1005 .gecmr = 1,
1006 .bculr = 1,
1007 .hw_swap = 1,
1008 .no_trimd = 1,
1009 .no_ade = 1,
1010 .xdfar_rw = 1,
1011 .tsu = 1,
1012 .csmr = 1,
1013 .rx_csum = 1,
1014 .select_mii = 1,
1015 .magic = 1,
1016 .cexcr = 1,
1017 };
1018
1019 /* SH7763 */
1020 static struct sh_eth_cpu_data sh7763_data = {
1021 .soft_reset = sh_eth_soft_reset_gether,
1022
1023 .chip_reset = sh_eth_chip_reset,
1024 .set_duplex = sh_eth_set_duplex,
1025 .set_rate = sh_eth_set_rate_gether,
1026
1027 .register_type = SH_ETH_REG_GIGABIT,
1028
1029 .edtrr_trns = EDTRR_TRNS_GETHER,
1030 .ecsr_value = ECSR_ICD | ECSR_MPD,
1031 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1032 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1033 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1034 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1035 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1036 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1037 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1038 EESIPR_PREIP | EESIPR_CERFIP,
1039
1040 .tx_check = EESR_TC1 | EESR_FTC,
1041 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1042 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1043
1044 .apr = 1,
1045 .mpr = 1,
1046 .tpauser = 1,
1047 .gecmr = 1,
1048 .bculr = 1,
1049 .hw_swap = 1,
1050 .no_trimd = 1,
1051 .no_ade = 1,
1052 .xdfar_rw = 1,
1053 .tsu = 1,
1054 .irq_flags = IRQF_SHARED,
1055 .magic = 1,
1056 .cexcr = 1,
1057 .rx_csum = 1,
1058 .dual_port = 1,
1059 };
1060
1061 static struct sh_eth_cpu_data sh7619_data = {
1062 .soft_reset = sh_eth_soft_reset,
1063
1064 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1065
1066 .edtrr_trns = EDTRR_TRNS_ETHER,
1067 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1068 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1069 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1070 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1071 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1072 EESIPR_CEEFIP | EESIPR_CELFIP |
1073 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1074 EESIPR_PREIP | EESIPR_CERFIP,
1075
1076 .apr = 1,
1077 .mpr = 1,
1078 .tpauser = 1,
1079 .hw_swap = 1,
1080 };
1081
1082 static struct sh_eth_cpu_data sh771x_data = {
1083 .soft_reset = sh_eth_soft_reset,
1084
1085 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1086
1087 .edtrr_trns = EDTRR_TRNS_ETHER,
1088 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1089 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1090 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1091 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1092 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1093 EESIPR_CEEFIP | EESIPR_CELFIP |
1094 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1095 EESIPR_PREIP | EESIPR_CERFIP,
1096
1097 .trscer_err_mask = DESC_I_RINT8,
1098
1099 .tsu = 1,
1100 .dual_port = 1,
1101 };
1102
sh_eth_set_default_cpu_data(struct sh_eth_cpu_data * cd)1103 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1104 {
1105 if (!cd->ecsr_value)
1106 cd->ecsr_value = DEFAULT_ECSR_INIT;
1107
1108 if (!cd->ecsipr_value)
1109 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1110
1111 if (!cd->fcftr_value)
1112 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1113 DEFAULT_FIFO_F_D_RFD;
1114
1115 if (!cd->fdr_value)
1116 cd->fdr_value = DEFAULT_FDR_INIT;
1117
1118 if (!cd->tx_check)
1119 cd->tx_check = DEFAULT_TX_CHECK;
1120
1121 if (!cd->eesr_err_check)
1122 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1123
1124 if (!cd->trscer_err_mask)
1125 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1126 }
1127
sh_eth_set_receive_align(struct sk_buff * skb)1128 static void sh_eth_set_receive_align(struct sk_buff *skb)
1129 {
1130 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1131
1132 if (reserve)
1133 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1134 }
1135
1136 /* Program the hardware MAC address from dev->dev_addr. */
update_mac_address(struct net_device * ndev)1137 static void update_mac_address(struct net_device *ndev)
1138 {
1139 sh_eth_write(ndev,
1140 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1141 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1142 sh_eth_write(ndev,
1143 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1144 }
1145
1146 /* Get MAC address from SuperH MAC address register
1147 *
1148 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1149 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1150 * When you want use this device, you must set MAC address in bootloader.
1151 *
1152 */
read_mac_address(struct net_device * ndev,unsigned char * mac)1153 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1154 {
1155 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1156 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1157 } else {
1158 u32 mahr = sh_eth_read(ndev, MAHR);
1159 u32 malr = sh_eth_read(ndev, MALR);
1160
1161 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1162 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1163 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1164 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1165 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1166 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1167 }
1168 }
1169
1170 struct bb_info {
1171 void (*set_gate)(void *addr);
1172 struct mdiobb_ctrl ctrl;
1173 void *addr;
1174 };
1175
sh_mdio_ctrl(struct mdiobb_ctrl * ctrl,u32 mask,int set)1176 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1177 {
1178 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1179 u32 pir;
1180
1181 if (bitbang->set_gate)
1182 bitbang->set_gate(bitbang->addr);
1183
1184 pir = ioread32(bitbang->addr);
1185 if (set)
1186 pir |= mask;
1187 else
1188 pir &= ~mask;
1189 iowrite32(pir, bitbang->addr);
1190 }
1191
1192 /* Data I/O pin control */
sh_mmd_ctrl(struct mdiobb_ctrl * ctrl,int bit)1193 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1194 {
1195 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1196 }
1197
1198 /* Set bit data*/
sh_set_mdio(struct mdiobb_ctrl * ctrl,int bit)1199 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1200 {
1201 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1202 }
1203
1204 /* Get bit data*/
sh_get_mdio(struct mdiobb_ctrl * ctrl)1205 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1206 {
1207 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1208
1209 if (bitbang->set_gate)
1210 bitbang->set_gate(bitbang->addr);
1211
1212 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1213 }
1214
1215 /* MDC pin control */
sh_mdc_ctrl(struct mdiobb_ctrl * ctrl,int bit)1216 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1217 {
1218 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1219 }
1220
1221 /* mdio bus control struct */
1222 static const struct mdiobb_ops bb_ops = {
1223 .owner = THIS_MODULE,
1224 .set_mdc = sh_mdc_ctrl,
1225 .set_mdio_dir = sh_mmd_ctrl,
1226 .set_mdio_data = sh_set_mdio,
1227 .get_mdio_data = sh_get_mdio,
1228 };
1229
1230 /* free Tx skb function */
sh_eth_tx_free(struct net_device * ndev,bool sent_only)1231 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1232 {
1233 struct sh_eth_private *mdp = netdev_priv(ndev);
1234 struct sh_eth_txdesc *txdesc;
1235 int free_num = 0;
1236 int entry;
1237 bool sent;
1238
1239 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1240 entry = mdp->dirty_tx % mdp->num_tx_ring;
1241 txdesc = &mdp->tx_ring[entry];
1242 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1243 if (sent_only && !sent)
1244 break;
1245 /* TACT bit must be checked before all the following reads */
1246 dma_rmb();
1247 netif_info(mdp, tx_done, ndev,
1248 "tx entry %d status 0x%08x\n",
1249 entry, le32_to_cpu(txdesc->status));
1250 /* Free the original skb. */
1251 if (mdp->tx_skbuff[entry]) {
1252 dma_unmap_single(&mdp->pdev->dev,
1253 le32_to_cpu(txdesc->addr),
1254 le32_to_cpu(txdesc->len) >> 16,
1255 DMA_TO_DEVICE);
1256 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1257 mdp->tx_skbuff[entry] = NULL;
1258 free_num++;
1259 }
1260 txdesc->status = cpu_to_le32(TD_TFP);
1261 if (entry >= mdp->num_tx_ring - 1)
1262 txdesc->status |= cpu_to_le32(TD_TDLE);
1263
1264 if (sent) {
1265 ndev->stats.tx_packets++;
1266 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1267 }
1268 }
1269 return free_num;
1270 }
1271
1272 /* free skb and descriptor buffer */
sh_eth_ring_free(struct net_device * ndev)1273 static void sh_eth_ring_free(struct net_device *ndev)
1274 {
1275 struct sh_eth_private *mdp = netdev_priv(ndev);
1276 int ringsize, i;
1277
1278 if (mdp->rx_ring) {
1279 for (i = 0; i < mdp->num_rx_ring; i++) {
1280 if (mdp->rx_skbuff[i]) {
1281 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1282
1283 dma_unmap_single(&mdp->pdev->dev,
1284 le32_to_cpu(rxdesc->addr),
1285 ALIGN(mdp->rx_buf_sz, 32),
1286 DMA_FROM_DEVICE);
1287 }
1288 }
1289 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1290 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1291 mdp->rx_desc_dma);
1292 mdp->rx_ring = NULL;
1293 }
1294
1295 /* Free Rx skb ringbuffer */
1296 if (mdp->rx_skbuff) {
1297 for (i = 0; i < mdp->num_rx_ring; i++)
1298 dev_kfree_skb(mdp->rx_skbuff[i]);
1299 }
1300 kfree(mdp->rx_skbuff);
1301 mdp->rx_skbuff = NULL;
1302
1303 if (mdp->tx_ring) {
1304 sh_eth_tx_free(ndev, false);
1305
1306 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1307 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1308 mdp->tx_desc_dma);
1309 mdp->tx_ring = NULL;
1310 }
1311
1312 /* Free Tx skb ringbuffer */
1313 kfree(mdp->tx_skbuff);
1314 mdp->tx_skbuff = NULL;
1315 }
1316
1317 /* format skb and descriptor buffer */
sh_eth_ring_format(struct net_device * ndev)1318 static void sh_eth_ring_format(struct net_device *ndev)
1319 {
1320 struct sh_eth_private *mdp = netdev_priv(ndev);
1321 int i;
1322 struct sk_buff *skb;
1323 struct sh_eth_rxdesc *rxdesc = NULL;
1324 struct sh_eth_txdesc *txdesc = NULL;
1325 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1326 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1327 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1328 dma_addr_t dma_addr;
1329 u32 buf_len;
1330
1331 mdp->cur_rx = 0;
1332 mdp->cur_tx = 0;
1333 mdp->dirty_rx = 0;
1334 mdp->dirty_tx = 0;
1335
1336 memset(mdp->rx_ring, 0, rx_ringsize);
1337
1338 /* build Rx ring buffer */
1339 for (i = 0; i < mdp->num_rx_ring; i++) {
1340 /* skb */
1341 mdp->rx_skbuff[i] = NULL;
1342 skb = netdev_alloc_skb(ndev, skbuff_size);
1343 if (skb == NULL)
1344 break;
1345 sh_eth_set_receive_align(skb);
1346
1347 /* The size of the buffer is a multiple of 32 bytes. */
1348 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1349 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1350 DMA_FROM_DEVICE);
1351 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1352 kfree_skb(skb);
1353 break;
1354 }
1355 mdp->rx_skbuff[i] = skb;
1356
1357 /* RX descriptor */
1358 rxdesc = &mdp->rx_ring[i];
1359 rxdesc->len = cpu_to_le32(buf_len << 16);
1360 rxdesc->addr = cpu_to_le32(dma_addr);
1361 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1362
1363 /* Rx descriptor address set */
1364 if (i == 0) {
1365 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1366 if (mdp->cd->xdfar_rw)
1367 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1368 }
1369 }
1370
1371 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1372
1373 /* Mark the last entry as wrapping the ring. */
1374 if (rxdesc)
1375 rxdesc->status |= cpu_to_le32(RD_RDLE);
1376
1377 memset(mdp->tx_ring, 0, tx_ringsize);
1378
1379 /* build Tx ring buffer */
1380 for (i = 0; i < mdp->num_tx_ring; i++) {
1381 mdp->tx_skbuff[i] = NULL;
1382 txdesc = &mdp->tx_ring[i];
1383 txdesc->status = cpu_to_le32(TD_TFP);
1384 txdesc->len = cpu_to_le32(0);
1385 if (i == 0) {
1386 /* Tx descriptor address set */
1387 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1388 if (mdp->cd->xdfar_rw)
1389 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1390 }
1391 }
1392
1393 txdesc->status |= cpu_to_le32(TD_TDLE);
1394 }
1395
1396 /* Get skb and descriptor buffer */
sh_eth_ring_init(struct net_device * ndev)1397 static int sh_eth_ring_init(struct net_device *ndev)
1398 {
1399 struct sh_eth_private *mdp = netdev_priv(ndev);
1400 int rx_ringsize, tx_ringsize;
1401
1402 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1403 * card needs room to do 8 byte alignment, +2 so we can reserve
1404 * the first 2 bytes, and +16 gets room for the status word from the
1405 * card.
1406 */
1407 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1408 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1409 if (mdp->cd->rpadir)
1410 mdp->rx_buf_sz += NET_IP_ALIGN;
1411
1412 /* Allocate RX and TX skb rings */
1413 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1414 GFP_KERNEL);
1415 if (!mdp->rx_skbuff)
1416 return -ENOMEM;
1417
1418 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1419 GFP_KERNEL);
1420 if (!mdp->tx_skbuff)
1421 goto ring_free;
1422
1423 /* Allocate all Rx descriptors. */
1424 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1425 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1426 &mdp->rx_desc_dma, GFP_KERNEL);
1427 if (!mdp->rx_ring)
1428 goto ring_free;
1429
1430 mdp->dirty_rx = 0;
1431
1432 /* Allocate all Tx descriptors. */
1433 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1434 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1435 &mdp->tx_desc_dma, GFP_KERNEL);
1436 if (!mdp->tx_ring)
1437 goto ring_free;
1438 return 0;
1439
1440 ring_free:
1441 /* Free Rx and Tx skb ring buffer and DMA buffer */
1442 sh_eth_ring_free(ndev);
1443
1444 return -ENOMEM;
1445 }
1446
sh_eth_dev_init(struct net_device * ndev)1447 static int sh_eth_dev_init(struct net_device *ndev)
1448 {
1449 struct sh_eth_private *mdp = netdev_priv(ndev);
1450 int ret;
1451
1452 /* Soft Reset */
1453 ret = mdp->cd->soft_reset(ndev);
1454 if (ret)
1455 return ret;
1456
1457 if (mdp->cd->rmiimode)
1458 sh_eth_write(ndev, 0x1, RMIIMODE);
1459
1460 /* Descriptor format */
1461 sh_eth_ring_format(ndev);
1462 if (mdp->cd->rpadir)
1463 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1464
1465 /* all sh_eth int mask */
1466 sh_eth_write(ndev, 0, EESIPR);
1467
1468 #if defined(__LITTLE_ENDIAN)
1469 if (mdp->cd->hw_swap)
1470 sh_eth_write(ndev, EDMR_EL, EDMR);
1471 else
1472 #endif
1473 sh_eth_write(ndev, 0, EDMR);
1474
1475 /* FIFO size set */
1476 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1477 sh_eth_write(ndev, 0, TFTR);
1478
1479 /* Frame recv control (enable multiple-packets per rx irq) */
1480 sh_eth_write(ndev, RMCR_RNC, RMCR);
1481
1482 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1483
1484 /* DMA transfer burst mode */
1485 if (mdp->cd->nbst)
1486 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1487
1488 /* Burst cycle count upper-limit */
1489 if (mdp->cd->bculr)
1490 sh_eth_write(ndev, 0x800, BCULR);
1491
1492 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1493
1494 if (!mdp->cd->no_trimd)
1495 sh_eth_write(ndev, 0, TRIMD);
1496
1497 /* Recv frame limit set register */
1498 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1499 RFLR);
1500
1501 sh_eth_modify(ndev, EESR, 0, 0);
1502 mdp->irq_enabled = true;
1503 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1504
1505 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
1506 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1507 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1508 ECMR_TE | ECMR_RE, ECMR);
1509
1510 if (mdp->cd->set_rate)
1511 mdp->cd->set_rate(ndev);
1512
1513 /* E-MAC Status Register clear */
1514 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1515
1516 /* E-MAC Interrupt Enable register */
1517 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1518
1519 /* Set MAC address */
1520 update_mac_address(ndev);
1521
1522 /* mask reset */
1523 if (mdp->cd->apr)
1524 sh_eth_write(ndev, 1, APR);
1525 if (mdp->cd->mpr)
1526 sh_eth_write(ndev, 1, MPR);
1527 if (mdp->cd->tpauser)
1528 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1529
1530 /* Setting the Rx mode will start the Rx process. */
1531 sh_eth_write(ndev, EDRRR_R, EDRRR);
1532
1533 return ret;
1534 }
1535
sh_eth_dev_exit(struct net_device * ndev)1536 static void sh_eth_dev_exit(struct net_device *ndev)
1537 {
1538 struct sh_eth_private *mdp = netdev_priv(ndev);
1539 int i;
1540
1541 /* Deactivate all TX descriptors, so DMA should stop at next
1542 * packet boundary if it's currently running
1543 */
1544 for (i = 0; i < mdp->num_tx_ring; i++)
1545 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1546
1547 /* Disable TX FIFO egress to MAC */
1548 sh_eth_rcv_snd_disable(ndev);
1549
1550 /* Stop RX DMA at next packet boundary */
1551 sh_eth_write(ndev, 0, EDRRR);
1552
1553 /* Aside from TX DMA, we can't tell when the hardware is
1554 * really stopped, so we need to reset to make sure.
1555 * Before doing that, wait for long enough to *probably*
1556 * finish transmitting the last packet and poll stats.
1557 */
1558 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1559 sh_eth_get_stats(ndev);
1560 mdp->cd->soft_reset(ndev);
1561
1562 /* Set the RMII mode again if required */
1563 if (mdp->cd->rmiimode)
1564 sh_eth_write(ndev, 0x1, RMIIMODE);
1565
1566 /* Set MAC address again */
1567 update_mac_address(ndev);
1568 }
1569
sh_eth_rx_csum(struct sk_buff * skb)1570 static void sh_eth_rx_csum(struct sk_buff *skb)
1571 {
1572 u8 *hw_csum;
1573
1574 /* The hardware checksum is 2 bytes appended to packet data */
1575 if (unlikely(skb->len < sizeof(__sum16)))
1576 return;
1577 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1578 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1579 skb->ip_summed = CHECKSUM_COMPLETE;
1580 skb_trim(skb, skb->len - sizeof(__sum16));
1581 }
1582
1583 /* Packet receive function */
sh_eth_rx(struct net_device * ndev,u32 intr_status,int * quota)1584 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1585 {
1586 struct sh_eth_private *mdp = netdev_priv(ndev);
1587 struct sh_eth_rxdesc *rxdesc;
1588
1589 int entry = mdp->cur_rx % mdp->num_rx_ring;
1590 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1591 int limit;
1592 struct sk_buff *skb;
1593 u32 desc_status;
1594 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1595 dma_addr_t dma_addr;
1596 u16 pkt_len;
1597 u32 buf_len;
1598
1599 boguscnt = min(boguscnt, *quota);
1600 limit = boguscnt;
1601 rxdesc = &mdp->rx_ring[entry];
1602 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1603 /* RACT bit must be checked before all the following reads */
1604 dma_rmb();
1605 desc_status = le32_to_cpu(rxdesc->status);
1606 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1607
1608 if (--boguscnt < 0)
1609 break;
1610
1611 netif_info(mdp, rx_status, ndev,
1612 "rx entry %d status 0x%08x len %d\n",
1613 entry, desc_status, pkt_len);
1614
1615 if (!(desc_status & RDFEND))
1616 ndev->stats.rx_length_errors++;
1617
1618 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1619 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1620 * bit 0. However, in case of the R8A7740 and R7S72100
1621 * the RFS bits are from bit 25 to bit 16. So, the
1622 * driver needs right shifting by 16.
1623 */
1624 if (mdp->cd->csmr)
1625 desc_status >>= 16;
1626
1627 skb = mdp->rx_skbuff[entry];
1628 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1629 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1630 ndev->stats.rx_errors++;
1631 if (desc_status & RD_RFS1)
1632 ndev->stats.rx_crc_errors++;
1633 if (desc_status & RD_RFS2)
1634 ndev->stats.rx_frame_errors++;
1635 if (desc_status & RD_RFS3)
1636 ndev->stats.rx_length_errors++;
1637 if (desc_status & RD_RFS4)
1638 ndev->stats.rx_length_errors++;
1639 if (desc_status & RD_RFS6)
1640 ndev->stats.rx_missed_errors++;
1641 if (desc_status & RD_RFS10)
1642 ndev->stats.rx_over_errors++;
1643 } else if (skb) {
1644 dma_addr = le32_to_cpu(rxdesc->addr);
1645 if (!mdp->cd->hw_swap)
1646 sh_eth_soft_swap(
1647 phys_to_virt(ALIGN(dma_addr, 4)),
1648 pkt_len + 2);
1649 mdp->rx_skbuff[entry] = NULL;
1650 if (mdp->cd->rpadir)
1651 skb_reserve(skb, NET_IP_ALIGN);
1652 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1653 ALIGN(mdp->rx_buf_sz, 32),
1654 DMA_FROM_DEVICE);
1655 skb_put(skb, pkt_len);
1656 skb->protocol = eth_type_trans(skb, ndev);
1657 if (ndev->features & NETIF_F_RXCSUM)
1658 sh_eth_rx_csum(skb);
1659 netif_receive_skb(skb);
1660 ndev->stats.rx_packets++;
1661 ndev->stats.rx_bytes += pkt_len;
1662 if (desc_status & RD_RFS8)
1663 ndev->stats.multicast++;
1664 }
1665 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1666 rxdesc = &mdp->rx_ring[entry];
1667 }
1668
1669 /* Refill the Rx ring buffers. */
1670 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1671 entry = mdp->dirty_rx % mdp->num_rx_ring;
1672 rxdesc = &mdp->rx_ring[entry];
1673 /* The size of the buffer is 32 byte boundary. */
1674 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1675 rxdesc->len = cpu_to_le32(buf_len << 16);
1676
1677 if (mdp->rx_skbuff[entry] == NULL) {
1678 skb = netdev_alloc_skb(ndev, skbuff_size);
1679 if (skb == NULL)
1680 break; /* Better luck next round. */
1681 sh_eth_set_receive_align(skb);
1682 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1683 buf_len, DMA_FROM_DEVICE);
1684 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1685 kfree_skb(skb);
1686 break;
1687 }
1688 mdp->rx_skbuff[entry] = skb;
1689
1690 skb_checksum_none_assert(skb);
1691 rxdesc->addr = cpu_to_le32(dma_addr);
1692 }
1693 dma_wmb(); /* RACT bit must be set after all the above writes */
1694 if (entry >= mdp->num_rx_ring - 1)
1695 rxdesc->status |=
1696 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1697 else
1698 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1699 }
1700
1701 /* Restart Rx engine if stopped. */
1702 /* If we don't need to check status, don't. -KDU */
1703 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1704 /* fix the values for the next receiving if RDE is set */
1705 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1706 u32 count = (sh_eth_read(ndev, RDFAR) -
1707 sh_eth_read(ndev, RDLAR)) >> 4;
1708
1709 mdp->cur_rx = count;
1710 mdp->dirty_rx = count;
1711 }
1712 sh_eth_write(ndev, EDRRR_R, EDRRR);
1713 }
1714
1715 *quota -= limit - boguscnt - 1;
1716
1717 return *quota <= 0;
1718 }
1719
sh_eth_rcv_snd_disable(struct net_device * ndev)1720 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1721 {
1722 /* disable tx and rx */
1723 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1724 }
1725
sh_eth_rcv_snd_enable(struct net_device * ndev)1726 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1727 {
1728 /* enable tx and rx */
1729 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1730 }
1731
1732 /* E-MAC interrupt handler */
sh_eth_emac_interrupt(struct net_device * ndev)1733 static void sh_eth_emac_interrupt(struct net_device *ndev)
1734 {
1735 struct sh_eth_private *mdp = netdev_priv(ndev);
1736 u32 felic_stat;
1737 u32 link_stat;
1738
1739 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1740 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1741 if (felic_stat & ECSR_ICD)
1742 ndev->stats.tx_carrier_errors++;
1743 if (felic_stat & ECSR_MPD)
1744 pm_wakeup_event(&mdp->pdev->dev, 0);
1745 if (felic_stat & ECSR_LCHNG) {
1746 /* Link Changed */
1747 if (mdp->cd->no_psr || mdp->no_ether_link)
1748 return;
1749 link_stat = sh_eth_read(ndev, PSR);
1750 if (mdp->ether_link_active_low)
1751 link_stat = ~link_stat;
1752 if (!(link_stat & PHY_ST_LINK)) {
1753 sh_eth_rcv_snd_disable(ndev);
1754 } else {
1755 /* Link Up */
1756 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1757 /* clear int */
1758 sh_eth_modify(ndev, ECSR, 0, 0);
1759 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1760 /* enable tx and rx */
1761 sh_eth_rcv_snd_enable(ndev);
1762 }
1763 }
1764 }
1765
1766 /* error control function */
sh_eth_error(struct net_device * ndev,u32 intr_status)1767 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1768 {
1769 struct sh_eth_private *mdp = netdev_priv(ndev);
1770 u32 mask;
1771
1772 if (intr_status & EESR_TWB) {
1773 /* Unused write back interrupt */
1774 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1775 ndev->stats.tx_aborted_errors++;
1776 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1777 }
1778 }
1779
1780 if (intr_status & EESR_RABT) {
1781 /* Receive Abort int */
1782 if (intr_status & EESR_RFRMER) {
1783 /* Receive Frame Overflow int */
1784 ndev->stats.rx_frame_errors++;
1785 }
1786 }
1787
1788 if (intr_status & EESR_TDE) {
1789 /* Transmit Descriptor Empty int */
1790 ndev->stats.tx_fifo_errors++;
1791 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1792 }
1793
1794 if (intr_status & EESR_TFE) {
1795 /* FIFO under flow */
1796 ndev->stats.tx_fifo_errors++;
1797 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1798 }
1799
1800 if (intr_status & EESR_RDE) {
1801 /* Receive Descriptor Empty int */
1802 ndev->stats.rx_over_errors++;
1803 }
1804
1805 if (intr_status & EESR_RFE) {
1806 /* Receive FIFO Overflow int */
1807 ndev->stats.rx_fifo_errors++;
1808 }
1809
1810 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1811 /* Address Error */
1812 ndev->stats.tx_fifo_errors++;
1813 netif_err(mdp, tx_err, ndev, "Address Error\n");
1814 }
1815
1816 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1817 if (mdp->cd->no_ade)
1818 mask &= ~EESR_ADE;
1819 if (intr_status & mask) {
1820 /* Tx error */
1821 u32 edtrr = sh_eth_read(ndev, EDTRR);
1822
1823 /* dmesg */
1824 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1825 intr_status, mdp->cur_tx, mdp->dirty_tx,
1826 (u32)ndev->state, edtrr);
1827 /* dirty buffer free */
1828 sh_eth_tx_free(ndev, true);
1829
1830 /* SH7712 BUG */
1831 if (edtrr ^ mdp->cd->edtrr_trns) {
1832 /* tx dma start */
1833 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1834 }
1835 /* wakeup */
1836 netif_wake_queue(ndev);
1837 }
1838 }
1839
sh_eth_interrupt(int irq,void * netdev)1840 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1841 {
1842 struct net_device *ndev = netdev;
1843 struct sh_eth_private *mdp = netdev_priv(ndev);
1844 struct sh_eth_cpu_data *cd = mdp->cd;
1845 irqreturn_t ret = IRQ_NONE;
1846 u32 intr_status, intr_enable;
1847
1848 spin_lock(&mdp->lock);
1849
1850 /* Get interrupt status */
1851 intr_status = sh_eth_read(ndev, EESR);
1852 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1853 * enabled since it's the one that comes thru regardless of the mask,
1854 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1855 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1856 * bit...
1857 */
1858 intr_enable = sh_eth_read(ndev, EESIPR);
1859 intr_status &= intr_enable | EESIPR_ECIIP;
1860 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1861 cd->eesr_err_check))
1862 ret = IRQ_HANDLED;
1863 else
1864 goto out;
1865
1866 if (unlikely(!mdp->irq_enabled)) {
1867 sh_eth_write(ndev, 0, EESIPR);
1868 goto out;
1869 }
1870
1871 if (intr_status & EESR_RX_CHECK) {
1872 if (napi_schedule_prep(&mdp->napi)) {
1873 /* Mask Rx interrupts */
1874 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1875 EESIPR);
1876 __napi_schedule(&mdp->napi);
1877 } else {
1878 netdev_warn(ndev,
1879 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1880 intr_status, intr_enable);
1881 }
1882 }
1883
1884 /* Tx Check */
1885 if (intr_status & cd->tx_check) {
1886 /* Clear Tx interrupts */
1887 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1888
1889 sh_eth_tx_free(ndev, true);
1890 netif_wake_queue(ndev);
1891 }
1892
1893 /* E-MAC interrupt */
1894 if (intr_status & EESR_ECI)
1895 sh_eth_emac_interrupt(ndev);
1896
1897 if (intr_status & cd->eesr_err_check) {
1898 /* Clear error interrupts */
1899 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1900
1901 sh_eth_error(ndev, intr_status);
1902 }
1903
1904 out:
1905 spin_unlock(&mdp->lock);
1906
1907 return ret;
1908 }
1909
sh_eth_poll(struct napi_struct * napi,int budget)1910 static int sh_eth_poll(struct napi_struct *napi, int budget)
1911 {
1912 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1913 napi);
1914 struct net_device *ndev = napi->dev;
1915 int quota = budget;
1916 u32 intr_status;
1917
1918 for (;;) {
1919 intr_status = sh_eth_read(ndev, EESR);
1920 if (!(intr_status & EESR_RX_CHECK))
1921 break;
1922 /* Clear Rx interrupts */
1923 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1924
1925 if (sh_eth_rx(ndev, intr_status, "a))
1926 goto out;
1927 }
1928
1929 napi_complete(napi);
1930
1931 /* Reenable Rx interrupts */
1932 if (mdp->irq_enabled)
1933 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1934 out:
1935 return budget - quota;
1936 }
1937
1938 /* PHY state control function */
sh_eth_adjust_link(struct net_device * ndev)1939 static void sh_eth_adjust_link(struct net_device *ndev)
1940 {
1941 struct sh_eth_private *mdp = netdev_priv(ndev);
1942 struct phy_device *phydev = ndev->phydev;
1943 unsigned long flags;
1944 int new_state = 0;
1945
1946 spin_lock_irqsave(&mdp->lock, flags);
1947
1948 /* Disable TX and RX right over here, if E-MAC change is ignored */
1949 if (mdp->cd->no_psr || mdp->no_ether_link)
1950 sh_eth_rcv_snd_disable(ndev);
1951
1952 if (phydev->link) {
1953 if (phydev->duplex != mdp->duplex) {
1954 new_state = 1;
1955 mdp->duplex = phydev->duplex;
1956 if (mdp->cd->set_duplex)
1957 mdp->cd->set_duplex(ndev);
1958 }
1959
1960 if (phydev->speed != mdp->speed) {
1961 new_state = 1;
1962 mdp->speed = phydev->speed;
1963 if (mdp->cd->set_rate)
1964 mdp->cd->set_rate(ndev);
1965 }
1966 if (!mdp->link) {
1967 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1968 new_state = 1;
1969 mdp->link = phydev->link;
1970 }
1971 } else if (mdp->link) {
1972 new_state = 1;
1973 mdp->link = 0;
1974 mdp->speed = 0;
1975 mdp->duplex = -1;
1976 }
1977
1978 /* Enable TX and RX right over here, if E-MAC change is ignored */
1979 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1980 sh_eth_rcv_snd_enable(ndev);
1981
1982 spin_unlock_irqrestore(&mdp->lock, flags);
1983
1984 if (new_state && netif_msg_link(mdp))
1985 phy_print_status(phydev);
1986 }
1987
1988 /* PHY init function */
sh_eth_phy_init(struct net_device * ndev)1989 static int sh_eth_phy_init(struct net_device *ndev)
1990 {
1991 struct device_node *np = ndev->dev.parent->of_node;
1992 struct sh_eth_private *mdp = netdev_priv(ndev);
1993 struct phy_device *phydev;
1994
1995 mdp->link = 0;
1996 mdp->speed = 0;
1997 mdp->duplex = -1;
1998
1999 /* Try connect to PHY */
2000 if (np) {
2001 struct device_node *pn;
2002
2003 pn = of_parse_phandle(np, "phy-handle", 0);
2004 phydev = of_phy_connect(ndev, pn,
2005 sh_eth_adjust_link, 0,
2006 mdp->phy_interface);
2007
2008 of_node_put(pn);
2009 if (!phydev)
2010 phydev = ERR_PTR(-ENOENT);
2011 } else {
2012 char phy_id[MII_BUS_ID_SIZE + 3];
2013
2014 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2015 mdp->mii_bus->id, mdp->phy_id);
2016
2017 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2018 mdp->phy_interface);
2019 }
2020
2021 if (IS_ERR(phydev)) {
2022 netdev_err(ndev, "failed to connect PHY\n");
2023 return PTR_ERR(phydev);
2024 }
2025
2026 /* mask with MAC supported features */
2027 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2028 int err = phy_set_max_speed(phydev, SPEED_100);
2029 if (err) {
2030 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2031 phy_disconnect(phydev);
2032 return err;
2033 }
2034 }
2035
2036 phy_attached_info(phydev);
2037
2038 return 0;
2039 }
2040
2041 /* PHY control start function */
sh_eth_phy_start(struct net_device * ndev)2042 static int sh_eth_phy_start(struct net_device *ndev)
2043 {
2044 int ret;
2045
2046 ret = sh_eth_phy_init(ndev);
2047 if (ret)
2048 return ret;
2049
2050 phy_start(ndev->phydev);
2051
2052 return 0;
2053 }
2054
2055 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2056 * version must be bumped as well. Just adding registers up to that
2057 * limit is fine, as long as the existing register indices don't
2058 * change.
2059 */
2060 #define SH_ETH_REG_DUMP_VERSION 1
2061 #define SH_ETH_REG_DUMP_MAX_REGS 256
2062
__sh_eth_get_regs(struct net_device * ndev,u32 * buf)2063 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2064 {
2065 struct sh_eth_private *mdp = netdev_priv(ndev);
2066 struct sh_eth_cpu_data *cd = mdp->cd;
2067 u32 *valid_map;
2068 size_t len;
2069
2070 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2071
2072 /* Dump starts with a bitmap that tells ethtool which
2073 * registers are defined for this chip.
2074 */
2075 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2076 if (buf) {
2077 valid_map = buf;
2078 buf += len;
2079 } else {
2080 valid_map = NULL;
2081 }
2082
2083 /* Add a register to the dump, if it has a defined offset.
2084 * This automatically skips most undefined registers, but for
2085 * some it is also necessary to check a capability flag in
2086 * struct sh_eth_cpu_data.
2087 */
2088 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2089 #define add_reg_from(reg, read_expr) do { \
2090 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2091 if (buf) { \
2092 mark_reg_valid(reg); \
2093 *buf++ = read_expr; \
2094 } \
2095 ++len; \
2096 } \
2097 } while (0)
2098 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2099 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2100
2101 add_reg(EDSR);
2102 add_reg(EDMR);
2103 add_reg(EDTRR);
2104 add_reg(EDRRR);
2105 add_reg(EESR);
2106 add_reg(EESIPR);
2107 add_reg(TDLAR);
2108 if (!cd->no_xdfar)
2109 add_reg(TDFAR);
2110 add_reg(TDFXR);
2111 add_reg(TDFFR);
2112 add_reg(RDLAR);
2113 if (!cd->no_xdfar)
2114 add_reg(RDFAR);
2115 add_reg(RDFXR);
2116 add_reg(RDFFR);
2117 add_reg(TRSCER);
2118 add_reg(RMFCR);
2119 add_reg(TFTR);
2120 add_reg(FDR);
2121 add_reg(RMCR);
2122 add_reg(TFUCR);
2123 add_reg(RFOCR);
2124 if (cd->rmiimode)
2125 add_reg(RMIIMODE);
2126 add_reg(FCFTR);
2127 if (cd->rpadir)
2128 add_reg(RPADIR);
2129 if (!cd->no_trimd)
2130 add_reg(TRIMD);
2131 add_reg(ECMR);
2132 add_reg(ECSR);
2133 add_reg(ECSIPR);
2134 add_reg(PIR);
2135 if (!cd->no_psr)
2136 add_reg(PSR);
2137 add_reg(RDMLR);
2138 add_reg(RFLR);
2139 add_reg(IPGR);
2140 if (cd->apr)
2141 add_reg(APR);
2142 if (cd->mpr)
2143 add_reg(MPR);
2144 add_reg(RFCR);
2145 add_reg(RFCF);
2146 if (cd->tpauser)
2147 add_reg(TPAUSER);
2148 add_reg(TPAUSECR);
2149 if (cd->gecmr)
2150 add_reg(GECMR);
2151 if (cd->bculr)
2152 add_reg(BCULR);
2153 add_reg(MAHR);
2154 add_reg(MALR);
2155 if (!cd->no_tx_cntrs) {
2156 add_reg(TROCR);
2157 add_reg(CDCR);
2158 add_reg(LCCR);
2159 add_reg(CNDCR);
2160 }
2161 add_reg(CEFCR);
2162 add_reg(FRECR);
2163 add_reg(TSFRCR);
2164 add_reg(TLFRCR);
2165 if (cd->cexcr) {
2166 add_reg(CERCR);
2167 add_reg(CEECR);
2168 }
2169 add_reg(MAFCR);
2170 if (cd->rtrate)
2171 add_reg(RTRATE);
2172 if (cd->csmr)
2173 add_reg(CSMR);
2174 if (cd->select_mii)
2175 add_reg(RMII_MII);
2176 if (cd->tsu) {
2177 add_tsu_reg(ARSTR);
2178 add_tsu_reg(TSU_CTRST);
2179 if (cd->dual_port) {
2180 add_tsu_reg(TSU_FWEN0);
2181 add_tsu_reg(TSU_FWEN1);
2182 add_tsu_reg(TSU_FCM);
2183 add_tsu_reg(TSU_BSYSL0);
2184 add_tsu_reg(TSU_BSYSL1);
2185 add_tsu_reg(TSU_PRISL0);
2186 add_tsu_reg(TSU_PRISL1);
2187 add_tsu_reg(TSU_FWSL0);
2188 add_tsu_reg(TSU_FWSL1);
2189 }
2190 add_tsu_reg(TSU_FWSLC);
2191 if (cd->dual_port) {
2192 add_tsu_reg(TSU_QTAGM0);
2193 add_tsu_reg(TSU_QTAGM1);
2194 add_tsu_reg(TSU_FWSR);
2195 add_tsu_reg(TSU_FWINMK);
2196 add_tsu_reg(TSU_ADQT0);
2197 add_tsu_reg(TSU_ADQT1);
2198 add_tsu_reg(TSU_VTAG0);
2199 add_tsu_reg(TSU_VTAG1);
2200 }
2201 add_tsu_reg(TSU_ADSBSY);
2202 add_tsu_reg(TSU_TEN);
2203 add_tsu_reg(TSU_POST1);
2204 add_tsu_reg(TSU_POST2);
2205 add_tsu_reg(TSU_POST3);
2206 add_tsu_reg(TSU_POST4);
2207 /* This is the start of a table, not just a single register. */
2208 if (buf) {
2209 unsigned int i;
2210
2211 mark_reg_valid(TSU_ADRH0);
2212 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2213 *buf++ = ioread32(mdp->tsu_addr +
2214 mdp->reg_offset[TSU_ADRH0] +
2215 i * 4);
2216 }
2217 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2218 }
2219
2220 #undef mark_reg_valid
2221 #undef add_reg_from
2222 #undef add_reg
2223 #undef add_tsu_reg
2224
2225 return len * 4;
2226 }
2227
sh_eth_get_regs_len(struct net_device * ndev)2228 static int sh_eth_get_regs_len(struct net_device *ndev)
2229 {
2230 return __sh_eth_get_regs(ndev, NULL);
2231 }
2232
sh_eth_get_regs(struct net_device * ndev,struct ethtool_regs * regs,void * buf)2233 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2234 void *buf)
2235 {
2236 struct sh_eth_private *mdp = netdev_priv(ndev);
2237
2238 regs->version = SH_ETH_REG_DUMP_VERSION;
2239
2240 pm_runtime_get_sync(&mdp->pdev->dev);
2241 __sh_eth_get_regs(ndev, buf);
2242 pm_runtime_put_sync(&mdp->pdev->dev);
2243 }
2244
sh_eth_get_msglevel(struct net_device * ndev)2245 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2246 {
2247 struct sh_eth_private *mdp = netdev_priv(ndev);
2248 return mdp->msg_enable;
2249 }
2250
sh_eth_set_msglevel(struct net_device * ndev,u32 value)2251 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2252 {
2253 struct sh_eth_private *mdp = netdev_priv(ndev);
2254 mdp->msg_enable = value;
2255 }
2256
2257 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2258 "rx_current", "tx_current",
2259 "rx_dirty", "tx_dirty",
2260 };
2261 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2262
sh_eth_get_sset_count(struct net_device * netdev,int sset)2263 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2264 {
2265 switch (sset) {
2266 case ETH_SS_STATS:
2267 return SH_ETH_STATS_LEN;
2268 default:
2269 return -EOPNOTSUPP;
2270 }
2271 }
2272
sh_eth_get_ethtool_stats(struct net_device * ndev,struct ethtool_stats * stats,u64 * data)2273 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2274 struct ethtool_stats *stats, u64 *data)
2275 {
2276 struct sh_eth_private *mdp = netdev_priv(ndev);
2277 int i = 0;
2278
2279 /* device-specific stats */
2280 data[i++] = mdp->cur_rx;
2281 data[i++] = mdp->cur_tx;
2282 data[i++] = mdp->dirty_rx;
2283 data[i++] = mdp->dirty_tx;
2284 }
2285
sh_eth_get_strings(struct net_device * ndev,u32 stringset,u8 * data)2286 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2287 {
2288 switch (stringset) {
2289 case ETH_SS_STATS:
2290 memcpy(data, sh_eth_gstrings_stats,
2291 sizeof(sh_eth_gstrings_stats));
2292 break;
2293 }
2294 }
2295
sh_eth_get_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)2296 static void sh_eth_get_ringparam(struct net_device *ndev,
2297 struct ethtool_ringparam *ring)
2298 {
2299 struct sh_eth_private *mdp = netdev_priv(ndev);
2300
2301 ring->rx_max_pending = RX_RING_MAX;
2302 ring->tx_max_pending = TX_RING_MAX;
2303 ring->rx_pending = mdp->num_rx_ring;
2304 ring->tx_pending = mdp->num_tx_ring;
2305 }
2306
sh_eth_set_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)2307 static int sh_eth_set_ringparam(struct net_device *ndev,
2308 struct ethtool_ringparam *ring)
2309 {
2310 struct sh_eth_private *mdp = netdev_priv(ndev);
2311 int ret;
2312
2313 if (ring->tx_pending > TX_RING_MAX ||
2314 ring->rx_pending > RX_RING_MAX ||
2315 ring->tx_pending < TX_RING_MIN ||
2316 ring->rx_pending < RX_RING_MIN)
2317 return -EINVAL;
2318 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2319 return -EINVAL;
2320
2321 if (netif_running(ndev)) {
2322 netif_device_detach(ndev);
2323 netif_tx_disable(ndev);
2324
2325 /* Serialise with the interrupt handler and NAPI, then
2326 * disable interrupts. We have to clear the
2327 * irq_enabled flag first to ensure that interrupts
2328 * won't be re-enabled.
2329 */
2330 mdp->irq_enabled = false;
2331 synchronize_irq(ndev->irq);
2332 napi_synchronize(&mdp->napi);
2333 sh_eth_write(ndev, 0x0000, EESIPR);
2334
2335 sh_eth_dev_exit(ndev);
2336
2337 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2338 sh_eth_ring_free(ndev);
2339 }
2340
2341 /* Set new parameters */
2342 mdp->num_rx_ring = ring->rx_pending;
2343 mdp->num_tx_ring = ring->tx_pending;
2344
2345 if (netif_running(ndev)) {
2346 ret = sh_eth_ring_init(ndev);
2347 if (ret < 0) {
2348 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2349 __func__);
2350 return ret;
2351 }
2352 ret = sh_eth_dev_init(ndev);
2353 if (ret < 0) {
2354 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2355 __func__);
2356 return ret;
2357 }
2358
2359 netif_device_attach(ndev);
2360 }
2361
2362 return 0;
2363 }
2364
sh_eth_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)2365 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2366 {
2367 struct sh_eth_private *mdp = netdev_priv(ndev);
2368
2369 wol->supported = 0;
2370 wol->wolopts = 0;
2371
2372 if (mdp->cd->magic) {
2373 wol->supported = WAKE_MAGIC;
2374 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2375 }
2376 }
2377
sh_eth_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)2378 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2379 {
2380 struct sh_eth_private *mdp = netdev_priv(ndev);
2381
2382 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2383 return -EOPNOTSUPP;
2384
2385 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2386
2387 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2388
2389 return 0;
2390 }
2391
2392 static const struct ethtool_ops sh_eth_ethtool_ops = {
2393 .get_regs_len = sh_eth_get_regs_len,
2394 .get_regs = sh_eth_get_regs,
2395 .nway_reset = phy_ethtool_nway_reset,
2396 .get_msglevel = sh_eth_get_msglevel,
2397 .set_msglevel = sh_eth_set_msglevel,
2398 .get_link = ethtool_op_get_link,
2399 .get_strings = sh_eth_get_strings,
2400 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2401 .get_sset_count = sh_eth_get_sset_count,
2402 .get_ringparam = sh_eth_get_ringparam,
2403 .set_ringparam = sh_eth_set_ringparam,
2404 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2405 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2406 .get_wol = sh_eth_get_wol,
2407 .set_wol = sh_eth_set_wol,
2408 };
2409
2410 /* network device open function */
sh_eth_open(struct net_device * ndev)2411 static int sh_eth_open(struct net_device *ndev)
2412 {
2413 struct sh_eth_private *mdp = netdev_priv(ndev);
2414 int ret;
2415
2416 pm_runtime_get_sync(&mdp->pdev->dev);
2417
2418 napi_enable(&mdp->napi);
2419
2420 ret = request_irq(ndev->irq, sh_eth_interrupt,
2421 mdp->cd->irq_flags, ndev->name, ndev);
2422 if (ret) {
2423 netdev_err(ndev, "Can not assign IRQ number\n");
2424 goto out_napi_off;
2425 }
2426
2427 /* Descriptor set */
2428 ret = sh_eth_ring_init(ndev);
2429 if (ret)
2430 goto out_free_irq;
2431
2432 /* device init */
2433 ret = sh_eth_dev_init(ndev);
2434 if (ret)
2435 goto out_free_irq;
2436
2437 /* PHY control start*/
2438 ret = sh_eth_phy_start(ndev);
2439 if (ret)
2440 goto out_free_irq;
2441
2442 netif_start_queue(ndev);
2443
2444 mdp->is_opened = 1;
2445
2446 return ret;
2447
2448 out_free_irq:
2449 free_irq(ndev->irq, ndev);
2450 out_napi_off:
2451 napi_disable(&mdp->napi);
2452 pm_runtime_put_sync(&mdp->pdev->dev);
2453 return ret;
2454 }
2455
2456 /* Timeout function */
sh_eth_tx_timeout(struct net_device * ndev,unsigned int txqueue)2457 static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
2458 {
2459 struct sh_eth_private *mdp = netdev_priv(ndev);
2460 struct sh_eth_rxdesc *rxdesc;
2461 int i;
2462
2463 netif_stop_queue(ndev);
2464
2465 netif_err(mdp, timer, ndev,
2466 "transmit timed out, status %8.8x, resetting...\n",
2467 sh_eth_read(ndev, EESR));
2468
2469 /* tx_errors count up */
2470 ndev->stats.tx_errors++;
2471
2472 /* Free all the skbuffs in the Rx queue. */
2473 for (i = 0; i < mdp->num_rx_ring; i++) {
2474 rxdesc = &mdp->rx_ring[i];
2475 rxdesc->status = cpu_to_le32(0);
2476 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2477 dev_kfree_skb(mdp->rx_skbuff[i]);
2478 mdp->rx_skbuff[i] = NULL;
2479 }
2480 for (i = 0; i < mdp->num_tx_ring; i++) {
2481 dev_kfree_skb(mdp->tx_skbuff[i]);
2482 mdp->tx_skbuff[i] = NULL;
2483 }
2484
2485 /* device init */
2486 sh_eth_dev_init(ndev);
2487
2488 netif_start_queue(ndev);
2489 }
2490
2491 /* Packet transmit function */
sh_eth_start_xmit(struct sk_buff * skb,struct net_device * ndev)2492 static netdev_tx_t sh_eth_start_xmit(struct sk_buff *skb,
2493 struct net_device *ndev)
2494 {
2495 struct sh_eth_private *mdp = netdev_priv(ndev);
2496 struct sh_eth_txdesc *txdesc;
2497 dma_addr_t dma_addr;
2498 u32 entry;
2499 unsigned long flags;
2500
2501 spin_lock_irqsave(&mdp->lock, flags);
2502 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2503 if (!sh_eth_tx_free(ndev, true)) {
2504 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2505 netif_stop_queue(ndev);
2506 spin_unlock_irqrestore(&mdp->lock, flags);
2507 return NETDEV_TX_BUSY;
2508 }
2509 }
2510 spin_unlock_irqrestore(&mdp->lock, flags);
2511
2512 if (skb_put_padto(skb, ETH_ZLEN))
2513 return NETDEV_TX_OK;
2514
2515 entry = mdp->cur_tx % mdp->num_tx_ring;
2516 mdp->tx_skbuff[entry] = skb;
2517 txdesc = &mdp->tx_ring[entry];
2518 /* soft swap. */
2519 if (!mdp->cd->hw_swap)
2520 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2521 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2522 DMA_TO_DEVICE);
2523 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2524 kfree_skb(skb);
2525 return NETDEV_TX_OK;
2526 }
2527 txdesc->addr = cpu_to_le32(dma_addr);
2528 txdesc->len = cpu_to_le32(skb->len << 16);
2529
2530 dma_wmb(); /* TACT bit must be set after all the above writes */
2531 if (entry >= mdp->num_tx_ring - 1)
2532 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2533 else
2534 txdesc->status |= cpu_to_le32(TD_TACT);
2535
2536 wmb(); /* cur_tx must be incremented after TACT bit was set */
2537 mdp->cur_tx++;
2538
2539 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2540 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2541
2542 return NETDEV_TX_OK;
2543 }
2544
2545 /* The statistics registers have write-clear behaviour, which means we
2546 * will lose any increment between the read and write. We mitigate
2547 * this by only clearing when we read a non-zero value, so we will
2548 * never falsely report a total of zero.
2549 */
2550 static void
sh_eth_update_stat(struct net_device * ndev,unsigned long * stat,int reg)2551 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2552 {
2553 u32 delta = sh_eth_read(ndev, reg);
2554
2555 if (delta) {
2556 *stat += delta;
2557 sh_eth_write(ndev, 0, reg);
2558 }
2559 }
2560
sh_eth_get_stats(struct net_device * ndev)2561 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2562 {
2563 struct sh_eth_private *mdp = netdev_priv(ndev);
2564
2565 if (mdp->cd->no_tx_cntrs)
2566 return &ndev->stats;
2567
2568 if (!mdp->is_opened)
2569 return &ndev->stats;
2570
2571 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2572 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2573 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2574
2575 if (mdp->cd->cexcr) {
2576 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2577 CERCR);
2578 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2579 CEECR);
2580 } else {
2581 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2582 CNDCR);
2583 }
2584
2585 return &ndev->stats;
2586 }
2587
2588 /* device close function */
sh_eth_close(struct net_device * ndev)2589 static int sh_eth_close(struct net_device *ndev)
2590 {
2591 struct sh_eth_private *mdp = netdev_priv(ndev);
2592
2593 netif_stop_queue(ndev);
2594
2595 /* Serialise with the interrupt handler and NAPI, then disable
2596 * interrupts. We have to clear the irq_enabled flag first to
2597 * ensure that interrupts won't be re-enabled.
2598 */
2599 mdp->irq_enabled = false;
2600 synchronize_irq(ndev->irq);
2601 napi_disable(&mdp->napi);
2602 sh_eth_write(ndev, 0x0000, EESIPR);
2603
2604 sh_eth_dev_exit(ndev);
2605
2606 /* PHY Disconnect */
2607 if (ndev->phydev) {
2608 phy_stop(ndev->phydev);
2609 phy_disconnect(ndev->phydev);
2610 }
2611
2612 free_irq(ndev->irq, ndev);
2613
2614 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2615 sh_eth_ring_free(ndev);
2616
2617 mdp->is_opened = 0;
2618
2619 pm_runtime_put(&mdp->pdev->dev);
2620
2621 return 0;
2622 }
2623
sh_eth_change_mtu(struct net_device * ndev,int new_mtu)2624 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2625 {
2626 if (netif_running(ndev))
2627 return -EBUSY;
2628
2629 ndev->mtu = new_mtu;
2630 netdev_update_features(ndev);
2631
2632 return 0;
2633 }
2634
2635 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
sh_eth_tsu_get_post_mask(int entry)2636 static u32 sh_eth_tsu_get_post_mask(int entry)
2637 {
2638 return 0x0f << (28 - ((entry % 8) * 4));
2639 }
2640
sh_eth_tsu_get_post_bit(struct sh_eth_private * mdp,int entry)2641 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2642 {
2643 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2644 }
2645
sh_eth_tsu_enable_cam_entry_post(struct net_device * ndev,int entry)2646 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2647 int entry)
2648 {
2649 struct sh_eth_private *mdp = netdev_priv(ndev);
2650 int reg = TSU_POST1 + entry / 8;
2651 u32 tmp;
2652
2653 tmp = sh_eth_tsu_read(mdp, reg);
2654 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2655 }
2656
sh_eth_tsu_disable_cam_entry_post(struct net_device * ndev,int entry)2657 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2658 int entry)
2659 {
2660 struct sh_eth_private *mdp = netdev_priv(ndev);
2661 int reg = TSU_POST1 + entry / 8;
2662 u32 post_mask, ref_mask, tmp;
2663
2664 post_mask = sh_eth_tsu_get_post_mask(entry);
2665 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2666
2667 tmp = sh_eth_tsu_read(mdp, reg);
2668 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2669
2670 /* If other port enables, the function returns "true" */
2671 return tmp & ref_mask;
2672 }
2673
sh_eth_tsu_busy(struct net_device * ndev)2674 static int sh_eth_tsu_busy(struct net_device *ndev)
2675 {
2676 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2677 struct sh_eth_private *mdp = netdev_priv(ndev);
2678
2679 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2680 udelay(10);
2681 timeout--;
2682 if (timeout <= 0) {
2683 netdev_err(ndev, "%s: timeout\n", __func__);
2684 return -ETIMEDOUT;
2685 }
2686 }
2687
2688 return 0;
2689 }
2690
sh_eth_tsu_write_entry(struct net_device * ndev,u16 offset,const u8 * addr)2691 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2692 const u8 *addr)
2693 {
2694 struct sh_eth_private *mdp = netdev_priv(ndev);
2695 u32 val;
2696
2697 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2698 iowrite32(val, mdp->tsu_addr + offset);
2699 if (sh_eth_tsu_busy(ndev) < 0)
2700 return -EBUSY;
2701
2702 val = addr[4] << 8 | addr[5];
2703 iowrite32(val, mdp->tsu_addr + offset + 4);
2704 if (sh_eth_tsu_busy(ndev) < 0)
2705 return -EBUSY;
2706
2707 return 0;
2708 }
2709
sh_eth_tsu_read_entry(struct net_device * ndev,u16 offset,u8 * addr)2710 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2711 {
2712 struct sh_eth_private *mdp = netdev_priv(ndev);
2713 u32 val;
2714
2715 val = ioread32(mdp->tsu_addr + offset);
2716 addr[0] = (val >> 24) & 0xff;
2717 addr[1] = (val >> 16) & 0xff;
2718 addr[2] = (val >> 8) & 0xff;
2719 addr[3] = val & 0xff;
2720 val = ioread32(mdp->tsu_addr + offset + 4);
2721 addr[4] = (val >> 8) & 0xff;
2722 addr[5] = val & 0xff;
2723 }
2724
2725
sh_eth_tsu_find_entry(struct net_device * ndev,const u8 * addr)2726 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2727 {
2728 struct sh_eth_private *mdp = netdev_priv(ndev);
2729 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2730 int i;
2731 u8 c_addr[ETH_ALEN];
2732
2733 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2734 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2735 if (ether_addr_equal(addr, c_addr))
2736 return i;
2737 }
2738
2739 return -ENOENT;
2740 }
2741
sh_eth_tsu_find_empty(struct net_device * ndev)2742 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2743 {
2744 u8 blank[ETH_ALEN];
2745 int entry;
2746
2747 memset(blank, 0, sizeof(blank));
2748 entry = sh_eth_tsu_find_entry(ndev, blank);
2749 return (entry < 0) ? -ENOMEM : entry;
2750 }
2751
sh_eth_tsu_disable_cam_entry_table(struct net_device * ndev,int entry)2752 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2753 int entry)
2754 {
2755 struct sh_eth_private *mdp = netdev_priv(ndev);
2756 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2757 int ret;
2758 u8 blank[ETH_ALEN];
2759
2760 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2761 ~(1 << (31 - entry)), TSU_TEN);
2762
2763 memset(blank, 0, sizeof(blank));
2764 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2765 if (ret < 0)
2766 return ret;
2767 return 0;
2768 }
2769
sh_eth_tsu_add_entry(struct net_device * ndev,const u8 * addr)2770 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2771 {
2772 struct sh_eth_private *mdp = netdev_priv(ndev);
2773 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2774 int i, ret;
2775
2776 if (!mdp->cd->tsu)
2777 return 0;
2778
2779 i = sh_eth_tsu_find_entry(ndev, addr);
2780 if (i < 0) {
2781 /* No entry found, create one */
2782 i = sh_eth_tsu_find_empty(ndev);
2783 if (i < 0)
2784 return -ENOMEM;
2785 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2786 if (ret < 0)
2787 return ret;
2788
2789 /* Enable the entry */
2790 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2791 (1 << (31 - i)), TSU_TEN);
2792 }
2793
2794 /* Entry found or created, enable POST */
2795 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2796
2797 return 0;
2798 }
2799
sh_eth_tsu_del_entry(struct net_device * ndev,const u8 * addr)2800 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2801 {
2802 struct sh_eth_private *mdp = netdev_priv(ndev);
2803 int i, ret;
2804
2805 if (!mdp->cd->tsu)
2806 return 0;
2807
2808 i = sh_eth_tsu_find_entry(ndev, addr);
2809 if (i) {
2810 /* Entry found */
2811 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2812 goto done;
2813
2814 /* Disable the entry if both ports was disabled */
2815 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2816 if (ret < 0)
2817 return ret;
2818 }
2819 done:
2820 return 0;
2821 }
2822
sh_eth_tsu_purge_all(struct net_device * ndev)2823 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2824 {
2825 struct sh_eth_private *mdp = netdev_priv(ndev);
2826 int i, ret;
2827
2828 if (!mdp->cd->tsu)
2829 return 0;
2830
2831 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2832 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2833 continue;
2834
2835 /* Disable the entry if both ports was disabled */
2836 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2837 if (ret < 0)
2838 return ret;
2839 }
2840
2841 return 0;
2842 }
2843
sh_eth_tsu_purge_mcast(struct net_device * ndev)2844 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2845 {
2846 struct sh_eth_private *mdp = netdev_priv(ndev);
2847 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2848 u8 addr[ETH_ALEN];
2849 int i;
2850
2851 if (!mdp->cd->tsu)
2852 return;
2853
2854 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2855 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2856 if (is_multicast_ether_addr(addr))
2857 sh_eth_tsu_del_entry(ndev, addr);
2858 }
2859 }
2860
2861 /* Update promiscuous flag and multicast filter */
sh_eth_set_rx_mode(struct net_device * ndev)2862 static void sh_eth_set_rx_mode(struct net_device *ndev)
2863 {
2864 struct sh_eth_private *mdp = netdev_priv(ndev);
2865 u32 ecmr_bits;
2866 int mcast_all = 0;
2867 unsigned long flags;
2868
2869 spin_lock_irqsave(&mdp->lock, flags);
2870 /* Initial condition is MCT = 1, PRM = 0.
2871 * Depending on ndev->flags, set PRM or clear MCT
2872 */
2873 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2874 if (mdp->cd->tsu)
2875 ecmr_bits |= ECMR_MCT;
2876
2877 if (!(ndev->flags & IFF_MULTICAST)) {
2878 sh_eth_tsu_purge_mcast(ndev);
2879 mcast_all = 1;
2880 }
2881 if (ndev->flags & IFF_ALLMULTI) {
2882 sh_eth_tsu_purge_mcast(ndev);
2883 ecmr_bits &= ~ECMR_MCT;
2884 mcast_all = 1;
2885 }
2886
2887 if (ndev->flags & IFF_PROMISC) {
2888 sh_eth_tsu_purge_all(ndev);
2889 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2890 } else if (mdp->cd->tsu) {
2891 struct netdev_hw_addr *ha;
2892 netdev_for_each_mc_addr(ha, ndev) {
2893 if (mcast_all && is_multicast_ether_addr(ha->addr))
2894 continue;
2895
2896 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2897 if (!mcast_all) {
2898 sh_eth_tsu_purge_mcast(ndev);
2899 ecmr_bits &= ~ECMR_MCT;
2900 mcast_all = 1;
2901 }
2902 }
2903 }
2904 }
2905
2906 /* update the ethernet mode */
2907 sh_eth_write(ndev, ecmr_bits, ECMR);
2908
2909 spin_unlock_irqrestore(&mdp->lock, flags);
2910 }
2911
sh_eth_set_rx_csum(struct net_device * ndev,bool enable)2912 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2913 {
2914 struct sh_eth_private *mdp = netdev_priv(ndev);
2915 unsigned long flags;
2916
2917 spin_lock_irqsave(&mdp->lock, flags);
2918
2919 /* Disable TX and RX */
2920 sh_eth_rcv_snd_disable(ndev);
2921
2922 /* Modify RX Checksum setting */
2923 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2924
2925 /* Enable TX and RX */
2926 sh_eth_rcv_snd_enable(ndev);
2927
2928 spin_unlock_irqrestore(&mdp->lock, flags);
2929 }
2930
sh_eth_set_features(struct net_device * ndev,netdev_features_t features)2931 static int sh_eth_set_features(struct net_device *ndev,
2932 netdev_features_t features)
2933 {
2934 netdev_features_t changed = ndev->features ^ features;
2935 struct sh_eth_private *mdp = netdev_priv(ndev);
2936
2937 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2938 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2939
2940 ndev->features = features;
2941
2942 return 0;
2943 }
2944
sh_eth_get_vtag_index(struct sh_eth_private * mdp)2945 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2946 {
2947 if (!mdp->port)
2948 return TSU_VTAG0;
2949 else
2950 return TSU_VTAG1;
2951 }
2952
sh_eth_vlan_rx_add_vid(struct net_device * ndev,__be16 proto,u16 vid)2953 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2954 __be16 proto, u16 vid)
2955 {
2956 struct sh_eth_private *mdp = netdev_priv(ndev);
2957 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2958
2959 if (unlikely(!mdp->cd->tsu))
2960 return -EPERM;
2961
2962 /* No filtering if vid = 0 */
2963 if (!vid)
2964 return 0;
2965
2966 mdp->vlan_num_ids++;
2967
2968 /* The controller has one VLAN tag HW filter. So, if the filter is
2969 * already enabled, the driver disables it and the filte
2970 */
2971 if (mdp->vlan_num_ids > 1) {
2972 /* disable VLAN filter */
2973 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2974 return 0;
2975 }
2976
2977 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2978 vtag_reg_index);
2979
2980 return 0;
2981 }
2982
sh_eth_vlan_rx_kill_vid(struct net_device * ndev,__be16 proto,u16 vid)2983 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2984 __be16 proto, u16 vid)
2985 {
2986 struct sh_eth_private *mdp = netdev_priv(ndev);
2987 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2988
2989 if (unlikely(!mdp->cd->tsu))
2990 return -EPERM;
2991
2992 /* No filtering if vid = 0 */
2993 if (!vid)
2994 return 0;
2995
2996 mdp->vlan_num_ids--;
2997 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2998
2999 return 0;
3000 }
3001
3002 /* SuperH's TSU register init function */
sh_eth_tsu_init(struct sh_eth_private * mdp)3003 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
3004 {
3005 if (!mdp->cd->dual_port) {
3006 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3007 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3008 TSU_FWSLC); /* Enable POST registers */
3009 return;
3010 }
3011
3012 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3013 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3014 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3015 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3016 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3017 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3018 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3019 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3020 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3021 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3022 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3023 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3024 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3025 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3026 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3027 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3028 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3029 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3030 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3031 }
3032
3033 /* MDIO bus release function */
sh_mdio_release(struct sh_eth_private * mdp)3034 static int sh_mdio_release(struct sh_eth_private *mdp)
3035 {
3036 /* unregister mdio bus */
3037 mdiobus_unregister(mdp->mii_bus);
3038
3039 /* free bitbang info */
3040 free_mdio_bitbang(mdp->mii_bus);
3041
3042 return 0;
3043 }
3044
3045 /* MDIO bus init function */
sh_mdio_init(struct sh_eth_private * mdp,struct sh_eth_plat_data * pd)3046 static int sh_mdio_init(struct sh_eth_private *mdp,
3047 struct sh_eth_plat_data *pd)
3048 {
3049 int ret;
3050 struct bb_info *bitbang;
3051 struct platform_device *pdev = mdp->pdev;
3052 struct device *dev = &mdp->pdev->dev;
3053
3054 /* create bit control struct for PHY */
3055 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3056 if (!bitbang)
3057 return -ENOMEM;
3058
3059 /* bitbang init */
3060 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3061 bitbang->set_gate = pd->set_mdio_gate;
3062 bitbang->ctrl.ops = &bb_ops;
3063
3064 /* MII controller setting */
3065 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3066 if (!mdp->mii_bus)
3067 return -ENOMEM;
3068
3069 /* Hook up MII support for ethtool */
3070 mdp->mii_bus->name = "sh_mii";
3071 mdp->mii_bus->parent = dev;
3072 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3073 pdev->name, pdev->id);
3074
3075 /* register MDIO bus */
3076 if (pd->phy_irq > 0)
3077 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3078
3079 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3080 if (ret)
3081 goto out_free_bus;
3082
3083 return 0;
3084
3085 out_free_bus:
3086 free_mdio_bitbang(mdp->mii_bus);
3087 return ret;
3088 }
3089
sh_eth_get_register_offset(int register_type)3090 static const u16 *sh_eth_get_register_offset(int register_type)
3091 {
3092 const u16 *reg_offset = NULL;
3093
3094 switch (register_type) {
3095 case SH_ETH_REG_GIGABIT:
3096 reg_offset = sh_eth_offset_gigabit;
3097 break;
3098 case SH_ETH_REG_FAST_RCAR:
3099 reg_offset = sh_eth_offset_fast_rcar;
3100 break;
3101 case SH_ETH_REG_FAST_SH4:
3102 reg_offset = sh_eth_offset_fast_sh4;
3103 break;
3104 case SH_ETH_REG_FAST_SH3_SH2:
3105 reg_offset = sh_eth_offset_fast_sh3_sh2;
3106 break;
3107 }
3108
3109 return reg_offset;
3110 }
3111
3112 static const struct net_device_ops sh_eth_netdev_ops = {
3113 .ndo_open = sh_eth_open,
3114 .ndo_stop = sh_eth_close,
3115 .ndo_start_xmit = sh_eth_start_xmit,
3116 .ndo_get_stats = sh_eth_get_stats,
3117 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3118 .ndo_tx_timeout = sh_eth_tx_timeout,
3119 .ndo_do_ioctl = phy_do_ioctl_running,
3120 .ndo_change_mtu = sh_eth_change_mtu,
3121 .ndo_validate_addr = eth_validate_addr,
3122 .ndo_set_mac_address = eth_mac_addr,
3123 .ndo_set_features = sh_eth_set_features,
3124 };
3125
3126 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3127 .ndo_open = sh_eth_open,
3128 .ndo_stop = sh_eth_close,
3129 .ndo_start_xmit = sh_eth_start_xmit,
3130 .ndo_get_stats = sh_eth_get_stats,
3131 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3132 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3133 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3134 .ndo_tx_timeout = sh_eth_tx_timeout,
3135 .ndo_do_ioctl = phy_do_ioctl_running,
3136 .ndo_change_mtu = sh_eth_change_mtu,
3137 .ndo_validate_addr = eth_validate_addr,
3138 .ndo_set_mac_address = eth_mac_addr,
3139 .ndo_set_features = sh_eth_set_features,
3140 };
3141
3142 #ifdef CONFIG_OF
sh_eth_parse_dt(struct device * dev)3143 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3144 {
3145 struct device_node *np = dev->of_node;
3146 struct sh_eth_plat_data *pdata;
3147 phy_interface_t interface;
3148 const char *mac_addr;
3149 int ret;
3150
3151 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3152 if (!pdata)
3153 return NULL;
3154
3155 ret = of_get_phy_mode(np, &interface);
3156 if (ret)
3157 return NULL;
3158 pdata->phy_interface = interface;
3159
3160 mac_addr = of_get_mac_address(np);
3161 if (!IS_ERR(mac_addr))
3162 ether_addr_copy(pdata->mac_addr, mac_addr);
3163
3164 pdata->no_ether_link =
3165 of_property_read_bool(np, "renesas,no-ether-link");
3166 pdata->ether_link_active_low =
3167 of_property_read_bool(np, "renesas,ether-link-active-low");
3168
3169 return pdata;
3170 }
3171
3172 static const struct of_device_id sh_eth_match_table[] = {
3173 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3174 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3175 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3176 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3177 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3178 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3179 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3180 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3181 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3182 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3183 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3184 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3185 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3186 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3187 { }
3188 };
3189 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3190 #else
sh_eth_parse_dt(struct device * dev)3191 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3192 {
3193 return NULL;
3194 }
3195 #endif
3196
sh_eth_drv_probe(struct platform_device * pdev)3197 static int sh_eth_drv_probe(struct platform_device *pdev)
3198 {
3199 struct resource *res;
3200 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3201 const struct platform_device_id *id = platform_get_device_id(pdev);
3202 struct sh_eth_private *mdp;
3203 struct net_device *ndev;
3204 int ret;
3205
3206 /* get base addr */
3207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3208
3209 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3210 if (!ndev)
3211 return -ENOMEM;
3212
3213 pm_runtime_enable(&pdev->dev);
3214 pm_runtime_get_sync(&pdev->dev);
3215
3216 ret = platform_get_irq(pdev, 0);
3217 if (ret < 0)
3218 goto out_release;
3219 ndev->irq = ret;
3220
3221 SET_NETDEV_DEV(ndev, &pdev->dev);
3222
3223 mdp = netdev_priv(ndev);
3224 mdp->num_tx_ring = TX_RING_SIZE;
3225 mdp->num_rx_ring = RX_RING_SIZE;
3226 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3227 if (IS_ERR(mdp->addr)) {
3228 ret = PTR_ERR(mdp->addr);
3229 goto out_release;
3230 }
3231
3232 ndev->base_addr = res->start;
3233
3234 spin_lock_init(&mdp->lock);
3235 mdp->pdev = pdev;
3236
3237 if (pdev->dev.of_node)
3238 pd = sh_eth_parse_dt(&pdev->dev);
3239 if (!pd) {
3240 dev_err(&pdev->dev, "no platform data\n");
3241 ret = -EINVAL;
3242 goto out_release;
3243 }
3244
3245 /* get PHY ID */
3246 mdp->phy_id = pd->phy;
3247 mdp->phy_interface = pd->phy_interface;
3248 mdp->no_ether_link = pd->no_ether_link;
3249 mdp->ether_link_active_low = pd->ether_link_active_low;
3250
3251 /* set cpu data */
3252 if (id)
3253 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3254 else
3255 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3256
3257 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3258 if (!mdp->reg_offset) {
3259 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3260 mdp->cd->register_type);
3261 ret = -EINVAL;
3262 goto out_release;
3263 }
3264 sh_eth_set_default_cpu_data(mdp->cd);
3265
3266 /* User's manual states max MTU should be 2048 but due to the
3267 * alignment calculations in sh_eth_ring_init() the practical
3268 * MTU is a bit less. Maybe this can be optimized some more.
3269 */
3270 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3271 ndev->min_mtu = ETH_MIN_MTU;
3272
3273 if (mdp->cd->rx_csum) {
3274 ndev->features = NETIF_F_RXCSUM;
3275 ndev->hw_features = NETIF_F_RXCSUM;
3276 }
3277
3278 /* set function */
3279 if (mdp->cd->tsu)
3280 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3281 else
3282 ndev->netdev_ops = &sh_eth_netdev_ops;
3283 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3284 ndev->watchdog_timeo = TX_TIMEOUT;
3285
3286 /* debug message level */
3287 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3288
3289 /* read and set MAC address */
3290 read_mac_address(ndev, pd->mac_addr);
3291 if (!is_valid_ether_addr(ndev->dev_addr)) {
3292 dev_warn(&pdev->dev,
3293 "no valid MAC address supplied, using a random one.\n");
3294 eth_hw_addr_random(ndev);
3295 }
3296
3297 if (mdp->cd->tsu) {
3298 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3299 struct resource *rtsu;
3300
3301 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3302 if (!rtsu) {
3303 dev_err(&pdev->dev, "no TSU resource\n");
3304 ret = -ENODEV;
3305 goto out_release;
3306 }
3307 /* We can only request the TSU region for the first port
3308 * of the two sharing this TSU for the probe to succeed...
3309 */
3310 if (port == 0 &&
3311 !devm_request_mem_region(&pdev->dev, rtsu->start,
3312 resource_size(rtsu),
3313 dev_name(&pdev->dev))) {
3314 dev_err(&pdev->dev, "can't request TSU resource.\n");
3315 ret = -EBUSY;
3316 goto out_release;
3317 }
3318 /* ioremap the TSU registers */
3319 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3320 resource_size(rtsu));
3321 if (!mdp->tsu_addr) {
3322 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3323 ret = -ENOMEM;
3324 goto out_release;
3325 }
3326 mdp->port = port;
3327 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3328
3329 /* Need to init only the first port of the two sharing a TSU */
3330 if (port == 0) {
3331 if (mdp->cd->chip_reset)
3332 mdp->cd->chip_reset(ndev);
3333
3334 /* TSU init (Init only)*/
3335 sh_eth_tsu_init(mdp);
3336 }
3337 }
3338
3339 if (mdp->cd->rmiimode)
3340 sh_eth_write(ndev, 0x1, RMIIMODE);
3341
3342 /* MDIO bus init */
3343 ret = sh_mdio_init(mdp, pd);
3344 if (ret) {
3345 if (ret != -EPROBE_DEFER)
3346 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3347 goto out_release;
3348 }
3349
3350 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3351
3352 /* network device register */
3353 ret = register_netdev(ndev);
3354 if (ret)
3355 goto out_napi_del;
3356
3357 if (mdp->cd->magic)
3358 device_set_wakeup_capable(&pdev->dev, 1);
3359
3360 /* print device information */
3361 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3362 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3363
3364 pm_runtime_put(&pdev->dev);
3365 platform_set_drvdata(pdev, ndev);
3366
3367 return ret;
3368
3369 out_napi_del:
3370 netif_napi_del(&mdp->napi);
3371 sh_mdio_release(mdp);
3372
3373 out_release:
3374 /* net_dev free */
3375 free_netdev(ndev);
3376
3377 pm_runtime_put(&pdev->dev);
3378 pm_runtime_disable(&pdev->dev);
3379 return ret;
3380 }
3381
sh_eth_drv_remove(struct platform_device * pdev)3382 static int sh_eth_drv_remove(struct platform_device *pdev)
3383 {
3384 struct net_device *ndev = platform_get_drvdata(pdev);
3385 struct sh_eth_private *mdp = netdev_priv(ndev);
3386
3387 unregister_netdev(ndev);
3388 netif_napi_del(&mdp->napi);
3389 sh_mdio_release(mdp);
3390 pm_runtime_disable(&pdev->dev);
3391 free_netdev(ndev);
3392
3393 return 0;
3394 }
3395
3396 #ifdef CONFIG_PM
3397 #ifdef CONFIG_PM_SLEEP
sh_eth_wol_setup(struct net_device * ndev)3398 static int sh_eth_wol_setup(struct net_device *ndev)
3399 {
3400 struct sh_eth_private *mdp = netdev_priv(ndev);
3401
3402 /* Only allow ECI interrupts */
3403 synchronize_irq(ndev->irq);
3404 napi_disable(&mdp->napi);
3405 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3406
3407 /* Enable MagicPacket */
3408 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3409
3410 return enable_irq_wake(ndev->irq);
3411 }
3412
sh_eth_wol_restore(struct net_device * ndev)3413 static int sh_eth_wol_restore(struct net_device *ndev)
3414 {
3415 struct sh_eth_private *mdp = netdev_priv(ndev);
3416 int ret;
3417
3418 napi_enable(&mdp->napi);
3419
3420 /* Disable MagicPacket */
3421 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3422
3423 /* The device needs to be reset to restore MagicPacket logic
3424 * for next wakeup. If we close and open the device it will
3425 * both be reset and all registers restored. This is what
3426 * happens during suspend and resume without WoL enabled.
3427 */
3428 ret = sh_eth_close(ndev);
3429 if (ret < 0)
3430 return ret;
3431 ret = sh_eth_open(ndev);
3432 if (ret < 0)
3433 return ret;
3434
3435 return disable_irq_wake(ndev->irq);
3436 }
3437
sh_eth_suspend(struct device * dev)3438 static int sh_eth_suspend(struct device *dev)
3439 {
3440 struct net_device *ndev = dev_get_drvdata(dev);
3441 struct sh_eth_private *mdp = netdev_priv(ndev);
3442 int ret = 0;
3443
3444 if (!netif_running(ndev))
3445 return 0;
3446
3447 netif_device_detach(ndev);
3448
3449 if (mdp->wol_enabled)
3450 ret = sh_eth_wol_setup(ndev);
3451 else
3452 ret = sh_eth_close(ndev);
3453
3454 return ret;
3455 }
3456
sh_eth_resume(struct device * dev)3457 static int sh_eth_resume(struct device *dev)
3458 {
3459 struct net_device *ndev = dev_get_drvdata(dev);
3460 struct sh_eth_private *mdp = netdev_priv(ndev);
3461 int ret = 0;
3462
3463 if (!netif_running(ndev))
3464 return 0;
3465
3466 if (mdp->wol_enabled)
3467 ret = sh_eth_wol_restore(ndev);
3468 else
3469 ret = sh_eth_open(ndev);
3470
3471 if (ret < 0)
3472 return ret;
3473
3474 netif_device_attach(ndev);
3475
3476 return ret;
3477 }
3478 #endif
3479
sh_eth_runtime_nop(struct device * dev)3480 static int sh_eth_runtime_nop(struct device *dev)
3481 {
3482 /* Runtime PM callback shared between ->runtime_suspend()
3483 * and ->runtime_resume(). Simply returns success.
3484 *
3485 * This driver re-initializes all registers after
3486 * pm_runtime_get_sync() anyway so there is no need
3487 * to save and restore registers here.
3488 */
3489 return 0;
3490 }
3491
3492 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3493 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3494 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3495 };
3496 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3497 #else
3498 #define SH_ETH_PM_OPS NULL
3499 #endif
3500
3501 static const struct platform_device_id sh_eth_id_table[] = {
3502 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3503 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3504 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3505 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3506 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3507 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3508 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3509 { }
3510 };
3511 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3512
3513 static struct platform_driver sh_eth_driver = {
3514 .probe = sh_eth_drv_probe,
3515 .remove = sh_eth_drv_remove,
3516 .id_table = sh_eth_id_table,
3517 .driver = {
3518 .name = CARDNAME,
3519 .pm = SH_ETH_PM_OPS,
3520 .of_match_table = of_match_ptr(sh_eth_match_table),
3521 },
3522 };
3523
3524 module_platform_driver(sh_eth_driver);
3525
3526 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3527 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3528 MODULE_LICENSE("GPL v2");
3529