1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/types.h>
64 #include <linux/slab.h>
65 #include <linux/export.h>
66 #include <linux/etherdevice.h>
67 #include <linux/pci.h>
68 #include <linux/firmware.h>
69
70 #include "iwl-drv.h"
71 #include "iwl-modparams.h"
72 #include "iwl-nvm-parse.h"
73 #include "iwl-prph.h"
74 #include "iwl-io.h"
75 #include "iwl-csr.h"
76 #include "fw/acpi.h"
77 #include "fw/api/nvm-reg.h"
78 #include "fw/api/commands.h"
79 #include "fw/api/cmdhdr.h"
80 #include "fw/img.h"
81
82 /* NVM offsets (in words) definitions */
83 enum nvm_offsets {
84 /* NVM HW-Section offset (in words) definitions */
85 SUBSYSTEM_ID = 0x0A,
86 HW_ADDR = 0x15,
87
88 /* NVM SW-Section offset (in words) definitions */
89 NVM_SW_SECTION = 0x1C0,
90 NVM_VERSION = 0,
91 RADIO_CFG = 1,
92 SKU = 2,
93 N_HW_ADDRS = 3,
94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
95
96 /* NVM calibration section offset (in words) definitions */
97 NVM_CALIB_SECTION = 0x2B8,
98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
99
100 /* NVM REGULATORY -Section offset (in words) definitions */
101 NVM_CHANNELS_SDP = 0,
102 };
103
104 enum ext_nvm_offsets {
105 /* NVM HW-Section offset (in words) definitions */
106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
107
108 /* NVM SW-Section offset (in words) definitions */
109 NVM_VERSION_EXT_NVM = 0,
110 RADIO_CFG_FAMILY_EXT_NVM = 0,
111 SKU_FAMILY_8000 = 2,
112 N_HW_ADDRS_FAMILY_8000 = 3,
113
114 /* NVM REGULATORY -Section offset (in words) definitions */
115 NVM_CHANNELS_EXTENDED = 0,
116 NVM_LAR_OFFSET_OLD = 0x4C7,
117 NVM_LAR_OFFSET = 0x507,
118 NVM_LAR_ENABLED = 0x7,
119 };
120
121 /* SKU Capabilities (actual values from NVM definition) */
122 enum nvm_sku_bits {
123 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
124 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
125 NVM_SKU_CAP_11N_ENABLE = BIT(2),
126 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
128 };
129
130 /*
131 * These are the channel numbers in the order that they are stored in the NVM
132 */
133 static const u16 iwl_nvm_channels[] = {
134 /* 2.4 GHz */
135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
136 /* 5 GHz */
137 36, 40, 44 , 48, 52, 56, 60, 64,
138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
139 149, 153, 157, 161, 165
140 };
141
142 static const u16 iwl_ext_nvm_channels[] = {
143 /* 2.4 GHz */
144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
145 /* 5 GHz */
146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
148 149, 153, 157, 161, 165, 169, 173, 177, 181
149 };
150
151 static const u16 iwl_uhb_nvm_channels[] = {
152 /* 2.4 GHz */
153 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
154 /* 5 GHz */
155 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
156 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
157 149, 153, 157, 161, 165, 169, 173, 177, 181,
158 /* 6-7 GHz */
159 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
160 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
161 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
162 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
163 };
164
165 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
166 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
167 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
168 #define NUM_2GHZ_CHANNELS 14
169 #define FIRST_2GHZ_HT_MINUS 5
170 #define LAST_2GHZ_HT_PLUS 9
171 #define N_HW_ADDR_MASK 0xF
172
173 /* rate data (static) */
174 static struct ieee80211_rate iwl_cfg80211_rates[] = {
175 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
176 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
177 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
178 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
179 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
180 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
181 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
182 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
183 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
184 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
185 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
186 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
187 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
188 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
189 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
190 };
191 #define RATES_24_OFFS 0
192 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
193 #define RATES_52_OFFS 4
194 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
195
196 /**
197 * enum iwl_nvm_channel_flags - channel flags in NVM
198 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
199 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
200 * @NVM_CHANNEL_ACTIVE: active scanning allowed
201 * @NVM_CHANNEL_RADAR: radar detection required
202 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
203 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
204 * on same channel on 2.4 or same UNII band on 5.2
205 * @NVM_CHANNEL_UNIFORM: uniform spreading required
206 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
207 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
208 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
209 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
210 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
211 */
212 enum iwl_nvm_channel_flags {
213 NVM_CHANNEL_VALID = BIT(0),
214 NVM_CHANNEL_IBSS = BIT(1),
215 NVM_CHANNEL_ACTIVE = BIT(3),
216 NVM_CHANNEL_RADAR = BIT(4),
217 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
218 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
219 NVM_CHANNEL_UNIFORM = BIT(7),
220 NVM_CHANNEL_20MHZ = BIT(8),
221 NVM_CHANNEL_40MHZ = BIT(9),
222 NVM_CHANNEL_80MHZ = BIT(10),
223 NVM_CHANNEL_160MHZ = BIT(11),
224 NVM_CHANNEL_DC_HIGH = BIT(12),
225 };
226
227 /**
228 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
229 * domain.
230 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
231 * 2.4Ghz band is allowed.
232 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
233 * 5Ghz band is allowed.
234 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
235 * for this regulatory domain (valid only in 5Ghz).
236 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
237 * for this regulatory domain (valid only in 5Ghz).
238 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
239 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
240 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
241 * for this regulatory domain (valid only in 5Ghz).
242 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
243 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
244 */
245 enum iwl_reg_capa_flags {
246 REG_CAPA_BF_CCD_LOW_BAND = BIT(0),
247 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1),
248 REG_CAPA_160MHZ_ALLOWED = BIT(2),
249 REG_CAPA_80MHZ_ALLOWED = BIT(3),
250 REG_CAPA_MCS_8_ALLOWED = BIT(4),
251 REG_CAPA_MCS_9_ALLOWED = BIT(5),
252 REG_CAPA_40MHZ_FORBIDDEN = BIT(7),
253 REG_CAPA_DC_HIGH_ENABLED = BIT(9),
254 REG_CAPA_11AX_DISABLED = BIT(10),
255 };
256
257 /**
258 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
259 * domain (version 2).
260 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are
261 * disabled.
262 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
263 * 2.4Ghz band is allowed.
264 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
265 * 5Ghz band is allowed.
266 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
267 * for this regulatory domain (valid only in 5Ghz).
268 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
269 * for this regulatory domain (valid only in 5Ghz).
270 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
271 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
272 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118,
273 * 126, 122) are disabled.
274 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed
275 * for this regulatory domain (uvalid only in 5Ghz).
276 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
277 */
278 enum iwl_reg_capa_flags_v2 {
279 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0),
280 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1),
281 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2),
282 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3),
283 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4),
284 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5),
285 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6),
286 REG_CAPA_V2_WEATHER_DISABLED = BIT(7),
287 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8),
288 REG_CAPA_V2_11AX_DISABLED = BIT(10),
289 };
290
291 /*
292 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the
293 * MCC update command response.
294 */
295 #define REG_CAPA_V2_RESP_VER 6
296
297 /**
298 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for
299 * handling the different APIs of reg_capa_flags.
300 *
301 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed
302 * for this regulatory domain (valid only in 5Ghz).
303 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
304 * for this regulatory domain (valid only in 5Ghz).
305 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
306 * for this regulatory domain (valid only in 5Ghz).
307 * @disable_11ax: 11ax is forbidden for this regulatory domain.
308 */
309 struct iwl_reg_capa {
310 u16 allow_40mhz;
311 u16 allow_80mhz;
312 u16 allow_160mhz;
313 u16 disable_11ax;
314 };
315
iwl_nvm_print_channel_flags(struct device * dev,u32 level,int chan,u32 flags)316 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
317 int chan, u32 flags)
318 {
319 #define CHECK_AND_PRINT_I(x) \
320 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
321
322 if (!(flags & NVM_CHANNEL_VALID)) {
323 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
324 chan, flags);
325 return;
326 }
327
328 /* Note: already can print up to 101 characters, 110 is the limit! */
329 IWL_DEBUG_DEV(dev, level,
330 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
331 chan, flags,
332 CHECK_AND_PRINT_I(VALID),
333 CHECK_AND_PRINT_I(IBSS),
334 CHECK_AND_PRINT_I(ACTIVE),
335 CHECK_AND_PRINT_I(RADAR),
336 CHECK_AND_PRINT_I(INDOOR_ONLY),
337 CHECK_AND_PRINT_I(GO_CONCURRENT),
338 CHECK_AND_PRINT_I(UNIFORM),
339 CHECK_AND_PRINT_I(20MHZ),
340 CHECK_AND_PRINT_I(40MHZ),
341 CHECK_AND_PRINT_I(80MHZ),
342 CHECK_AND_PRINT_I(160MHZ),
343 CHECK_AND_PRINT_I(DC_HIGH));
344 #undef CHECK_AND_PRINT_I
345 }
346
iwl_get_channel_flags(u8 ch_num,int ch_idx,enum nl80211_band band,u32 nvm_flags,const struct iwl_cfg * cfg)347 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
348 u32 nvm_flags, const struct iwl_cfg *cfg)
349 {
350 u32 flags = IEEE80211_CHAN_NO_HT40;
351
352 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
353 if (ch_num <= LAST_2GHZ_HT_PLUS)
354 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
355 if (ch_num >= FIRST_2GHZ_HT_MINUS)
356 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
357 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
358 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
359 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
360 else
361 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
362 }
363 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
364 flags |= IEEE80211_CHAN_NO_80MHZ;
365 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
366 flags |= IEEE80211_CHAN_NO_160MHZ;
367
368 if (!(nvm_flags & NVM_CHANNEL_IBSS))
369 flags |= IEEE80211_CHAN_NO_IR;
370
371 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
372 flags |= IEEE80211_CHAN_NO_IR;
373
374 if (nvm_flags & NVM_CHANNEL_RADAR)
375 flags |= IEEE80211_CHAN_RADAR;
376
377 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
378 flags |= IEEE80211_CHAN_INDOOR_ONLY;
379
380 /* Set the GO concurrent flag only in case that NO_IR is set.
381 * Otherwise it is meaningless
382 */
383 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
384 (flags & IEEE80211_CHAN_NO_IR))
385 flags |= IEEE80211_CHAN_IR_CONCURRENT;
386
387 return flags;
388 }
389
iwl_nl80211_band_from_channel_idx(int ch_idx)390 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
391 {
392 if (ch_idx >= NUM_2GHZ_CHANNELS)
393 return NL80211_BAND_5GHZ;
394 return NL80211_BAND_2GHZ;
395 }
396
iwl_init_channel_map(struct device * dev,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const void * const nvm_ch_flags,u32 sbands_flags,bool v4)397 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
398 struct iwl_nvm_data *data,
399 const void * const nvm_ch_flags,
400 u32 sbands_flags, bool v4)
401 {
402 int ch_idx;
403 int n_channels = 0;
404 struct ieee80211_channel *channel;
405 u32 ch_flags;
406 int num_of_ch;
407 const u16 *nvm_chan;
408
409 if (cfg->uhb_supported) {
410 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
411 nvm_chan = iwl_uhb_nvm_channels;
412 } else if (cfg->nvm_type == IWL_NVM_EXT) {
413 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
414 nvm_chan = iwl_ext_nvm_channels;
415 } else {
416 num_of_ch = IWL_NVM_NUM_CHANNELS;
417 nvm_chan = iwl_nvm_channels;
418 }
419
420 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
421 enum nl80211_band band =
422 iwl_nl80211_band_from_channel_idx(ch_idx);
423
424 if (v4)
425 ch_flags =
426 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
427 else
428 ch_flags =
429 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
430
431 if (band == NL80211_BAND_5GHZ &&
432 !data->sku_cap_band_52ghz_enable)
433 continue;
434
435 /* workaround to disable wide channels in 5GHz */
436 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
437 band == NL80211_BAND_5GHZ) {
438 ch_flags &= ~(NVM_CHANNEL_40MHZ |
439 NVM_CHANNEL_80MHZ |
440 NVM_CHANNEL_160MHZ);
441 }
442
443 if (ch_flags & NVM_CHANNEL_160MHZ)
444 data->vht160_supported = true;
445
446 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
447 !(ch_flags & NVM_CHANNEL_VALID)) {
448 /*
449 * Channels might become valid later if lar is
450 * supported, hence we still want to add them to
451 * the list of supported channels to cfg80211.
452 */
453 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
454 nvm_chan[ch_idx], ch_flags);
455 continue;
456 }
457
458 channel = &data->channels[n_channels];
459 n_channels++;
460
461 channel->hw_value = nvm_chan[ch_idx];
462 channel->band = band;
463 channel->center_freq =
464 ieee80211_channel_to_frequency(
465 channel->hw_value, channel->band);
466
467 /* Initialize regulatory-based run-time data */
468
469 /*
470 * Default value - highest tx power value. max_power
471 * is not used in mvm, and is used for backwards compatibility
472 */
473 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
474
475 /* don't put limitations in case we're using LAR */
476 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
477 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
478 ch_idx, band,
479 ch_flags, cfg);
480 else
481 channel->flags = 0;
482
483 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
484 channel->hw_value, ch_flags);
485 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
486 channel->hw_value, channel->max_power);
487 }
488
489 return n_channels;
490 }
491
iwl_init_vht_hw_capab(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_sta_vht_cap * vht_cap,u8 tx_chains,u8 rx_chains)492 static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
493 struct iwl_nvm_data *data,
494 struct ieee80211_sta_vht_cap *vht_cap,
495 u8 tx_chains, u8 rx_chains)
496 {
497 const struct iwl_cfg *cfg = trans->cfg;
498 int num_rx_ants = num_of_ant(rx_chains);
499 int num_tx_ants = num_of_ant(tx_chains);
500 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
501 IEEE80211_VHT_MAX_AMPDU_1024K);
502
503 vht_cap->vht_supported = true;
504
505 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
506 IEEE80211_VHT_CAP_RXSTBC_1 |
507 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
508 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
509 max_ampdu_exponent <<
510 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
511
512 if (data->vht160_supported)
513 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
514 IEEE80211_VHT_CAP_SHORT_GI_160;
515
516 if (cfg->vht_mu_mimo_supported)
517 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
518
519 if (cfg->ht_params->ldpc)
520 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
521
522 if (data->sku_cap_mimo_disabled) {
523 num_rx_ants = 1;
524 num_tx_ants = 1;
525 }
526
527 if (num_tx_ants > 1)
528 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
529 else
530 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
531
532 switch (iwlwifi_mod_params.amsdu_size) {
533 case IWL_AMSDU_DEF:
534 if (trans->trans_cfg->mq_rx_supported)
535 vht_cap->cap |=
536 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
537 else
538 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
539 break;
540 case IWL_AMSDU_2K:
541 if (trans->trans_cfg->mq_rx_supported)
542 vht_cap->cap |=
543 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
544 else
545 WARN(1, "RB size of 2K is not supported by this device\n");
546 break;
547 case IWL_AMSDU_4K:
548 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
549 break;
550 case IWL_AMSDU_8K:
551 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
552 break;
553 case IWL_AMSDU_12K:
554 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
555 break;
556 default:
557 break;
558 }
559
560 vht_cap->vht_mcs.rx_mcs_map =
561 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
562 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
563 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
564 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
565 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
566 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
567 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
568 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
569
570 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
571 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
572 /* this works because NOT_SUPPORTED == 3 */
573 vht_cap->vht_mcs.rx_mcs_map |=
574 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
575 }
576
577 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
578
579 vht_cap->vht_mcs.tx_highest |=
580 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
581 }
582
583 static struct ieee80211_sband_iftype_data iwl_he_capa[] = {
584 {
585 .types_mask = BIT(NL80211_IFTYPE_STATION),
586 .he_cap = {
587 .has_he = true,
588 .he_cap_elem = {
589 .mac_cap_info[0] =
590 IEEE80211_HE_MAC_CAP0_HTC_HE,
591 .mac_cap_info[1] =
592 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
593 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
594 .mac_cap_info[2] =
595 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
596 .mac_cap_info[3] =
597 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
598 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
599 .mac_cap_info[4] =
600 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU |
601 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
602 .mac_cap_info[5] =
603 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
604 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
605 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
606 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
607 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
608 .phy_cap_info[0] =
609 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
610 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
611 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
612 .phy_cap_info[1] =
613 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
614 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
615 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
616 .phy_cap_info[2] =
617 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
618 .phy_cap_info[3] =
619 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
620 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
621 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
622 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
623 .phy_cap_info[4] =
624 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
625 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
626 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
627 .phy_cap_info[5] =
628 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
629 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
630 .phy_cap_info[6] =
631 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
632 .phy_cap_info[7] =
633 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
634 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
635 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
636 .phy_cap_info[8] =
637 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
638 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
639 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
640 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
641 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
642 .phy_cap_info[9] =
643 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
644 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
645 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
646 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
647 },
648 /*
649 * Set default Tx/Rx HE MCS NSS Support field.
650 * Indicate support for up to 2 spatial streams and all
651 * MCS, without any special cases
652 */
653 .he_mcs_nss_supp = {
654 .rx_mcs_80 = cpu_to_le16(0xfffa),
655 .tx_mcs_80 = cpu_to_le16(0xfffa),
656 .rx_mcs_160 = cpu_to_le16(0xfffa),
657 .tx_mcs_160 = cpu_to_le16(0xfffa),
658 .rx_mcs_80p80 = cpu_to_le16(0xffff),
659 .tx_mcs_80p80 = cpu_to_le16(0xffff),
660 },
661 /*
662 * Set default PPE thresholds, with PPET16 set to 0,
663 * PPET8 set to 7
664 */
665 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
666 },
667 },
668 {
669 .types_mask = BIT(NL80211_IFTYPE_AP),
670 .he_cap = {
671 .has_he = true,
672 .he_cap_elem = {
673 .mac_cap_info[0] =
674 IEEE80211_HE_MAC_CAP0_HTC_HE,
675 .mac_cap_info[1] =
676 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
677 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
678 .mac_cap_info[2] =
679 IEEE80211_HE_MAC_CAP2_BSR,
680 .mac_cap_info[3] =
681 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
682 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
683 .mac_cap_info[4] =
684 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU,
685 .mac_cap_info[5] =
686 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU,
687 .phy_cap_info[0] =
688 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
689 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
690 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
691 .phy_cap_info[1] =
692 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
693 .phy_cap_info[2] =
694 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
695 .phy_cap_info[3] =
696 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
697 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
698 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
699 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
700 .phy_cap_info[4] =
701 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
702 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
703 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
704 .phy_cap_info[5] =
705 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
706 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
707 .phy_cap_info[6] =
708 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
709 .phy_cap_info[7] =
710 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
711 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
712 .phy_cap_info[8] =
713 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
714 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
715 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
716 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
717 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
718 .phy_cap_info[9] =
719 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
720 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
721 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
722 },
723 /*
724 * Set default Tx/Rx HE MCS NSS Support field.
725 * Indicate support for up to 2 spatial streams and all
726 * MCS, without any special cases
727 */
728 .he_mcs_nss_supp = {
729 .rx_mcs_80 = cpu_to_le16(0xfffa),
730 .tx_mcs_80 = cpu_to_le16(0xfffa),
731 .rx_mcs_160 = cpu_to_le16(0xfffa),
732 .tx_mcs_160 = cpu_to_le16(0xfffa),
733 .rx_mcs_80p80 = cpu_to_le16(0xffff),
734 .tx_mcs_80p80 = cpu_to_le16(0xffff),
735 },
736 /*
737 * Set default PPE thresholds, with PPET16 set to 0,
738 * PPET8 set to 7
739 */
740 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
741 },
742 },
743 };
744
iwl_init_he_hw_capab(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_supported_band * sband,u8 tx_chains,u8 rx_chains)745 static void iwl_init_he_hw_capab(struct iwl_trans *trans,
746 struct iwl_nvm_data *data,
747 struct ieee80211_supported_band *sband,
748 u8 tx_chains, u8 rx_chains)
749 {
750 sband->iftype_data = iwl_he_capa;
751 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
752
753 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
754 if ((tx_chains & rx_chains) != ANT_AB) {
755 int i;
756
757 for (i = 0; i < sband->n_iftype_data; i++) {
758 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &=
759 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
760 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &=
761 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
762 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &=
763 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
764 }
765 }
766 }
767
iwl_init_sbands(struct iwl_trans * trans,struct iwl_nvm_data * data,const void * nvm_ch_flags,u8 tx_chains,u8 rx_chains,u32 sbands_flags,bool v4)768 static void iwl_init_sbands(struct iwl_trans *trans,
769 struct iwl_nvm_data *data,
770 const void *nvm_ch_flags, u8 tx_chains,
771 u8 rx_chains, u32 sbands_flags, bool v4)
772 {
773 struct device *dev = trans->dev;
774 const struct iwl_cfg *cfg = trans->cfg;
775 int n_channels;
776 int n_used = 0;
777 struct ieee80211_supported_band *sband;
778
779 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
780 sbands_flags, v4);
781 sband = &data->bands[NL80211_BAND_2GHZ];
782 sband->band = NL80211_BAND_2GHZ;
783 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
784 sband->n_bitrates = N_RATES_24;
785 n_used += iwl_init_sband_channels(data, sband, n_channels,
786 NL80211_BAND_2GHZ);
787 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
788 tx_chains, rx_chains);
789
790 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
791 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
792
793 sband = &data->bands[NL80211_BAND_5GHZ];
794 sband->band = NL80211_BAND_5GHZ;
795 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
796 sband->n_bitrates = N_RATES_52;
797 n_used += iwl_init_sband_channels(data, sband, n_channels,
798 NL80211_BAND_5GHZ);
799 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
800 tx_chains, rx_chains);
801 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
802 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
803 tx_chains, rx_chains);
804
805 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
806 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
807
808 if (n_channels != n_used)
809 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
810 n_used, n_channels);
811 }
812
iwl_get_sku(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)813 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
814 const __le16 *phy_sku)
815 {
816 if (cfg->nvm_type != IWL_NVM_EXT)
817 return le16_to_cpup(nvm_sw + SKU);
818
819 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
820 }
821
iwl_get_nvm_version(const struct iwl_cfg * cfg,const __le16 * nvm_sw)822 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
823 {
824 if (cfg->nvm_type != IWL_NVM_EXT)
825 return le16_to_cpup(nvm_sw + NVM_VERSION);
826 else
827 return le32_to_cpup((__le32 *)(nvm_sw +
828 NVM_VERSION_EXT_NVM));
829 }
830
iwl_get_radio_cfg(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)831 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
832 const __le16 *phy_sku)
833 {
834 if (cfg->nvm_type != IWL_NVM_EXT)
835 return le16_to_cpup(nvm_sw + RADIO_CFG);
836
837 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
838
839 }
840
iwl_get_n_hw_addrs(const struct iwl_cfg * cfg,const __le16 * nvm_sw)841 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
842 {
843 int n_hw_addr;
844
845 if (cfg->nvm_type != IWL_NVM_EXT)
846 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
847
848 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
849
850 return n_hw_addr & N_HW_ADDR_MASK;
851 }
852
iwl_set_radio_cfg(const struct iwl_cfg * cfg,struct iwl_nvm_data * data,u32 radio_cfg)853 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
854 struct iwl_nvm_data *data,
855 u32 radio_cfg)
856 {
857 if (cfg->nvm_type != IWL_NVM_EXT) {
858 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
859 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
860 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
861 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
862 return;
863 }
864
865 /* set the radio configuration for family 8000 */
866 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
867 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
868 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
869 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
870 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
871 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
872 }
873
iwl_flip_hw_address(__le32 mac_addr0,__le32 mac_addr1,u8 * dest)874 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
875 {
876 const u8 *hw_addr;
877
878 hw_addr = (const u8 *)&mac_addr0;
879 dest[0] = hw_addr[3];
880 dest[1] = hw_addr[2];
881 dest[2] = hw_addr[1];
882 dest[3] = hw_addr[0];
883
884 hw_addr = (const u8 *)&mac_addr1;
885 dest[4] = hw_addr[1];
886 dest[5] = hw_addr[0];
887 }
888
iwl_set_hw_address_from_csr(struct iwl_trans * trans,struct iwl_nvm_data * data)889 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
890 struct iwl_nvm_data *data)
891 {
892 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
893 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
894
895 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
896 /*
897 * If the OEM fused a valid address, use it instead of the one in the
898 * OTP
899 */
900 if (is_valid_ether_addr(data->hw_addr))
901 return;
902
903 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
904 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
905
906 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
907 }
908
iwl_set_hw_address_family_8000(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __le16 * mac_override,const __be16 * nvm_hw)909 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
910 const struct iwl_cfg *cfg,
911 struct iwl_nvm_data *data,
912 const __le16 *mac_override,
913 const __be16 *nvm_hw)
914 {
915 const u8 *hw_addr;
916
917 if (mac_override) {
918 static const u8 reserved_mac[] = {
919 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
920 };
921
922 hw_addr = (const u8 *)(mac_override +
923 MAC_ADDRESS_OVERRIDE_EXT_NVM);
924
925 /*
926 * Store the MAC address from MAO section.
927 * No byte swapping is required in MAO section
928 */
929 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
930
931 /*
932 * Force the use of the OTP MAC address in case of reserved MAC
933 * address in the NVM, or if address is given but invalid.
934 */
935 if (is_valid_ether_addr(data->hw_addr) &&
936 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
937 return;
938
939 IWL_ERR(trans,
940 "mac address from nvm override section is not valid\n");
941 }
942
943 if (nvm_hw) {
944 /* read the mac address from WFMP registers */
945 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
946 WFMP_MAC_ADDR_0));
947 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
948 WFMP_MAC_ADDR_1));
949
950 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
951
952 return;
953 }
954
955 IWL_ERR(trans, "mac address is not found\n");
956 }
957
iwl_set_hw_address(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __be16 * nvm_hw,const __le16 * mac_override)958 static int iwl_set_hw_address(struct iwl_trans *trans,
959 const struct iwl_cfg *cfg,
960 struct iwl_nvm_data *data, const __be16 *nvm_hw,
961 const __le16 *mac_override)
962 {
963 if (cfg->mac_addr_from_csr) {
964 iwl_set_hw_address_from_csr(trans, data);
965 } else if (cfg->nvm_type != IWL_NVM_EXT) {
966 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
967
968 /* The byte order is little endian 16 bit, meaning 214365 */
969 data->hw_addr[0] = hw_addr[1];
970 data->hw_addr[1] = hw_addr[0];
971 data->hw_addr[2] = hw_addr[3];
972 data->hw_addr[3] = hw_addr[2];
973 data->hw_addr[4] = hw_addr[5];
974 data->hw_addr[5] = hw_addr[4];
975 } else {
976 iwl_set_hw_address_family_8000(trans, cfg, data,
977 mac_override, nvm_hw);
978 }
979
980 if (!is_valid_ether_addr(data->hw_addr)) {
981 IWL_ERR(trans, "no valid mac address was found\n");
982 return -EINVAL;
983 }
984
985 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
986
987 return 0;
988 }
989
990 static bool
iwl_nvm_no_wide_in_5ghz(struct iwl_trans * trans,const struct iwl_cfg * cfg,const __be16 * nvm_hw)991 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
992 const __be16 *nvm_hw)
993 {
994 /*
995 * Workaround a bug in Indonesia SKUs where the regulatory in
996 * some 7000-family OTPs erroneously allow wide channels in
997 * 5GHz. To check for Indonesia, we take the SKU value from
998 * bits 1-4 in the subsystem ID and check if it is either 5 or
999 * 9. In those cases, we need to force-disable wide channels
1000 * in 5GHz otherwise the FW will throw a sysassert when we try
1001 * to use them.
1002 */
1003 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1004 /*
1005 * Unlike the other sections in the NVM, the hw
1006 * section uses big-endian.
1007 */
1008 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
1009 u8 sku = (subsystem_id & 0x1e) >> 1;
1010
1011 if (sku == 5 || sku == 9) {
1012 IWL_DEBUG_EEPROM(trans->dev,
1013 "disabling wide channels in 5GHz (0x%0x %d)\n",
1014 subsystem_id, sku);
1015 return true;
1016 }
1017 }
1018
1019 return false;
1020 }
1021
1022 struct iwl_nvm_data *
iwl_parse_nvm_data(struct iwl_trans * trans,const struct iwl_cfg * cfg,const struct iwl_fw * fw,const __be16 * nvm_hw,const __le16 * nvm_sw,const __le16 * nvm_calib,const __le16 * regulatory,const __le16 * mac_override,const __le16 * phy_sku,u8 tx_chains,u8 rx_chains)1023 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1024 const struct iwl_fw *fw,
1025 const __be16 *nvm_hw, const __le16 *nvm_sw,
1026 const __le16 *nvm_calib, const __le16 *regulatory,
1027 const __le16 *mac_override, const __le16 *phy_sku,
1028 u8 tx_chains, u8 rx_chains)
1029 {
1030 struct iwl_nvm_data *data;
1031 bool lar_enabled;
1032 u32 sku, radio_cfg;
1033 u32 sbands_flags = 0;
1034 u16 lar_config;
1035 const __le16 *ch_section;
1036
1037 if (cfg->uhb_supported)
1038 data = kzalloc(struct_size(data, channels,
1039 IWL_NVM_NUM_CHANNELS_UHB),
1040 GFP_KERNEL);
1041 else if (cfg->nvm_type != IWL_NVM_EXT)
1042 data = kzalloc(struct_size(data, channels,
1043 IWL_NVM_NUM_CHANNELS),
1044 GFP_KERNEL);
1045 else
1046 data = kzalloc(struct_size(data, channels,
1047 IWL_NVM_NUM_CHANNELS_EXT),
1048 GFP_KERNEL);
1049 if (!data)
1050 return NULL;
1051
1052 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1053
1054 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1055 iwl_set_radio_cfg(cfg, data, radio_cfg);
1056 if (data->valid_tx_ant)
1057 tx_chains &= data->valid_tx_ant;
1058 if (data->valid_rx_ant)
1059 rx_chains &= data->valid_rx_ant;
1060
1061 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1062 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1063 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1064 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1065 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1066 data->sku_cap_11n_enable = false;
1067 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1068 (sku & NVM_SKU_CAP_11AC_ENABLE);
1069 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1070
1071 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1072
1073 if (cfg->nvm_type != IWL_NVM_EXT) {
1074 /* Checking for required sections */
1075 if (!nvm_calib) {
1076 IWL_ERR(trans,
1077 "Can't parse empty Calib NVM sections\n");
1078 kfree(data);
1079 return NULL;
1080 }
1081
1082 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1083 ®ulatory[NVM_CHANNELS_SDP] :
1084 &nvm_sw[NVM_CHANNELS];
1085
1086 /* in family 8000 Xtal calibration values moved to OTP */
1087 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1088 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1089 lar_enabled = true;
1090 } else {
1091 u16 lar_offset = data->nvm_version < 0xE39 ?
1092 NVM_LAR_OFFSET_OLD :
1093 NVM_LAR_OFFSET;
1094
1095 lar_config = le16_to_cpup(regulatory + lar_offset);
1096 data->lar_enabled = !!(lar_config &
1097 NVM_LAR_ENABLED);
1098 lar_enabled = data->lar_enabled;
1099 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED];
1100 }
1101
1102 /* If no valid mac address was found - bail out */
1103 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1104 kfree(data);
1105 return NULL;
1106 }
1107
1108 if (lar_enabled &&
1109 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1110 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1111
1112 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1113 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1114
1115 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1116 sbands_flags, false);
1117 data->calib_version = 255;
1118
1119 return data;
1120 }
1121 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1122
iwl_nvm_get_regdom_bw_flags(const u16 * nvm_chan,int ch_idx,u16 nvm_flags,struct iwl_reg_capa reg_capa,const struct iwl_cfg * cfg)1123 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1124 int ch_idx, u16 nvm_flags,
1125 struct iwl_reg_capa reg_capa,
1126 const struct iwl_cfg *cfg)
1127 {
1128 u32 flags = NL80211_RRF_NO_HT40;
1129
1130 if (ch_idx < NUM_2GHZ_CHANNELS &&
1131 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1132 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1133 flags &= ~NL80211_RRF_NO_HT40PLUS;
1134 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1135 flags &= ~NL80211_RRF_NO_HT40MINUS;
1136 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1137 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1138 flags &= ~NL80211_RRF_NO_HT40PLUS;
1139 else
1140 flags &= ~NL80211_RRF_NO_HT40MINUS;
1141 }
1142
1143 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1144 flags |= NL80211_RRF_NO_80MHZ;
1145 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1146 flags |= NL80211_RRF_NO_160MHZ;
1147
1148 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1149 flags |= NL80211_RRF_NO_IR;
1150
1151 if (nvm_flags & NVM_CHANNEL_RADAR)
1152 flags |= NL80211_RRF_DFS;
1153
1154 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1155 flags |= NL80211_RRF_NO_OUTDOOR;
1156
1157 /* Set the GO concurrent flag only in case that NO_IR is set.
1158 * Otherwise it is meaningless
1159 */
1160 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1161 (flags & NL80211_RRF_NO_IR))
1162 flags |= NL80211_RRF_GO_CONCURRENT;
1163
1164 /*
1165 * reg_capa is per regulatory domain so apply it for every channel
1166 */
1167 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1168 if (!reg_capa.allow_40mhz)
1169 flags |= NL80211_RRF_NO_HT40;
1170
1171 if (!reg_capa.allow_80mhz)
1172 flags |= NL80211_RRF_NO_80MHZ;
1173
1174 if (!reg_capa.allow_160mhz)
1175 flags |= NL80211_RRF_NO_160MHZ;
1176 }
1177 if (reg_capa.disable_11ax)
1178 flags |= NL80211_RRF_NO_HE;
1179
1180 return flags;
1181 }
1182
iwl_get_reg_capa(u16 flags,u8 resp_ver)1183 static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver)
1184 {
1185 struct iwl_reg_capa reg_capa;
1186
1187 if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1188 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1189 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1190 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1191 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1192 } else {
1193 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN);
1194 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED;
1195 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED;
1196 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED;
1197 }
1198 return reg_capa;
1199 }
1200
1201 struct ieee80211_regdomain *
iwl_parse_nvm_mcc_info(struct device * dev,const struct iwl_cfg * cfg,int num_of_ch,__le32 * channels,u16 fw_mcc,u16 geo_info,u16 cap,u8 resp_ver)1202 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1203 int num_of_ch, __le32 *channels, u16 fw_mcc,
1204 u16 geo_info, u16 cap, u8 resp_ver)
1205 {
1206 int ch_idx;
1207 u16 ch_flags;
1208 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1209 const u16 *nvm_chan;
1210 struct ieee80211_regdomain *regd, *copy_rd;
1211 struct ieee80211_reg_rule *rule;
1212 enum nl80211_band band;
1213 int center_freq, prev_center_freq = 0;
1214 int valid_rules = 0;
1215 bool new_rule;
1216 int max_num_ch;
1217 struct iwl_reg_capa reg_capa;
1218
1219 if (cfg->uhb_supported) {
1220 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1221 nvm_chan = iwl_uhb_nvm_channels;
1222 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1223 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1224 nvm_chan = iwl_ext_nvm_channels;
1225 } else {
1226 max_num_ch = IWL_NVM_NUM_CHANNELS;
1227 nvm_chan = iwl_nvm_channels;
1228 }
1229
1230 if (WARN_ON(num_of_ch > max_num_ch))
1231 num_of_ch = max_num_ch;
1232
1233 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1234 return ERR_PTR(-EINVAL);
1235
1236 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1237 num_of_ch);
1238
1239 /* build a regdomain rule for every valid channel */
1240 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1241 if (!regd)
1242 return ERR_PTR(-ENOMEM);
1243
1244 /* set alpha2 from FW. */
1245 regd->alpha2[0] = fw_mcc >> 8;
1246 regd->alpha2[1] = fw_mcc & 0xff;
1247
1248 /* parse regulatory capability flags */
1249 reg_capa = iwl_get_reg_capa(cap, resp_ver);
1250
1251 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1252 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1253 band = iwl_nl80211_band_from_channel_idx(ch_idx);
1254 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1255 band);
1256 new_rule = false;
1257
1258 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1259 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1260 nvm_chan[ch_idx], ch_flags);
1261 continue;
1262 }
1263
1264 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1265 ch_flags, reg_capa,
1266 cfg);
1267
1268 /* we can't continue the same rule */
1269 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1270 center_freq - prev_center_freq > 20) {
1271 valid_rules++;
1272 new_rule = true;
1273 }
1274
1275 rule = ®d->reg_rules[valid_rules - 1];
1276
1277 if (new_rule)
1278 rule->freq_range.start_freq_khz =
1279 MHZ_TO_KHZ(center_freq - 10);
1280
1281 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1282
1283 /* this doesn't matter - not used by FW */
1284 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1285 rule->power_rule.max_eirp =
1286 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1287
1288 rule->flags = reg_rule_flags;
1289
1290 /* rely on auto-calculation to merge BW of contiguous chans */
1291 rule->flags |= NL80211_RRF_AUTO_BW;
1292 rule->freq_range.max_bandwidth_khz = 0;
1293
1294 prev_center_freq = center_freq;
1295 prev_reg_rule_flags = reg_rule_flags;
1296
1297 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1298 nvm_chan[ch_idx], ch_flags);
1299
1300 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1301 band == NL80211_BAND_2GHZ)
1302 continue;
1303
1304 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1305 }
1306
1307 regd->n_reg_rules = valid_rules;
1308
1309 /*
1310 * Narrow down regdom for unused regulatory rules to prevent hole
1311 * between reg rules to wmm rules.
1312 */
1313 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1314 GFP_KERNEL);
1315 if (!copy_rd)
1316 copy_rd = ERR_PTR(-ENOMEM);
1317
1318 kfree(regd);
1319 return copy_rd;
1320 }
1321 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1322
1323 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1324 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1325 #define MAX_NVM_FILE_LEN 16384
1326
iwl_nvm_fixups(u32 hw_id,unsigned int section,u8 * data,unsigned int len)1327 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1328 unsigned int len)
1329 {
1330 #define IWL_4165_DEVICE_ID 0x5501
1331 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1332
1333 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1334 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1335 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1336 /* OTP 0x52 bug work around: it's a 1x1 device */
1337 data[3] = ANT_B | (ANT_B << 4);
1338 }
1339 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1340
1341 /*
1342 * Reads external NVM from a file into mvm->nvm_sections
1343 *
1344 * HOW TO CREATE THE NVM FILE FORMAT:
1345 * ------------------------------
1346 * 1. create hex file, format:
1347 * 3800 -> header
1348 * 0000 -> header
1349 * 5a40 -> data
1350 *
1351 * rev - 6 bit (word1)
1352 * len - 10 bit (word1)
1353 * id - 4 bit (word2)
1354 * rsv - 12 bit (word2)
1355 *
1356 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1357 *
1358 * 3. create binary file from the hex file
1359 *
1360 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1361 */
iwl_read_external_nvm(struct iwl_trans * trans,const char * nvm_file_name,struct iwl_nvm_section * nvm_sections)1362 int iwl_read_external_nvm(struct iwl_trans *trans,
1363 const char *nvm_file_name,
1364 struct iwl_nvm_section *nvm_sections)
1365 {
1366 int ret, section_size;
1367 u16 section_id;
1368 const struct firmware *fw_entry;
1369 const struct {
1370 __le16 word1;
1371 __le16 word2;
1372 u8 data[];
1373 } *file_sec;
1374 const u8 *eof;
1375 u8 *temp;
1376 int max_section_size;
1377 const __le32 *dword_buff;
1378
1379 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1380 #define NVM_WORD2_ID(x) (x >> 12)
1381 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1382 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1383 #define NVM_HEADER_0 (0x2A504C54)
1384 #define NVM_HEADER_1 (0x4E564D2A)
1385 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1386
1387 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1388
1389 /* Maximal size depends on NVM version */
1390 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1391 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1392 else
1393 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1394
1395 /*
1396 * Obtain NVM image via request_firmware. Since we already used
1397 * request_firmware_nowait() for the firmware binary load and only
1398 * get here after that we assume the NVM request can be satisfied
1399 * synchronously.
1400 */
1401 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1402 if (ret) {
1403 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1404 nvm_file_name, ret);
1405 return ret;
1406 }
1407
1408 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1409 nvm_file_name, fw_entry->size);
1410
1411 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1412 IWL_ERR(trans, "NVM file too large\n");
1413 ret = -EINVAL;
1414 goto out;
1415 }
1416
1417 eof = fw_entry->data + fw_entry->size;
1418 dword_buff = (__le32 *)fw_entry->data;
1419
1420 /* some NVM file will contain a header.
1421 * The header is identified by 2 dwords header as follow:
1422 * dword[0] = 0x2A504C54
1423 * dword[1] = 0x4E564D2A
1424 *
1425 * This header must be skipped when providing the NVM data to the FW.
1426 */
1427 if (fw_entry->size > NVM_HEADER_SIZE &&
1428 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1429 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1430 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1431 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1432 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1433 le32_to_cpu(dword_buff[3]));
1434
1435 /* nvm file validation, dword_buff[2] holds the file version */
1436 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1437 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1438 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1439 ret = -EFAULT;
1440 goto out;
1441 }
1442 } else {
1443 file_sec = (void *)fw_entry->data;
1444 }
1445
1446 while (true) {
1447 if (file_sec->data > eof) {
1448 IWL_ERR(trans,
1449 "ERROR - NVM file too short for section header\n");
1450 ret = -EINVAL;
1451 break;
1452 }
1453
1454 /* check for EOF marker */
1455 if (!file_sec->word1 && !file_sec->word2) {
1456 ret = 0;
1457 break;
1458 }
1459
1460 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1461 section_size =
1462 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1463 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1464 } else {
1465 section_size = 2 * EXT_NVM_WORD2_LEN(
1466 le16_to_cpu(file_sec->word2));
1467 section_id = EXT_NVM_WORD1_ID(
1468 le16_to_cpu(file_sec->word1));
1469 }
1470
1471 if (section_size > max_section_size) {
1472 IWL_ERR(trans, "ERROR - section too large (%d)\n",
1473 section_size);
1474 ret = -EINVAL;
1475 break;
1476 }
1477
1478 if (!section_size) {
1479 IWL_ERR(trans, "ERROR - section empty\n");
1480 ret = -EINVAL;
1481 break;
1482 }
1483
1484 if (file_sec->data + section_size > eof) {
1485 IWL_ERR(trans,
1486 "ERROR - NVM file too short for section (%d bytes)\n",
1487 section_size);
1488 ret = -EINVAL;
1489 break;
1490 }
1491
1492 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1493 "Invalid NVM section ID %d\n", section_id)) {
1494 ret = -EINVAL;
1495 break;
1496 }
1497
1498 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1499 if (!temp) {
1500 ret = -ENOMEM;
1501 break;
1502 }
1503
1504 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1505
1506 kfree(nvm_sections[section_id].data);
1507 nvm_sections[section_id].data = temp;
1508 nvm_sections[section_id].length = section_size;
1509
1510 /* advance to the next section */
1511 file_sec = (void *)(file_sec->data + section_size);
1512 }
1513 out:
1514 release_firmware(fw_entry);
1515 return ret;
1516 }
1517 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1518
iwl_get_nvm(struct iwl_trans * trans,const struct iwl_fw * fw)1519 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1520 const struct iwl_fw *fw)
1521 {
1522 struct iwl_nvm_get_info cmd = {};
1523 struct iwl_nvm_data *nvm;
1524 struct iwl_host_cmd hcmd = {
1525 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1526 .data = { &cmd, },
1527 .len = { sizeof(cmd) },
1528 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1529 };
1530 int ret;
1531 bool empty_otp;
1532 u32 mac_flags;
1533 u32 sbands_flags = 0;
1534 /*
1535 * All the values in iwl_nvm_get_info_rsp v4 are the same as
1536 * in v3, except for the channel profile part of the
1537 * regulatory. So we can just access the new struct, with the
1538 * exception of the latter.
1539 */
1540 struct iwl_nvm_get_info_rsp *rsp;
1541 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1542 bool v4 = fw_has_api(&fw->ucode_capa,
1543 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1544 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1545 void *channel_profile;
1546
1547 ret = iwl_trans_send_cmd(trans, &hcmd);
1548 if (ret)
1549 return ERR_PTR(ret);
1550
1551 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1552 "Invalid payload len in NVM response from FW %d",
1553 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1554 ret = -EINVAL;
1555 goto out;
1556 }
1557
1558 rsp = (void *)hcmd.resp_pkt->data;
1559 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1560 NVM_GENERAL_FLAGS_EMPTY_OTP);
1561 if (empty_otp)
1562 IWL_INFO(trans, "OTP is empty\n");
1563
1564 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1565 if (!nvm) {
1566 ret = -ENOMEM;
1567 goto out;
1568 }
1569
1570 iwl_set_hw_address_from_csr(trans, nvm);
1571 /* TODO: if platform NVM has MAC address - override it here */
1572
1573 if (!is_valid_ether_addr(nvm->hw_addr)) {
1574 IWL_ERR(trans, "no valid mac address was found\n");
1575 ret = -EINVAL;
1576 goto err_free;
1577 }
1578
1579 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1580
1581 /* Initialize general data */
1582 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1583 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1584 if (nvm->n_hw_addrs == 0)
1585 IWL_WARN(trans,
1586 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1587 empty_otp);
1588
1589 /* Initialize MAC sku data */
1590 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1591 nvm->sku_cap_11ac_enable =
1592 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1593 nvm->sku_cap_11n_enable =
1594 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1595 nvm->sku_cap_11ax_enable =
1596 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1597 nvm->sku_cap_band_24ghz_enable =
1598 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1599 nvm->sku_cap_band_52ghz_enable =
1600 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1601 nvm->sku_cap_mimo_disabled =
1602 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1603
1604 /* Initialize PHY sku data */
1605 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1606 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1607
1608 if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
1609 fw_has_capa(&fw->ucode_capa,
1610 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
1611 nvm->lar_enabled = true;
1612 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1613 }
1614
1615 rsp_v3 = (void *)rsp;
1616 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1617 (void *)rsp_v3->regulatory.channel_profile;
1618
1619 iwl_init_sbands(trans, nvm,
1620 channel_profile,
1621 nvm->valid_tx_ant & fw->valid_tx_ant,
1622 nvm->valid_rx_ant & fw->valid_rx_ant,
1623 sbands_flags, v4);
1624
1625 iwl_free_resp(&hcmd);
1626 return nvm;
1627
1628 err_free:
1629 kfree(nvm);
1630 out:
1631 iwl_free_resp(&hcmd);
1632 return ERR_PTR(ret);
1633 }
1634 IWL_EXPORT_SYMBOL(iwl_get_nvm);
1635