1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "rf.h"
11 #include "dm.h"
12 #include "table.h"
13 #include "trx.h"
14 #include "../btcoexist/halbt_precomp.h"
15 #include "hw.h"
16 #include "../efuse.h"
17
18 #define READ_NEXT_PAIR(array_table, v1, v2, i) \
19 do { \
20 i += 2; \
21 v1 = array_table[i]; \
22 v2 = array_table[i+1]; \
23 } while (0)
24
25 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
26 enum radio_path rfpath, u32 offset);
27 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
28 enum radio_path rfpath, u32 offset,
29 u32 data);
_rtl8821ae_phy_calculate_bit_shift(u32 bitmask)30 static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask)
31 {
32 u32 i = ffs(bitmask);
33
34 return i ? i - 1 : 32;
35 }
36 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw);
37 /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/
38 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
39 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
40 u8 configtype);
41 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
42 u8 configtype);
43 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
44
45 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
46 enum wireless_mode wirelessmode,
47 u8 txpwridx);
48 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw);
49 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw);
50
rtl8812ae_fixspur(struct ieee80211_hw * hw,enum ht_channel_width band_width,u8 channel)51 static void rtl8812ae_fixspur(struct ieee80211_hw *hw,
52 enum ht_channel_width band_width, u8 channel)
53 {
54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
55
56 /*C cut Item12 ADC FIFO CLOCK*/
57 if (IS_VENDOR_8812A_C_CUT(rtlhal->version)) {
58 if (band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11)
59 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3);
60 /* 0x8AC[11:10] = 2'b11*/
61 else
62 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2);
63 /* 0x8AC[11:10] = 2'b10*/
64
65 /* <20120914, Kordan> A workarould to resolve
66 * 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)
67 */
68 if (band_width == HT_CHANNEL_WIDTH_20 &&
69 (channel == 13 || channel == 14)) {
70 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
71 /*0x8AC[9:8] = 2'b11*/
72 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
73 /* 0x8C4[30] = 1*/
74 } else if (band_width == HT_CHANNEL_WIDTH_20_40 &&
75 channel == 11) {
76 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
77 /*0x8C4[30] = 1*/
78 } else if (band_width != HT_CHANNEL_WIDTH_80) {
79 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
80 /*0x8AC[9:8] = 2'b10*/
81 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
82 /*0x8C4[30] = 0*/
83 }
84 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
85 /* <20120914, Kordan> A workarould to resolve
86 * 2480Mhz spur by setting ADC clock as 160M.
87 */
88 if (band_width == HT_CHANNEL_WIDTH_20 &&
89 (channel == 13 || channel == 14))
90 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
91 /*0x8AC[9:8] = 11*/
92 else if (channel <= 14) /*2.4G only*/
93 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
94 /*0x8AC[9:8] = 10*/
95 }
96 }
97
rtl8821ae_phy_query_bb_reg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)98 u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
99 u32 bitmask)
100 {
101 struct rtl_priv *rtlpriv = rtl_priv(hw);
102 u32 returnvalue, originalvalue, bitshift;
103
104 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
105 "regaddr(%#x), bitmask(%#x)\n",
106 regaddr, bitmask);
107 originalvalue = rtl_read_dword(rtlpriv, regaddr);
108 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
109 returnvalue = (originalvalue & bitmask) >> bitshift;
110
111 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
112 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
113 bitmask, regaddr, originalvalue);
114 return returnvalue;
115 }
116
rtl8821ae_phy_set_bb_reg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)117 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
118 u32 regaddr, u32 bitmask, u32 data)
119 {
120 struct rtl_priv *rtlpriv = rtl_priv(hw);
121 u32 originalvalue, bitshift;
122
123 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
124 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
125 regaddr, bitmask, data);
126
127 if (bitmask != MASKDWORD) {
128 originalvalue = rtl_read_dword(rtlpriv, regaddr);
129 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
130 data = ((originalvalue & (~bitmask)) |
131 ((data << bitshift) & bitmask));
132 }
133
134 rtl_write_dword(rtlpriv, regaddr, data);
135
136 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
137 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
138 regaddr, bitmask, data);
139 }
140
rtl8821ae_phy_query_rf_reg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)141 u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
142 enum radio_path rfpath, u32 regaddr,
143 u32 bitmask)
144 {
145 struct rtl_priv *rtlpriv = rtl_priv(hw);
146 u32 original_value, readback_value, bitshift;
147
148 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
149 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
150 regaddr, rfpath, bitmask);
151
152 spin_lock(&rtlpriv->locks.rf_lock);
153
154 original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
155 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
156 readback_value = (original_value & bitmask) >> bitshift;
157
158 spin_unlock(&rtlpriv->locks.rf_lock);
159
160 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
161 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
162 regaddr, rfpath, bitmask, original_value);
163
164 return readback_value;
165 }
166
rtl8821ae_phy_set_rf_reg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)167 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
168 enum radio_path rfpath,
169 u32 regaddr, u32 bitmask, u32 data)
170 {
171 struct rtl_priv *rtlpriv = rtl_priv(hw);
172 u32 original_value, bitshift;
173
174 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
175 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
176 regaddr, bitmask, data, rfpath);
177
178 spin_lock(&rtlpriv->locks.rf_lock);
179
180 if (bitmask != RFREG_OFFSET_MASK) {
181 original_value =
182 _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
183 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
184 data = ((original_value & (~bitmask)) | (data << bitshift));
185 }
186
187 _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data);
188
189 spin_unlock(&rtlpriv->locks.rf_lock);
190
191 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
192 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
193 regaddr, bitmask, data, rfpath);
194 }
195
_rtl8821ae_phy_rf_serial_read(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset)196 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
197 enum radio_path rfpath, u32 offset)
198 {
199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200 bool is_pi_mode = false;
201 u32 retvalue = 0;
202
203 /* 2009/06/17 MH We can not execute IO for power
204 save or other accident mode.*/
205 if (RT_CANNOT_IO(hw)) {
206 pr_err("return all one\n");
207 return 0xFFFFFFFF;
208 }
209 /* <20120809, Kordan> CCA OFF(when entering),
210 asked by James to avoid reading the wrong value.
211 <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
212 if (offset != 0x0 &&
213 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
214 (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
215 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1);
216 offset &= 0xff;
217
218 if (rfpath == RF90_PATH_A)
219 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xC00, 0x4);
220 else if (rfpath == RF90_PATH_B)
221 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xE00, 0x4);
222
223 rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset);
224
225 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
226 (IS_VENDOR_8812A_C_CUT(rtlhal->version)))
227 udelay(20);
228
229 if (is_pi_mode) {
230 if (rfpath == RF90_PATH_A)
231 retvalue =
232 rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA);
233 else if (rfpath == RF90_PATH_B)
234 retvalue =
235 rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA);
236 } else {
237 if (rfpath == RF90_PATH_A)
238 retvalue =
239 rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA);
240 else if (rfpath == RF90_PATH_B)
241 retvalue =
242 rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA);
243 }
244
245 /*<20120809, Kordan> CCA ON(when exiting),
246 * asked by James to avoid reading the wrong value.
247 * <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!
248 */
249 if (offset != 0x0 &&
250 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
251 (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
252 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0);
253 return retvalue;
254 }
255
_rtl8821ae_phy_rf_serial_write(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset,u32 data)256 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
257 enum radio_path rfpath, u32 offset,
258 u32 data)
259 {
260 struct rtl_priv *rtlpriv = rtl_priv(hw);
261 struct rtl_phy *rtlphy = &rtlpriv->phy;
262 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
263 u32 data_and_addr;
264 u32 newoffset;
265
266 if (RT_CANNOT_IO(hw)) {
267 pr_err("stop\n");
268 return;
269 }
270 offset &= 0xff;
271 newoffset = offset;
272 data_and_addr = ((newoffset << 20) |
273 (data & 0x000fffff)) & 0x0fffffff;
274 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
275 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
276 "RFW-%d Addr[0x%x]=0x%x\n",
277 rfpath, pphyreg->rf3wire_offset, data_and_addr);
278 }
279
rtl8821ae_phy_mac_config(struct ieee80211_hw * hw)280 bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw)
281 {
282 bool rtstatus = 0;
283
284 rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw);
285
286 return rtstatus;
287 }
288
rtl8821ae_phy_bb_config(struct ieee80211_hw * hw)289 bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw)
290 {
291 bool rtstatus = true;
292 struct rtl_priv *rtlpriv = rtl_priv(hw);
293 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
294 struct rtl_phy *rtlphy = &rtlpriv->phy;
295 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
296 u8 regval;
297 u8 crystal_cap;
298
299 phy_init_bb_rf_register_definition(hw);
300
301 regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
302 regval |= FEN_PCIEA;
303 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval);
304 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
305 regval | FEN_BB_GLB_RSTN | FEN_BBRSTB);
306
307 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7);
308 rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7);
309
310 rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw);
311
312 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
313 crystal_cap = rtlefuse->crystalcap & 0x3F;
314 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000,
315 (crystal_cap | (crystal_cap << 6)));
316 } else {
317 crystal_cap = rtlefuse->crystalcap & 0x3F;
318 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
319 (crystal_cap | (crystal_cap << 6)));
320 }
321 rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837);
322
323 return rtstatus;
324 }
325
rtl8821ae_phy_rf_config(struct ieee80211_hw * hw)326 bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw)
327 {
328 return rtl8821ae_phy_rf6052_config(hw);
329 }
330
_rtl8812ae_phy_set_rfe_reg_24g(struct ieee80211_hw * hw)331 static void _rtl8812ae_phy_set_rfe_reg_24g(struct ieee80211_hw *hw)
332 {
333 struct rtl_priv *rtlpriv = rtl_priv(hw);
334 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
335 u8 tmp;
336
337 switch (rtlhal->rfe_type) {
338 case 3:
339 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337770);
340 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337770);
341 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
342 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
343 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
344 break;
345 case 4:
346 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
347 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
348 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x001);
349 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x001);
350 break;
351 case 5:
352 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x77);
353 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
354 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3);
355 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp & ~0x1);
356 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
357 break;
358 case 1:
359 if (rtlpriv->btcoexist.bt_coexistence) {
360 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x777777);
361 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
362 0x77777777);
363 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
364 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
365 break;
366 }
367 fallthrough;
368 case 0:
369 case 2:
370 default:
371 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
372 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
373 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
374 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
375 break;
376 }
377 }
378
_rtl8812ae_phy_set_rfe_reg_5g(struct ieee80211_hw * hw)379 static void _rtl8812ae_phy_set_rfe_reg_5g(struct ieee80211_hw *hw)
380 {
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
382 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
383 u8 tmp;
384
385 switch (rtlhal->rfe_type) {
386 case 0:
387 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337717);
388 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337717);
389 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
390 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
391 break;
392 case 1:
393 if (rtlpriv->btcoexist.bt_coexistence) {
394 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x337717);
395 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
396 0x77337717);
397 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
398 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
399 } else {
400 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD,
401 0x77337717);
402 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
403 0x77337717);
404 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
405 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
406 }
407 break;
408 case 3:
409 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337717);
410 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337717);
411 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
412 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
413 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
414 break;
415 case 5:
416 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x33);
417 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
418 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3);
419 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp | 0x1);
420 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
421 break;
422 case 2:
423 case 4:
424 default:
425 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777);
426 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
427 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
428 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
429 break;
430 }
431 }
432
phy_get_tx_swing_8812A(struct ieee80211_hw * hw,u8 band,u8 rf_path)433 u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band,
434 u8 rf_path)
435 {
436 struct rtl_priv *rtlpriv = rtl_priv(hw);
437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
438 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
439 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
440 s8 reg_swing_2g = -1;/* 0xff; */
441 s8 reg_swing_5g = -1;/* 0xff; */
442 s8 swing_2g = -1 * reg_swing_2g;
443 s8 swing_5g = -1 * reg_swing_5g;
444 u32 out = 0x200;
445 const s8 auto_temp = -1;
446
447 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
448 "===> PHY_GetTXBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d,autoload_failflag=%d.\n",
449 (int)swing_2g, (int)swing_5g,
450 (int)rtlefuse->autoload_failflag);
451
452 if (rtlefuse->autoload_failflag) {
453 if (band == BAND_ON_2_4G) {
454 rtldm->swing_diff_2g = swing_2g;
455 if (swing_2g == 0) {
456 out = 0x200; /* 0 dB */
457 } else if (swing_2g == -3) {
458 out = 0x16A; /* -3 dB */
459 } else if (swing_2g == -6) {
460 out = 0x101; /* -6 dB */
461 } else if (swing_2g == -9) {
462 out = 0x0B6; /* -9 dB */
463 } else {
464 rtldm->swing_diff_2g = 0;
465 out = 0x200;
466 }
467 } else if (band == BAND_ON_5G) {
468 rtldm->swing_diff_5g = swing_5g;
469 if (swing_5g == 0) {
470 out = 0x200; /* 0 dB */
471 } else if (swing_5g == -3) {
472 out = 0x16A; /* -3 dB */
473 } else if (swing_5g == -6) {
474 out = 0x101; /* -6 dB */
475 } else if (swing_5g == -9) {
476 out = 0x0B6; /* -9 dB */
477 } else {
478 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
479 rtldm->swing_diff_5g = -3;
480 out = 0x16A;
481 } else {
482 rtldm->swing_diff_5g = 0;
483 out = 0x200;
484 }
485 }
486 } else {
487 rtldm->swing_diff_2g = -3;
488 rtldm->swing_diff_5g = -3;
489 out = 0x16A; /* -3 dB */
490 }
491 } else {
492 u32 swing = 0, swing_a = 0, swing_b = 0;
493
494 if (band == BAND_ON_2_4G) {
495 if (reg_swing_2g == auto_temp) {
496 efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing);
497 swing = (swing == 0xFF) ? 0x00 : swing;
498 } else if (swing_2g == 0) {
499 swing = 0x00; /* 0 dB */
500 } else if (swing_2g == -3) {
501 swing = 0x05; /* -3 dB */
502 } else if (swing_2g == -6) {
503 swing = 0x0A; /* -6 dB */
504 } else if (swing_2g == -9) {
505 swing = 0xFF; /* -9 dB */
506 } else {
507 swing = 0x00;
508 }
509 } else {
510 if (reg_swing_5g == auto_temp) {
511 efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing);
512 swing = (swing == 0xFF) ? 0x00 : swing;
513 } else if (swing_5g == 0) {
514 swing = 0x00; /* 0 dB */
515 } else if (swing_5g == -3) {
516 swing = 0x05; /* -3 dB */
517 } else if (swing_5g == -6) {
518 swing = 0x0A; /* -6 dB */
519 } else if (swing_5g == -9) {
520 swing = 0xFF; /* -9 dB */
521 } else {
522 swing = 0x00;
523 }
524 }
525
526 swing_a = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */
527 swing_b = (swing & 0xC) >> 2; /* 0xC6/C7[3:2] */
528 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
529 "===> PHY_GetTXBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n",
530 swing_a, swing_b);
531
532 /* 3 Path-A */
533 if (swing_a == 0x0) {
534 if (band == BAND_ON_2_4G)
535 rtldm->swing_diff_2g = 0;
536 else
537 rtldm->swing_diff_5g = 0;
538 out = 0x200; /* 0 dB */
539 } else if (swing_a == 0x1) {
540 if (band == BAND_ON_2_4G)
541 rtldm->swing_diff_2g = -3;
542 else
543 rtldm->swing_diff_5g = -3;
544 out = 0x16A; /* -3 dB */
545 } else if (swing_a == 0x2) {
546 if (band == BAND_ON_2_4G)
547 rtldm->swing_diff_2g = -6;
548 else
549 rtldm->swing_diff_5g = -6;
550 out = 0x101; /* -6 dB */
551 } else if (swing_a == 0x3) {
552 if (band == BAND_ON_2_4G)
553 rtldm->swing_diff_2g = -9;
554 else
555 rtldm->swing_diff_5g = -9;
556 out = 0x0B6; /* -9 dB */
557 }
558 /* 3 Path-B */
559 if (swing_b == 0x0) {
560 if (band == BAND_ON_2_4G)
561 rtldm->swing_diff_2g = 0;
562 else
563 rtldm->swing_diff_5g = 0;
564 out = 0x200; /* 0 dB */
565 } else if (swing_b == 0x1) {
566 if (band == BAND_ON_2_4G)
567 rtldm->swing_diff_2g = -3;
568 else
569 rtldm->swing_diff_5g = -3;
570 out = 0x16A; /* -3 dB */
571 } else if (swing_b == 0x2) {
572 if (band == BAND_ON_2_4G)
573 rtldm->swing_diff_2g = -6;
574 else
575 rtldm->swing_diff_5g = -6;
576 out = 0x101; /* -6 dB */
577 } else if (swing_b == 0x3) {
578 if (band == BAND_ON_2_4G)
579 rtldm->swing_diff_2g = -9;
580 else
581 rtldm->swing_diff_5g = -9;
582 out = 0x0B6; /* -9 dB */
583 }
584 }
585
586 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
587 "<=== PHY_GetTXBBSwing_8812A, out = 0x%X\n", out);
588 return out;
589 }
590
rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw * hw,u8 band)591 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
592 {
593 struct rtl_priv *rtlpriv = rtl_priv(hw);
594 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
595 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
596 u8 current_band = rtlhal->current_bandtype;
597 u32 txpath, rxpath;
598 s8 bb_diff_between_band;
599
600 txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0);
601 rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000);
602 rtlhal->current_bandtype = (enum band_type) band;
603 /* reconfig BB/RF according to wireless mode */
604 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
605 /* BB & RF Config */
606 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
607
608 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
609 /* 0xCB0[15:12] = 0x7 (LNA_On)*/
610 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7);
611 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
612 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7);
613 }
614
615 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
616 /*0x834[1:0] = 0x1*/
617 rtl_set_bbreg(hw, 0x834, 0x3, 0x1);
618 }
619
620 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
621 /* 0xC1C[11:8] = 0 */
622 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0);
623 } else {
624 /* 0x82C[1:0] = 2b'00 */
625 rtl_set_bbreg(hw, 0x82c, 0x3, 0);
626 }
627
628 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
629 _rtl8812ae_phy_set_rfe_reg_24g(hw);
630
631 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1);
632 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1);
633
634 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0);
635 } else {/* 5G band */
636 u16 count, reg_41a;
637
638 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
639 /*0xCB0[15:12] = 0x5 (LNA_On)*/
640 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5);
641 /*0xCB0[7:4] = 0x4 (PAPE_A)*/
642 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4);
643 }
644 /*CCK_CHECK_en*/
645 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80);
646
647 count = 0;
648 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
649 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
650 "Reg41A value %d\n", reg_41a);
651 reg_41a &= 0x30;
652 while ((reg_41a != 0x30) && (count < 50)) {
653 udelay(50);
654 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "Delay 50us\n");
655
656 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
657 reg_41a &= 0x30;
658 count++;
659 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
660 "Reg41A value %d\n", reg_41a);
661 }
662 if (count != 0)
663 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
664 "PHY_SwitchWirelessBand8812(): Switch to 5G Band. Count = %d reg41A=0x%x\n",
665 count, reg_41a);
666
667 /* 2012/02/01, Sinda add registry to switch workaround
668 without long-run verification for scan issue. */
669 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
670
671 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
672 /*0x834[1:0] = 0x2*/
673 rtl_set_bbreg(hw, 0x834, 0x3, 0x2);
674 }
675
676 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
677 /* AGC table select */
678 /* 0xC1C[11:8] = 1*/
679 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1);
680 } else
681 /* 0x82C[1:0] = 2'b00 */
682 rtl_set_bbreg(hw, 0x82c, 0x3, 1);
683
684 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
685 _rtl8812ae_phy_set_rfe_reg_5g(hw);
686
687 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0);
688 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf);
689
690 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
691 "==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n",
692 rtlpriv->dm.ofdm_index[RF90_PATH_A]);
693 }
694
695 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
696 (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) {
697 /* 0xC1C[31:21] */
698 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
699 phy_get_tx_swing_8812A(hw, band, RF90_PATH_A));
700 /* 0xE1C[31:21] */
701 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
702 phy_get_tx_swing_8812A(hw, band, RF90_PATH_B));
703
704 /* <20121005, Kordan> When TxPowerTrack is ON,
705 * we should take care of the change of BB swing.
706 * That is, reset all info to trigger Tx power tracking.
707 */
708 if (band != current_band) {
709 bb_diff_between_band =
710 (rtldm->swing_diff_2g - rtldm->swing_diff_5g);
711 bb_diff_between_band = (band == BAND_ON_2_4G) ?
712 bb_diff_between_band :
713 (-1 * bb_diff_between_band);
714 rtldm->default_ofdm_index += bb_diff_between_band * 2;
715 }
716 rtl8821ae_dm_clear_txpower_tracking_state(hw);
717 }
718
719 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
720 "<==%s():Switch Band OK.\n", __func__);
721 return;
722 }
723
_rtl8821ae_check_positive(struct ieee80211_hw * hw,const u32 condition1,const u32 condition2)724 static bool _rtl8821ae_check_positive(struct ieee80211_hw *hw,
725 const u32 condition1,
726 const u32 condition2)
727 {
728 struct rtl_priv *rtlpriv = rtl_priv(hw);
729 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
730 u32 cut_ver = ((rtlhal->version & CHIP_VER_RTL_MASK)
731 >> CHIP_VER_RTL_SHIFT);
732 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0));
733
734 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */
735 ((rtlhal->board_type & BIT(3)) >> 3) << 1 | /* _GPA */
736 ((rtlhal->board_type & BIT(7)) >> 7) << 2 | /* _ALNA */
737 ((rtlhal->board_type & BIT(6)) >> 6) << 3 | /* _APA */
738 ((rtlhal->board_type & BIT(2)) >> 2) << 4; /* _BT */
739
740 u32 cond1 = condition1, cond2 = condition2;
741 u32 driver1 = cut_ver << 24 | /* CUT ver */
742 0 << 20 | /* interface 2/2 */
743 0x04 << 16 | /* platform */
744 rtlhal->package_type << 12 |
745 intf << 8 | /* interface 1/2 */
746 board_type;
747
748 u32 driver2 = rtlhal->type_glna << 0 |
749 rtlhal->type_gpa << 8 |
750 rtlhal->type_alna << 16 |
751 rtlhal->type_apa << 24;
752
753 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
754 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
755 cond1, cond2);
756 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
757 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
758 driver1, driver2);
759
760 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
761 " (Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf);
762 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
763 " (Board, Package) = (0x%X, 0x%X)\n",
764 rtlhal->board_type, rtlhal->package_type);
765
766 /*============== Value Defined Check ===============*/
767 /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
768
769 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) !=
770 (driver1 & 0x0000F000)))
771 return false;
772 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) !=
773 (driver1 & 0x0F000000)))
774 return false;
775
776 /*=============== Bit Defined Check ================*/
777 /* We don't care [31:28] */
778
779 cond1 &= 0x00FF0FFF;
780 driver1 &= 0x00FF0FFF;
781
782 if ((cond1 & driver1) == cond1) {
783 u32 mask = 0;
784
785 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
786 return true;
787
788 if ((cond1 & BIT(0)) != 0) /*GLNA*/
789 mask |= 0x000000FF;
790 if ((cond1 & BIT(1)) != 0) /*GPA*/
791 mask |= 0x0000FF00;
792 if ((cond1 & BIT(2)) != 0) /*ALNA*/
793 mask |= 0x00FF0000;
794 if ((cond1 & BIT(3)) != 0) /*APA*/
795 mask |= 0xFF000000;
796
797 /* BoardType of each RF path is matched*/
798 if ((cond2 & mask) == (driver2 & mask))
799 return true;
800 else
801 return false;
802 } else
803 return false;
804 }
805
_rtl8821ae_check_condition(struct ieee80211_hw * hw,const u32 condition)806 static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw,
807 const u32 condition)
808 {
809 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
810 u32 _board = rtlefuse->board_type; /*need efuse define*/
811 u32 _interface = 0x01; /* ODM_ITRF_PCIE */
812 u32 _platform = 0x08;/* ODM_WIN */
813 u32 cond = condition;
814
815 if (condition == 0xCDCDCDCD)
816 return true;
817
818 cond = condition & 0xFF;
819 if ((_board != cond) && cond != 0xFF)
820 return false;
821
822 cond = condition & 0xFF00;
823 cond = cond >> 8;
824 if ((_interface & cond) == 0 && cond != 0x07)
825 return false;
826
827 cond = condition & 0xFF0000;
828 cond = cond >> 16;
829 if ((_platform & cond) == 0 && cond != 0x0F)
830 return false;
831 return true;
832 }
833
_rtl8821ae_config_rf_reg(struct ieee80211_hw * hw,u32 addr,u32 data,enum radio_path rfpath,u32 regaddr)834 static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw,
835 u32 addr, u32 data,
836 enum radio_path rfpath, u32 regaddr)
837 {
838 if (addr == 0xfe || addr == 0xffe) {
839 /* In order not to disturb BT music when
840 * wifi init.(1ant NIC only)
841 */
842 mdelay(50);
843 } else {
844 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
845 udelay(1);
846 }
847 }
848
_rtl8821ae_config_rf_radio_a(struct ieee80211_hw * hw,u32 addr,u32 data)849 static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw,
850 u32 addr, u32 data)
851 {
852 u32 content = 0x1000; /*RF Content: radio_a_txt*/
853 u32 maskforphyset = (u32)(content & 0xE000);
854
855 _rtl8821ae_config_rf_reg(hw, addr, data,
856 RF90_PATH_A, addr | maskforphyset);
857 }
858
_rtl8821ae_config_rf_radio_b(struct ieee80211_hw * hw,u32 addr,u32 data)859 static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw,
860 u32 addr, u32 data)
861 {
862 u32 content = 0x1001; /*RF Content: radio_b_txt*/
863 u32 maskforphyset = (u32)(content & 0xE000);
864
865 _rtl8821ae_config_rf_reg(hw, addr, data,
866 RF90_PATH_B, addr | maskforphyset);
867 }
868
_rtl8821ae_config_bb_reg(struct ieee80211_hw * hw,u32 addr,u32 data)869 static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw,
870 u32 addr, u32 data)
871 {
872 if (addr == 0xfe)
873 mdelay(50);
874 else if (addr == 0xfd)
875 mdelay(5);
876 else if (addr == 0xfc)
877 mdelay(1);
878 else if (addr == 0xfb)
879 udelay(50);
880 else if (addr == 0xfa)
881 udelay(5);
882 else if (addr == 0xf9)
883 udelay(1);
884 else
885 rtl_set_bbreg(hw, addr, MASKDWORD, data);
886
887 udelay(1);
888 }
889
_rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw * hw)890 static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
891 {
892 struct rtl_priv *rtlpriv = rtl_priv(hw);
893 struct rtl_phy *rtlphy = &rtlpriv->phy;
894 u8 band, rfpath, txnum, rate_section;
895
896 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
897 for (rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath)
898 for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
899 for (rate_section = 0;
900 rate_section < TX_PWR_BY_RATE_NUM_SECTION;
901 ++rate_section)
902 rtlphy->tx_power_by_rate_offset[band]
903 [rfpath][txnum][rate_section] = 0;
904 }
905
_rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw * hw,u8 band,u8 path,u8 rate_section,u8 txnum,u8 value)906 static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
907 u8 band, u8 path,
908 u8 rate_section,
909 u8 txnum, u8 value)
910 {
911 struct rtl_priv *rtlpriv = rtl_priv(hw);
912 struct rtl_phy *rtlphy = &rtlpriv->phy;
913
914 if (path > RF90_PATH_D) {
915 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
916 "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path);
917 return;
918 }
919
920 if (band == BAND_ON_2_4G) {
921 switch (rate_section) {
922 case CCK:
923 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
924 break;
925 case OFDM:
926 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
927 break;
928 case HT_MCS0_MCS7:
929 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
930 break;
931 case HT_MCS8_MCS15:
932 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
933 break;
934 case VHT_1SSMCS0_1SSMCS9:
935 rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value;
936 break;
937 case VHT_2SSMCS0_2SSMCS9:
938 rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value;
939 break;
940 default:
941 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
942 "Invalid RateSection %d in Band 2.4G,Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
943 rate_section, path, txnum);
944 break;
945 }
946 } else if (band == BAND_ON_5G) {
947 switch (rate_section) {
948 case OFDM:
949 rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value;
950 break;
951 case HT_MCS0_MCS7:
952 rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value;
953 break;
954 case HT_MCS8_MCS15:
955 rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value;
956 break;
957 case VHT_1SSMCS0_1SSMCS9:
958 rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value;
959 break;
960 case VHT_2SSMCS0_2SSMCS9:
961 rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value;
962 break;
963 default:
964 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
965 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
966 rate_section, path, txnum);
967 break;
968 }
969 } else {
970 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
971 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band);
972 }
973 }
974
_rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw * hw,u8 band,u8 path,u8 txnum,u8 rate_section)975 static u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
976 u8 band, u8 path,
977 u8 txnum, u8 rate_section)
978 {
979 struct rtl_priv *rtlpriv = rtl_priv(hw);
980 struct rtl_phy *rtlphy = &rtlpriv->phy;
981 u8 value = 0;
982
983 if (path > RF90_PATH_D) {
984 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
985 "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
986 path);
987 return 0;
988 }
989
990 if (band == BAND_ON_2_4G) {
991 switch (rate_section) {
992 case CCK:
993 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
994 break;
995 case OFDM:
996 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
997 break;
998 case HT_MCS0_MCS7:
999 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
1000 break;
1001 case HT_MCS8_MCS15:
1002 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
1003 break;
1004 case VHT_1SSMCS0_1SSMCS9:
1005 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4];
1006 break;
1007 case VHT_2SSMCS0_2SSMCS9:
1008 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5];
1009 break;
1010 default:
1011 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1012 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
1013 rate_section, path, txnum);
1014 break;
1015 }
1016 } else if (band == BAND_ON_5G) {
1017 switch (rate_section) {
1018 case OFDM:
1019 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0];
1020 break;
1021 case HT_MCS0_MCS7:
1022 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1];
1023 break;
1024 case HT_MCS8_MCS15:
1025 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2];
1026 break;
1027 case VHT_1SSMCS0_1SSMCS9:
1028 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3];
1029 break;
1030 case VHT_2SSMCS0_2SSMCS9:
1031 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4];
1032 break;
1033 default:
1034 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1035 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
1036 rate_section, path, txnum);
1037 break;
1038 }
1039 } else {
1040 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1041 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band);
1042 }
1043
1044 return value;
1045 }
1046
_rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw * hw)1047 static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
1048 {
1049 struct rtl_priv *rtlpriv = rtl_priv(hw);
1050 struct rtl_phy *rtlphy = &rtlpriv->phy;
1051 u16 rawvalue = 0;
1052 u8 base = 0, path = 0;
1053
1054 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
1055 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF;
1056 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1057 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base);
1058
1059 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF;
1060 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1061 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base);
1062
1063 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF;
1064 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1065 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base);
1066
1067 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF;
1068 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1069 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base);
1070
1071 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF;
1072 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1073 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
1074
1075 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF;
1076 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1077 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
1078
1079 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF;
1080 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1081 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base);
1082
1083 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF;
1084 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1085 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base);
1086
1087 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF;
1088 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1089 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base);
1090
1091 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF;
1092 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1093 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
1094
1095 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF;
1096 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1097 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
1098 }
1099 }
1100
_phy_convert_txpower_dbm_to_relative_value(u32 * data,u8 start,u8 end,u8 base_val)1101 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
1102 u8 end, u8 base_val)
1103 {
1104 int i;
1105 u8 temp_value = 0;
1106 u32 temp_data = 0;
1107
1108 for (i = 3; i >= 0; --i) {
1109 if (i >= start && i <= end) {
1110 /* Get the exact value */
1111 temp_value = (u8)(*data >> (i * 8)) & 0xF;
1112 temp_value += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10;
1113
1114 /* Change the value to a relative value */
1115 temp_value = (temp_value > base_val) ? temp_value -
1116 base_val : base_val - temp_value;
1117 } else {
1118 temp_value = (u8)(*data >> (i * 8)) & 0xFF;
1119 }
1120 temp_data <<= 8;
1121 temp_data |= temp_value;
1122 }
1123 *data = temp_data;
1124 }
1125
_rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw * hw)1126 static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw)
1127 {
1128 struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 struct rtl_phy *rtlphy = &rtlpriv->phy;
1130 u8 regulation, bw, channel, rate_section;
1131 s8 temp_pwrlmt = 0;
1132
1133 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1134 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
1135 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1136 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1137 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
1138 [bw][rate_section][channel][RF90_PATH_A];
1139 if (temp_pwrlmt == MAX_POWER_INDEX) {
1140 if (bw == 0 || bw == 1) { /*5G 20M 40M VHT and HT can cross reference*/
1141 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1142 "No power limit table of the specified band %d, bandwidth %d, ratesection %d, channel %d, rf path %d\n",
1143 1, bw, rate_section, channel, RF90_PATH_A);
1144 if (rate_section == 2) {
1145 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A] =
1146 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A];
1147 } else if (rate_section == 4) {
1148 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A] =
1149 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A];
1150 } else if (rate_section == 3) {
1151 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A] =
1152 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A];
1153 } else if (rate_section == 5) {
1154 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A] =
1155 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A];
1156 }
1157
1158 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1159 "use other value %d\n",
1160 temp_pwrlmt);
1161 }
1162 }
1163 }
1164 }
1165 }
1166 }
1167 }
1168
_rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw * hw,enum band_type band,u8 rate)1169 static u8 _rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw *hw,
1170 enum band_type band, u8 rate)
1171 {
1172 struct rtl_priv *rtlpriv = rtl_priv(hw);
1173 u8 index = 0;
1174 if (band == BAND_ON_2_4G) {
1175 switch (rate) {
1176 case MGN_1M:
1177 case MGN_2M:
1178 case MGN_5_5M:
1179 case MGN_11M:
1180 index = 0;
1181 break;
1182
1183 case MGN_6M:
1184 case MGN_9M:
1185 case MGN_12M:
1186 case MGN_18M:
1187 case MGN_24M:
1188 case MGN_36M:
1189 case MGN_48M:
1190 case MGN_54M:
1191 index = 1;
1192 break;
1193
1194 case MGN_MCS0:
1195 case MGN_MCS1:
1196 case MGN_MCS2:
1197 case MGN_MCS3:
1198 case MGN_MCS4:
1199 case MGN_MCS5:
1200 case MGN_MCS6:
1201 case MGN_MCS7:
1202 index = 2;
1203 break;
1204
1205 case MGN_MCS8:
1206 case MGN_MCS9:
1207 case MGN_MCS10:
1208 case MGN_MCS11:
1209 case MGN_MCS12:
1210 case MGN_MCS13:
1211 case MGN_MCS14:
1212 case MGN_MCS15:
1213 index = 3;
1214 break;
1215
1216 default:
1217 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1218 "Wrong rate 0x%x to obtain index in 2.4G in PHY_GetTxPowerByRateBaseIndex()\n",
1219 rate);
1220 break;
1221 }
1222 } else if (band == BAND_ON_5G) {
1223 switch (rate) {
1224 case MGN_6M:
1225 case MGN_9M:
1226 case MGN_12M:
1227 case MGN_18M:
1228 case MGN_24M:
1229 case MGN_36M:
1230 case MGN_48M:
1231 case MGN_54M:
1232 index = 0;
1233 break;
1234
1235 case MGN_MCS0:
1236 case MGN_MCS1:
1237 case MGN_MCS2:
1238 case MGN_MCS3:
1239 case MGN_MCS4:
1240 case MGN_MCS5:
1241 case MGN_MCS6:
1242 case MGN_MCS7:
1243 index = 1;
1244 break;
1245
1246 case MGN_MCS8:
1247 case MGN_MCS9:
1248 case MGN_MCS10:
1249 case MGN_MCS11:
1250 case MGN_MCS12:
1251 case MGN_MCS13:
1252 case MGN_MCS14:
1253 case MGN_MCS15:
1254 index = 2;
1255 break;
1256
1257 case MGN_VHT1SS_MCS0:
1258 case MGN_VHT1SS_MCS1:
1259 case MGN_VHT1SS_MCS2:
1260 case MGN_VHT1SS_MCS3:
1261 case MGN_VHT1SS_MCS4:
1262 case MGN_VHT1SS_MCS5:
1263 case MGN_VHT1SS_MCS6:
1264 case MGN_VHT1SS_MCS7:
1265 case MGN_VHT1SS_MCS8:
1266 case MGN_VHT1SS_MCS9:
1267 index = 3;
1268 break;
1269
1270 case MGN_VHT2SS_MCS0:
1271 case MGN_VHT2SS_MCS1:
1272 case MGN_VHT2SS_MCS2:
1273 case MGN_VHT2SS_MCS3:
1274 case MGN_VHT2SS_MCS4:
1275 case MGN_VHT2SS_MCS5:
1276 case MGN_VHT2SS_MCS6:
1277 case MGN_VHT2SS_MCS7:
1278 case MGN_VHT2SS_MCS8:
1279 case MGN_VHT2SS_MCS9:
1280 index = 4;
1281 break;
1282
1283 default:
1284 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1285 "Wrong rate 0x%x to obtain index in 5G in PHY_GetTxPowerByRateBaseIndex()\n",
1286 rate);
1287 break;
1288 }
1289 }
1290
1291 return index;
1292 }
1293
_rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw * hw)1294 static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw)
1295 {
1296 struct rtl_priv *rtlpriv = rtl_priv(hw);
1297 struct rtl_phy *rtlphy = &rtlpriv->phy;
1298 u8 bw40_pwr_base_dbm2_4G, bw40_pwr_base_dbm5G;
1299 u8 regulation, bw, channel, rate_section;
1300 u8 base_index2_4G = 0;
1301 u8 base_index5G = 0;
1302 s8 temp_value = 0, temp_pwrlmt = 0;
1303 u8 rf_path = 0;
1304
1305 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1306 "=====> _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n");
1307
1308 _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw);
1309
1310 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1311 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
1312 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
1313 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1314 /* obtain the base dBm values in 2.4G band
1315 CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15*/
1316 if (rate_section == 0) { /*CCK*/
1317 base_index2_4G =
1318 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1319 BAND_ON_2_4G, MGN_11M);
1320 } else if (rate_section == 1) { /*OFDM*/
1321 base_index2_4G =
1322 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1323 BAND_ON_2_4G, MGN_54M);
1324 } else if (rate_section == 2) { /*HT IT*/
1325 base_index2_4G =
1326 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1327 BAND_ON_2_4G, MGN_MCS7);
1328 } else if (rate_section == 3) { /*HT 2T*/
1329 base_index2_4G =
1330 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1331 BAND_ON_2_4G, MGN_MCS15);
1332 }
1333
1334 temp_pwrlmt = rtlphy->txpwr_limit_2_4g[regulation]
1335 [bw][rate_section][channel][RF90_PATH_A];
1336
1337 for (rf_path = RF90_PATH_A;
1338 rf_path < MAX_RF_PATH_NUM;
1339 ++rf_path) {
1340 if (rate_section == 3)
1341 bw40_pwr_base_dbm2_4G =
1342 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_2TX][base_index2_4G];
1343 else
1344 bw40_pwr_base_dbm2_4G =
1345 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_1TX][base_index2_4G];
1346
1347 if (temp_pwrlmt != MAX_POWER_INDEX) {
1348 temp_value = temp_pwrlmt - bw40_pwr_base_dbm2_4G;
1349 rtlphy->txpwr_limit_2_4g[regulation]
1350 [bw][rate_section][channel][rf_path] =
1351 temp_value;
1352 }
1353
1354 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1355 "TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfpath %d] %d)\n",
1356 regulation, bw, rate_section, channel,
1357 rtlphy->txpwr_limit_2_4g[regulation][bw]
1358 [rate_section][channel][rf_path], (temp_pwrlmt == 63)
1359 ? 0 : temp_pwrlmt/2, channel, rf_path,
1360 bw40_pwr_base_dbm2_4G);
1361 }
1362 }
1363 }
1364 }
1365 }
1366 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1367 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
1368 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1369 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1370 /* obtain the base dBm values in 5G band
1371 OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15,
1372 VHT => 1SSMCS7, VHT 2T => 2SSMCS7*/
1373 if (rate_section == 1) { /*OFDM*/
1374 base_index5G =
1375 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1376 BAND_ON_5G, MGN_54M);
1377 } else if (rate_section == 2) { /*HT 1T*/
1378 base_index5G =
1379 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1380 BAND_ON_5G, MGN_MCS7);
1381 } else if (rate_section == 3) { /*HT 2T*/
1382 base_index5G =
1383 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1384 BAND_ON_5G, MGN_MCS15);
1385 } else if (rate_section == 4) { /*VHT 1T*/
1386 base_index5G =
1387 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1388 BAND_ON_5G, MGN_VHT1SS_MCS7);
1389 } else if (rate_section == 5) { /*VHT 2T*/
1390 base_index5G =
1391 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1392 BAND_ON_5G, MGN_VHT2SS_MCS7);
1393 }
1394
1395 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
1396 [bw][rate_section][channel]
1397 [RF90_PATH_A];
1398
1399 for (rf_path = RF90_PATH_A;
1400 rf_path < MAX_RF_PATH_NUM;
1401 ++rf_path) {
1402 if (rate_section == 3 || rate_section == 5)
1403 bw40_pwr_base_dbm5G =
1404 rtlphy->txpwr_by_rate_base_5g[rf_path]
1405 [RF_2TX][base_index5G];
1406 else
1407 bw40_pwr_base_dbm5G =
1408 rtlphy->txpwr_by_rate_base_5g[rf_path]
1409 [RF_1TX][base_index5G];
1410
1411 if (temp_pwrlmt != MAX_POWER_INDEX) {
1412 temp_value =
1413 temp_pwrlmt - bw40_pwr_base_dbm5G;
1414 rtlphy->txpwr_limit_5g[regulation]
1415 [bw][rate_section][channel]
1416 [rf_path] = temp_value;
1417 }
1418
1419 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1420 "TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfpath %d] %d)\n",
1421 regulation, bw, rate_section,
1422 channel, rtlphy->txpwr_limit_5g[regulation]
1423 [bw][rate_section][channel][rf_path],
1424 temp_pwrlmt, channel, rf_path, bw40_pwr_base_dbm5G);
1425 }
1426 }
1427 }
1428 }
1429 }
1430 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1431 "<===== %s()\n", __func__);
1432 }
1433
_rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw * hw)1434 static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw *hw)
1435 {
1436 struct rtl_priv *rtlpriv = rtl_priv(hw);
1437 struct rtl_phy *rtlphy = &rtlpriv->phy;
1438 u8 i, j, k, l, m;
1439
1440 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1441 "=====>`%s()!\n", __func__);
1442
1443 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1444 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
1445 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1446 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
1447 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1448 rtlphy->txpwr_limit_2_4g
1449 [i][j][k][m][l]
1450 = MAX_POWER_INDEX;
1451 }
1452 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1453 for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
1454 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1455 for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m)
1456 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1457 rtlphy->txpwr_limit_5g
1458 [i][j][k][m][l]
1459 = MAX_POWER_INDEX;
1460 }
1461
1462 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1463 "<===== %s()!\n", __func__);
1464 }
1465
_rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw * hw)1466 static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
1467 {
1468 struct rtl_priv *rtlpriv = rtl_priv(hw);
1469 struct rtl_phy *rtlphy = &rtlpriv->phy;
1470 u8 base = 0, rfpath = 0;
1471
1472 for (rfpath = RF90_PATH_A; rfpath <= RF90_PATH_B; ++rfpath) {
1473 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, CCK);
1474 _phy_convert_txpower_dbm_to_relative_value(
1475 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0],
1476 0, 3, base);
1477
1478 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, OFDM);
1479 _phy_convert_txpower_dbm_to_relative_value(
1480 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][1],
1481 0, 3, base);
1482 _phy_convert_txpower_dbm_to_relative_value(
1483 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][2],
1484 0, 3, base);
1485
1486 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, HT_MCS0_MCS7);
1487 _phy_convert_txpower_dbm_to_relative_value(
1488 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][3],
1489 0, 3, base);
1490 _phy_convert_txpower_dbm_to_relative_value(
1491 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][4],
1492 0, 3, base);
1493
1494 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, HT_MCS8_MCS15);
1495
1496 _phy_convert_txpower_dbm_to_relative_value(
1497 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][5],
1498 0, 3, base);
1499
1500 _phy_convert_txpower_dbm_to_relative_value(
1501 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][6],
1502 0, 3, base);
1503
1504 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1505 _phy_convert_txpower_dbm_to_relative_value(
1506 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][7],
1507 0, 3, base);
1508 _phy_convert_txpower_dbm_to_relative_value(
1509 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][8],
1510 0, 3, base);
1511 _phy_convert_txpower_dbm_to_relative_value(
1512 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9],
1513 0, 1, base);
1514
1515 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1516 _phy_convert_txpower_dbm_to_relative_value(
1517 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9],
1518 2, 3, base);
1519 _phy_convert_txpower_dbm_to_relative_value(
1520 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][10],
1521 0, 3, base);
1522 _phy_convert_txpower_dbm_to_relative_value(
1523 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][11],
1524 0, 3, base);
1525
1526 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, OFDM);
1527 _phy_convert_txpower_dbm_to_relative_value(
1528 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][1],
1529 0, 3, base);
1530 _phy_convert_txpower_dbm_to_relative_value(
1531 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][2],
1532 0, 3, base);
1533
1534 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, HT_MCS0_MCS7);
1535 _phy_convert_txpower_dbm_to_relative_value(
1536 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][3],
1537 0, 3, base);
1538 _phy_convert_txpower_dbm_to_relative_value(
1539 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][4],
1540 0, 3, base);
1541
1542 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, HT_MCS8_MCS15);
1543 _phy_convert_txpower_dbm_to_relative_value(
1544 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][5],
1545 0, 3, base);
1546 _phy_convert_txpower_dbm_to_relative_value(
1547 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][6],
1548 0, 3, base);
1549
1550 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1551 _phy_convert_txpower_dbm_to_relative_value(
1552 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][7],
1553 0, 3, base);
1554 _phy_convert_txpower_dbm_to_relative_value(
1555 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][8],
1556 0, 3, base);
1557 _phy_convert_txpower_dbm_to_relative_value(
1558 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9],
1559 0, 1, base);
1560
1561 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1562 _phy_convert_txpower_dbm_to_relative_value(
1563 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9],
1564 2, 3, base);
1565 _phy_convert_txpower_dbm_to_relative_value(
1566 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][10],
1567 0, 3, base);
1568 _phy_convert_txpower_dbm_to_relative_value(
1569 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][11],
1570 0, 3, base);
1571 }
1572
1573 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1574 "<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n");
1575 }
1576
_rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw * hw)1577 static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
1578 {
1579 _rtl8821ae_phy_store_txpower_by_rate_base(hw);
1580 _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw);
1581 }
1582
1583 /* string is in decimal */
_rtl8812ae_get_integer_from_string(const char * str,u8 * pint)1584 static bool _rtl8812ae_get_integer_from_string(const char *str, u8 *pint)
1585 {
1586 u16 i = 0;
1587 *pint = 0;
1588
1589 while (str[i] != '\0') {
1590 if (str[i] >= '0' && str[i] <= '9') {
1591 *pint *= 10;
1592 *pint += (str[i] - '0');
1593 } else {
1594 return false;
1595 }
1596 ++i;
1597 }
1598
1599 return true;
1600 }
1601
_rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw * hw,u8 band,u8 channel)1602 static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw,
1603 u8 band, u8 channel)
1604 {
1605 struct rtl_priv *rtlpriv = rtl_priv(hw);
1606 s8 channel_index = -1;
1607 u8 i = 0;
1608
1609 if (band == BAND_ON_2_4G)
1610 channel_index = channel - 1;
1611 else if (band == BAND_ON_5G) {
1612 for (i = 0; i < sizeof(channel5g)/sizeof(u8); ++i) {
1613 if (channel5g[i] == channel)
1614 channel_index = i;
1615 }
1616 } else
1617 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Band %d in %s\n",
1618 band, __func__);
1619
1620 if (channel_index == -1)
1621 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1622 "Invalid Channel %d of Band %d in %s\n", channel,
1623 band, __func__);
1624
1625 return channel_index;
1626 }
1627
_rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw * hw,const char * pregulation,const char * pband,const char * pbandwidth,const char * prate_section,const char * prf_path,const char * pchannel,const char * ppower_limit)1628 static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw,
1629 const char *pregulation,
1630 const char *pband, const char *pbandwidth,
1631 const char *prate_section, const char *prf_path,
1632 const char *pchannel, const char *ppower_limit)
1633 {
1634 struct rtl_priv *rtlpriv = rtl_priv(hw);
1635 struct rtl_phy *rtlphy = &rtlpriv->phy;
1636 u8 regulation = 0, bandwidth = 0, rate_section = 0, channel;
1637 u8 channel_index;
1638 s8 power_limit = 0, prev_power_limit, ret;
1639
1640 if (!_rtl8812ae_get_integer_from_string(pchannel, &channel) ||
1641 !_rtl8812ae_get_integer_from_string(ppower_limit,
1642 &power_limit)) {
1643 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1644 "Illegal index of pwr_lmt table [chnl %d][val %d]\n",
1645 channel, power_limit);
1646 }
1647
1648 power_limit = power_limit > MAX_POWER_INDEX ?
1649 MAX_POWER_INDEX : power_limit;
1650
1651 if (strcmp(pregulation, "FCC") == 0)
1652 regulation = 0;
1653 else if (strcmp(pregulation, "MKK") == 0)
1654 regulation = 1;
1655 else if (strcmp(pregulation, "ETSI") == 0)
1656 regulation = 2;
1657 else if (strcmp(pregulation, "WW13") == 0)
1658 regulation = 3;
1659
1660 if (strcmp(prate_section, "CCK") == 0)
1661 rate_section = 0;
1662 else if (strcmp(prate_section, "OFDM") == 0)
1663 rate_section = 1;
1664 else if (strcmp(prate_section, "HT") == 0 &&
1665 strcmp(prf_path, "1T") == 0)
1666 rate_section = 2;
1667 else if (strcmp(prate_section, "HT") == 0 &&
1668 strcmp(prf_path, "2T") == 0)
1669 rate_section = 3;
1670 else if (strcmp(prate_section, "VHT") == 0 &&
1671 strcmp(prf_path, "1T") == 0)
1672 rate_section = 4;
1673 else if (strcmp(prate_section, "VHT") == 0 &&
1674 strcmp(prf_path, "2T") == 0)
1675 rate_section = 5;
1676
1677 if (strcmp(pbandwidth, "20M") == 0)
1678 bandwidth = 0;
1679 else if (strcmp(pbandwidth, "40M") == 0)
1680 bandwidth = 1;
1681 else if (strcmp(pbandwidth, "80M") == 0)
1682 bandwidth = 2;
1683 else if (strcmp(pbandwidth, "160M") == 0)
1684 bandwidth = 3;
1685
1686 if (strcmp(pband, "2.4G") == 0) {
1687 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1688 BAND_ON_2_4G,
1689 channel);
1690
1691 if (ret == -1)
1692 return;
1693
1694 channel_index = ret;
1695
1696 prev_power_limit = rtlphy->txpwr_limit_2_4g[regulation]
1697 [bandwidth][rate_section]
1698 [channel_index][RF90_PATH_A];
1699
1700 if (power_limit < prev_power_limit)
1701 rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1702 [rate_section][channel_index][RF90_PATH_A] =
1703 power_limit;
1704
1705 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1706 "2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n",
1707 regulation, bandwidth, rate_section, channel_index,
1708 rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1709 [rate_section][channel_index][RF90_PATH_A]);
1710 } else if (strcmp(pband, "5G") == 0) {
1711 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1712 BAND_ON_5G,
1713 channel);
1714
1715 if (ret == -1)
1716 return;
1717
1718 channel_index = ret;
1719
1720 prev_power_limit = rtlphy->txpwr_limit_5g[regulation][bandwidth]
1721 [rate_section][channel_index]
1722 [RF90_PATH_A];
1723
1724 if (power_limit < prev_power_limit)
1725 rtlphy->txpwr_limit_5g[regulation][bandwidth]
1726 [rate_section][channel_index][RF90_PATH_A] = power_limit;
1727
1728 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1729 "5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n",
1730 regulation, bandwidth, rate_section, channel,
1731 rtlphy->txpwr_limit_5g[regulation][bandwidth]
1732 [rate_section][channel_index][RF90_PATH_A]);
1733 } else {
1734 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1735 "Cannot recognize the band info in %s\n", pband);
1736 return;
1737 }
1738 }
1739
_rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw * hw,const char * regulation,const char * band,const char * bandwidth,const char * rate_section,const char * rf_path,const char * channel,const char * power_limit)1740 static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw,
1741 const char *regulation, const char *band,
1742 const char *bandwidth, const char *rate_section,
1743 const char *rf_path, const char *channel,
1744 const char *power_limit)
1745 {
1746 _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth,
1747 rate_section, rf_path, channel,
1748 power_limit);
1749 }
1750
_rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw * hw)1751 static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw)
1752 {
1753 struct rtl_priv *rtlpriv = rtl_priv(hw);
1754 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1755 u32 i = 0;
1756 u32 array_len;
1757 const char **array;
1758
1759 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1760 array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN;
1761 array = RTL8812AE_TXPWR_LMT;
1762 } else {
1763 array_len = RTL8821AE_TXPWR_LMT_ARRAY_LEN;
1764 array = RTL8821AE_TXPWR_LMT;
1765 }
1766
1767 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
1768
1769 for (i = 0; i < array_len; i += 7) {
1770 const char *regulation = array[i];
1771 const char *band = array[i+1];
1772 const char *bandwidth = array[i+2];
1773 const char *rate = array[i+3];
1774 const char *rf_path = array[i+4];
1775 const char *chnl = array[i+5];
1776 const char *val = array[i+6];
1777
1778 _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band,
1779 bandwidth, rate, rf_path,
1780 chnl, val);
1781 }
1782 }
1783
_rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw * hw)1784 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw)
1785 {
1786 struct rtl_priv *rtlpriv = rtl_priv(hw);
1787 struct rtl_phy *rtlphy = &rtlpriv->phy;
1788 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1789 bool rtstatus;
1790
1791 _rtl8821ae_phy_init_txpower_limit(hw);
1792
1793 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1794 if (rtlefuse->eeprom_regulatory != 2)
1795 _rtl8821ae_phy_read_and_config_txpwr_lmt(hw);
1796
1797 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1798 BASEBAND_CONFIG_PHY_REG);
1799 if (!rtstatus) {
1800 pr_err("Write BB Reg Fail!!\n");
1801 return false;
1802 }
1803 _rtl8821ae_phy_init_tx_power_by_rate(hw);
1804 if (rtlefuse->autoload_failflag == false) {
1805 rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw,
1806 BASEBAND_CONFIG_PHY_REG);
1807 }
1808 if (!rtstatus) {
1809 pr_err("BB_PG Reg Fail!!\n");
1810 return false;
1811 }
1812
1813 _rtl8821ae_phy_txpower_by_rate_configuration(hw);
1814
1815 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1816 if (rtlefuse->eeprom_regulatory != 2)
1817 _rtl8812ae_phy_convert_txpower_limit_to_power_index(hw);
1818
1819 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1820 BASEBAND_CONFIG_AGC_TAB);
1821
1822 if (!rtstatus) {
1823 pr_err("AGC Table Fail\n");
1824 return false;
1825 }
1826 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
1827 RFPGA0_XA_HSSIPARAMETER2, 0x200));
1828 return true;
1829 }
1830
1831 static bool
__rtl8821ae_phy_config_with_headerfile(struct ieee80211_hw * hw,u32 * array_table,u16 arraylen,void (* set_reg)(struct ieee80211_hw * hw,u32 regaddr,u32 data))1832 __rtl8821ae_phy_config_with_headerfile(struct ieee80211_hw *hw,
1833 u32 *array_table, u16 arraylen,
1834 void (*set_reg)(struct ieee80211_hw *hw,
1835 u32 regaddr, u32 data))
1836 {
1837 #define COND_ELSE 2
1838 #define COND_ENDIF 3
1839
1840 int i = 0;
1841 u8 cond;
1842 bool matched = true, skipped = false;
1843
1844 while ((i + 1) < arraylen) {
1845 u32 v1 = array_table[i];
1846 u32 v2 = array_table[i + 1];
1847
1848 if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
1849 if (v1 & BIT(31)) {/* positive condition*/
1850 cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
1851 if (cond == COND_ENDIF) {/*end*/
1852 matched = true;
1853 skipped = false;
1854 } else if (cond == COND_ELSE) /*else*/
1855 matched = skipped ? false : true;
1856 else {/*if , else if*/
1857 if (skipped) {
1858 matched = false;
1859 } else {
1860 if (_rtl8821ae_check_positive(
1861 hw, v1, v2)) {
1862 matched = true;
1863 skipped = true;
1864 } else {
1865 matched = false;
1866 skipped = false;
1867 }
1868 }
1869 }
1870 } else if (v1 & BIT(30)) { /*negative condition*/
1871 /*do nothing*/
1872 }
1873 } else {
1874 if (matched)
1875 set_reg(hw, v1, v2);
1876 }
1877 i = i + 2;
1878 }
1879
1880 return true;
1881 }
1882
_rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw * hw)1883 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1884 {
1885 struct rtl_priv *rtlpriv = rtl_priv(hw);
1886 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1887 u32 arraylength;
1888 u32 *ptrarray;
1889
1890 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read MAC_REG_Array\n");
1891 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1892 arraylength = RTL8821AE_MAC_1T_ARRAYLEN;
1893 ptrarray = RTL8821AE_MAC_REG_ARRAY;
1894 } else {
1895 arraylength = RTL8812AE_MAC_1T_ARRAYLEN;
1896 ptrarray = RTL8812AE_MAC_REG_ARRAY;
1897 }
1898 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1899 "Img: MAC_REG_ARRAY LEN %d\n", arraylength);
1900
1901 return __rtl8821ae_phy_config_with_headerfile(hw,
1902 ptrarray, arraylength, rtl_write_byte_with_val32);
1903 }
1904
_rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw * hw,u8 configtype)1905 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1906 u8 configtype)
1907 {
1908 struct rtl_priv *rtlpriv = rtl_priv(hw);
1909 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1910 u32 *array_table;
1911 u16 arraylen;
1912
1913 if (configtype == BASEBAND_CONFIG_PHY_REG) {
1914 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1915 arraylen = RTL8812AE_PHY_REG_1TARRAYLEN;
1916 array_table = RTL8812AE_PHY_REG_ARRAY;
1917 } else {
1918 arraylen = RTL8821AE_PHY_REG_1TARRAYLEN;
1919 array_table = RTL8821AE_PHY_REG_ARRAY;
1920 }
1921
1922 return __rtl8821ae_phy_config_with_headerfile(hw,
1923 array_table, arraylen,
1924 _rtl8821ae_config_bb_reg);
1925 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1926 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1927 arraylen = RTL8812AE_AGC_TAB_1TARRAYLEN;
1928 array_table = RTL8812AE_AGC_TAB_ARRAY;
1929 } else {
1930 arraylen = RTL8821AE_AGC_TAB_1TARRAYLEN;
1931 array_table = RTL8821AE_AGC_TAB_ARRAY;
1932 }
1933
1934 return __rtl8821ae_phy_config_with_headerfile(hw,
1935 array_table, arraylen,
1936 rtl_set_bbreg_with_dwmask);
1937 }
1938 return true;
1939 }
1940
_rtl8821ae_get_rate_section_index(u32 regaddr)1941 static u8 _rtl8821ae_get_rate_section_index(u32 regaddr)
1942 {
1943 u8 index = 0;
1944 regaddr &= 0xFFF;
1945 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
1946 index = (u8)((regaddr - 0xC20) / 4);
1947 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
1948 index = (u8)((regaddr - 0xE20) / 4);
1949 else
1950 WARN_ONCE(true,
1951 "rtl8821ae: Invalid RegAddr 0x%x\n", regaddr);
1952 return index;
1953 }
1954
_rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw * hw,u32 band,u32 rfpath,u32 txnum,u32 regaddr,u32 bitmask,u32 data)1955 static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw,
1956 u32 band, u32 rfpath,
1957 u32 txnum, u32 regaddr,
1958 u32 bitmask, u32 data)
1959 {
1960 struct rtl_priv *rtlpriv = rtl_priv(hw);
1961 struct rtl_phy *rtlphy = &rtlpriv->phy;
1962 u8 rate_section = _rtl8821ae_get_rate_section_index(regaddr);
1963
1964 if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
1965 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid Band %d\n", band);
1966 band = BAND_ON_2_4G;
1967 }
1968 if (rfpath >= MAX_RF_PATH) {
1969 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid RfPath %d\n", rfpath);
1970 rfpath = MAX_RF_PATH - 1;
1971 }
1972 if (txnum >= MAX_RF_PATH) {
1973 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid TxNum %d\n", txnum);
1974 txnum = MAX_RF_PATH - 1;
1975 }
1976 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data;
1977 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1978 "TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n",
1979 band, rfpath, txnum, rate_section,
1980 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]);
1981 }
1982
_rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw * hw,u8 configtype)1983 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
1984 u8 configtype)
1985 {
1986 struct rtl_priv *rtlpriv = rtl_priv(hw);
1987 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1988 int i;
1989 u32 *array;
1990 u16 arraylen;
1991 u32 v1, v2, v3, v4, v5, v6;
1992
1993 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1994 arraylen = RTL8812AE_PHY_REG_ARRAY_PGLEN;
1995 array = RTL8812AE_PHY_REG_ARRAY_PG;
1996 } else {
1997 arraylen = RTL8821AE_PHY_REG_ARRAY_PGLEN;
1998 array = RTL8821AE_PHY_REG_ARRAY_PG;
1999 }
2000
2001 if (configtype != BASEBAND_CONFIG_PHY_REG) {
2002 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
2003 "configtype != BaseBand_Config_PHY_REG\n");
2004 return true;
2005 }
2006 for (i = 0; i < arraylen; i += 6) {
2007 v1 = array[i];
2008 v2 = array[i+1];
2009 v3 = array[i+2];
2010 v4 = array[i+3];
2011 v5 = array[i+4];
2012 v6 = array[i+5];
2013
2014 if (v1 < 0xCDCDCDCD) {
2015 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
2016 (v4 == 0xfe || v4 == 0xffe)) {
2017 msleep(50);
2018 continue;
2019 }
2020
2021 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2022 if (v4 == 0xfe)
2023 msleep(50);
2024 else if (v4 == 0xfd)
2025 mdelay(5);
2026 else if (v4 == 0xfc)
2027 mdelay(1);
2028 else if (v4 == 0xfb)
2029 udelay(50);
2030 else if (v4 == 0xfa)
2031 udelay(5);
2032 else if (v4 == 0xf9)
2033 udelay(1);
2034 }
2035 _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3,
2036 v4, v5, v6);
2037 continue;
2038 } else {
2039 /*don't need the hw_body*/
2040 if (!_rtl8821ae_check_condition(hw, v1)) {
2041 i += 2; /* skip the pair of expression*/
2042 v1 = array[i];
2043 v2 = array[i+1];
2044 v3 = array[i+2];
2045 while (v2 != 0xDEAD) {
2046 i += 3;
2047 v1 = array[i];
2048 v2 = array[i+1];
2049 v3 = array[i+2];
2050 }
2051 }
2052 }
2053 }
2054
2055 return true;
2056 }
2057
rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw * hw,enum radio_path rfpath)2058 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
2059 enum radio_path rfpath)
2060 {
2061 u32 *radioa_array_table_a, *radioa_array_table_b;
2062 u16 radioa_arraylen_a, radioa_arraylen_b;
2063 struct rtl_priv *rtlpriv = rtl_priv(hw);
2064
2065 radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN;
2066 radioa_array_table_a = RTL8812AE_RADIOA_ARRAY;
2067 radioa_arraylen_b = RTL8812AE_RADIOB_1TARRAYLEN;
2068 radioa_array_table_b = RTL8812AE_RADIOB_ARRAY;
2069 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2070 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen_a);
2071 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2072 switch (rfpath) {
2073 case RF90_PATH_A:
2074 return __rtl8821ae_phy_config_with_headerfile(hw,
2075 radioa_array_table_a, radioa_arraylen_a,
2076 _rtl8821ae_config_rf_radio_a);
2077 break;
2078 case RF90_PATH_B:
2079 return __rtl8821ae_phy_config_with_headerfile(hw,
2080 radioa_array_table_b, radioa_arraylen_b,
2081 _rtl8821ae_config_rf_radio_b);
2082 break;
2083 case RF90_PATH_C:
2084 case RF90_PATH_D:
2085 pr_err("switch case %#x not processed\n", rfpath);
2086 break;
2087 }
2088 return true;
2089 }
2090
rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw * hw,enum radio_path rfpath)2091 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
2092 enum radio_path rfpath)
2093 {
2094 u32 *radioa_array_table;
2095 u16 radioa_arraylen;
2096 struct rtl_priv *rtlpriv = rtl_priv(hw);
2097
2098 radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN;
2099 radioa_array_table = RTL8821AE_RADIOA_ARRAY;
2100 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2101 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen);
2102 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2103 switch (rfpath) {
2104 case RF90_PATH_A:
2105 return __rtl8821ae_phy_config_with_headerfile(hw,
2106 radioa_array_table, radioa_arraylen,
2107 _rtl8821ae_config_rf_radio_a);
2108 break;
2109
2110 case RF90_PATH_B:
2111 case RF90_PATH_C:
2112 case RF90_PATH_D:
2113 pr_err("switch case %#x not processed\n", rfpath);
2114 break;
2115 }
2116 return true;
2117 }
2118
rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw * hw)2119 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
2120 {
2121 struct rtl_priv *rtlpriv = rtl_priv(hw);
2122 struct rtl_phy *rtlphy = &rtlpriv->phy;
2123
2124 rtlphy->default_initialgain[0] =
2125 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
2126 rtlphy->default_initialgain[1] =
2127 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
2128 rtlphy->default_initialgain[2] =
2129 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
2130 rtlphy->default_initialgain[3] =
2131 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
2132
2133 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2134 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
2135 rtlphy->default_initialgain[0],
2136 rtlphy->default_initialgain[1],
2137 rtlphy->default_initialgain[2],
2138 rtlphy->default_initialgain[3]);
2139
2140 rtlphy->framesync = (u8)rtl_get_bbreg(hw,
2141 ROFDM0_RXDETECTOR3, MASKBYTE0);
2142 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
2143 ROFDM0_RXDETECTOR2, MASKDWORD);
2144
2145 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2146 "Default framesync (0x%x) = 0x%x\n",
2147 ROFDM0_RXDETECTOR3, rtlphy->framesync);
2148 }
2149
phy_init_bb_rf_register_definition(struct ieee80211_hw * hw)2150 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
2151 {
2152 struct rtl_priv *rtlpriv = rtl_priv(hw);
2153 struct rtl_phy *rtlphy = &rtlpriv->phy;
2154
2155 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2156 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2157
2158 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
2159 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
2160
2161 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
2162 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
2163
2164 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A;
2165 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A;
2166
2167 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE;
2168 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE;
2169
2170 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8821A;
2171 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8821A;
2172
2173 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8821A;
2174 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8821A;
2175 }
2176
rtl8821ae_phy_get_txpower_level(struct ieee80211_hw * hw,long * powerlevel)2177 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
2178 {
2179 struct rtl_priv *rtlpriv = rtl_priv(hw);
2180 struct rtl_phy *rtlphy = &rtlpriv->phy;
2181 u8 txpwr_level;
2182 long txpwr_dbm;
2183
2184 txpwr_level = rtlphy->cur_cck_txpwridx;
2185 txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2186 WIRELESS_MODE_B, txpwr_level);
2187 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2188 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2189 WIRELESS_MODE_G,
2190 txpwr_level) > txpwr_dbm)
2191 txpwr_dbm =
2192 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
2193 txpwr_level);
2194 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2195 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2196 WIRELESS_MODE_N_24G,
2197 txpwr_level) > txpwr_dbm)
2198 txpwr_dbm =
2199 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
2200 txpwr_level);
2201 *powerlevel = txpwr_dbm;
2202 }
2203
_rtl8821ae_phy_get_chnl_index(u8 channel,u8 * chnl_index)2204 static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index)
2205 {
2206 u8 i = 0;
2207 bool in_24g = true;
2208
2209 if (channel <= 14) {
2210 in_24g = true;
2211 *chnl_index = channel - 1;
2212 } else {
2213 in_24g = false;
2214
2215 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; ++i) {
2216 if (channel5g[i] == channel) {
2217 *chnl_index = i;
2218 return in_24g;
2219 }
2220 }
2221 }
2222 return in_24g;
2223 }
2224
_rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path,u8 rate)2225 static s8 _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate)
2226 {
2227 s8 rate_section = 0;
2228 switch (rate) {
2229 case DESC_RATE1M:
2230 case DESC_RATE2M:
2231 case DESC_RATE5_5M:
2232 case DESC_RATE11M:
2233 rate_section = 0;
2234 break;
2235 case DESC_RATE6M:
2236 case DESC_RATE9M:
2237 case DESC_RATE12M:
2238 case DESC_RATE18M:
2239 rate_section = 1;
2240 break;
2241 case DESC_RATE24M:
2242 case DESC_RATE36M:
2243 case DESC_RATE48M:
2244 case DESC_RATE54M:
2245 rate_section = 2;
2246 break;
2247 case DESC_RATEMCS0:
2248 case DESC_RATEMCS1:
2249 case DESC_RATEMCS2:
2250 case DESC_RATEMCS3:
2251 rate_section = 3;
2252 break;
2253 case DESC_RATEMCS4:
2254 case DESC_RATEMCS5:
2255 case DESC_RATEMCS6:
2256 case DESC_RATEMCS7:
2257 rate_section = 4;
2258 break;
2259 case DESC_RATEMCS8:
2260 case DESC_RATEMCS9:
2261 case DESC_RATEMCS10:
2262 case DESC_RATEMCS11:
2263 rate_section = 5;
2264 break;
2265 case DESC_RATEMCS12:
2266 case DESC_RATEMCS13:
2267 case DESC_RATEMCS14:
2268 case DESC_RATEMCS15:
2269 rate_section = 6;
2270 break;
2271 case DESC_RATEVHT1SS_MCS0:
2272 case DESC_RATEVHT1SS_MCS1:
2273 case DESC_RATEVHT1SS_MCS2:
2274 case DESC_RATEVHT1SS_MCS3:
2275 rate_section = 7;
2276 break;
2277 case DESC_RATEVHT1SS_MCS4:
2278 case DESC_RATEVHT1SS_MCS5:
2279 case DESC_RATEVHT1SS_MCS6:
2280 case DESC_RATEVHT1SS_MCS7:
2281 rate_section = 8;
2282 break;
2283 case DESC_RATEVHT1SS_MCS8:
2284 case DESC_RATEVHT1SS_MCS9:
2285 case DESC_RATEVHT2SS_MCS0:
2286 case DESC_RATEVHT2SS_MCS1:
2287 rate_section = 9;
2288 break;
2289 case DESC_RATEVHT2SS_MCS2:
2290 case DESC_RATEVHT2SS_MCS3:
2291 case DESC_RATEVHT2SS_MCS4:
2292 case DESC_RATEVHT2SS_MCS5:
2293 rate_section = 10;
2294 break;
2295 case DESC_RATEVHT2SS_MCS6:
2296 case DESC_RATEVHT2SS_MCS7:
2297 case DESC_RATEVHT2SS_MCS8:
2298 case DESC_RATEVHT2SS_MCS9:
2299 rate_section = 11;
2300 break;
2301 default:
2302 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n");
2303 break;
2304 }
2305
2306 return rate_section;
2307 }
2308
_rtl8812ae_phy_get_world_wide_limit(s8 * limit_table)2309 static s8 _rtl8812ae_phy_get_world_wide_limit(s8 *limit_table)
2310 {
2311 s8 min = limit_table[0];
2312 u8 i = 0;
2313
2314 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
2315 if (limit_table[i] < min)
2316 min = limit_table[i];
2317 }
2318 return min;
2319 }
2320
_rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw * hw,u8 band,enum ht_channel_width bandwidth,enum radio_path rf_path,u8 rate,u8 channel)2321 static s8 _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw *hw,
2322 u8 band,
2323 enum ht_channel_width bandwidth,
2324 enum radio_path rf_path,
2325 u8 rate, u8 channel)
2326 {
2327 struct rtl_priv *rtlpriv = rtl_priv(hw);
2328 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
2329 struct rtl_phy *rtlphy = &rtlpriv->phy;
2330 short band_temp = -1, regulation = -1, bandwidth_temp = -1,
2331 rate_section = -1, channel_temp = -1;
2332 u16 regu, bdwidth, sec, chnl;
2333 s8 power_limit = MAX_POWER_INDEX;
2334
2335 if (rtlefuse->eeprom_regulatory == 2)
2336 return MAX_POWER_INDEX;
2337
2338 regulation = TXPWR_LMT_WW;
2339
2340 if (band == BAND_ON_2_4G)
2341 band_temp = 0;
2342 else if (band == BAND_ON_5G)
2343 band_temp = 1;
2344
2345 if (bandwidth == HT_CHANNEL_WIDTH_20)
2346 bandwidth_temp = 0;
2347 else if (bandwidth == HT_CHANNEL_WIDTH_20_40)
2348 bandwidth_temp = 1;
2349 else if (bandwidth == HT_CHANNEL_WIDTH_80)
2350 bandwidth_temp = 2;
2351
2352 switch (rate) {
2353 case DESC_RATE1M:
2354 case DESC_RATE2M:
2355 case DESC_RATE5_5M:
2356 case DESC_RATE11M:
2357 rate_section = 0;
2358 break;
2359 case DESC_RATE6M:
2360 case DESC_RATE9M:
2361 case DESC_RATE12M:
2362 case DESC_RATE18M:
2363 case DESC_RATE24M:
2364 case DESC_RATE36M:
2365 case DESC_RATE48M:
2366 case DESC_RATE54M:
2367 rate_section = 1;
2368 break;
2369 case DESC_RATEMCS0:
2370 case DESC_RATEMCS1:
2371 case DESC_RATEMCS2:
2372 case DESC_RATEMCS3:
2373 case DESC_RATEMCS4:
2374 case DESC_RATEMCS5:
2375 case DESC_RATEMCS6:
2376 case DESC_RATEMCS7:
2377 rate_section = 2;
2378 break;
2379 case DESC_RATEMCS8:
2380 case DESC_RATEMCS9:
2381 case DESC_RATEMCS10:
2382 case DESC_RATEMCS11:
2383 case DESC_RATEMCS12:
2384 case DESC_RATEMCS13:
2385 case DESC_RATEMCS14:
2386 case DESC_RATEMCS15:
2387 rate_section = 3;
2388 break;
2389 case DESC_RATEVHT1SS_MCS0:
2390 case DESC_RATEVHT1SS_MCS1:
2391 case DESC_RATEVHT1SS_MCS2:
2392 case DESC_RATEVHT1SS_MCS3:
2393 case DESC_RATEVHT1SS_MCS4:
2394 case DESC_RATEVHT1SS_MCS5:
2395 case DESC_RATEVHT1SS_MCS6:
2396 case DESC_RATEVHT1SS_MCS7:
2397 case DESC_RATEVHT1SS_MCS8:
2398 case DESC_RATEVHT1SS_MCS9:
2399 rate_section = 4;
2400 break;
2401 case DESC_RATEVHT2SS_MCS0:
2402 case DESC_RATEVHT2SS_MCS1:
2403 case DESC_RATEVHT2SS_MCS2:
2404 case DESC_RATEVHT2SS_MCS3:
2405 case DESC_RATEVHT2SS_MCS4:
2406 case DESC_RATEVHT2SS_MCS5:
2407 case DESC_RATEVHT2SS_MCS6:
2408 case DESC_RATEVHT2SS_MCS7:
2409 case DESC_RATEVHT2SS_MCS8:
2410 case DESC_RATEVHT2SS_MCS9:
2411 rate_section = 5;
2412 break;
2413 default:
2414 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2415 "Wrong rate 0x%x\n", rate);
2416 break;
2417 }
2418
2419 if (band_temp == BAND_ON_5G && rate_section == 0)
2420 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2421 "Wrong rate 0x%x: No CCK in 5G Band\n", rate);
2422
2423 /*workaround for wrong index combination to obtain tx power limit,
2424 OFDM only exists in BW 20M*/
2425 if (rate_section == 1)
2426 bandwidth_temp = 0;
2427
2428 /*workaround for wrong index combination to obtain tx power limit,
2429 *HT on 80M will reference to HT on 40M
2430 */
2431 if ((rate_section == 2 || rate_section == 3) && band == BAND_ON_5G &&
2432 bandwidth_temp == 2)
2433 bandwidth_temp = 1;
2434
2435 if (band == BAND_ON_2_4G)
2436 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2437 BAND_ON_2_4G, channel);
2438 else if (band == BAND_ON_5G)
2439 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2440 BAND_ON_5G, channel);
2441 else if (band == BAND_ON_BOTH)
2442 ;/* BAND_ON_BOTH don't care temporarily */
2443
2444 if (band_temp == -1 || regulation == -1 || bandwidth_temp == -1 ||
2445 rate_section == -1 || channel_temp == -1) {
2446 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2447 "Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n",
2448 band_temp, regulation, bandwidth_temp, rf_path,
2449 rate_section, channel_temp);
2450 return MAX_POWER_INDEX;
2451 }
2452
2453 regu = regulation;
2454 bdwidth = bandwidth_temp;
2455 sec = rate_section;
2456 chnl = channel_temp;
2457
2458 if (band == BAND_ON_2_4G) {
2459 s8 limits[10] = {0};
2460 u8 i;
2461
2462 for (i = 0; i < 4; ++i)
2463 limits[i] = rtlphy->txpwr_limit_2_4g[i][bdwidth]
2464 [sec][chnl][rf_path];
2465
2466 power_limit = (regulation == TXPWR_LMT_WW) ?
2467 _rtl8812ae_phy_get_world_wide_limit(limits) :
2468 rtlphy->txpwr_limit_2_4g[regu][bdwidth]
2469 [sec][chnl][rf_path];
2470 } else if (band == BAND_ON_5G) {
2471 s8 limits[10] = {0};
2472 u8 i;
2473
2474 for (i = 0; i < MAX_REGULATION_NUM; ++i)
2475 limits[i] = rtlphy->txpwr_limit_5g[i][bdwidth]
2476 [sec][chnl][rf_path];
2477
2478 power_limit = (regulation == TXPWR_LMT_WW) ?
2479 _rtl8812ae_phy_get_world_wide_limit(limits) :
2480 rtlphy->txpwr_limit_5g[regu][chnl]
2481 [sec][chnl][rf_path];
2482 } else {
2483 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2484 "No power limit table of the specified band\n");
2485 }
2486 return power_limit;
2487 }
2488
_rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw * hw,u8 band,u8 path,u8 rate)2489 static s8 _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw,
2490 u8 band, u8 path, u8 rate)
2491 {
2492 struct rtl_priv *rtlpriv = rtl_priv(hw);
2493 struct rtl_phy *rtlphy = &rtlpriv->phy;
2494 u8 shift = 0, rate_section, tx_num;
2495 s8 tx_pwr_diff = 0;
2496 s8 limit = 0;
2497
2498 rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate);
2499 tx_num = RF_TX_NUM_NONIMPLEMENT;
2500
2501 if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
2502 if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
2503 (rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9))
2504 tx_num = RF_2TX;
2505 else
2506 tx_num = RF_1TX;
2507 }
2508
2509 switch (rate) {
2510 case DESC_RATE1M:
2511 case DESC_RATE6M:
2512 case DESC_RATE24M:
2513 case DESC_RATEMCS0:
2514 case DESC_RATEMCS4:
2515 case DESC_RATEMCS8:
2516 case DESC_RATEMCS12:
2517 case DESC_RATEVHT1SS_MCS0:
2518 case DESC_RATEVHT1SS_MCS4:
2519 case DESC_RATEVHT1SS_MCS8:
2520 case DESC_RATEVHT2SS_MCS2:
2521 case DESC_RATEVHT2SS_MCS6:
2522 shift = 0;
2523 break;
2524 case DESC_RATE2M:
2525 case DESC_RATE9M:
2526 case DESC_RATE36M:
2527 case DESC_RATEMCS1:
2528 case DESC_RATEMCS5:
2529 case DESC_RATEMCS9:
2530 case DESC_RATEMCS13:
2531 case DESC_RATEVHT1SS_MCS1:
2532 case DESC_RATEVHT1SS_MCS5:
2533 case DESC_RATEVHT1SS_MCS9:
2534 case DESC_RATEVHT2SS_MCS3:
2535 case DESC_RATEVHT2SS_MCS7:
2536 shift = 8;
2537 break;
2538 case DESC_RATE5_5M:
2539 case DESC_RATE12M:
2540 case DESC_RATE48M:
2541 case DESC_RATEMCS2:
2542 case DESC_RATEMCS6:
2543 case DESC_RATEMCS10:
2544 case DESC_RATEMCS14:
2545 case DESC_RATEVHT1SS_MCS2:
2546 case DESC_RATEVHT1SS_MCS6:
2547 case DESC_RATEVHT2SS_MCS0:
2548 case DESC_RATEVHT2SS_MCS4:
2549 case DESC_RATEVHT2SS_MCS8:
2550 shift = 16;
2551 break;
2552 case DESC_RATE11M:
2553 case DESC_RATE18M:
2554 case DESC_RATE54M:
2555 case DESC_RATEMCS3:
2556 case DESC_RATEMCS7:
2557 case DESC_RATEMCS11:
2558 case DESC_RATEMCS15:
2559 case DESC_RATEVHT1SS_MCS3:
2560 case DESC_RATEVHT1SS_MCS7:
2561 case DESC_RATEVHT2SS_MCS1:
2562 case DESC_RATEVHT2SS_MCS5:
2563 case DESC_RATEVHT2SS_MCS9:
2564 shift = 24;
2565 break;
2566 default:
2567 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n");
2568 break;
2569 }
2570
2571 tx_pwr_diff = (u8)(rtlphy->tx_power_by_rate_offset[band][path]
2572 [tx_num][rate_section] >> shift) & 0xff;
2573
2574 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
2575 if (rtlpriv->efuse.eeprom_regulatory != 2) {
2576 limit = _rtl8812ae_phy_get_txpower_limit(hw, band,
2577 rtlphy->current_chan_bw, path, rate,
2578 rtlphy->current_channel);
2579
2580 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2581 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) {
2582 if (limit < 0) {
2583 if (tx_pwr_diff < (-limit))
2584 tx_pwr_diff = -limit;
2585 }
2586 } else {
2587 if (limit < 0)
2588 tx_pwr_diff = limit;
2589 else
2590 tx_pwr_diff = tx_pwr_diff > limit ? limit : tx_pwr_diff;
2591 }
2592 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2593 "Maximum power by rate %d, final power by rate %d\n",
2594 limit, tx_pwr_diff);
2595 }
2596
2597 return tx_pwr_diff;
2598 }
2599
_rtl8821ae_get_txpower_index(struct ieee80211_hw * hw,u8 path,u8 rate,u8 bandwidth,u8 channel)2600 static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path,
2601 u8 rate, u8 bandwidth, u8 channel)
2602 {
2603 struct rtl_priv *rtlpriv = rtl_priv(hw);
2604 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2605 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2606 u8 index = (channel - 1);
2607 u8 txpower = 0;
2608 bool in_24g = false;
2609 s8 powerdiff_byrate = 0;
2610
2611 if (((rtlhal->current_bandtype == BAND_ON_2_4G) &&
2612 (channel > 14 || channel < 1)) ||
2613 ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) {
2614 index = 0;
2615 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2616 "Illegal channel!!\n");
2617 }
2618
2619 in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index);
2620 if (in_24g) {
2621 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2622 txpower = rtlefuse->txpwrlevel_cck[path][index];
2623 else if (DESC_RATE6M <= rate)
2624 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
2625 else
2626 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "invalid rate\n");
2627
2628 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2629 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2630 txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S];
2631
2632 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2633 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2634 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2635 txpower += rtlefuse->txpwr_ht20diff[path][TX_1S];
2636 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2637 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2638 txpower += rtlefuse->txpwr_ht20diff[path][TX_2S];
2639 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2640 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2641 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2642 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2643 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2644 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2645 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2646 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2647 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2648 (DESC_RATEVHT1SS_MCS0 <= rate &&
2649 rate <= DESC_RATEVHT2SS_MCS9))
2650 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2651 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2652 (DESC_RATEVHT2SS_MCS0 <= rate &&
2653 rate <= DESC_RATEVHT2SS_MCS9))
2654 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2655 }
2656 } else {
2657 if (DESC_RATE6M <= rate)
2658 txpower = rtlefuse->txpwr_5g_bw40base[path][index];
2659 else
2660 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_WARNING,
2661 "INVALID Rate.\n");
2662
2663 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2664 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2665 txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S];
2666
2667 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2668 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2669 (DESC_RATEVHT1SS_MCS0 <= rate &&
2670 rate <= DESC_RATEVHT2SS_MCS9))
2671 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S];
2672 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2673 (DESC_RATEVHT2SS_MCS0 <= rate &&
2674 rate <= DESC_RATEVHT2SS_MCS9))
2675 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S];
2676 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2677 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2678 (DESC_RATEVHT1SS_MCS0 <= rate &&
2679 rate <= DESC_RATEVHT2SS_MCS9))
2680 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S];
2681 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2682 (DESC_RATEVHT2SS_MCS0 <= rate &&
2683 rate <= DESC_RATEVHT2SS_MCS9))
2684 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S];
2685 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2686 u8 i;
2687
2688 for (i = 0; i < sizeof(channel5g_80m) / sizeof(u8); ++i)
2689 if (channel5g_80m[i] == channel)
2690 index = i;
2691
2692 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2693 (DESC_RATEVHT1SS_MCS0 <= rate &&
2694 rate <= DESC_RATEVHT2SS_MCS9))
2695 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2696 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S];
2697 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2698 (DESC_RATEVHT2SS_MCS0 <= rate &&
2699 rate <= DESC_RATEVHT2SS_MCS9))
2700 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2701 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S]
2702 + rtlefuse->txpwr_5g_bw80diff[path][TX_2S];
2703 }
2704 }
2705 if (rtlefuse->eeprom_regulatory != 2)
2706 powerdiff_byrate =
2707 _rtl8821ae_phy_get_txpower_by_rate(hw, (u8)(!in_24g),
2708 path, rate);
2709
2710 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2711 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9)
2712 txpower -= powerdiff_byrate;
2713 else
2714 txpower += powerdiff_byrate;
2715
2716 if (rate > DESC_RATE11M)
2717 txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path];
2718 else
2719 txpower += rtlpriv->dm.remnant_cck_idx;
2720
2721 if (txpower > MAX_POWER_INDEX)
2722 txpower = MAX_POWER_INDEX;
2723
2724 return txpower;
2725 }
2726
_rtl8821ae_phy_set_txpower_index(struct ieee80211_hw * hw,u8 power_index,u8 path,u8 rate)2727 static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw,
2728 u8 power_index, u8 path, u8 rate)
2729 {
2730 struct rtl_priv *rtlpriv = rtl_priv(hw);
2731
2732 if (path == RF90_PATH_A) {
2733 switch (rate) {
2734 case DESC_RATE1M:
2735 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2736 MASKBYTE0, power_index);
2737 break;
2738 case DESC_RATE2M:
2739 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2740 MASKBYTE1, power_index);
2741 break;
2742 case DESC_RATE5_5M:
2743 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2744 MASKBYTE2, power_index);
2745 break;
2746 case DESC_RATE11M:
2747 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2748 MASKBYTE3, power_index);
2749 break;
2750 case DESC_RATE6M:
2751 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2752 MASKBYTE0, power_index);
2753 break;
2754 case DESC_RATE9M:
2755 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2756 MASKBYTE1, power_index);
2757 break;
2758 case DESC_RATE12M:
2759 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2760 MASKBYTE2, power_index);
2761 break;
2762 case DESC_RATE18M:
2763 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2764 MASKBYTE3, power_index);
2765 break;
2766 case DESC_RATE24M:
2767 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2768 MASKBYTE0, power_index);
2769 break;
2770 case DESC_RATE36M:
2771 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2772 MASKBYTE1, power_index);
2773 break;
2774 case DESC_RATE48M:
2775 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2776 MASKBYTE2, power_index);
2777 break;
2778 case DESC_RATE54M:
2779 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2780 MASKBYTE3, power_index);
2781 break;
2782 case DESC_RATEMCS0:
2783 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2784 MASKBYTE0, power_index);
2785 break;
2786 case DESC_RATEMCS1:
2787 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2788 MASKBYTE1, power_index);
2789 break;
2790 case DESC_RATEMCS2:
2791 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2792 MASKBYTE2, power_index);
2793 break;
2794 case DESC_RATEMCS3:
2795 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2796 MASKBYTE3, power_index);
2797 break;
2798 case DESC_RATEMCS4:
2799 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2800 MASKBYTE0, power_index);
2801 break;
2802 case DESC_RATEMCS5:
2803 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2804 MASKBYTE1, power_index);
2805 break;
2806 case DESC_RATEMCS6:
2807 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2808 MASKBYTE2, power_index);
2809 break;
2810 case DESC_RATEMCS7:
2811 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2812 MASKBYTE3, power_index);
2813 break;
2814 case DESC_RATEMCS8:
2815 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2816 MASKBYTE0, power_index);
2817 break;
2818 case DESC_RATEMCS9:
2819 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2820 MASKBYTE1, power_index);
2821 break;
2822 case DESC_RATEMCS10:
2823 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2824 MASKBYTE2, power_index);
2825 break;
2826 case DESC_RATEMCS11:
2827 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2828 MASKBYTE3, power_index);
2829 break;
2830 case DESC_RATEMCS12:
2831 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2832 MASKBYTE0, power_index);
2833 break;
2834 case DESC_RATEMCS13:
2835 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2836 MASKBYTE1, power_index);
2837 break;
2838 case DESC_RATEMCS14:
2839 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2840 MASKBYTE2, power_index);
2841 break;
2842 case DESC_RATEMCS15:
2843 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2844 MASKBYTE3, power_index);
2845 break;
2846 case DESC_RATEVHT1SS_MCS0:
2847 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2848 MASKBYTE0, power_index);
2849 break;
2850 case DESC_RATEVHT1SS_MCS1:
2851 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2852 MASKBYTE1, power_index);
2853 break;
2854 case DESC_RATEVHT1SS_MCS2:
2855 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2856 MASKBYTE2, power_index);
2857 break;
2858 case DESC_RATEVHT1SS_MCS3:
2859 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2860 MASKBYTE3, power_index);
2861 break;
2862 case DESC_RATEVHT1SS_MCS4:
2863 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2864 MASKBYTE0, power_index);
2865 break;
2866 case DESC_RATEVHT1SS_MCS5:
2867 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2868 MASKBYTE1, power_index);
2869 break;
2870 case DESC_RATEVHT1SS_MCS6:
2871 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2872 MASKBYTE2, power_index);
2873 break;
2874 case DESC_RATEVHT1SS_MCS7:
2875 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2876 MASKBYTE3, power_index);
2877 break;
2878 case DESC_RATEVHT1SS_MCS8:
2879 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2880 MASKBYTE0, power_index);
2881 break;
2882 case DESC_RATEVHT1SS_MCS9:
2883 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2884 MASKBYTE1, power_index);
2885 break;
2886 case DESC_RATEVHT2SS_MCS0:
2887 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2888 MASKBYTE2, power_index);
2889 break;
2890 case DESC_RATEVHT2SS_MCS1:
2891 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2892 MASKBYTE3, power_index);
2893 break;
2894 case DESC_RATEVHT2SS_MCS2:
2895 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2896 MASKBYTE0, power_index);
2897 break;
2898 case DESC_RATEVHT2SS_MCS3:
2899 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2900 MASKBYTE1, power_index);
2901 break;
2902 case DESC_RATEVHT2SS_MCS4:
2903 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2904 MASKBYTE2, power_index);
2905 break;
2906 case DESC_RATEVHT2SS_MCS5:
2907 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2908 MASKBYTE3, power_index);
2909 break;
2910 case DESC_RATEVHT2SS_MCS6:
2911 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2912 MASKBYTE0, power_index);
2913 break;
2914 case DESC_RATEVHT2SS_MCS7:
2915 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2916 MASKBYTE1, power_index);
2917 break;
2918 case DESC_RATEVHT2SS_MCS8:
2919 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2920 MASKBYTE2, power_index);
2921 break;
2922 case DESC_RATEVHT2SS_MCS9:
2923 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2924 MASKBYTE3, power_index);
2925 break;
2926 default:
2927 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2928 "Invalid Rate!!\n");
2929 break;
2930 }
2931 } else if (path == RF90_PATH_B) {
2932 switch (rate) {
2933 case DESC_RATE1M:
2934 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2935 MASKBYTE0, power_index);
2936 break;
2937 case DESC_RATE2M:
2938 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2939 MASKBYTE1, power_index);
2940 break;
2941 case DESC_RATE5_5M:
2942 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2943 MASKBYTE2, power_index);
2944 break;
2945 case DESC_RATE11M:
2946 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2947 MASKBYTE3, power_index);
2948 break;
2949 case DESC_RATE6M:
2950 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2951 MASKBYTE0, power_index);
2952 break;
2953 case DESC_RATE9M:
2954 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2955 MASKBYTE1, power_index);
2956 break;
2957 case DESC_RATE12M:
2958 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2959 MASKBYTE2, power_index);
2960 break;
2961 case DESC_RATE18M:
2962 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2963 MASKBYTE3, power_index);
2964 break;
2965 case DESC_RATE24M:
2966 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2967 MASKBYTE0, power_index);
2968 break;
2969 case DESC_RATE36M:
2970 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2971 MASKBYTE1, power_index);
2972 break;
2973 case DESC_RATE48M:
2974 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2975 MASKBYTE2, power_index);
2976 break;
2977 case DESC_RATE54M:
2978 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2979 MASKBYTE3, power_index);
2980 break;
2981 case DESC_RATEMCS0:
2982 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2983 MASKBYTE0, power_index);
2984 break;
2985 case DESC_RATEMCS1:
2986 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2987 MASKBYTE1, power_index);
2988 break;
2989 case DESC_RATEMCS2:
2990 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2991 MASKBYTE2, power_index);
2992 break;
2993 case DESC_RATEMCS3:
2994 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2995 MASKBYTE3, power_index);
2996 break;
2997 case DESC_RATEMCS4:
2998 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
2999 MASKBYTE0, power_index);
3000 break;
3001 case DESC_RATEMCS5:
3002 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3003 MASKBYTE1, power_index);
3004 break;
3005 case DESC_RATEMCS6:
3006 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3007 MASKBYTE2, power_index);
3008 break;
3009 case DESC_RATEMCS7:
3010 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3011 MASKBYTE3, power_index);
3012 break;
3013 case DESC_RATEMCS8:
3014 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3015 MASKBYTE0, power_index);
3016 break;
3017 case DESC_RATEMCS9:
3018 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3019 MASKBYTE1, power_index);
3020 break;
3021 case DESC_RATEMCS10:
3022 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3023 MASKBYTE2, power_index);
3024 break;
3025 case DESC_RATEMCS11:
3026 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3027 MASKBYTE3, power_index);
3028 break;
3029 case DESC_RATEMCS12:
3030 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3031 MASKBYTE0, power_index);
3032 break;
3033 case DESC_RATEMCS13:
3034 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3035 MASKBYTE1, power_index);
3036 break;
3037 case DESC_RATEMCS14:
3038 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3039 MASKBYTE2, power_index);
3040 break;
3041 case DESC_RATEMCS15:
3042 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3043 MASKBYTE3, power_index);
3044 break;
3045 case DESC_RATEVHT1SS_MCS0:
3046 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3047 MASKBYTE0, power_index);
3048 break;
3049 case DESC_RATEVHT1SS_MCS1:
3050 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3051 MASKBYTE1, power_index);
3052 break;
3053 case DESC_RATEVHT1SS_MCS2:
3054 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3055 MASKBYTE2, power_index);
3056 break;
3057 case DESC_RATEVHT1SS_MCS3:
3058 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3059 MASKBYTE3, power_index);
3060 break;
3061 case DESC_RATEVHT1SS_MCS4:
3062 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3063 MASKBYTE0, power_index);
3064 break;
3065 case DESC_RATEVHT1SS_MCS5:
3066 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3067 MASKBYTE1, power_index);
3068 break;
3069 case DESC_RATEVHT1SS_MCS6:
3070 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3071 MASKBYTE2, power_index);
3072 break;
3073 case DESC_RATEVHT1SS_MCS7:
3074 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3075 MASKBYTE3, power_index);
3076 break;
3077 case DESC_RATEVHT1SS_MCS8:
3078 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3079 MASKBYTE0, power_index);
3080 break;
3081 case DESC_RATEVHT1SS_MCS9:
3082 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3083 MASKBYTE1, power_index);
3084 break;
3085 case DESC_RATEVHT2SS_MCS0:
3086 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3087 MASKBYTE2, power_index);
3088 break;
3089 case DESC_RATEVHT2SS_MCS1:
3090 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3091 MASKBYTE3, power_index);
3092 break;
3093 case DESC_RATEVHT2SS_MCS2:
3094 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3095 MASKBYTE0, power_index);
3096 break;
3097 case DESC_RATEVHT2SS_MCS3:
3098 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3099 MASKBYTE1, power_index);
3100 break;
3101 case DESC_RATEVHT2SS_MCS4:
3102 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3103 MASKBYTE2, power_index);
3104 break;
3105 case DESC_RATEVHT2SS_MCS5:
3106 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3107 MASKBYTE3, power_index);
3108 break;
3109 case DESC_RATEVHT2SS_MCS6:
3110 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3111 MASKBYTE0, power_index);
3112 break;
3113 case DESC_RATEVHT2SS_MCS7:
3114 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3115 MASKBYTE1, power_index);
3116 break;
3117 case DESC_RATEVHT2SS_MCS8:
3118 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3119 MASKBYTE2, power_index);
3120 break;
3121 case DESC_RATEVHT2SS_MCS9:
3122 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3123 MASKBYTE3, power_index);
3124 break;
3125 default:
3126 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3127 "Invalid Rate!!\n");
3128 break;
3129 }
3130 } else {
3131 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3132 "Invalid RFPath!!\n");
3133 }
3134 }
3135
_rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw * hw,u8 * array,u8 path,u8 channel,u8 size)3136 static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3137 u8 *array, u8 path,
3138 u8 channel, u8 size)
3139 {
3140 struct rtl_priv *rtlpriv = rtl_priv(hw);
3141 struct rtl_phy *rtlphy = &rtlpriv->phy;
3142 u8 i;
3143 u8 power_index;
3144
3145 for (i = 0; i < size; i++) {
3146 power_index =
3147 _rtl8821ae_get_txpower_index(hw, path, array[i],
3148 rtlphy->current_chan_bw,
3149 channel);
3150 _rtl8821ae_phy_set_txpower_index(hw, power_index, path,
3151 array[i]);
3152 }
3153 }
3154
_rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw * hw,u8 bw,u8 channel,u8 path)3155 static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw,
3156 u8 bw, u8 channel, u8 path)
3157 {
3158 struct rtl_priv *rtlpriv = rtl_priv(hw);
3159 struct rtl_phy *rtlphy = &rtlpriv->phy;
3160
3161 u8 i;
3162 u32 power_level, data, offset;
3163
3164 if (path >= rtlphy->num_total_rfpath)
3165 return;
3166
3167 data = 0;
3168 if (path == RF90_PATH_A) {
3169 power_level =
3170 _rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
3171 DESC_RATEMCS7, bw, channel);
3172 offset = RA_TXPWRTRAING;
3173 } else {
3174 power_level =
3175 _rtl8821ae_get_txpower_index(hw, RF90_PATH_B,
3176 DESC_RATEMCS7, bw, channel);
3177 offset = RB_TXPWRTRAING;
3178 }
3179
3180 for (i = 0; i < 3; i++) {
3181 if (i == 0)
3182 power_level = power_level - 10;
3183 else if (i == 1)
3184 power_level = power_level - 8;
3185 else
3186 power_level = power_level - 6;
3187
3188 data |= (((power_level > 2) ? (power_level) : 2) << (i * 8));
3189 }
3190 rtl_set_bbreg(hw, offset, 0xffffff, data);
3191 }
3192
rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw * hw,u8 channel,u8 path)3193 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3194 u8 channel, u8 path)
3195 {
3196 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
3197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3198 struct rtl_priv *rtlpriv = rtl_priv(hw);
3199 struct rtl_phy *rtlphy = &rtlpriv->phy;
3200 u8 cck_rates[] = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M,
3201 DESC_RATE11M};
3202 u8 sizes_of_cck_retes = 4;
3203 u8 ofdm_rates[] = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
3204 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
3205 DESC_RATE48M, DESC_RATE54M};
3206 u8 sizes_of_ofdm_retes = 8;
3207 u8 ht_rates_1t[] = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
3208 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
3209 DESC_RATEMCS6, DESC_RATEMCS7};
3210 u8 sizes_of_ht_retes_1t = 8;
3211 u8 ht_rates_2t[] = {DESC_RATEMCS8, DESC_RATEMCS9,
3212 DESC_RATEMCS10, DESC_RATEMCS11,
3213 DESC_RATEMCS12, DESC_RATEMCS13,
3214 DESC_RATEMCS14, DESC_RATEMCS15};
3215 u8 sizes_of_ht_retes_2t = 8;
3216 u8 vht_rates_1t[] = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
3217 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
3218 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
3219 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
3220 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
3221 u8 vht_rates_2t[] = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
3222 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
3223 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
3224 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
3225 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
3226 u8 sizes_of_vht_retes = 10;
3227
3228 if (rtlhal->current_bandtype == BAND_ON_2_4G)
3229 _rtl8821ae_phy_set_txpower_level_by_path(hw, cck_rates, path, channel,
3230 sizes_of_cck_retes);
3231
3232 _rtl8821ae_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel,
3233 sizes_of_ofdm_retes);
3234 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel,
3235 sizes_of_ht_retes_1t);
3236 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_1t, path, channel,
3237 sizes_of_vht_retes);
3238
3239 if (rtlphy->num_total_rfpath >= 2) {
3240 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_2t, path,
3241 channel,
3242 sizes_of_ht_retes_2t);
3243 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_2t, path,
3244 channel,
3245 sizes_of_vht_retes);
3246 }
3247
3248 _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw,
3249 channel, path);
3250 }
3251
3252 /*just in case, write txpower in DW, to reduce time*/
rtl8821ae_phy_set_txpower_level(struct ieee80211_hw * hw,u8 channel)3253 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
3254 {
3255 struct rtl_priv *rtlpriv = rtl_priv(hw);
3256 struct rtl_phy *rtlphy = &rtlpriv->phy;
3257 u8 path = 0;
3258
3259 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path)
3260 rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path);
3261 }
3262
_rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw * hw,enum wireless_mode wirelessmode,u8 txpwridx)3263 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
3264 enum wireless_mode wirelessmode,
3265 u8 txpwridx)
3266 {
3267 long offset;
3268 long pwrout_dbm;
3269
3270 switch (wirelessmode) {
3271 case WIRELESS_MODE_B:
3272 offset = -7;
3273 break;
3274 case WIRELESS_MODE_G:
3275 case WIRELESS_MODE_N_24G:
3276 offset = -8;
3277 break;
3278 default:
3279 offset = -8;
3280 break;
3281 }
3282 pwrout_dbm = txpwridx / 2 + offset;
3283 return pwrout_dbm;
3284 }
3285
rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw * hw,u8 operation)3286 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
3287 {
3288 struct rtl_priv *rtlpriv = rtl_priv(hw);
3289 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3290 enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3291
3292 if (!is_hal_stop(rtlhal)) {
3293 switch (operation) {
3294 case SCAN_OPT_BACKUP_BAND0:
3295 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3296 rtlpriv->cfg->ops->set_hw_reg(hw,
3297 HW_VAR_IO_CMD,
3298 (u8 *)&iotype);
3299
3300 break;
3301 case SCAN_OPT_BACKUP_BAND1:
3302 iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN;
3303 rtlpriv->cfg->ops->set_hw_reg(hw,
3304 HW_VAR_IO_CMD,
3305 (u8 *)&iotype);
3306
3307 break;
3308 case SCAN_OPT_RESTORE:
3309 iotype = IO_CMD_RESUME_DM_BY_SCAN;
3310 rtlpriv->cfg->ops->set_hw_reg(hw,
3311 HW_VAR_IO_CMD,
3312 (u8 *)&iotype);
3313 break;
3314 default:
3315 pr_err("Unknown Scan Backup operation.\n");
3316 break;
3317 }
3318 }
3319 }
3320
_rtl8821ae_phy_set_reg_bw(struct rtl_priv * rtlpriv,u8 bw)3321 static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv *rtlpriv, u8 bw)
3322 {
3323 u16 reg_rf_mode_bw, tmp = 0;
3324
3325 reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL);
3326 switch (bw) {
3327 case HT_CHANNEL_WIDTH_20:
3328 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F);
3329 break;
3330 case HT_CHANNEL_WIDTH_20_40:
3331 tmp = reg_rf_mode_bw | BIT(7);
3332 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF);
3333 break;
3334 case HT_CHANNEL_WIDTH_80:
3335 tmp = reg_rf_mode_bw | BIT(8);
3336 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F);
3337 break;
3338 default:
3339 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "unknown Bandwidth: 0x%x\n", bw);
3340 break;
3341 }
3342 }
3343
_rtl8821ae_phy_get_secondary_chnl(struct rtl_priv * rtlpriv)3344 static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv *rtlpriv)
3345 {
3346 struct rtl_phy *rtlphy = &rtlpriv->phy;
3347 struct rtl_mac *mac = rtl_mac(rtlpriv);
3348 u8 sc_set_40 = 0, sc_set_20 = 0;
3349
3350 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3351 if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3352 sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
3353 else if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3354 sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
3355 else
3356 pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3357
3358 if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3359 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3360 sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
3361 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3362 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3363 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3364 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3365 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3366 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3367 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3368 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3369 sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
3370 else
3371 pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3372 } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
3373 if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3374 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3375 else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3376 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3377 else
3378 pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3379 }
3380 return (sc_set_40 << 4) | sc_set_20;
3381 }
3382
rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw * hw)3383 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
3384 {
3385 struct rtl_priv *rtlpriv = rtl_priv(hw);
3386 struct rtl_phy *rtlphy = &rtlpriv->phy;
3387 u8 sub_chnl = 0;
3388 u8 l1pk_val = 0;
3389
3390 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3391 "Switch to %s bandwidth\n",
3392 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
3393 "20MHz" :
3394 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ?
3395 "40MHz" : "80MHz")));
3396
3397 _rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw);
3398 sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv);
3399 rtl_write_byte(rtlpriv, 0x0483, sub_chnl);
3400
3401 switch (rtlphy->current_chan_bw) {
3402 case HT_CHANNEL_WIDTH_20:
3403 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200);
3404 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3405
3406 if (rtlphy->rf_type == RF_2T2R)
3407 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7);
3408 else
3409 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8);
3410 break;
3411 case HT_CHANNEL_WIDTH_20_40:
3412 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201);
3413 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3414 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3415 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3416
3417 if (rtlphy->reg_837 & BIT(2))
3418 l1pk_val = 6;
3419 else {
3420 if (rtlphy->rf_type == RF_2T2R)
3421 l1pk_val = 7;
3422 else
3423 l1pk_val = 8;
3424 }
3425 /* 0x848[25:22] = 0x6 */
3426 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3427
3428 if (sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ)
3429 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1);
3430 else
3431 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0);
3432 break;
3433
3434 case HT_CHANNEL_WIDTH_80:
3435 /* 0x8ac[21,20,9:6,1,0]=8'b11100010 */
3436 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202);
3437 /* 0x8c4[30] = 1 */
3438 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
3439 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3440 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3441
3442 if (rtlphy->reg_837 & BIT(2))
3443 l1pk_val = 5;
3444 else {
3445 if (rtlphy->rf_type == RF_2T2R)
3446 l1pk_val = 6;
3447 else
3448 l1pk_val = 7;
3449 }
3450 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3451
3452 break;
3453 default:
3454 pr_err("unknown bandwidth: %#X\n",
3455 rtlphy->current_chan_bw);
3456 break;
3457 }
3458
3459 rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel);
3460
3461 rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
3462 rtlphy->set_bwmode_inprogress = false;
3463
3464 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
3465 }
3466
rtl8821ae_phy_set_bw_mode(struct ieee80211_hw * hw,enum nl80211_channel_type ch_type)3467 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
3468 enum nl80211_channel_type ch_type)
3469 {
3470 struct rtl_priv *rtlpriv = rtl_priv(hw);
3471 struct rtl_phy *rtlphy = &rtlpriv->phy;
3472 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3473 u8 tmp_bw = rtlphy->current_chan_bw;
3474
3475 if (rtlphy->set_bwmode_inprogress)
3476 return;
3477 rtlphy->set_bwmode_inprogress = true;
3478 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
3479 rtl8821ae_phy_set_bw_mode_callback(hw);
3480 else {
3481 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3482 "FALSE driver sleep or unload\n");
3483 rtlphy->set_bwmode_inprogress = false;
3484 rtlphy->current_chan_bw = tmp_bw;
3485 }
3486 }
3487
rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw * hw)3488 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
3489 {
3490 struct rtl_priv *rtlpriv = rtl_priv(hw);
3491 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3492 struct rtl_phy *rtlphy = &rtlpriv->phy;
3493 u8 channel = rtlphy->current_channel;
3494 u8 path;
3495 u32 data;
3496
3497 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3498 "switch to channel%d\n", rtlphy->current_channel);
3499 if (is_hal_stop(rtlhal))
3500 return;
3501
3502 if (36 <= channel && channel <= 48)
3503 data = 0x494;
3504 else if (50 <= channel && channel <= 64)
3505 data = 0x453;
3506 else if (100 <= channel && channel <= 116)
3507 data = 0x452;
3508 else if (118 <= channel)
3509 data = 0x412;
3510 else
3511 data = 0x96a;
3512 rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data);
3513
3514 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++) {
3515 if (36 <= channel && channel <= 64)
3516 data = 0x101;
3517 else if (100 <= channel && channel <= 140)
3518 data = 0x301;
3519 else if (140 < channel)
3520 data = 0x501;
3521 else
3522 data = 0x000;
3523 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3524 BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data);
3525
3526 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3527 BMASKBYTE0, channel);
3528
3529 if (channel > 14) {
3530 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
3531 if (36 <= channel && channel <= 64)
3532 data = 0x114E9;
3533 else
3534 data = 0x110E9;
3535 rtl8821ae_phy_set_rf_reg(hw, path, RF_APK,
3536 BRFREGOFFSETMASK, data);
3537 }
3538 }
3539 }
3540 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3541 }
3542
rtl8821ae_phy_sw_chnl(struct ieee80211_hw * hw)3543 u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw)
3544 {
3545 struct rtl_priv *rtlpriv = rtl_priv(hw);
3546 struct rtl_phy *rtlphy = &rtlpriv->phy;
3547 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3548 u32 timeout = 1000, timecount = 0;
3549 u8 channel = rtlphy->current_channel;
3550
3551 if (rtlphy->sw_chnl_inprogress)
3552 return 0;
3553 if (rtlphy->set_bwmode_inprogress)
3554 return 0;
3555
3556 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3557 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
3558 "sw_chnl_inprogress false driver sleep or unload\n");
3559 return 0;
3560 }
3561 while (rtlphy->lck_inprogress && timecount < timeout) {
3562 mdelay(50);
3563 timecount += 50;
3564 }
3565
3566 if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G)
3567 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G);
3568 else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G)
3569 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3570
3571 rtlphy->sw_chnl_inprogress = true;
3572 if (channel == 0)
3573 channel = 1;
3574
3575 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3576 "switch to channel%d, band type is %d\n",
3577 rtlphy->current_channel, rtlhal->current_bandtype);
3578
3579 rtl8821ae_phy_sw_chnl_callback(hw);
3580
3581 rtl8821ae_dm_clear_txpower_tracking_state(hw);
3582 rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel);
3583
3584 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3585 rtlphy->sw_chnl_inprogress = false;
3586 return 1;
3587 }
3588
_rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl)3589 u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl)
3590 {
3591 static const u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] = {
3592 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3593 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
3594 56, 58, 60, 62, 64, 100, 102, 104, 106, 108,
3595 110, 112, 114, 116, 118, 120, 122, 124, 126,
3596 128, 130, 132, 134, 136, 138, 140, 149, 151,
3597 153, 155, 157, 159, 161, 163, 165};
3598 u8 place;
3599
3600 if (chnl > 14) {
3601 for (place = 14; place < sizeof(channel_all); place++)
3602 if (channel_all[place] == chnl)
3603 return place-13;
3604 }
3605
3606 return 0;
3607 }
3608
3609 #define MACBB_REG_NUM 10
3610 #define AFE_REG_NUM 14
3611 #define RF_REG_NUM 3
3612
_rtl8821ae_iqk_backup_macbb(struct ieee80211_hw * hw,u32 * macbb_backup,u32 * backup_macbb_reg,u32 mac_bb_num)3613 static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw *hw,
3614 u32 *macbb_backup,
3615 u32 *backup_macbb_reg, u32 mac_bb_num)
3616 {
3617 struct rtl_priv *rtlpriv = rtl_priv(hw);
3618 u32 i;
3619
3620 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3621 /*save MACBB default value*/
3622 for (i = 0; i < mac_bb_num; i++)
3623 macbb_backup[i] = rtl_read_dword(rtlpriv, backup_macbb_reg[i]);
3624
3625 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupMacBB Success!!!!\n");
3626 }
3627
_rtl8821ae_iqk_backup_afe(struct ieee80211_hw * hw,u32 * afe_backup,u32 * backup_afe_REG,u32 afe_num)3628 static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw *hw, u32 *afe_backup,
3629 u32 *backup_afe_REG, u32 afe_num)
3630 {
3631 struct rtl_priv *rtlpriv = rtl_priv(hw);
3632 u32 i;
3633
3634 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3635 /*Save AFE Parameters */
3636 for (i = 0; i < afe_num; i++)
3637 afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
3638 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupAFE Success!!!!\n");
3639 }
3640
_rtl8821ae_iqk_backup_rf(struct ieee80211_hw * hw,u32 * rfa_backup,u32 * rfb_backup,u32 * backup_rf_reg,u32 rf_num)3641 static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw *hw, u32 *rfa_backup,
3642 u32 *rfb_backup, u32 *backup_rf_reg,
3643 u32 rf_num)
3644 {
3645 struct rtl_priv *rtlpriv = rtl_priv(hw);
3646 u32 i;
3647
3648 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3649 /*Save RF Parameters*/
3650 for (i = 0; i < rf_num; i++) {
3651 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i],
3652 BMASKDWORD);
3653 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i],
3654 BMASKDWORD);
3655 }
3656 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupRF Success!!!!\n");
3657 }
3658
_rtl8821ae_iqk_configure_mac(struct ieee80211_hw * hw)3659 static void _rtl8821ae_iqk_configure_mac(
3660 struct ieee80211_hw *hw
3661 )
3662 {
3663 struct rtl_priv *rtlpriv = rtl_priv(hw);
3664 /* ========MAC register setting========*/
3665 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3666 rtl_write_byte(rtlpriv, 0x522, 0x3f);
3667 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
3668 rtl_write_byte(rtlpriv, 0x808, 0x00); /*RX ante off*/
3669 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/
3670 }
3671
_rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw * hw,enum radio_path path,u32 tx_x,u32 tx_y)3672 static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw *hw,
3673 enum radio_path path, u32 tx_x, u32 tx_y)
3674 {
3675 struct rtl_priv *rtlpriv = rtl_priv(hw);
3676 switch (path) {
3677 case RF90_PATH_A:
3678 /* [31] = 1 --> Page C1 */
3679 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1);
3680 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3681 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
3682 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
3683 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
3684 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
3685 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3686 "TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3687 tx_x, tx_y);
3688 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3689 "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
3690 rtl_get_bbreg(hw, 0xcd4, 0x000007ff),
3691 rtl_get_bbreg(hw, 0xccc, 0x000007ff));
3692 break;
3693 default:
3694 break;
3695 }
3696 }
3697
_rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw * hw,enum radio_path path,u32 rx_x,u32 rx_y)3698 static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw *hw,
3699 enum radio_path path, u32 rx_x, u32 rx_y)
3700 {
3701 struct rtl_priv *rtlpriv = rtl_priv(hw);
3702 switch (path) {
3703 case RF90_PATH_A:
3704 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3705 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1);
3706 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1);
3707 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3708 "rx_x = %x;;rx_y = %x ====>fill to IQC\n",
3709 rx_x >> 1, rx_y >> 1);
3710 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3711 "0xc10 = %x ====>fill to IQC\n",
3712 rtl_read_dword(rtlpriv, 0xc10));
3713 break;
3714 default:
3715 break;
3716 }
3717 }
3718
3719 #define cal_num 10
3720
_rtl8821ae_iqk_tx(struct ieee80211_hw * hw,enum radio_path path)3721 static void _rtl8821ae_iqk_tx(struct ieee80211_hw *hw, enum radio_path path)
3722 {
3723 struct rtl_priv *rtlpriv = rtl_priv(hw);
3724 struct rtl_phy *rtlphy = &rtlpriv->phy;
3725 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3726
3727 u32 tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65;
3728 int tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0;
3729 int tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num],
3730 tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num],
3731 tx_dt[cal_num], rx_dt[cal_num];
3732 bool tx0iqkok = false, rx0iqkok = false;
3733 bool vdf_enable = false;
3734 int i, k, vdf_y[3], vdf_x[3],
3735 ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0;
3736
3737 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3738 "BandWidth = %d.\n",
3739 rtlphy->current_chan_bw);
3740 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3741 vdf_enable = true;
3742
3743 while (cal < cal_num) {
3744 switch (path) {
3745 case RF90_PATH_A:
3746 temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff);
3747 /* Path-A LOK */
3748 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3749 /*========Path-A AFE all on========*/
3750 /*Port 0 DAC/ADC on*/
3751 rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
3752 rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
3753 rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
3754 rtl_write_dword(rtlpriv, 0xc6c, 0x19791979);
3755 rtl_write_dword(rtlpriv, 0xc70, 0x19791979);
3756 rtl_write_dword(rtlpriv, 0xc74, 0x19791979);
3757 rtl_write_dword(rtlpriv, 0xc78, 0x19791979);
3758 rtl_write_dword(rtlpriv, 0xc7c, 0x19791979);
3759 rtl_write_dword(rtlpriv, 0xc80, 0x19791979);
3760 rtl_write_dword(rtlpriv, 0xc84, 0x19791979);
3761
3762 rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
3763
3764 /* LOK Setting */
3765 /* ====== LOK ====== */
3766 /*DAC/ADC sampling rate (160 MHz)*/
3767 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3768
3769 /* 2. LoK RF Setting (at BW = 20M) */
3770 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002);
3771 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3); /* BW 20M */
3772 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3773 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3774 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3775 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3776 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3777 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
3778 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3779 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3780 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3781 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3782 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3783 rtl_write_dword(rtlpriv, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
3784
3785 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3786 rtl_write_dword(rtlpriv, 0xc88, 0x821403f4);
3787
3788 if (rtlhal->current_bandtype)
3789 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
3790 else
3791 rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
3792
3793 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3794 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3795 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3796 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3797 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3798
3799 mdelay(10); /* Delay 10ms */
3800 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3801
3802 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3803 rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); /* Load LOK */
3804
3805 switch (rtlphy->current_chan_bw) {
3806 case 1:
3807 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1);
3808 break;
3809 case 2:
3810 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0);
3811 break;
3812 default:
3813 break;
3814 }
3815
3816 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3817
3818 /* 3. TX RF Setting */
3819 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3820 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
3821 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3822 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3823 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3824 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3825 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3826 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
3827 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd); */
3828 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3829 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3830 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3831 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3832 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3833 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
3834
3835 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3836 rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
3837 if (rtlhal->current_bandtype)
3838 rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96);
3839 else
3840 rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96);
3841
3842 if (vdf_enable == 1) {
3843 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "VDF_enable\n");
3844 for (k = 0; k <= 2; k++) {
3845 switch (k) {
3846 case 0:
3847 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3848 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3849 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3850 break;
3851 case 1:
3852 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0);
3853 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0);
3854 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3855 break;
3856 case 2:
3857 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3858 "vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff);
3859 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3860 "vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff);
3861 tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
3862 tx_dt[cal] = ((16*tx_dt[cal])*10000/15708);
3863 tx_dt[cal] = (tx_dt[cal] >> 1)+(tx_dt[cal] & BIT(0));
3864 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3865 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3866 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);
3867 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
3868 break;
3869 default:
3870 break;
3871 }
3872 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3873 cal_retry = 0;
3874 while (1) {
3875 /* one shot */
3876 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3877 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3878
3879 mdelay(10); /* Delay 10ms */
3880 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3881 delay_count = 0;
3882 while (1) {
3883 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3884 if ((~iqk_ready) || (delay_count > 20))
3885 break;
3886 else{
3887 mdelay(1);
3888 delay_count++;
3889 }
3890 }
3891
3892 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
3893 /* ============TXIQK Check============== */
3894 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3895
3896 if (~tx_fail) {
3897 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3898 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3899 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3900 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3901 tx0iqkok = true;
3902 break;
3903 } else {
3904 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3905 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3906 tx0iqkok = false;
3907 cal_retry++;
3908 if (cal_retry == 10)
3909 break;
3910 }
3911 } else {
3912 tx0iqkok = false;
3913 cal_retry++;
3914 if (cal_retry == 10)
3915 break;
3916 }
3917 }
3918 }
3919 if (k == 3) {
3920 tx_x0[cal] = vdf_x[k-1];
3921 tx_y0[cal] = vdf_y[k-1];
3922 }
3923 } else {
3924 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3925 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3926 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3927 cal_retry = 0;
3928 while (1) {
3929 /* one shot */
3930 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3931 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3932
3933 mdelay(10); /* Delay 10ms */
3934 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3935 delay_count = 0;
3936 while (1) {
3937 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3938 if ((~iqk_ready) || (delay_count > 20))
3939 break;
3940 else{
3941 mdelay(1);
3942 delay_count++;
3943 }
3944 }
3945
3946 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
3947 /* ============TXIQK Check============== */
3948 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3949
3950 if (~tx_fail) {
3951 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3952 tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3953 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3954 tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3955 tx0iqkok = true;
3956 break;
3957 } else {
3958 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3959 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3960 tx0iqkok = false;
3961 cal_retry++;
3962 if (cal_retry == 10)
3963 break;
3964 }
3965 } else {
3966 tx0iqkok = false;
3967 cal_retry++;
3968 if (cal_retry == 10)
3969 break;
3970 }
3971 }
3972 }
3973
3974 if (tx0iqkok == false)
3975 break; /* TXK fail, Don't do RXK */
3976
3977 if (vdf_enable == 1) {
3978 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); /* TX VDF Disable */
3979 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RXVDF Start\n");
3980 for (k = 0; k <= 2; k++) {
3981 /* ====== RX mode TXK (RXK Step 1) ====== */
3982 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3983 /* 1. TX RF Setting */
3984 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
3985 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
3986 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
3987 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
3988 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
3989 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3990 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
3991
3992 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
3993 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3994 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3995 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
3996 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3997 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3998 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3999 switch (k) {
4000 case 0:
4001 {
4002 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4003 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4004 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4005 }
4006 break;
4007 case 1:
4008 {
4009 rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4010 rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4011 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4012 }
4013 break;
4014 case 2:
4015 {
4016 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4017 "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n",
4018 vdf_y[1] >> 21 & 0x00007ff,
4019 vdf_y[0] >> 21 & 0x00007ff);
4020 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4021 "VDF_X[1] = %x;;;VDF_X[0] = %x\n",
4022 vdf_x[1] >> 21 & 0x00007ff,
4023 vdf_x[0] >> 21 & 0x00007ff);
4024 rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4025 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "Rx_dt = %d\n",
4026 rx_dt[cal]);
4027 rx_dt[cal] = ((16*rx_dt[cal])*10000/13823);
4028 rx_dt[cal] = (rx_dt[cal] >> 1)+(rx_dt[cal] & BIT(0));
4029 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4030 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4031 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff);
4032 }
4033 break;
4034 default:
4035 break;
4036 }
4037 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4038 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4039 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4040 cal_retry = 0;
4041 while (1) {
4042 /* one shot */
4043 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4044 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4045
4046 mdelay(10); /* Delay 10ms */
4047 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4048 delay_count = 0;
4049 while (1) {
4050 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4051 if ((~iqk_ready) || (delay_count > 20))
4052 break;
4053 else{
4054 mdelay(1);
4055 delay_count++;
4056 }
4057 }
4058
4059 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4060 /* ============TXIQK Check============== */
4061 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4062
4063 if (~tx_fail) {
4064 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4065 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4066 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4067 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4068 tx0iqkok = true;
4069 break;
4070 } else{
4071 tx0iqkok = false;
4072 cal_retry++;
4073 if (cal_retry == 10)
4074 break;
4075 }
4076 } else {
4077 tx0iqkok = false;
4078 cal_retry++;
4079 if (cal_retry == 10)
4080 break;
4081 }
4082 }
4083
4084 if (tx0iqkok == false) { /* If RX mode TXK fail, then take TXK Result */
4085 tx_x0_rxk[cal] = tx_x0[cal];
4086 tx_y0_rxk[cal] = tx_y0[cal];
4087 tx0iqkok = true;
4088 rtl_dbg(rtlpriv,
4089 COMP_IQK,
4090 DBG_LOUD,
4091 "RXK Step 1 fail\n");
4092 }
4093
4094 /* ====== RX IQK ====== */
4095 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4096 /* 1. RX RF Setting */
4097 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4098 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4099 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4100 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4101 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4102 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4103 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4104
4105 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4106 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4107 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4108 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4109 rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe);
4110 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4111 rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4112
4113 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4114 rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1);
4115 rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0);
4116 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4117
4118 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */
4119
4120 if (k == 2)
4121 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); /* RX VDF Enable */
4122 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4123
4124 cal_retry = 0;
4125 while (1) {
4126 /* one shot */
4127 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4128 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4129
4130 mdelay(10); /* Delay 10ms */
4131 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4132 delay_count = 0;
4133 while (1) {
4134 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4135 if ((~iqk_ready) || (delay_count > 20))
4136 break;
4137 else{
4138 mdelay(1);
4139 delay_count++;
4140 }
4141 }
4142
4143 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4144 /* ============RXIQK Check============== */
4145 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4146 if (rx_fail == 0) {
4147 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4148 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4149 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4150 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4151 rx0iqkok = true;
4152 break;
4153 } else {
4154 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4155 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4156 rx0iqkok = false;
4157 cal_retry++;
4158 if (cal_retry == 10)
4159 break;
4160
4161 }
4162 } else{
4163 rx0iqkok = false;
4164 cal_retry++;
4165 if (cal_retry == 10)
4166 break;
4167 }
4168 }
4169
4170 }
4171 if (k == 3) {
4172 rx_x0[cal] = vdf_x[k-1];
4173 rx_y0[cal] = vdf_y[k-1];
4174 }
4175 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); /* TX VDF Enable */
4176 }
4177
4178 else{
4179 /* ====== RX mode TXK (RXK Step 1) ====== */
4180 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4181 /* 1. TX RF Setting */
4182 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4183 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4184 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4185 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4186 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4187 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4188 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4189 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4190 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4191 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4192
4193 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4194 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4195 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4196 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4197 /* ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); */
4198 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4199 cal_retry = 0;
4200 while (1) {
4201 /* one shot */
4202 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4203 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4204
4205 mdelay(10); /* Delay 10ms */
4206 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4207 delay_count = 0;
4208 while (1) {
4209 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4210 if ((~iqk_ready) || (delay_count > 20))
4211 break;
4212 else{
4213 mdelay(1);
4214 delay_count++;
4215 }
4216 }
4217
4218 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4219 /* ============TXIQK Check============== */
4220 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4221
4222 if (~tx_fail) {
4223 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4224 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4225 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4226 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4227 tx0iqkok = true;
4228 break;
4229 } else {
4230 tx0iqkok = false;
4231 cal_retry++;
4232 if (cal_retry == 10)
4233 break;
4234 }
4235 } else{
4236 tx0iqkok = false;
4237 cal_retry++;
4238 if (cal_retry == 10)
4239 break;
4240 }
4241 }
4242
4243 if (tx0iqkok == false) { /* If RX mode TXK fail, then take TXK Result */
4244 tx_x0_rxk[cal] = tx_x0[cal];
4245 tx_y0_rxk[cal] = tx_y0[cal];
4246 tx0iqkok = true;
4247 rtl_dbg(rtlpriv, COMP_IQK,
4248 DBG_LOUD, "1");
4249 }
4250
4251 /* ====== RX IQK ====== */
4252 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4253 /* 1. RX RF Setting */
4254 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4255 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4256 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4257 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4258 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4259 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4260 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4261
4262 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4263 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4264 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4265 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4266 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe); */
4267 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4268 rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4269
4270 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4271 rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4272 rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4273 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4274
4275 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/
4276
4277 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4278
4279 cal_retry = 0;
4280 while (1) {
4281 /* one shot */
4282 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4283 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4284
4285 mdelay(10); /* Delay 10ms */
4286 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4287 delay_count = 0;
4288 while (1) {
4289 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4290 if ((~iqk_ready) || (delay_count > 20))
4291 break;
4292 else{
4293 mdelay(1);
4294 delay_count++;
4295 }
4296 }
4297
4298 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4299 /* ============RXIQK Check============== */
4300 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4301 if (rx_fail == 0) {
4302 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4303 rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4304 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4305 rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4306 rx0iqkok = true;
4307 break;
4308 } else{
4309 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4310 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4311 rx0iqkok = false;
4312 cal_retry++;
4313 if (cal_retry == 10)
4314 break;
4315
4316 }
4317 } else{
4318 rx0iqkok = false;
4319 cal_retry++;
4320 if (cal_retry == 10)
4321 break;
4322 }
4323 }
4324 }
4325
4326 if (tx0iqkok)
4327 tx_average++;
4328 if (rx0iqkok)
4329 rx_average++;
4330 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4331 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4332 break;
4333 default:
4334 break;
4335 }
4336 cal++;
4337 }
4338
4339 /* FillIQK Result */
4340 switch (path) {
4341 case RF90_PATH_A:
4342 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4343 "========Path_A =======\n");
4344 if (tx_average == 0)
4345 break;
4346
4347 for (i = 0; i < tx_average; i++) {
4348 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4349 "TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i,
4350 (tx_x0_rxk[i]) >> 21 & 0x000007ff, i,
4351 (tx_y0_rxk[i]) >> 21 & 0x000007ff);
4352 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4353 "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i,
4354 (tx_x0[i]) >> 21 & 0x000007ff, i,
4355 (tx_y0[i]) >> 21 & 0x000007ff);
4356 }
4357 for (i = 0; i < tx_average; i++) {
4358 for (ii = i+1; ii < tx_average; ii++) {
4359 dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21);
4360 if (dx < 3 && dx > -3) {
4361 dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
4362 if (dy < 3 && dy > -3) {
4363 tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2;
4364 tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2;
4365 tx_finish = 1;
4366 break;
4367 }
4368 }
4369 }
4370 if (tx_finish == 1)
4371 break;
4372 }
4373
4374 if (tx_finish == 1)
4375 _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); /* ? */
4376 else
4377 _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0);
4378
4379 if (rx_average == 0)
4380 break;
4381
4382 for (i = 0; i < rx_average; i++)
4383 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4384 "RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i,
4385 (rx_x0[i])>>21&0x000007ff, i,
4386 (rx_y0[i])>>21&0x000007ff);
4387 for (i = 0; i < rx_average; i++) {
4388 for (ii = i+1; ii < rx_average; ii++) {
4389 dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21);
4390 if (dx < 4 && dx > -4) {
4391 dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21);
4392 if (dy < 4 && dy > -4) {
4393 rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2;
4394 rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2;
4395 rx_finish = 1;
4396 break;
4397 }
4398 }
4399 }
4400 if (rx_finish == 1)
4401 break;
4402 }
4403
4404 if (rx_finish == 1)
4405 _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y);
4406 else
4407 _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0);
4408 break;
4409 default:
4410 break;
4411 }
4412 }
4413
_rtl8821ae_iqk_restore_rf(struct ieee80211_hw * hw,enum radio_path path,u32 * backup_rf_reg,u32 * rf_backup,u32 rf_reg_num)4414 static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw *hw,
4415 enum radio_path path,
4416 u32 *backup_rf_reg,
4417 u32 *rf_backup, u32 rf_reg_num)
4418 {
4419 struct rtl_priv *rtlpriv = rtl_priv(hw);
4420 u32 i;
4421
4422 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4423 for (i = 0; i < RF_REG_NUM; i++)
4424 rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK,
4425 rf_backup[i]);
4426
4427 switch (path) {
4428 case RF90_PATH_A:
4429 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4430 "RestoreRF Path A Success!!!!\n");
4431 break;
4432 default:
4433 break;
4434 }
4435 }
4436
_rtl8821ae_iqk_restore_afe(struct ieee80211_hw * hw,u32 * afe_backup,u32 * backup_afe_reg,u32 afe_num)4437 static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw *hw,
4438 u32 *afe_backup, u32 *backup_afe_reg,
4439 u32 afe_num)
4440 {
4441 u32 i;
4442 struct rtl_priv *rtlpriv = rtl_priv(hw);
4443
4444 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4445 /* Reload AFE Parameters */
4446 for (i = 0; i < afe_num; i++)
4447 rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
4448 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4449 rtl_write_dword(rtlpriv, 0xc80, 0x0);
4450 rtl_write_dword(rtlpriv, 0xc84, 0x0);
4451 rtl_write_dword(rtlpriv, 0xc88, 0x0);
4452 rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
4453 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4454 rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4455 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4456 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4457 rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4458 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreAFE Success!!!!\n");
4459 }
4460
_rtl8821ae_iqk_restore_macbb(struct ieee80211_hw * hw,u32 * macbb_backup,u32 * backup_macbb_reg,u32 macbb_num)4461 static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw *hw,
4462 u32 *macbb_backup,
4463 u32 *backup_macbb_reg,
4464 u32 macbb_num)
4465 {
4466 u32 i;
4467 struct rtl_priv *rtlpriv = rtl_priv(hw);
4468
4469 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4470 /* Reload MacBB Parameters */
4471 for (i = 0; i < macbb_num; i++)
4472 rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);
4473 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreMacBB Success!!!!\n");
4474 }
4475
4476 #undef MACBB_REG_NUM
4477 #undef AFE_REG_NUM
4478 #undef RF_REG_NUM
4479
4480 #define MACBB_REG_NUM 11
4481 #define AFE_REG_NUM 12
4482 #define RF_REG_NUM 3
4483
_rtl8821ae_phy_iq_calibrate(struct ieee80211_hw * hw)4484 static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw)
4485 {
4486 u32 macbb_backup[MACBB_REG_NUM];
4487 u32 afe_backup[AFE_REG_NUM];
4488 u32 rfa_backup[RF_REG_NUM];
4489 u32 rfb_backup[RF_REG_NUM];
4490 u32 backup_macbb_reg[MACBB_REG_NUM] = {
4491 0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50,
4492 0xe00, 0xe50, 0x838, 0x82c
4493 };
4494 u32 backup_afe_reg[AFE_REG_NUM] = {
4495 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
4496 0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8
4497 };
4498 u32 backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
4499
4500 _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg,
4501 MACBB_REG_NUM);
4502 _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4503 _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg,
4504 RF_REG_NUM);
4505
4506 _rtl8821ae_iqk_configure_mac(hw);
4507 _rtl8821ae_iqk_tx(hw, RF90_PATH_A);
4508 _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup,
4509 RF_REG_NUM);
4510
4511 _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4512 _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg,
4513 MACBB_REG_NUM);
4514 }
4515
_rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw * hw,bool main)4516 static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main)
4517 {
4518 struct rtl_priv *rtlpriv = rtl_priv(hw);
4519 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */
4520 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
4521 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
4522
4523 if (main)
4524 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1);
4525 else
4526 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2);
4527 }
4528
4529 #undef IQK_ADDA_REG_NUM
4530 #undef IQK_DELAY_TIME
4531
rtl8812ae_phy_iq_calibrate(struct ieee80211_hw * hw,bool b_recovery)4532 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4533 {
4534 }
4535
rtl8812ae_do_iqk(struct ieee80211_hw * hw,u8 delta_thermal_index,u8 thermal_value,u8 threshold)4536 void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4537 u8 thermal_value, u8 threshold)
4538 {
4539 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
4540
4541 rtldm->thermalvalue_iqk = thermal_value;
4542 rtl8812ae_phy_iq_calibrate(hw, false);
4543 }
4544
rtl8821ae_phy_iq_calibrate(struct ieee80211_hw * hw,bool b_recovery)4545 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4546 {
4547 struct rtl_priv *rtlpriv = rtl_priv(hw);
4548 struct rtl_phy *rtlphy = &rtlpriv->phy;
4549
4550 if (!rtlphy->lck_inprogress) {
4551 spin_lock(&rtlpriv->locks.iqk_lock);
4552 rtlphy->lck_inprogress = true;
4553 spin_unlock(&rtlpriv->locks.iqk_lock);
4554
4555 _rtl8821ae_phy_iq_calibrate(hw);
4556
4557 spin_lock(&rtlpriv->locks.iqk_lock);
4558 rtlphy->lck_inprogress = false;
4559 spin_unlock(&rtlpriv->locks.iqk_lock);
4560 }
4561 }
4562
rtl8821ae_reset_iqk_result(struct ieee80211_hw * hw)4563 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw)
4564 {
4565 struct rtl_priv *rtlpriv = rtl_priv(hw);
4566 struct rtl_phy *rtlphy = &rtlpriv->phy;
4567 u8 i;
4568
4569 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4570 "rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
4571 (int)(sizeof(rtlphy->iqk_matrix) /
4572 sizeof(struct iqk_matrix_regs)),
4573 IQK_MATRIX_SETTINGS_NUM);
4574
4575 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
4576 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
4577 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
4578 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
4579 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
4580
4581 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
4582 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
4583 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
4584 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
4585
4586 rtlphy->iqk_matrix[i].iqk_done = false;
4587 }
4588 }
4589
rtl8821ae_do_iqk(struct ieee80211_hw * hw,u8 delta_thermal_index,u8 thermal_value,u8 threshold)4590 void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4591 u8 thermal_value, u8 threshold)
4592 {
4593 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
4594
4595 rtl8821ae_reset_iqk_result(hw);
4596
4597 rtldm->thermalvalue_iqk = thermal_value;
4598 rtl8821ae_phy_iq_calibrate(hw, false);
4599 }
4600
rtl8821ae_phy_lc_calibrate(struct ieee80211_hw * hw)4601 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw)
4602 {
4603 }
4604
rtl8821ae_phy_ap_calibrate(struct ieee80211_hw * hw,s8 delta)4605 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
4606 {
4607 }
4608
rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw * hw,bool bmain)4609 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
4610 {
4611 _rtl8821ae_phy_set_rfpath_switch(hw, bmain);
4612 }
4613
rtl8821ae_phy_set_io_cmd(struct ieee80211_hw * hw,enum io_type iotype)4614 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
4615 {
4616 struct rtl_priv *rtlpriv = rtl_priv(hw);
4617 struct rtl_phy *rtlphy = &rtlpriv->phy;
4618 bool postprocessing = false;
4619
4620 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4621 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
4622 iotype, rtlphy->set_io_inprogress);
4623 do {
4624 switch (iotype) {
4625 case IO_CMD_RESUME_DM_BY_SCAN:
4626 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4627 "[IO CMD] Resume DM after scan.\n");
4628 postprocessing = true;
4629 break;
4630 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4631 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4632 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4633 "[IO CMD] Pause DM before scan.\n");
4634 postprocessing = true;
4635 break;
4636 default:
4637 pr_err("switch case %#x not processed\n",
4638 iotype);
4639 break;
4640 }
4641 } while (false);
4642 if (postprocessing && !rtlphy->set_io_inprogress) {
4643 rtlphy->set_io_inprogress = true;
4644 rtlphy->current_io_type = iotype;
4645 } else {
4646 return false;
4647 }
4648 rtl8821ae_phy_set_io(hw);
4649 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
4650 return true;
4651 }
4652
rtl8821ae_phy_set_io(struct ieee80211_hw * hw)4653 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw)
4654 {
4655 struct rtl_priv *rtlpriv = rtl_priv(hw);
4656 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
4657 struct rtl_phy *rtlphy = &rtlpriv->phy;
4658
4659 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4660 "--->Cmd(%#x), set_io_inprogress(%d)\n",
4661 rtlphy->current_io_type, rtlphy->set_io_inprogress);
4662 switch (rtlphy->current_io_type) {
4663 case IO_CMD_RESUME_DM_BY_SCAN:
4664 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4665 _rtl8821ae_resume_tx_beacon(hw);
4666 rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
4667 rtl8821ae_dm_write_cck_cca_thres(hw,
4668 rtlphy->initgain_backup.cca);
4669 break;
4670 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4671 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4672 _rtl8821ae_stop_tx_beacon(hw);
4673 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
4674 rtl8821ae_dm_write_dig(hw, 0x17);
4675 rtlphy->initgain_backup.cca = dm_digtable->cur_cck_cca_thres;
4676 rtl8821ae_dm_write_cck_cca_thres(hw, 0x40);
4677 break;
4678 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4679 break;
4680 default:
4681 pr_err("switch case %#x not processed\n",
4682 rtlphy->current_io_type);
4683 break;
4684 }
4685 rtlphy->set_io_inprogress = false;
4686 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4687 "(%#x)\n", rtlphy->current_io_type);
4688 }
4689
rtl8821ae_phy_set_rf_on(struct ieee80211_hw * hw)4690 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw)
4691 {
4692 struct rtl_priv *rtlpriv = rtl_priv(hw);
4693
4694 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
4695 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4696 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
4697 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4698 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
4699 }
4700
_rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw * hw,enum rf_pwrstate rfpwr_state)4701 static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4702 enum rf_pwrstate rfpwr_state)
4703 {
4704 struct rtl_priv *rtlpriv = rtl_priv(hw);
4705 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
4706 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
4707 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4708 bool bresult = true;
4709 u8 i, queue_id;
4710 struct rtl8192_tx_ring *ring = NULL;
4711
4712 switch (rfpwr_state) {
4713 case ERFON:
4714 if ((ppsc->rfpwr_state == ERFOFF) &&
4715 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
4716 bool rtstatus = false;
4717 u32 initializecount = 0;
4718
4719 do {
4720 initializecount++;
4721 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4722 "IPS Set eRf nic enable\n");
4723 rtstatus = rtl_ps_enable_nic(hw);
4724 } while (!rtstatus && (initializecount < 10));
4725 RT_CLEAR_PS_LEVEL(ppsc,
4726 RT_RF_OFF_LEVL_HALT_NIC);
4727 } else {
4728 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4729 "Set ERFON slept:%d ms\n",
4730 jiffies_to_msecs(jiffies -
4731 ppsc->last_sleep_jiffies));
4732 ppsc->last_awake_jiffies = jiffies;
4733 rtl8821ae_phy_set_rf_on(hw);
4734 }
4735 if (mac->link_state == MAC80211_LINKED) {
4736 rtlpriv->cfg->ops->led_control(hw,
4737 LED_CTL_LINK);
4738 } else {
4739 rtlpriv->cfg->ops->led_control(hw,
4740 LED_CTL_NO_LINK);
4741 }
4742 break;
4743 case ERFOFF:
4744 for (queue_id = 0, i = 0;
4745 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
4746 ring = &pcipriv->dev.tx_ring[queue_id];
4747 if (queue_id == BEACON_QUEUE ||
4748 skb_queue_len(&ring->queue) == 0) {
4749 queue_id++;
4750 continue;
4751 } else {
4752 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
4753 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
4754 (i + 1), queue_id,
4755 skb_queue_len(&ring->queue));
4756
4757 udelay(10);
4758 i++;
4759 }
4760 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
4761 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
4762 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
4763 MAX_DOZE_WAITING_TIMES_9x,
4764 queue_id,
4765 skb_queue_len(&ring->queue));
4766 break;
4767 }
4768 }
4769
4770 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
4771 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4772 "IPS Set eRf nic disable\n");
4773 rtl_ps_disable_nic(hw);
4774 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
4775 } else {
4776 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
4777 rtlpriv->cfg->ops->led_control(hw,
4778 LED_CTL_NO_LINK);
4779 } else {
4780 rtlpriv->cfg->ops->led_control(hw,
4781 LED_CTL_POWER_OFF);
4782 }
4783 }
4784 break;
4785 default:
4786 pr_err("switch case %#x not processed\n",
4787 rfpwr_state);
4788 bresult = false;
4789 break;
4790 }
4791 if (bresult)
4792 ppsc->rfpwr_state = rfpwr_state;
4793 return bresult;
4794 }
4795
rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw * hw,enum rf_pwrstate rfpwr_state)4796 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4797 enum rf_pwrstate rfpwr_state)
4798 {
4799 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4800
4801 bool bresult = false;
4802
4803 if (rfpwr_state == ppsc->rfpwr_state)
4804 return bresult;
4805 bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state);
4806 return bresult;
4807 }
4808