1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 MediaTek Inc. 4 */ 5 6 #ifndef _UFS_MEDIATEK_H 7 #define _UFS_MEDIATEK_H 8 9 #include <linux/bitops.h> 10 #include <linux/soc/mediatek/mtk_sip_svc.h> 11 12 /* 13 * Vendor specific UFSHCI Registers 14 */ 15 #define REG_UFS_REFCLK_CTRL 0x144 16 #define REG_UFS_EXTREG 0x2100 17 #define REG_UFS_MPHYCTRL 0x2200 18 #define REG_UFS_REJECT_MON 0x22AC 19 #define REG_UFS_DEBUG_SEL 0x22C0 20 #define REG_UFS_PROBE 0x22C8 21 22 /* 23 * Ref-clk control 24 * 25 * Values for register REG_UFS_REFCLK_CTRL 26 */ 27 #define REFCLK_RELEASE 0x0 28 #define REFCLK_REQUEST BIT(0) 29 #define REFCLK_ACK BIT(1) 30 31 #define REFCLK_REQ_TIMEOUT_US 3000 32 33 /* 34 * Vendor specific pre-defined parameters 35 */ 36 #define UFS_MTK_LIMIT_NUM_LANES_RX 2 37 #define UFS_MTK_LIMIT_NUM_LANES_TX 2 38 #define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G3 39 #define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G3 40 #define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4 41 #define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4 42 #define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE 43 #define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE 44 #define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE 45 #define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE 46 #define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B 47 #define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE 48 49 /* 50 * Other attributes 51 */ 52 #define VS_DEBUGCLOCKENABLE 0xD0A1 53 #define VS_SAVEPOWERCONTROL 0xD0A6 54 #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 55 56 /* 57 * Vendor specific link state 58 */ 59 enum { 60 VS_LINK_DISABLED = 0, 61 VS_LINK_DOWN = 1, 62 VS_LINK_UP = 2, 63 VS_LINK_HIBERN8 = 3, 64 VS_LINK_LOST = 4, 65 VS_LINK_CFG = 5, 66 }; 67 68 /* 69 * SiP commands 70 */ 71 #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) 72 #define UFS_MTK_SIP_DEVICE_RESET BIT(1) 73 #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) 74 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) 75 76 /* 77 * VS_DEBUGCLOCKENABLE 78 */ 79 enum { 80 TX_SYMBOL_CLK_REQ_FORCE = 5, 81 }; 82 83 /* 84 * VS_SAVEPOWERCONTROL 85 */ 86 enum { 87 RX_SYMBOL_CLK_GATE_EN = 0, 88 SYS_CLK_GATE_EN = 2, 89 TX_CLK_GATE_EN = 3, 90 }; 91 92 /* 93 * Host capability 94 */ 95 enum ufs_mtk_host_caps { 96 UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0, 97 }; 98 99 struct ufs_mtk_crypt_cfg { 100 struct regulator *reg_vcore; 101 struct clk *clk_crypt_perf; 102 struct clk *clk_crypt_mux; 103 struct clk *clk_crypt_lp; 104 int vcore_volt; 105 }; 106 107 struct ufs_mtk_host_cfg { 108 enum ufs_mtk_host_caps caps; 109 }; 110 111 struct ufs_mtk_host { 112 struct ufs_hba *hba; 113 struct phy *mphy; 114 struct ufs_mtk_host_cfg *cfg; 115 struct ufs_mtk_crypt_cfg *crypt; 116 enum ufs_mtk_host_caps caps; 117 struct reset_control *hci_reset; 118 struct reset_control *unipro_reset; 119 struct reset_control *crypto_reset; 120 bool mphy_powered_on; 121 bool unipro_lpm; 122 bool ref_clk_enabled; 123 u16 ref_clk_ungating_wait_us; 124 u16 ref_clk_gating_wait_us; 125 }; 126 127 #endif /* !_UFS_MEDIATEK_H */ 128