1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017, Maxim Integrated
3
4 #include <linux/acpi.h>
5 #include <linux/delay.h>
6 #include <linux/i2c.h>
7 #include <linux/module.h>
8 #include <linux/regmap.h>
9 #include <linux/slab.h>
10 #include <linux/cdev.h>
11 #include <sound/pcm.h>
12 #include <sound/pcm_params.h>
13 #include <sound/soc.h>
14 #include <linux/gpio.h>
15 #include <linux/of.h>
16 #include <linux/of_gpio.h>
17 #include <sound/tlv.h>
18 #include "max98373.h"
19
max98373_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)20 static int max98373_dac_event(struct snd_soc_dapm_widget *w,
21 struct snd_kcontrol *kcontrol, int event)
22 {
23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
24 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
25
26 switch (event) {
27 case SND_SOC_DAPM_POST_PMU:
28 regmap_update_bits(max98373->regmap,
29 MAX98373_R20FF_GLOBAL_SHDN,
30 MAX98373_GLOBAL_EN_MASK, 1);
31 usleep_range(30000, 31000);
32 break;
33 case SND_SOC_DAPM_POST_PMD:
34 regmap_update_bits(max98373->regmap,
35 MAX98373_R20FF_GLOBAL_SHDN,
36 MAX98373_GLOBAL_EN_MASK, 0);
37 usleep_range(30000, 31000);
38 max98373->tdm_mode = false;
39 break;
40 default:
41 return 0;
42 }
43 return 0;
44 }
45
46 static const char * const max98373_switch_text[] = {
47 "Left", "Right", "LeftRight"};
48
49 static const struct soc_enum dai_sel_enum =
50 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
51 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
52 3, max98373_switch_text);
53
54 static const struct snd_kcontrol_new max98373_dai_controls =
55 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
56
57 static const struct snd_kcontrol_new max98373_vi_control =
58 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
59
60 static const struct snd_kcontrol_new max98373_spkfb_control =
61 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
62
63 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
64 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
65 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
66 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
67 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
68 &max98373_dai_controls),
69 SND_SOC_DAPM_OUTPUT("BE_OUT"),
70 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
71 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
72 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
73 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
74 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
75 SND_SOC_NOPM, 0, 0),
76 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
77 &max98373_vi_control),
78 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
79 &max98373_spkfb_control),
80 SND_SOC_DAPM_SIGGEN("VMON"),
81 SND_SOC_DAPM_SIGGEN("IMON"),
82 SND_SOC_DAPM_SIGGEN("FBMON"),
83 };
84
85 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
86 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
87 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
88 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
89 );
90 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
91 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
92 );
93 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
94 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
95 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
96 );
97 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
98 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
99 );
100 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
101 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
102 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
103 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
104 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
105 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
106 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
107 );
108 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
109 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
110 );
111
112 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
113 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
114 );
115
116 static const char * const max98373_output_voltage_lvl_text[] = {
117 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
118 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
119 };
120
121 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
122 MAX98373_R203E_AMP_PATH_GAIN, 0,
123 max98373_output_voltage_lvl_text);
124
125 static const char * const max98373_dht_attack_rate_text[] = {
126 "17.5us", "35us", "70us", "140us",
127 "280us", "560us", "1120us", "2240us"
128 };
129
130 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
131 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
132 max98373_dht_attack_rate_text);
133
134 static const char * const max98373_dht_release_rate_text[] = {
135 "45ms", "225ms", "450ms", "1150ms",
136 "2250ms", "3100ms", "4500ms", "6750ms"
137 };
138
139 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
140 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
141 max98373_dht_release_rate_text);
142
143 static const char * const max98373_limiter_attack_rate_text[] = {
144 "10us", "20us", "40us", "80us",
145 "160us", "320us", "640us", "1.28ms",
146 "2.56ms", "5.12ms", "10.24ms", "20.48ms",
147 "40.96ms", "81.92ms", "16.384ms", "32.768ms"
148 };
149
150 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
151 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
152 max98373_limiter_attack_rate_text);
153
154 static const char * const max98373_limiter_release_rate_text[] = {
155 "40us", "80us", "160us", "320us",
156 "640us", "1.28ms", "2.56ms", "5.120ms",
157 "10.24ms", "20.48ms", "40.96ms", "81.92ms",
158 "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
159 };
160
161 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
162 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
163 max98373_limiter_release_rate_text);
164
165 static const char * const max98373_ADC_samplerate_text[] = {
166 "333kHz", "192kHz", "64kHz", "48kHz"
167 };
168
169 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
170 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
171 max98373_ADC_samplerate_text);
172
173 static const struct snd_kcontrol_new max98373_snd_controls[] = {
174 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
175 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
176 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
177 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
178 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
179 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
180 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
181 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
182 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
183 MAX98373_CLOCK_MON_SHIFT, 1, 0),
184 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
185 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
186 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
187 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
188 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
189 0, 0x7F, 1, max98373_digital_tlv),
190 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
191 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
192 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
193 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
194 SOC_ENUM("Output Voltage", max98373_out_volt_enum),
195 /* Dynamic Headroom Tracking */
196 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
197 MAX98373_DHT_EN_SHIFT, 1, 0),
198 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
199 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
200 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
201 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
202 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
203 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
204 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
205 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
206 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
207 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
208 /* ADC configuration */
209 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
210 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
211 MAX98373_FLT_EN_SHIFT, 1, 0),
212 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
213 MAX98373_FLT_EN_SHIFT, 1, 0),
214 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
215 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
216 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
217 0, 0x3, 0),
218 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
219 0, 0x3, 0),
220 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
221 /* Brownout Detection Engine */
222 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
223 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
224 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
225 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
226 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
227 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
228 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
229 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
230 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
231 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
232 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
233 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
234 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
235 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
236 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
237 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
238 0, 0x3C, 1, max98373_bde_gain_tlv),
239 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
240 0, 0x3C, 1, max98373_bde_gain_tlv),
241 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
242 0, 0x3C, 1, max98373_bde_gain_tlv),
243 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
244 0, 0x3C, 1, max98373_bde_gain_tlv),
245 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
246 0, 0x3C, 1, max98373_bde_gain_tlv),
247 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
248 0, 0x3C, 1, max98373_bde_gain_tlv),
249 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
250 0, 0x3C, 1, max98373_bde_gain_tlv),
251 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
252 0, 0x3C, 1, max98373_bde_gain_tlv),
253 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
254 0, 0xF, 1, max98373_limiter_thresh_tlv),
255 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
256 0, 0xF, 1, max98373_limiter_thresh_tlv),
257 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
258 0, 0xF, 1, max98373_limiter_thresh_tlv),
259 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
260 0, 0xF, 1, max98373_limiter_thresh_tlv),
261 /* Limiter */
262 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
263 MAX98373_LIMITER_EN_SHIFT, 1, 0),
264 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
265 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
266 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
267 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
268 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
269 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
270 };
271
272 static const struct snd_soc_dapm_route max98373_audio_map[] = {
273 /* Plabyack */
274 {"DAI Sel Mux", "Left", "Amp Enable"},
275 {"DAI Sel Mux", "Right", "Amp Enable"},
276 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
277 {"BE_OUT", NULL, "DAI Sel Mux"},
278 /* Capture */
279 { "VI Sense", "Switch", "VMON" },
280 { "VI Sense", "Switch", "IMON" },
281 { "SpkFB Sense", "Switch", "FBMON" },
282 { "Voltage Sense", NULL, "VI Sense" },
283 { "Current Sense", NULL, "VI Sense" },
284 { "Speaker FB Sense", NULL, "SpkFB Sense" },
285 };
286
max98373_reset(struct max98373_priv * max98373,struct device * dev)287 void max98373_reset(struct max98373_priv *max98373, struct device *dev)
288 {
289 int ret, reg, count;
290
291 /* Software Reset */
292 ret = regmap_update_bits(max98373->regmap,
293 MAX98373_R2000_SW_RESET,
294 MAX98373_SOFT_RESET,
295 MAX98373_SOFT_RESET);
296 if (ret)
297 dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
298
299 count = 0;
300 while (count < 3) {
301 usleep_range(10000, 11000);
302 /* Software Reset Verification */
303 ret = regmap_read(max98373->regmap,
304 MAX98373_R21FF_REV_ID, ®);
305 if (!ret) {
306 dev_info(dev, "Reset completed (retry:%d)\n", count);
307 return;
308 }
309 count++;
310 }
311 dev_err(dev, "Reset failed. (ret:%d)\n", ret);
312 }
313 EXPORT_SYMBOL_GPL(max98373_reset);
314
max98373_probe(struct snd_soc_component * component)315 static int max98373_probe(struct snd_soc_component *component)
316 {
317 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
318
319 /* Software Reset */
320 max98373_reset(max98373, component->dev);
321
322 /* IV default slot configuration */
323 regmap_write(max98373->regmap,
324 MAX98373_R2020_PCM_TX_HIZ_EN_1,
325 0xFF);
326 regmap_write(max98373->regmap,
327 MAX98373_R2021_PCM_TX_HIZ_EN_2,
328 0xFF);
329 /* L/R mix configuration */
330 regmap_write(max98373->regmap,
331 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
332 0x80);
333 regmap_write(max98373->regmap,
334 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
335 0x1);
336 /* Enable DC blocker */
337 regmap_write(max98373->regmap,
338 MAX98373_R203F_AMP_DSP_CFG,
339 0x3);
340 /* Enable IMON VMON DC blocker */
341 regmap_write(max98373->regmap,
342 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
343 0x7);
344 /* voltage, current slot configuration */
345 regmap_write(max98373->regmap,
346 MAX98373_R2022_PCM_TX_SRC_1,
347 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
348 max98373->v_slot) & 0xFF);
349 if (max98373->v_slot < 8)
350 regmap_update_bits(max98373->regmap,
351 MAX98373_R2020_PCM_TX_HIZ_EN_1,
352 1 << max98373->v_slot, 0);
353 else
354 regmap_update_bits(max98373->regmap,
355 MAX98373_R2021_PCM_TX_HIZ_EN_2,
356 1 << (max98373->v_slot - 8), 0);
357
358 if (max98373->i_slot < 8)
359 regmap_update_bits(max98373->regmap,
360 MAX98373_R2020_PCM_TX_HIZ_EN_1,
361 1 << max98373->i_slot, 0);
362 else
363 regmap_update_bits(max98373->regmap,
364 MAX98373_R2021_PCM_TX_HIZ_EN_2,
365 1 << (max98373->i_slot - 8), 0);
366
367 /* speaker feedback slot configuration */
368 regmap_write(max98373->regmap,
369 MAX98373_R2023_PCM_TX_SRC_2,
370 max98373->spkfb_slot & 0xFF);
371
372 /* Set interleave mode */
373 if (max98373->interleave_mode)
374 regmap_update_bits(max98373->regmap,
375 MAX98373_R2024_PCM_DATA_FMT_CFG,
376 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
377 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
378
379 /* Speaker enable */
380 regmap_update_bits(max98373->regmap,
381 MAX98373_R2043_AMP_EN,
382 MAX98373_SPK_EN_MASK, 1);
383
384 return 0;
385 }
386
387 const struct snd_soc_component_driver soc_codec_dev_max98373 = {
388 .probe = max98373_probe,
389 .controls = max98373_snd_controls,
390 .num_controls = ARRAY_SIZE(max98373_snd_controls),
391 .dapm_widgets = max98373_dapm_widgets,
392 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
393 .dapm_routes = max98373_audio_map,
394 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
395 .use_pmdown_time = 1,
396 .endianness = 1,
397 .non_legacy_dai_naming = 1,
398 };
399 EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
400
401 const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
402 .probe = NULL,
403 .controls = max98373_snd_controls,
404 .num_controls = ARRAY_SIZE(max98373_snd_controls),
405 .dapm_widgets = max98373_dapm_widgets,
406 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
407 .dapm_routes = max98373_audio_map,
408 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
409 .use_pmdown_time = 1,
410 .endianness = 1,
411 .non_legacy_dai_naming = 1,
412 };
413 EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
414
max98373_slot_config(struct device * dev,struct max98373_priv * max98373)415 void max98373_slot_config(struct device *dev,
416 struct max98373_priv *max98373)
417 {
418 int value;
419
420 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
421 max98373->v_slot = value & 0xF;
422 else
423 max98373->v_slot = 0;
424
425 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
426 max98373->i_slot = value & 0xF;
427 else
428 max98373->i_slot = 1;
429 if (dev->of_node) {
430 max98373->reset_gpio = of_get_named_gpio(dev->of_node,
431 "maxim,reset-gpio", 0);
432 if (!gpio_is_valid(max98373->reset_gpio)) {
433 dev_err(dev, "Looking up %s property in node %s failed %d\n",
434 "maxim,reset-gpio", dev->of_node->full_name,
435 max98373->reset_gpio);
436 } else {
437 dev_dbg(dev, "maxim,reset-gpio=%d",
438 max98373->reset_gpio);
439 }
440 } else {
441 /* this makes reset_gpio as invalid */
442 max98373->reset_gpio = -1;
443 }
444
445 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
446 max98373->spkfb_slot = value & 0xF;
447 else
448 max98373->spkfb_slot = 2;
449 }
450 EXPORT_SYMBOL_GPL(max98373_slot_config);
451
452 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
453 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
454 MODULE_LICENSE("GPL");
455