1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef __VMWGFX_DRM_H__ 7 #define __VMWGFX_DRM_H__ 8 #include "drm.h" 9 #if defined(__cplusplus) 10 extern "C" { 11 #endif 12 #define DRM_VMW_MAX_SURFACE_FACES 6 13 #define DRM_VMW_MAX_MIP_LEVELS 24 14 #define DRM_VMW_GET_PARAM 0 15 #define DRM_VMW_ALLOC_DMABUF 1 16 #define DRM_VMW_ALLOC_BO 1 17 #define DRM_VMW_UNREF_DMABUF 2 18 #define DRM_VMW_HANDLE_CLOSE 2 19 #define DRM_VMW_CURSOR_BYPASS 3 20 #define DRM_VMW_CONTROL_STREAM 4 21 #define DRM_VMW_CLAIM_STREAM 5 22 #define DRM_VMW_UNREF_STREAM 6 23 #define DRM_VMW_CREATE_CONTEXT 7 24 #define DRM_VMW_UNREF_CONTEXT 8 25 #define DRM_VMW_CREATE_SURFACE 9 26 #define DRM_VMW_UNREF_SURFACE 10 27 #define DRM_VMW_REF_SURFACE 11 28 #define DRM_VMW_EXECBUF 12 29 #define DRM_VMW_GET_3D_CAP 13 30 #define DRM_VMW_FENCE_WAIT 14 31 #define DRM_VMW_FENCE_SIGNALED 15 32 #define DRM_VMW_FENCE_UNREF 16 33 #define DRM_VMW_FENCE_EVENT 17 34 #define DRM_VMW_PRESENT 18 35 #define DRM_VMW_PRESENT_READBACK 19 36 #define DRM_VMW_UPDATE_LAYOUT 20 37 #define DRM_VMW_CREATE_SHADER 21 38 #define DRM_VMW_UNREF_SHADER 22 39 #define DRM_VMW_GB_SURFACE_CREATE 23 40 #define DRM_VMW_GB_SURFACE_REF 24 41 #define DRM_VMW_SYNCCPU 25 42 #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 43 #define DRM_VMW_GB_SURFACE_CREATE_EXT 27 44 #define DRM_VMW_GB_SURFACE_REF_EXT 28 45 #define DRM_VMW_PARAM_NUM_STREAMS 0 46 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 47 #define DRM_VMW_PARAM_3D 2 48 #define DRM_VMW_PARAM_HW_CAPS 3 49 #define DRM_VMW_PARAM_FIFO_CAPS 4 50 #define DRM_VMW_PARAM_MAX_FB_SIZE 5 51 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 52 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 53 #define DRM_VMW_PARAM_3D_CAPS_SIZE 8 54 #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 55 #define DRM_VMW_PARAM_MAX_MOB_SIZE 10 56 #define DRM_VMW_PARAM_SCREEN_TARGET 11 57 #define DRM_VMW_PARAM_DX 12 58 #define DRM_VMW_PARAM_HW_CAPS2 13 59 #define DRM_VMW_PARAM_SM4_1 14 60 enum drm_vmw_handle_type { 61 DRM_VMW_HANDLE_LEGACY = 0, 62 DRM_VMW_HANDLE_PRIME = 1 63 }; 64 struct drm_vmw_getparam_arg { 65 __u64 value; 66 __u32 param; 67 __u32 pad64; 68 }; 69 struct drm_vmw_context_arg { 70 __s32 cid; 71 __u32 pad64; 72 }; 73 struct drm_vmw_surface_create_req { 74 __u32 flags; 75 __u32 format; 76 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES]; 77 __u64 size_addr; 78 __s32 shareable; 79 __s32 scanout; 80 }; 81 struct drm_vmw_surface_arg { 82 __s32 sid; 83 enum drm_vmw_handle_type handle_type; 84 }; 85 struct drm_vmw_size { 86 __u32 width; 87 __u32 height; 88 __u32 depth; 89 __u32 pad64; 90 }; 91 union drm_vmw_surface_create_arg { 92 struct drm_vmw_surface_arg rep; 93 struct drm_vmw_surface_create_req req; 94 }; 95 union drm_vmw_surface_reference_arg { 96 struct drm_vmw_surface_create_req rep; 97 struct drm_vmw_surface_arg req; 98 }; 99 #define DRM_VMW_EXECBUF_VERSION 2 100 #define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0) 101 #define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1) 102 struct drm_vmw_execbuf_arg { 103 __u64 commands; 104 __u32 command_size; 105 __u32 throttle_us; 106 __u64 fence_rep; 107 __u32 version; 108 __u32 flags; 109 __u32 context_handle; 110 __s32 imported_fence_fd; 111 }; 112 struct drm_vmw_fence_rep { 113 __u32 handle; 114 __u32 mask; 115 __u32 seqno; 116 __u32 passed_seqno; 117 __s32 fd; 118 __s32 error; 119 }; 120 struct drm_vmw_alloc_bo_req { 121 __u32 size; 122 __u32 pad64; 123 }; 124 #define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req 125 struct drm_vmw_bo_rep { 126 __u64 map_handle; 127 __u32 handle; 128 __u32 cur_gmr_id; 129 __u32 cur_gmr_offset; 130 __u32 pad64; 131 }; 132 #define drm_vmw_dmabuf_rep drm_vmw_bo_rep 133 union drm_vmw_alloc_bo_arg { 134 struct drm_vmw_alloc_bo_req req; 135 struct drm_vmw_bo_rep rep; 136 }; 137 #define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg 138 struct drm_vmw_rect { 139 __s32 x; 140 __s32 y; 141 __u32 w; 142 __u32 h; 143 }; 144 struct drm_vmw_control_stream_arg { 145 __u32 stream_id; 146 __u32 enabled; 147 __u32 flags; 148 __u32 color_key; 149 __u32 handle; 150 __u32 offset; 151 __s32 format; 152 __u32 size; 153 __u32 width; 154 __u32 height; 155 __u32 pitch[3]; 156 __u32 pad64; 157 struct drm_vmw_rect src; 158 struct drm_vmw_rect dst; 159 }; 160 #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) 161 #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) 162 struct drm_vmw_cursor_bypass_arg { 163 __u32 flags; 164 __u32 crtc_id; 165 __s32 xpos; 166 __s32 ypos; 167 __s32 xhot; 168 __s32 yhot; 169 }; 170 struct drm_vmw_stream_arg { 171 __u32 stream_id; 172 __u32 pad64; 173 }; 174 struct drm_vmw_get_3d_cap_arg { 175 __u64 buffer; 176 __u32 max_size; 177 __u32 pad64; 178 }; 179 #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) 180 #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) 181 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) 182 struct drm_vmw_fence_wait_arg { 183 __u32 handle; 184 __s32 cookie_valid; 185 __u64 kernel_cookie; 186 __u64 timeout_us; 187 __s32 lazy; 188 __s32 flags; 189 __s32 wait_options; 190 __s32 pad64; 191 }; 192 struct drm_vmw_fence_signaled_arg { 193 __u32 handle; 194 __u32 flags; 195 __s32 signaled; 196 __u32 passed_seqno; 197 __u32 signaled_flags; 198 __u32 pad64; 199 }; 200 struct drm_vmw_fence_arg { 201 __u32 handle; 202 __u32 pad64; 203 }; 204 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 205 struct drm_vmw_event_fence { 206 struct drm_event base; 207 __u64 user_data; 208 __u32 tv_sec; 209 __u32 tv_usec; 210 }; 211 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) 212 struct drm_vmw_fence_event_arg { 213 __u64 fence_rep; 214 __u64 user_data; 215 __u32 handle; 216 __u32 flags; 217 }; 218 struct drm_vmw_present_arg { 219 __u32 fb_id; 220 __u32 sid; 221 __s32 dest_x; 222 __s32 dest_y; 223 __u64 clips_ptr; 224 __u32 num_clips; 225 __u32 pad64; 226 }; 227 struct drm_vmw_present_readback_arg { 228 __u32 fb_id; 229 __u32 num_clips; 230 __u64 clips_ptr; 231 __u64 fence_rep; 232 }; 233 struct drm_vmw_update_layout_arg { 234 __u32 num_outputs; 235 __u32 pad64; 236 __u64 rects; 237 }; 238 enum drm_vmw_shader_type { 239 drm_vmw_shader_type_vs = 0, 240 drm_vmw_shader_type_ps, 241 }; 242 struct drm_vmw_shader_create_arg { 243 enum drm_vmw_shader_type shader_type; 244 __u32 size; 245 __u32 buffer_handle; 246 __u32 shader_handle; 247 __u64 offset; 248 }; 249 struct drm_vmw_shader_arg { 250 __u32 handle; 251 __u32 pad64; 252 }; 253 enum drm_vmw_surface_flags { 254 drm_vmw_surface_flag_shareable = (1 << 0), 255 drm_vmw_surface_flag_scanout = (1 << 1), 256 drm_vmw_surface_flag_create_buffer = (1 << 2) 257 }; 258 struct drm_vmw_gb_surface_create_req { 259 __u32 svga3d_flags; 260 __u32 format; 261 __u32 mip_levels; 262 enum drm_vmw_surface_flags drm_surface_flags; 263 __u32 multisample_count; 264 __u32 autogen_filter; 265 __u32 buffer_handle; 266 __u32 array_size; 267 struct drm_vmw_size base_size; 268 }; 269 struct drm_vmw_gb_surface_create_rep { 270 __u32 handle; 271 __u32 backup_size; 272 __u32 buffer_handle; 273 __u32 buffer_size; 274 __u64 buffer_map_handle; 275 }; 276 union drm_vmw_gb_surface_create_arg { 277 struct drm_vmw_gb_surface_create_rep rep; 278 struct drm_vmw_gb_surface_create_req req; 279 }; 280 struct drm_vmw_gb_surface_ref_rep { 281 struct drm_vmw_gb_surface_create_req creq; 282 struct drm_vmw_gb_surface_create_rep crep; 283 }; 284 union drm_vmw_gb_surface_reference_arg { 285 struct drm_vmw_gb_surface_ref_rep rep; 286 struct drm_vmw_surface_arg req; 287 }; 288 enum drm_vmw_synccpu_flags { 289 drm_vmw_synccpu_read = (1 << 0), 290 drm_vmw_synccpu_write = (1 << 1), 291 drm_vmw_synccpu_dontblock = (1 << 2), 292 drm_vmw_synccpu_allow_cs = (1 << 3) 293 }; 294 enum drm_vmw_synccpu_op { 295 drm_vmw_synccpu_grab, 296 drm_vmw_synccpu_release 297 }; 298 struct drm_vmw_synccpu_arg { 299 enum drm_vmw_synccpu_op op; 300 enum drm_vmw_synccpu_flags flags; 301 __u32 handle; 302 __u32 pad64; 303 }; 304 enum drm_vmw_extended_context { 305 drm_vmw_context_legacy, 306 drm_vmw_context_dx 307 }; 308 union drm_vmw_extended_context_arg { 309 enum drm_vmw_extended_context req; 310 struct drm_vmw_context_arg rep; 311 }; 312 struct drm_vmw_handle_close_arg { 313 __u32 handle; 314 __u32 pad64; 315 }; 316 #define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg 317 enum drm_vmw_surface_version { 318 drm_vmw_gb_surface_v1 319 }; 320 struct drm_vmw_gb_surface_create_ext_req { 321 struct drm_vmw_gb_surface_create_req base; 322 enum drm_vmw_surface_version version; 323 uint32_t svga3d_flags_upper_32_bits; 324 SVGA3dMSPattern multisample_pattern; 325 SVGA3dMSQualityLevel quality_level; 326 uint64_t must_be_zero; 327 }; 328 union drm_vmw_gb_surface_create_ext_arg { 329 struct drm_vmw_gb_surface_create_rep rep; 330 struct drm_vmw_gb_surface_create_ext_req req; 331 }; 332 struct drm_vmw_gb_surface_ref_ext_rep { 333 struct drm_vmw_gb_surface_create_ext_req creq; 334 struct drm_vmw_gb_surface_create_rep crep; 335 }; 336 union drm_vmw_gb_surface_reference_ext_arg { 337 struct drm_vmw_gb_surface_ref_ext_rep rep; 338 struct drm_vmw_surface_arg req; 339 }; 340 #if defined(__cplusplus) 341 } 342 #endif 343 #endif 344