1 /*
2 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS SC000 Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup SC000
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS SC000 definitions */
66
67 #define __CORTEX_SC (000U) /*!< Cortex Secure Core */
68
69 /** __FPU_USED indicates whether an FPU is used or not.
70 This core does not support an FPU at all
71 */
72 #define __FPU_USED 0U
73
74 #if defined ( __CC_ARM )
75 #if defined (__TARGET_FPU_VFP)
76 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
77 #endif
78
79 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
80 #if defined (__ARM_FP)
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #endif
83
84 #elif defined (__ti__)
85 #if defined (__ARM_FP)
86 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
87 #endif
88
89 #elif defined ( __GNUC__ )
90 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
91 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
92 #endif
93
94 #elif defined ( __ICCARM__ )
95 #if defined (__ARMVFP__)
96 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
97 #endif
98
99 #elif defined ( __TI_ARM__ )
100 #if defined (__TI_VFP_SUPPORT__)
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #endif
103
104 #elif defined ( __TASKING__ )
105 #if defined (__FPU_VFP__)
106 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #endif
108
109 #elif defined ( __CSMC__ )
110 #if ( __CSMC__ & 0x400U)
111 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112 #endif
113
114 #endif
115
116 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
117
118
119 #ifdef __cplusplus
120 }
121 #endif
122
123 #endif /* __CORE_SC000_H_GENERIC */
124
125 #ifndef __CMSIS_GENERIC
126
127 #ifndef __CORE_SC000_H_DEPENDANT
128 #define __CORE_SC000_H_DEPENDANT
129
130 #ifdef __cplusplus
131 extern "C" {
132 #endif
133
134 /* check device defines and use defaults */
135 #if defined __CHECK_DEVICE_DEFINES
136 #ifndef __SC000_REV
137 #define __SC000_REV 0x0000U
138 #warning "__SC000_REV not defined in device header file; using default!"
139 #endif
140
141 #ifndef __MPU_PRESENT
142 #define __MPU_PRESENT 0U
143 #warning "__MPU_PRESENT not defined in device header file; using default!"
144 #endif
145
146 #ifndef __VTOR_PRESENT
147 #define __VTOR_PRESENT 0U
148 #warning "__VTOR_PRESENT not defined in device header file; using default!"
149 #endif
150
151 #ifndef __NVIC_PRIO_BITS
152 #define __NVIC_PRIO_BITS 2U
153 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
154 #endif
155
156 #ifndef __Vendor_SysTickConfig
157 #define __Vendor_SysTickConfig 0U
158 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
159 #endif
160 #endif
161
162 /* IO definitions (access restrictions to peripheral registers) */
163 /**
164 \defgroup CMSIS_glob_defs CMSIS Global Defines
165
166 <strong>IO Type Qualifiers</strong> are used
167 \li to specify the access to peripheral variables.
168 \li for automatic generation of peripheral register debug information.
169 */
170 #ifdef __cplusplus
171 #define __I volatile /*!< Defines 'read only' permissions */
172 #else
173 #define __I volatile const /*!< Defines 'read only' permissions */
174 #endif
175 #define __O volatile /*!< Defines 'write only' permissions */
176 #define __IO volatile /*!< Defines 'read / write' permissions */
177
178 /* following defines should be used for structure members */
179 #define __IM volatile const /*! Defines 'read only' structure member permissions */
180 #define __OM volatile /*! Defines 'write only' structure member permissions */
181 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
182
183 /*@} end of group SC000 */
184
185
186
187 /*******************************************************************************
188 * Register Abstraction
189 Core Register contain:
190 - Core Register
191 - Core NVIC Register
192 - Core SCB Register
193 - Core SysTick Register
194 - Core MPU Register
195 ******************************************************************************/
196 /**
197 \defgroup CMSIS_core_register Defines and Type Definitions
198 \brief Type definitions and defines for Cortex-M processor based devices.
199 */
200
201 /**
202 \ingroup CMSIS_core_register
203 \defgroup CMSIS_CORE Status and Control Registers
204 \brief Core Register type definitions.
205 @{
206 */
207
208 /**
209 \brief Union type to access the Application Program Status Register (APSR).
210 */
211 typedef union
212 {
213 struct
214 {
215 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
216 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
217 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
218 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
219 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
220 } b; /*!< Structure used for bit access */
221 uint32_t w; /*!< Type used for word access */
222 } APSR_Type;
223
224 /** \brief APSR Register Definitions */
225 #define APSR_N_Pos 31U /*!< APSR: N Position */
226 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
227
228 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
229 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
230
231 #define APSR_C_Pos 29U /*!< APSR: C Position */
232 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
233
234 #define APSR_V_Pos 28U /*!< APSR: V Position */
235 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
236
237
238 /**
239 \brief Union type to access the Interrupt Program Status Register (IPSR).
240 */
241 typedef union
242 {
243 struct
244 {
245 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
246 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
247 } b; /*!< Structure used for bit access */
248 uint32_t w; /*!< Type used for word access */
249 } IPSR_Type;
250
251 /** \brief IPSR Register Definitions */
252 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
253 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
254
255
256 /**
257 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
258 */
259 typedef union
260 {
261 struct
262 {
263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
264 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
265 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
266 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
271 } b; /*!< Structure used for bit access */
272 uint32_t w; /*!< Type used for word access */
273 } xPSR_Type;
274
275 /** \brief xPSR Register Definitions */
276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
278
279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
281
282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
284
285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
287
288 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
289 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
290
291 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
292 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
293
294
295 /**
296 \brief Union type to access the Control Registers (CONTROL).
297 */
298 typedef union
299 {
300 struct
301 {
302 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
303 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
304 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
305 } b; /*!< Structure used for bit access */
306 uint32_t w; /*!< Type used for word access */
307 } CONTROL_Type;
308
309 /** \brief CONTROL Register Definitions */
310 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
311 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
312
313 /*@} end of group CMSIS_CORE */
314
315
316 /**
317 \ingroup CMSIS_core_register
318 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
319 \brief Type definitions for the NVIC Registers
320 @{
321 */
322
323 /**
324 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
325 */
326 typedef struct
327 {
328 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
329 uint32_t RESERVED0[31U];
330 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
331 uint32_t RESERVED1[31U];
332 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
333 uint32_t RESERVED2[31U];
334 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
335 uint32_t RESERVED3[31U];
336 uint32_t RESERVED4[64U];
337 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
338 } NVIC_Type;
339
340 /*@} end of group CMSIS_NVIC */
341
342
343 /**
344 \ingroup CMSIS_core_register
345 \defgroup CMSIS_SCB System Control Block (SCB)
346 \brief Type definitions for the System Control Block Registers
347 @{
348 */
349
350 /**
351 \brief Structure type to access the System Control Block (SCB).
352 */
353 typedef struct
354 {
355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
356 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
357 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
358 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
359 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
360 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
361 uint32_t RESERVED0[1U];
362 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
363 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
364 uint32_t RESERVED1[154U];
365 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
366 } SCB_Type;
367
368 /** \brief SCB CPUID Register Definitions */
369 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
370 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
371
372 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
373 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
374
375 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
376 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
377
378 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
379 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
380
381 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
382 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
383
384 /** \brief SCB Interrupt Control State Register Definitions */
385 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
386 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
387
388 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
389 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
390
391 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
392 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
393
394 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
395 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
396
397 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
398 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
399
400 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
401 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
402
403 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
404 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
405
406 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
407 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
408
409 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
410 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
411
412 /** \brief SCB Vector Table Offset Register Definitions */
413 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
414 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
415
416 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
417 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
419
420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
422
423 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
425
426 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
428
429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
431
432 /** \brief SCB System Control Register Definitions */
433 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
435
436 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
438
439 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
441
442 /** \brief SCB Configuration Control Register Definitions */
443 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
445
446 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
448
449 /** \brief SCB System Handler Control and State Register Definitions */
450 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
452
453 /*@} end of group CMSIS_SCB */
454
455
456 /**
457 \ingroup CMSIS_core_register
458 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
459 \brief Type definitions for the System Control and ID Register not in the SCB
460 @{
461 */
462
463 /**
464 \brief Structure type to access the System Control and ID Register not in the SCB.
465 */
466 typedef struct
467 {
468 uint32_t RESERVED0[2U];
469 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
470 } SCnSCB_Type;
471
472 /** \brief SCnSCB Auxiliary Control Register Definitions */
473 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
474 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
475
476 /*@} end of group CMSIS_SCnotSCB */
477
478
479 /**
480 \ingroup CMSIS_core_register
481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
482 \brief Type definitions for the System Timer Registers.
483 @{
484 */
485
486 /**
487 \brief Structure type to access the System Timer (SysTick).
488 */
489 typedef struct
490 {
491 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
492 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
493 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
494 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
495 } SysTick_Type;
496
497 /** \brief SysTick Control / Status Register Definitions */
498 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
499 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
500
501 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
502 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
503
504 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
505 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
506
507 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
508 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
509
510 /** \brief SysTick Reload Register Definitions */
511 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
512 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
513
514 /** \brief SysTick Current Register Definitions */
515 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
516 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
517
518 /** \brief SysTick Calibration Register Definitions */
519 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
520 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
521
522 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
523 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
524
525 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
526 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
527
528 /*@} end of group CMSIS_SysTick */
529
530 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
531 /**
532 \ingroup CMSIS_core_register
533 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
534 \brief Type definitions for the Memory Protection Unit (MPU)
535 @{
536 */
537
538 /**
539 \brief Structure type to access the Memory Protection Unit (MPU).
540 */
541 typedef struct
542 {
543 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
544 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
545 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
546 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
547 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
548 } MPU_Type;
549
550 #define MPU_TYPE_RALIASES 1U
551
552 /** \brief MPU Type Register Definitions */
553 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
554 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
555
556 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
557 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
558
559 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
560 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
561
562 /** \brief MPU Control Register Definitions */
563 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
564 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
565
566 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
567 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
568
569 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
570 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
571
572 /** \brief MPU Region Number Register Definitions */
573 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
574 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
575
576 /** \brief MPU Region Base Address Register Definitions */
577 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
578 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
579
580 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
581 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
582
583 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
584 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
585
586 /** \brief MPU Region Attribute and Size Register Definitions */
587 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
588 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
589
590 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
591 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
592
593 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
594 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
595
596 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
597 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
598
599 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
600 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
601
602 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
603 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
604
605 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
606 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
607
608 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
609 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
610
611 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
612 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
613
614 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
615 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
616
617 /*@} end of group CMSIS_MPU */
618 #endif
619
620
621 /**
622 \ingroup CMSIS_core_register
623 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
624 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
625 Therefore they are not covered by the SC000 header file.
626 @{
627 */
628 /*@} end of group CMSIS_CoreDebug */
629
630
631 /**
632 \ingroup CMSIS_core_register
633 \defgroup CMSIS_core_bitfield Core register bit field macros
634 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
635 @{
636 */
637
638 /**
639 \brief Mask and shift a bit field value for use in a register bit range.
640 \param[in] field Name of the register bit field.
641 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
642 \return Masked and shifted value.
643 */
644 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
645
646 /**
647 \brief Mask and shift a register value to extract a bit filed value.
648 \param[in] field Name of the register bit field.
649 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
650 \return Masked and shifted bit field value.
651 */
652 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
653
654 /*@} end of group CMSIS_core_bitfield */
655
656
657 /**
658 \ingroup CMSIS_core_register
659 \defgroup CMSIS_core_base Core Definitions
660 \brief Definitions for base addresses, unions, and structures.
661 @{
662 */
663
664 /* Memory mapping of Core Hardware */
665 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
666 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
667 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
668 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
669
670 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
671 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
672 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
673 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
674
675 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
676 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
677 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
678 #endif
679
680 /*@} */
681
682
683 /**
684 \ingroup CMSIS_core_register
685 \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
686 \brief Register alias definitions for backwards compatibility.
687 @{
688 */
689
690 /*@} */
691
692
693 /*******************************************************************************
694 * Hardware Abstraction Layer
695 Core Function Interface contains:
696 - Core NVIC Functions
697 - Core SysTick Functions
698 - Core Register Access Functions
699 ******************************************************************************/
700 /**
701 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
702 */
703
704
705
706 /* ########################## NVIC functions #################################### */
707 /**
708 \ingroup CMSIS_Core_FunctionInterface
709 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
710 \brief Functions that manage interrupts and exceptions via the NVIC.
711 @{
712 */
713
714 #ifdef CMSIS_NVIC_VIRTUAL
715 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
716 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
717 #endif
718 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
719 #else
720 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
721 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
722 #define NVIC_EnableIRQ __NVIC_EnableIRQ
723 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
724 #define NVIC_DisableIRQ __NVIC_DisableIRQ
725 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
726 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
727 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
728 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
729 #define NVIC_SetPriority __NVIC_SetPriority
730 #define NVIC_GetPriority __NVIC_GetPriority
731 #define NVIC_SystemReset __NVIC_SystemReset
732 #endif /* CMSIS_NVIC_VIRTUAL */
733
734 #ifdef CMSIS_VECTAB_VIRTUAL
735 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
736 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
737 #endif
738 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
739 #else
740 #define NVIC_SetVector __NVIC_SetVector
741 #define NVIC_GetVector __NVIC_GetVector
742 #endif /* (CMSIS_VECTAB_VIRTUAL) */
743
744 #define NVIC_USER_IRQ_OFFSET 16
745
746
747 /* The following EXC_RETURN values are saved the LR on exception entry */
748 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
749 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
750 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
751
752
753 /* Interrupt Priorities are WORD accessible only under Armv6-M */
754 /* The following MACROS handle generation of the register offset and byte masks */
755 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
756 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
757 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
758
759
760 /**
761 \brief Enable Interrupt
762 \details Enables a device specific interrupt in the NVIC interrupt controller.
763 \param [in] IRQn Device specific interrupt number.
764 \note IRQn must not be negative.
765 */
__NVIC_EnableIRQ(IRQn_Type IRQn)766 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
767 {
768 if ((int32_t)(IRQn) >= 0)
769 {
770 __COMPILER_BARRIER();
771 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
772 __COMPILER_BARRIER();
773 }
774 }
775
776
777 /**
778 \brief Get Interrupt Enable status
779 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
780 \param [in] IRQn Device specific interrupt number.
781 \return 0 Interrupt is not enabled.
782 \return 1 Interrupt is enabled.
783 \note IRQn must not be negative.
784 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)785 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
786 {
787 if ((int32_t)(IRQn) >= 0)
788 {
789 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
790 }
791 else
792 {
793 return(0U);
794 }
795 }
796
797
798 /**
799 \brief Disable Interrupt
800 \details Disables a device specific interrupt in the NVIC interrupt controller.
801 \param [in] IRQn Device specific interrupt number.
802 \note IRQn must not be negative.
803 */
__NVIC_DisableIRQ(IRQn_Type IRQn)804 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
805 {
806 if ((int32_t)(IRQn) >= 0)
807 {
808 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
809 __DSB();
810 __ISB();
811 }
812 }
813
814
815 /**
816 \brief Get Pending Interrupt
817 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
818 \param [in] IRQn Device specific interrupt number.
819 \return 0 Interrupt status is not pending.
820 \return 1 Interrupt status is pending.
821 \note IRQn must not be negative.
822 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)823 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
824 {
825 if ((int32_t)(IRQn) >= 0)
826 {
827 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
828 }
829 else
830 {
831 return(0U);
832 }
833 }
834
835
836 /**
837 \brief Set Pending Interrupt
838 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
839 \param [in] IRQn Device specific interrupt number.
840 \note IRQn must not be negative.
841 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)842 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
843 {
844 if ((int32_t)(IRQn) >= 0)
845 {
846 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
847 }
848 }
849
850
851 /**
852 \brief Clear Pending Interrupt
853 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
854 \param [in] IRQn Device specific interrupt number.
855 \note IRQn must not be negative.
856 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)857 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
858 {
859 if ((int32_t)(IRQn) >= 0)
860 {
861 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
862 }
863 }
864
865
866 /**
867 \brief Set Interrupt Priority
868 \details Sets the priority of a device specific interrupt or a processor exception.
869 The interrupt number can be positive to specify a device specific interrupt,
870 or negative to specify a processor exception.
871 \param [in] IRQn Interrupt number.
872 \param [in] priority Priority to set.
873 \note The priority cannot be set for every processor exception.
874 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)875 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
876 {
877 if ((int32_t)(IRQn) >= 0)
878 {
879 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
880 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
881 }
882 else
883 {
884 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
885 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
886 }
887 }
888
889
890 /**
891 \brief Get Interrupt Priority
892 \details Reads the priority of a device specific interrupt or a processor exception.
893 The interrupt number can be positive to specify a device specific interrupt,
894 or negative to specify a processor exception.
895 \param [in] IRQn Interrupt number.
896 \return Interrupt Priority.
897 Value is aligned automatically to the implemented priority bits of the microcontroller.
898 */
__NVIC_GetPriority(IRQn_Type IRQn)899 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
900 {
901
902 if ((int32_t)(IRQn) >= 0)
903 {
904 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
905 }
906 else
907 {
908 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
909 }
910 }
911
912
913 /**
914 \brief Set Interrupt Vector
915 \details Sets an interrupt vector in SRAM based interrupt vector table.
916 The interrupt number can be positive to specify a device specific interrupt,
917 or negative to specify a processor exception.
918 VTOR must been relocated to SRAM before.
919 \param [in] IRQn Interrupt number
920 \param [in] vector Address of interrupt handler function
921 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)922 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
923 {
924 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
925 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
926 /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
927 }
928
929
930 /**
931 \brief Get Interrupt Vector
932 \details Reads an interrupt vector from interrupt vector table.
933 The interrupt number can be positive to specify a device specific interrupt,
934 or negative to specify a processor exception.
935 \param [in] IRQn Interrupt number.
936 \return Address of interrupt handler function
937 */
__NVIC_GetVector(IRQn_Type IRQn)938 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
939 {
940 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
941 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
942 }
943
944
945 /**
946 \brief System Reset
947 \details Initiates a system reset request to reset the MCU.
948 */
__NVIC_SystemReset(void)949 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
950 {
951 __DSB(); /* Ensure all outstanding memory accesses included
952 buffered write are completed before reset */
953 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
954 SCB_AIRCR_SYSRESETREQ_Msk);
955 __DSB(); /* Ensure completion of memory access */
956
957 for(;;) /* wait until reset */
958 {
959 __NOP();
960 }
961 }
962
963 /*@} end of CMSIS_Core_NVICFunctions */
964
965 /* ########################## MPU functions #################################### */
966
967 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
968
969 #include "m-profile/armv7m_mpu.h"
970
971 #endif
972
973 /* ########################## FPU functions #################################### */
974 /**
975 \ingroup CMSIS_Core_FunctionInterface
976 \defgroup CMSIS_Core_FpuFunctions FPU Functions
977 \brief Function that provides FPU type.
978 @{
979 */
980
981 /**
982 \brief get FPU type
983 \details returns the FPU type
984 \returns
985 - \b 0: No FPU
986 - \b 1: Single precision FPU
987 - \b 2: Double + Single precision FPU
988 */
SCB_GetFPUType(void)989 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
990 {
991 return 0U; /* No FPU */
992 }
993
994
995 /*@} end of CMSIS_Core_FpuFunctions */
996
997
998
999 /* ################################## SysTick function ############################################ */
1000 /**
1001 \ingroup CMSIS_Core_FunctionInterface
1002 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1003 \brief Functions that configure the System.
1004 @{
1005 */
1006
1007 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1008
1009 /**
1010 \brief System Tick Configuration
1011 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1012 Counter is in free running mode to generate periodic interrupts.
1013 \param [in] ticks Number of ticks between two interrupts.
1014 \return 0 Function succeeded.
1015 \return 1 Function failed.
1016 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1017 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1018 must contain a vendor-specific implementation of this function.
1019 */
SysTick_Config(uint32_t ticks)1020 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1021 {
1022 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1023 {
1024 return (1UL); /* Reload value impossible */
1025 }
1026
1027 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1028 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1029 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1030 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1031 SysTick_CTRL_TICKINT_Msk |
1032 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1033 return (0UL); /* Function successful */
1034 }
1035
1036 #endif
1037
1038 /*@} end of CMSIS_Core_SysTickFunctions */
1039
1040
1041
1042
1043 #ifdef __cplusplus
1044 }
1045 #endif
1046
1047 #endif /* __CORE_SC000_H_DEPENDANT */
1048
1049 #endif /* __CMSIS_GENERIC */
1050