1 /*
2 * Copyright (c) 2009-2023 Arm Limited.
3 * Copyright (c) 2018-2022 Arm China.
4 * All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Licensed under the Apache License, Version 2.0 (the License); you may
8 * not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 */
19
20 /*
21 * CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File
22 */
23
24 #if defined ( __ICCARM__ )
25 #pragma system_include /* treat file as system include file for MISRA check */
26 #elif defined (__clang__)
27 #pragma clang system_header /* treat file as system include file */
28 #elif defined ( __GNUC__ )
29 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
30 #endif
31
32 #ifndef __CORE_STAR_H_GENERIC
33 #define __CORE_STAR_H_GENERIC
34
35 #include <stdint.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
43 CMSIS violates the following MISRA-C:2004 rules:
44
45 \li Required Rule 8.5, object/function definition in header file.<br>
46 Function definitions in header files are used to allow 'inlining'.
47
48 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
49 Unions are used for effective representation of core registers.
50
51 \li Advisory Rule 19.7, Function-like macro defined.<br>
52 Function-like macros are used to allow more efficient code.
53 */
54
55
56 /*******************************************************************************
57 * CMSIS definitions
58 ******************************************************************************/
59 /**
60 \ingroup STAR-MC1
61 @{
62 */
63
64 #include "cmsis_version.h"
65
66 /* Macro Define for STAR-MC1 */
67
68 #define __STAR_MC (1U) /*!< STAR-MC Core */
69
70 /** __FPU_USED indicates whether an FPU is used or not.
71 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
72 */
73 #if defined ( __CC_ARM )
74 #if defined (__TARGET_FPU_VFP)
75 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
76 #define __FPU_USED 1U
77 #else
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #define __FPU_USED 0U
80 #endif
81 #else
82 #define __FPU_USED 0U
83 #endif
84
85 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
86 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
87 #define __DSP_USED 1U
88 #else
89 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
90 #define __DSP_USED 0U
91 #endif
92 #else
93 #define __DSP_USED 0U
94 #endif
95
96 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
97 #if defined (__ARM_FP)
98 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
99 #define __FPU_USED 1U
100 #else
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #define __FPU_USED 0U
103 #endif
104 #else
105 #define __FPU_USED 0U
106 #endif
107
108 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
109 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
110 #define __DSP_USED 1U
111 #else
112 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
113 #define __DSP_USED 0U
114 #endif
115 #else
116 #define __DSP_USED 0U
117 #endif
118
119 #elif defined (__ti__)
120 #if defined (__ARM_FP)
121 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
122 #define __FPU_USED 1U
123 #else
124 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
125 #define __FPU_USED 0U
126 #endif
127 #else
128 #define __FPU_USED 0U
129 #endif
130
131 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
132 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
133 #define __DSP_USED 1U
134 #else
135 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
136 #define __DSP_USED 0U
137 #endif
138 #else
139 #define __DSP_USED 0U
140 #endif
141
142 #elif defined ( __GNUC__ )
143 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
144 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
145 #define __FPU_USED 1U
146 #else
147 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
148 #define __FPU_USED 0U
149 #endif
150 #else
151 #define __FPU_USED 0U
152 #endif
153
154 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
155 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
156 #define __DSP_USED 1U
157 #else
158 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
159 #define __DSP_USED 0U
160 #endif
161 #else
162 #define __DSP_USED 0U
163 #endif
164
165 #elif defined ( __ICCARM__ )
166 #if defined (__ARMVFP__)
167 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
168 #define __FPU_USED 1U
169 #else
170 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
171 #define __FPU_USED 0U
172 #endif
173 #else
174 #define __FPU_USED 0U
175 #endif
176
177 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
178 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
179 #define __DSP_USED 1U
180 #else
181 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
182 #define __DSP_USED 0U
183 #endif
184 #else
185 #define __DSP_USED 0U
186 #endif
187
188 #elif defined ( __TI_ARM__ )
189 #if defined (__TI_VFP_SUPPORT__)
190 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
191 #define __FPU_USED 1U
192 #else
193 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
194 #define __FPU_USED 0U
195 #endif
196 #else
197 #define __FPU_USED 0U
198 #endif
199
200 #elif defined ( __TASKING__ )
201 #if defined (__FPU_VFP__)
202 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
203 #define __FPU_USED 1U
204 #else
205 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
206 #define __FPU_USED 0U
207 #endif
208 #else
209 #define __FPU_USED 0U
210 #endif
211
212 #elif defined ( __CSMC__ )
213 #if ( __CSMC__ & 0x400U)
214 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
215 #define __FPU_USED 1U
216 #else
217 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
218 #define __FPU_USED 0U
219 #endif
220 #else
221 #define __FPU_USED 0U
222 #endif
223
224 #endif
225
226 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
227
228
229 #ifdef __cplusplus
230 }
231 #endif
232
233 #endif /* __CORE_STAR_H_GENERIC */
234
235 #ifndef __CMSIS_GENERIC
236
237 #ifndef __CORE_STAR_H_DEPENDANT
238 #define __CORE_STAR_H_DEPENDANT
239
240 #ifdef __cplusplus
241 extern "C" {
242 #endif
243
244 /* check device defines and use defaults */
245 #if defined __CHECK_DEVICE_DEFINES
246 #ifndef __STAR_REV
247 #define __STAR_REV 0x0000U
248 #warning "__STAR_REV not defined in device header file; using default!"
249 #endif
250
251 #ifndef __FPU_PRESENT
252 #define __FPU_PRESENT 0U
253 #warning "__FPU_PRESENT not defined in device header file; using default!"
254 #endif
255
256 #ifndef __MPU_PRESENT
257 #define __MPU_PRESENT 0U
258 #warning "__MPU_PRESENT not defined in device header file; using default!"
259 #endif
260
261 #ifndef __SAUREGION_PRESENT
262 #define __SAUREGION_PRESENT 0U
263 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
264 #endif
265
266 #ifndef __DSP_PRESENT
267 #define __DSP_PRESENT 0U
268 #warning "__DSP_PRESENT not defined in device header file; using default!"
269 #endif
270
271 #ifndef __ICACHE_PRESENT
272 #define __ICACHE_PRESENT 0U
273 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
274 #endif
275
276 #ifndef __DCACHE_PRESENT
277 #define __DCACHE_PRESENT 0U
278 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
279 #endif
280
281 #ifndef __DTCM_PRESENT
282 #define __DTCM_PRESENT 0U
283 #warning "__DTCM_PRESENT not defined in device header file; using default!"
284 #endif
285
286 #ifndef __NVIC_PRIO_BITS
287 #define __NVIC_PRIO_BITS 3U
288 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
289 #endif
290
291 #ifndef __Vendor_SysTickConfig
292 #define __Vendor_SysTickConfig 0U
293 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
294 #endif
295 #endif
296
297 /* IO definitions (access restrictions to peripheral registers) */
298 /**
299 \defgroup CMSIS_glob_defs CMSIS Global Defines
300
301 <strong>IO Type Qualifiers</strong> are used
302 \li to specify the access to peripheral variables.
303 \li for automatic generation of peripheral register debug information.
304 */
305 #ifdef __cplusplus
306 #define __I volatile /*!< Defines 'read only' permissions */
307 #else
308 #define __I volatile const /*!< Defines 'read only' permissions */
309 #endif
310 #define __O volatile /*!< Defines 'write only' permissions */
311 #define __IO volatile /*!< Defines 'read / write' permissions */
312
313 /* following defines should be used for structure members */
314 #define __IM volatile const /*! Defines 'read only' structure member permissions */
315 #define __OM volatile /*! Defines 'write only' structure member permissions */
316 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
317
318 /*@} end of group STAR-MC1 */
319
320
321
322 /*******************************************************************************
323 * Register Abstraction
324 Core Register contain:
325 - Core Register
326 - Core NVIC Register
327 - Core SCB Register
328 - Core SysTick Register
329 - Core Debug Register
330 - Core MPU Register
331 - Core SAU Register
332 - Core FPU Register
333 ******************************************************************************/
334 /**
335 \defgroup CMSIS_core_register Defines and Type Definitions
336 \brief Type definitions and defines for STAR-MC1 processor based devices.
337 */
338
339 /**
340 \ingroup CMSIS_core_register
341 \defgroup CMSIS_CORE Status and Control Registers
342 \brief Core Register type definitions.
343 @{
344 */
345
346 /**
347 \brief Union type to access the Application Program Status Register (APSR).
348 */
349 typedef union
350 {
351 struct
352 {
353 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
355 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
356 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
357 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
358 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
359 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
360 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
361 } b; /*!< Structure used for bit access */
362 uint32_t w; /*!< Type used for word access */
363 } APSR_Type;
364
365 /** \brief APSR Register Definitions */
366 #define APSR_N_Pos 31U /*!< APSR: N Position */
367 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
368
369 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
370 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
371
372 #define APSR_C_Pos 29U /*!< APSR: C Position */
373 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
374
375 #define APSR_V_Pos 28U /*!< APSR: V Position */
376 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
377
378 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
379 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
380
381 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
382 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
383
384
385 /**
386 \brief Union type to access the Interrupt Program Status Register (IPSR).
387 */
388 typedef union
389 {
390 struct
391 {
392 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
393 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
394 } b; /*!< Structure used for bit access */
395 uint32_t w; /*!< Type used for word access */
396 } IPSR_Type;
397
398 /** \brief IPSR Register Definitions */
399 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
400 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
401
402
403 /**
404 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
405 */
406 typedef union
407 {
408 struct
409 {
410 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
411 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
412 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
413 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
414 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
415 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
416 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
417 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
418 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
419 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
420 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
421 } b; /*!< Structure used for bit access */
422 uint32_t w; /*!< Type used for word access */
423 } xPSR_Type;
424
425 /** \brief xPSR Register Definitions */
426 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
427 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
428
429 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
430 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
431
432 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
433 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
434
435 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
436 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
437
438 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
439 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
440
441 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
442 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
443
444 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
445 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
446
447 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
448 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
449
450 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
451 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
452
453
454 /**
455 \brief Union type to access the Control Registers (CONTROL).
456 */
457 typedef union
458 {
459 struct
460 {
461 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
462 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
463 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
464 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
465 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
466 } b; /*!< Structure used for bit access */
467 uint32_t w; /*!< Type used for word access */
468 } CONTROL_Type;
469
470 /** \brief CONTROL Register Definitions */
471 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
472 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
473
474 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
475 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
476
477 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
478 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
479
480 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
481 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
482
483 /*@} end of group CMSIS_CORE */
484
485
486 /**
487 \ingroup CMSIS_core_register
488 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
489 \brief Type definitions for the NVIC Registers
490 @{
491 */
492
493 /**
494 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
495 */
496 typedef struct
497 {
498 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
499 uint32_t RESERVED0[16U];
500 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
501 uint32_t RESERVED1[16U];
502 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
503 uint32_t RESERVED2[16U];
504 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
505 uint32_t RESERVED3[16U];
506 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
507 uint32_t RESERVED4[16U];
508 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
509 uint32_t RESERVED5[16U];
510 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
511 uint32_t RESERVED6[580U];
512 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
513 } NVIC_Type;
514
515 /** \brief NVIC Software Triggered Interrupt Register Definitions */
516 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
517 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
518
519 /*@} end of group CMSIS_NVIC */
520
521
522 /**
523 \ingroup CMSIS_core_register
524 \defgroup CMSIS_SCB System Control Block (SCB)
525 \brief Type definitions for the System Control Block Registers
526 @{
527 */
528
529 /**
530 \brief Structure type to access the System Control Block (SCB).
531 */
532 typedef struct
533 {
534 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
535 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
536 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
537 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
538 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
539 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
540 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
541 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
542 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
543 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
544 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
545 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
546 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
547 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
548 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
549 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
550 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
551 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
552 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
553 uint32_t RESERVED0[1U];
554 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
555 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
556 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
557 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
558 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
559 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
560 uint32_t RESERVED_ADD1[21U];
561 __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
562 __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
563 uint32_t RESERVED3[69U];
564 __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */
565 uint32_t RESERVED4[15U];
566 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
567 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
568 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
569 uint32_t RESERVED5[1U];
570 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
571 uint32_t RESERVED6[1U];
572 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
573 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
574 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
575 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
576 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
577 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
578 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
579 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
580 } SCB_Type;
581
582 typedef struct
583 {
584 __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */
585 __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */
586 __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */
587 } EMSS_Type;
588
589 /** \brief SCB CPUID Register Definitions */
590 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
591 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
592
593 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
594 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
595
596 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
597 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
598
599 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
600 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
601
602 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
603 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
604
605 /** \brief SCB Interrupt Control State Register Definitions */
606 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
607 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
608
609 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
610 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
611
612 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
613 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
614
615 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
616 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
617
618 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
619 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
620
621 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
622 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
623
624 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
625 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
626
627 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
628 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
629
630 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
631 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
632
633 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
634 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
635
636 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
637 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
638
639 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
640 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
641
642 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
643 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
644
645 /** \brief SCB Vector Table Offset Register Definitions */
646 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
647 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
648
649 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
650 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
651 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
652
653 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
654 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
655
656 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
657 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
658
659 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
660 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
661
662 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
663 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
664
665 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
666 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
667
668 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
669 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
670
671 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
672 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
673
674 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
675 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
676
677 /** \brief SCB System Control Register Definitions */
678 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
679 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
680
681 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
682 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
683
684 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
685 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
686
687 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
688 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
689
690 /** \brief SCB Configuration Control Register Definitions */
691 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
692 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
693
694 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
695 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
696
697 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
698 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
699
700 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
701 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
702
703 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
704 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
705
706 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
707 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
708
709 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
710 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
711
712 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
713 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
714
715 /** \brief SCB System Handler Control and State Register Definitions */
716 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
717 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
718
719 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
720 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
721
722 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
723 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
724
725 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
726 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
727
728 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
729 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
730
731 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
732 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
733
734 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
735 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
736
737 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
738 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
739
740 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
741 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
742
743 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
744 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
745
746 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
747 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
748
749 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
750 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
751
752 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
753 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
754
755 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
756 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
757
758 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
759 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
760
761 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
762 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
763
764 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
765 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
766
767 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
768 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
769
770 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
771 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
772
773 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
774 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
775
776 /** \brief SCB Configurable Fault Status Register Definitions */
777 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
778 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
779
780 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
781 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
782
783 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
784 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
785
786 /** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
787 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
788 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
789
790 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
791 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
792
793 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
794 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
795
796 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
797 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
798
799 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
800 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
801
802 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
803 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
804
805 /** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
806 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
807 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
808
809 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
810 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
811
812 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
813 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
814
815 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
816 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
817
818 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
819 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
820
821 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
822 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
823
824 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
825 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
826
827 /** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
828 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
829 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
830
831 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
832 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
833
834 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
835 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
836
837 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
838 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
839
840 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
841 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
842
843 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
844 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
845
846 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
847 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
848
849 /** \brief SCB Hard Fault Status Register Definitions */
850 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
851 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
852
853 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
854 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
855
856 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
857 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
858
859 /** \brief SCB Debug Fault Status Register Definitions */
860 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
861 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
862
863 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
864 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
865
866 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
867 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
868
869 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
870 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
871
872 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
873 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
874
875 /** \brief SCB Non-Secure Access Control Register Definitions */
876 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
877 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
878
879 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
880 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
881
882 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
883 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
884
885 /** \brief SCB Cache Level ID Register Definitions */
886 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
887 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
888
889 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
890 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
891
892 #define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */
893 #define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */
894
895 #define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */
896 #define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */
897
898 /** \brief SCB Cache Type Register Definitions */
899 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
900 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
901
902 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
903 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
904
905 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
906 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
907
908 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
909 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
910
911 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
912 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
913
914 /** \brief SCB Cache Size ID Register Definitions */
915 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
916 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
917
918 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
919 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
920
921 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
922 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
923
924 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
925 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
926
927 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
928 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
929
930 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
931 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
932
933 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
934 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
935
936 /** \brief SCB Cache Size Selection Register Definitions */
937 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
938 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
939
940 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
941 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
942
943 /** \brief SCB Software Triggered Interrupt Register Definitions */
944 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
945 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
946
947 /** \brief SCB D-Cache line Invalidate by Set-way Register Definitions */
948 #define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */
949 #define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */
950
951 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
952 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
953
954 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
955 #define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
956
957 /** \brief SCB D-Cache Clean line by Set-way Register Definitions */
958 #define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */
959 #define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */
960
961 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
962 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
963
964 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
965 #define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
966
967 /** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
968 #define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */
969 #define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */
970
971 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
972 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
973
974 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
975 #define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
976
977 /* ArmChina: Implementation Defined */
978 /** \brief Instruction Tightly-Coupled Memory Control Register Definitions */
979 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
980 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
981
982 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
983 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
984
985 /** \brief Data Tightly-Coupled Memory Control Register Definitions */
986 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
987 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
988
989 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
990 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
991
992 /** \brief L1 Cache Control Register Definitions */
993 #define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */
994 #define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */
995
996 #define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */
997 #define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */
998
999 #define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */
1000 #define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */
1001
1002 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
1003 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
1004
1005 /*@} end of group CMSIS_SCB */
1006
1007
1008 /**
1009 \ingroup CMSIS_core_register
1010 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
1011 \brief Type definitions for the System Control and ID Register not in the SCB
1012 @{
1013 */
1014
1015 /**
1016 \brief Structure type to access the System Control and ID Register not in the SCB.
1017 */
1018 typedef struct
1019 {
1020 uint32_t RESERVED0[1U];
1021 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
1022 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
1023 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
1024 } SCnSCB_Type;
1025
1026 /** \brief SCnSCB Interrupt Controller Type Register Definitions */
1027 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
1028 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
1029
1030 /*@} end of group CMSIS_SCnotSCB */
1031
1032
1033 /**
1034 \ingroup CMSIS_core_register
1035 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
1036 \brief Type definitions for the System Timer Registers.
1037 @{
1038 */
1039
1040 /**
1041 \brief Structure type to access the System Timer (SysTick).
1042 */
1043 typedef struct
1044 {
1045 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
1046 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
1047 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
1048 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
1049 } SysTick_Type;
1050
1051 /** \brief SysTick Control / Status Register Definitions */
1052 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1053 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1054
1055 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1056 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1057
1058 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1059 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1060
1061 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1062 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1063
1064 /** \brief SysTick Reload Register Definitions */
1065 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1066 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1067
1068 /** \brief SysTick Current Register Definitions */
1069 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1070 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1071
1072 /** \brief SysTick Calibration Register Definitions */
1073 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1074 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1075
1076 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1077 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1078
1079 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1080 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1081
1082 /*@} end of group CMSIS_SysTick */
1083
1084
1085 /**
1086 \ingroup CMSIS_core_register
1087 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1088 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1089 @{
1090 */
1091
1092 /**
1093 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1094 */
1095 typedef struct
1096 {
1097 __OM union
1098 {
1099 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
1100 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
1101 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
1102 } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */
1103 uint32_t RESERVED0[864U];
1104 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */
1105 uint32_t RESERVED1[15U];
1106 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */
1107 uint32_t RESERVED2[15U];
1108 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */
1109 uint32_t RESERVED3[32U];
1110 uint32_t RESERVED4[43U];
1111 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */
1112 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */
1113 uint32_t RESERVED5[1U];
1114 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1115 } ITM_Type;
1116
1117 /** \brief ITM Stimulus Port Register Definitions */
1118 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1119 #define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1120
1121 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1122 #define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1123
1124 /** \brief ITM Trace Privilege Register Definitions */
1125 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1126 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1127
1128 /** \brief ITM Trace Control Register Definitions */
1129 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1130 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1131
1132 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1133 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1134
1135 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1136 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1137
1138 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1139 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1140
1141 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1142 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1143
1144 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1145 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1146
1147 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1148 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1149
1150 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1151 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1152
1153 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1154 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1155
1156 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1157 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1158
1159 /** \brief ITM Lock Status Register Definitions */
1160 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1161 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1162
1163 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1164 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1165
1166 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1167 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1168
1169 /*@}*/ /* end of group CMSIS_ITM */
1170
1171
1172 /**
1173 \ingroup CMSIS_core_register
1174 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1175 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1176 @{
1177 */
1178
1179 /**
1180 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1181 */
1182 typedef struct
1183 {
1184 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1185 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1186 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1187 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1188 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1189 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1190 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1191 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1192 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1193 uint32_t RESERVED1[1U];
1194 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1195 uint32_t RESERVED2[1U];
1196 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1197 uint32_t RESERVED3[1U];
1198 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1199 uint32_t RESERVED4[1U];
1200 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1201 uint32_t RESERVED5[1U];
1202 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1203 uint32_t RESERVED6[1U];
1204 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1205 uint32_t RESERVED7[1U];
1206 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1207 uint32_t RESERVED8[1U];
1208 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1209 uint32_t RESERVED9[1U];
1210 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1211 uint32_t RESERVED10[1U];
1212 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1213 uint32_t RESERVED11[1U];
1214 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1215 uint32_t RESERVED12[1U];
1216 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1217 uint32_t RESERVED13[1U];
1218 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1219 uint32_t RESERVED14[1U];
1220 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1221 uint32_t RESERVED15[1U];
1222 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1223 uint32_t RESERVED16[1U];
1224 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1225 uint32_t RESERVED17[1U];
1226 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1227 uint32_t RESERVED18[1U];
1228 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1229 uint32_t RESERVED19[1U];
1230 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1231 uint32_t RESERVED20[1U];
1232 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1233 uint32_t RESERVED21[1U];
1234 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1235 uint32_t RESERVED22[1U];
1236 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1237 uint32_t RESERVED23[1U];
1238 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1239 uint32_t RESERVED24[1U];
1240 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1241 uint32_t RESERVED25[1U];
1242 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1243 uint32_t RESERVED26[1U];
1244 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1245 uint32_t RESERVED27[1U];
1246 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1247 uint32_t RESERVED28[1U];
1248 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1249 uint32_t RESERVED29[1U];
1250 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1251 uint32_t RESERVED30[1U];
1252 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1253 uint32_t RESERVED31[1U];
1254 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1255 uint32_t RESERVED32[934U];
1256 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1257 uint32_t RESERVED33[1U];
1258 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1259 } DWT_Type;
1260
1261 /** \brief DWT Control Register Definitions */
1262 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1263 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1264
1265 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1266 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1267
1268 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1269 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1270
1271 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1272 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1273
1274 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1275 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1276
1277 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1278 #define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1279
1280 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1281 #define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1282
1283 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1284 #define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1285
1286 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1287 #define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1288
1289 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1290 #define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1291
1292 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1293 #define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1294
1295 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1296 #define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1297
1298 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1299 #define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1300
1301 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1302 #define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1303
1304 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1305 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1306
1307 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1308 #define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1309
1310 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1311 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1312
1313 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1314 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1315
1316 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1317 #define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1318
1319 /** \brief DWT CPI Count Register Definitions */
1320 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1321 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1322
1323 /** \brief DWT Exception Overhead Count Register Definitions */
1324 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1325 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1326
1327 /** \brief DWT Sleep Count Register Definitions */
1328 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1329 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1330
1331 /** \brief DWT LSU Count Register Definitions */
1332 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1333 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1334
1335 /** \brief DWT Folded-instruction Count Register Definitions */
1336 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1337 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1338
1339 /** \brief DWT Comparator Function Register Definitions */
1340 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1341 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1342
1343 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1344 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1345
1346 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1347 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1348
1349 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1350 #define DWT_FUNCTION_ACTION_Msk (1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1351
1352 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1353 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1354
1355 /*@}*/ /* end of group CMSIS_DWT */
1356
1357
1358 /**
1359 \ingroup CMSIS_core_register
1360 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
1361 \brief Type definitions for the Trace Port Interface Unit (TPIU)
1362 @{
1363 */
1364
1365 /**
1366 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
1367 */
1368 typedef struct
1369 {
1370 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1371 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1372 uint32_t RESERVED0[2U];
1373 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1374 uint32_t RESERVED1[55U];
1375 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1376 uint32_t RESERVED2[131U];
1377 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1378 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1379 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1380 uint32_t RESERVED3[759U];
1381 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1382 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
1383 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
1384 uint32_t RESERVED4[1U];
1385 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
1386 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
1387 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1388 uint32_t RESERVED5[39U];
1389 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1390 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1391 uint32_t RESERVED7[8U];
1392 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1393 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1394 } TPIU_Type;
1395
1396 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
1397 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
1398 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
1399
1400 /** \brief TPIU Selected Pin Protocol Register Definitions */
1401 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
1402 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
1403
1404 /** \brief TPIU Formatter and Flush Status Register Definitions */
1405 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
1406 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
1407
1408 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
1409 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
1410
1411 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
1412 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
1413
1414 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
1415 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
1416
1417 /** \brief TPIU Formatter and Flush Control Register Definitions */
1418 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
1419 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
1420
1421 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */
1422 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */
1423
1424 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
1425 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
1426
1427 /** \brief TPIU Periodic Synchronization Control Register Definitions */
1428 #define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */
1429 #define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */
1430
1431 /** \brief TPIU TRIGGER Register Definitions */
1432 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
1433 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
1434
1435 /** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */
1436 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */
1437 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */
1438
1439 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */
1440 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */
1441
1442 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */
1443 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */
1444
1445 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */
1446 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */
1447
1448 #define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */
1449 #define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */
1450
1451 #define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */
1452 #define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */
1453
1454 #define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */
1455 #define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */
1456
1457 /** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */
1458 #define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */
1459 #define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */
1460
1461 #define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */
1462 #define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */
1463
1464 #define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */
1465 #define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */
1466
1467 #define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */
1468 #define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */
1469
1470 /** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */
1471 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */
1472 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */
1473
1474 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */
1475 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */
1476
1477 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */
1478 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */
1479
1480 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */
1481 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */
1482
1483 #define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */
1484 #define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */
1485
1486 #define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */
1487 #define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */
1488
1489 #define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */
1490 #define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */
1491
1492 /** \brief TPIU Integration Test ATB Control Register 0 Definitions */
1493 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */
1494 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */
1495
1496 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */
1497 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */
1498
1499 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */
1500 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */
1501
1502 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */
1503 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
1504
1505 /** \brief TPIU Integration Mode Control Register Definitions */
1506 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
1507 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
1508
1509 /** \brief TPIU DEVID Register Definitions */
1510 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
1511 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
1512
1513 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
1514 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
1515
1516 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
1517 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
1518
1519 #define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */
1520 #define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */
1521
1522 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
1523 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
1524
1525 /** \brief TPIU DEVTYPE Register Definitions */
1526 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
1527 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
1528
1529 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
1530 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
1531
1532 /*@}*/ /* end of group CMSIS_TPIU */
1533
1534
1535 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1536 /**
1537 \ingroup CMSIS_core_register
1538 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1539 \brief Type definitions for the Memory Protection Unit (MPU)
1540 @{
1541 */
1542
1543 /**
1544 \brief Structure type to access the Memory Protection Unit (MPU).
1545 */
1546 typedef struct
1547 {
1548 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1549 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1550 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1551 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1552 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1553 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1554 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1555 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1556 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1557 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1558 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1559 uint32_t RESERVED0[1];
1560 union {
1561 __IOM uint32_t MAIR[2];
1562 struct {
1563 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1564 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1565 };
1566 };
1567 } MPU_Type;
1568
1569 #define MPU_TYPE_RALIASES 4U
1570
1571 /** \brief MPU Type Register Definitions */
1572 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1573 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1574
1575 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1576 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1577
1578 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1579 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1580
1581 /** \brief MPU Control Register Definitions */
1582 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1583 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1584
1585 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1586 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1587
1588 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1589 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1590
1591 /** \brief MPU Region Number Register Definitions */
1592 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1593 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1594
1595 /** \brief MPU Region Base Address Register Definitions */
1596 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
1597 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
1598
1599 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1600 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1601
1602 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1603 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1604
1605 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1606 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1607
1608 /** \brief MPU Region Limit Address Register Definitions */
1609 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1610 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1611
1612 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1613 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1614
1615 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1616 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */
1617
1618 /** \brief MPU Memory Attribute Indirection Register 0 Definitions */
1619 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1620 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1621
1622 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1623 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1624
1625 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1626 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1627
1628 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1629 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1630
1631 /** \brief MPU Memory Attribute Indirection Register 1 Definitions */
1632 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1633 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1634
1635 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1636 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1637
1638 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1639 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1640
1641 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1642 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1643
1644 /*@} end of group CMSIS_MPU */
1645 #endif
1646
1647
1648 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1649 /**
1650 \ingroup CMSIS_core_register
1651 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1652 \brief Type definitions for the Security Attribution Unit (SAU)
1653 @{
1654 */
1655
1656 /**
1657 \brief Structure type to access the Security Attribution Unit (SAU).
1658 */
1659 typedef struct
1660 {
1661 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1662 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1663 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1664 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1665 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1666 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1667 #else
1668 uint32_t RESERVED0[3];
1669 #endif
1670 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1671 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1672 } SAU_Type;
1673
1674 /** \brief SAU Control Register Definitions */
1675 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1676 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1677
1678 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1679 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1680
1681 /** \brief SAU Type Register Definitions */
1682 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1683 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1684
1685 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1686 /** \brief SAU Region Number Register Definitions */
1687 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1688 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1689
1690 /** \brief SAU Region Base Address Register Definitions */
1691 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1692 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1693
1694 /** \brief SAU Region Limit Address Register Definitions */
1695 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1696 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1697
1698 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1699 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1700
1701 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1702 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1703
1704 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1705
1706 /** \brief SAU Secure Fault Status Register Definitions */
1707 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1708 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1709
1710 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1711 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1712
1713 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1714 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1715
1716 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1717 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1718
1719 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1720 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1721
1722 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1723 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1724
1725 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1726 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1727
1728 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1729 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1730
1731 /*@} end of group CMSIS_SAU */
1732 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1733
1734
1735 /**
1736 \ingroup CMSIS_core_register
1737 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1738 \brief Type definitions for the Floating Point Unit (FPU)
1739 @{
1740 */
1741
1742 /**
1743 \brief Structure type to access the Floating Point Unit (FPU).
1744 */
1745 typedef struct
1746 {
1747 uint32_t RESERVED0[1U];
1748 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1749 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1750 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1751 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1752 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1753 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1754 } FPU_Type;
1755
1756 /** \brief FPU Floating-Point Context Control Register Definitions */
1757 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1758 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1759
1760 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1761 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1762
1763 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1764 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1765
1766 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1767 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1768
1769 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1770 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1771
1772 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1773 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1774
1775 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1776 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1777
1778 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1779 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1780
1781 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1782 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1783
1784 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1785 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1786
1787 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1788 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1789
1790 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1791 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1792
1793 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1794 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1795
1796 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1797 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1798
1799 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1800 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1801
1802 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1803 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1804
1805 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1806 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1807
1808 /** \brief FPU Floating-Point Context Address Register Definitions */
1809 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1810 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1811
1812 /** \brief FPU Floating-Point Default Status Control Register Definitions */
1813 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1814 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1815
1816 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1817 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1818
1819 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1820 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1821
1822 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1823 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1824
1825 /** \brief FPU Media and VFP Feature Register 0 Definitions */
1826 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */
1827 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */
1828
1829 #define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */
1830 #define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */
1831
1832 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */
1833 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */
1834
1835 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */
1836 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
1837
1838 #define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */
1839 #define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */
1840
1841 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */
1842 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
1843
1844 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */
1845 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
1846
1847 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */
1848 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */
1849
1850 /** \brief FPU Media and VFP Feature Register 1 Definitions */
1851 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */
1852 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */
1853
1854 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1855 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1856
1857 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1858 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1859
1860 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1861 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1862
1863 /** \brief FPU Media and VFP Feature Register 2 Definitions */
1864 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1865 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1866
1867 /*@} end of group CMSIS_FPU */
1868
1869
1870 /**
1871 \ingroup CMSIS_core_register
1872 \defgroup CMSIS_DCB Debug Control Block
1873 \brief Type definitions for the Debug Control Block Registers
1874 @{
1875 */
1876
1877 /**
1878 \brief Structure type to access the Debug Control Block Registers (DCB).
1879 */
1880 typedef struct
1881 {
1882 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1883 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1884 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1885 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1886 uint32_t RESERVED0[1U];
1887 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1888 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1889 } DCB_Type;
1890
1891 /** \brief DCB Debug Halting Control and Status Register Definitions */
1892 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1893 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1894
1895 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1896 #define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1897
1898 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1899 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1900
1901 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1902 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1903
1904 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1905 #define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1906
1907 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1908 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1909
1910 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1911 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1912
1913 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1914 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1915
1916 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1917 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1918
1919 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1920 #define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1921
1922 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1923 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1924
1925 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1926 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1927
1928 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1929 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1930
1931 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1932 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1933
1934 /** \brief DCB Debug Core Register Selector Register Definitions */
1935 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1936 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1937
1938 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1939 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1940
1941 /** \brief DCB Debug Core Register Data Register Definitions */
1942 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1943 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1944
1945 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
1946 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1947 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1948
1949 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
1950 #define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
1951
1952 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
1953 #define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
1954
1955 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
1956 #define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
1957
1958 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
1959 #define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
1960
1961 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
1962 #define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
1963
1964 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
1965 #define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
1966
1967 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
1968 #define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
1969
1970 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
1971 #define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
1972
1973 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1974 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1975
1976 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
1977 #define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
1978
1979 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
1980 #define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
1981
1982 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
1983 #define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
1984
1985 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
1986 #define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
1987
1988 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
1989 #define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
1990
1991 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
1992 #define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
1993
1994 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1995 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1996
1997 /** \brief DCB Debug Authentication Control Register Definitions */
1998 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
1999 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
2000
2001 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
2002 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
2003
2004 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
2005 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
2006
2007 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
2008 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
2009
2010 /** \brief DCB Debug Security Control and Status Register Definitions */
2011 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
2012 #define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
2013
2014 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
2015 #define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
2016
2017 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
2018 #define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
2019
2020 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
2021 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
2022
2023 /*@} end of group CMSIS_DCB */
2024
2025
2026 /**
2027 \ingroup CMSIS_core_register
2028 \defgroup CMSIS_DIB Debug Identification Block
2029 \brief Type definitions for the Debug Identification Block Registers
2030 @{
2031 */
2032
2033 /**
2034 \brief Structure type to access the Debug Identification Block Registers (DIB).
2035 */
2036 typedef struct
2037 {
2038 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
2039 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
2040 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
2041 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
2042 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
2043 } DIB_Type;
2044
2045 /** \brief DIB SCS Software Lock Access Register Definitions */
2046 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
2047 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
2048
2049 /** \brief DIB SCS Software Lock Status Register Definitions */
2050 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
2051 #define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
2052
2053 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
2054 #define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
2055
2056 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
2057 #define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
2058
2059 /** \brief DIB Debug Authentication Status Register Definitions */
2060 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
2061 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
2062
2063 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
2064 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
2065
2066 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
2067 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
2068
2069 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
2070 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
2071
2072 /** \brief DIB SCS Device Architecture Register Definitions */
2073 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
2074 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
2075
2076 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
2077 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
2078
2079 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
2080 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
2081
2082 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
2083 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
2084
2085 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
2086 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
2087
2088 /** \brief DIB SCS Device Type Register Definitions */
2089 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
2090 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
2091
2092 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
2093 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
2094
2095 /*@} end of group CMSIS_DIB */
2096
2097
2098 /**
2099 \ingroup CMSIS_core_register
2100 \defgroup CMSIS_core_bitfield Core register bit field macros
2101 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2102 @{
2103 */
2104
2105 /**
2106 \brief Mask and shift a bit field value for use in a register bit range.
2107 \param[in] field Name of the register bit field.
2108 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2109 \return Masked and shifted value.
2110 */
2111 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2112
2113 /**
2114 \brief Mask and shift a register value to extract a bit filed value.
2115 \param[in] field Name of the register bit field.
2116 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2117 \return Masked and shifted bit field value.
2118 */
2119 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2120
2121 /*@} end of group CMSIS_core_bitfield */
2122
2123
2124 /**
2125 \ingroup CMSIS_core_register
2126 \defgroup CMSIS_core_base Core Definitions
2127 \brief Definitions for base addresses, unions, and structures.
2128 @{
2129 */
2130
2131 /* Memory mapping of Core Hardware */
2132 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2133 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2134 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2135 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
2136 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
2137 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
2138 #define EMSS_BASE (0xE001E000UL) /*!<Enhanced Memory SubSystem Base Address */
2139
2140 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2141 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2142 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2143
2144 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2145 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2146 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2147 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2148 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2149 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2150 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
2151 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
2152 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
2153 #define EMSS ((EMSS_Type *) EMSS_BASE ) /*!<Ehanced MSS Registers struct */
2154
2155 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2156 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2157 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2158 #endif
2159
2160 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2161 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2162 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2163 #endif
2164
2165 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2166 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2167
2168 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2169 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2170 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
2171 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
2172 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2173 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2174 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2175
2176 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2177 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2178 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2179 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2180 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
2181 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
2182
2183 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2184 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2185 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2186 #endif
2187
2188 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2189 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2190
2191 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2192 /*@} */
2193
2194
2195 /**
2196 \ingroup CMSIS_core_register
2197 \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
2198 \brief Register alias definitions for backwards compatibility.
2199 @{
2200 */
2201
2202 /*@} */
2203
2204
2205 /*******************************************************************************
2206 * Hardware Abstraction Layer
2207 Core Function Interface contains:
2208 - Core NVIC Functions
2209 - Core SysTick Functions
2210 - Core Debug Functions
2211 - Core Register Access Functions
2212 ******************************************************************************/
2213 /**
2214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2215 */
2216
2217
2218
2219 /* ########################## NVIC functions #################################### */
2220 /**
2221 \ingroup CMSIS_Core_FunctionInterface
2222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2223 \brief Functions that manage interrupts and exceptions via the NVIC.
2224 @{
2225 */
2226
2227 #ifdef CMSIS_NVIC_VIRTUAL
2228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2230 #endif
2231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2232 #else
2233 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2234 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2235 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2237 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2241 #define NVIC_GetActive __NVIC_GetActive
2242 #define NVIC_SetPriority __NVIC_SetPriority
2243 #define NVIC_GetPriority __NVIC_GetPriority
2244 #define NVIC_SystemReset __NVIC_SystemReset
2245 #define SW_SystemReset __SW_SystemReset
2246 #endif /* CMSIS_NVIC_VIRTUAL */
2247
2248 #ifdef CMSIS_VECTAB_VIRTUAL
2249 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2250 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2251 #endif
2252 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2253 #else
2254 #define NVIC_SetVector __NVIC_SetVector
2255 #define NVIC_GetVector __NVIC_GetVector
2256 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2257
2258 #define NVIC_USER_IRQ_OFFSET 16
2259
2260
2261 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2262
2263 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2264 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2265
2266 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2267 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2268 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2269 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2270 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2271 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2272 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2273 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2274
2275 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2276 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2277 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2278 #else
2279 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2280 #endif
2281
2282
2283 /**
2284 \brief Set Priority Grouping
2285 \details Sets the priority grouping field using the required unlock sequence.
2286 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2287 Only values from 0..7 are used.
2288 In case of a conflict between priority grouping and available
2289 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2290 \param [in] PriorityGroup Priority grouping field.
2291 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2292 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2293 {
2294 uint32_t reg_value;
2295 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2296
2297 reg_value = SCB->AIRCR; /* read old register configuration */
2298 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2299 reg_value = (reg_value |
2300 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2301 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2302 SCB->AIRCR = reg_value;
2303 }
2304
2305
2306 /**
2307 \brief Get Priority Grouping
2308 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2310 */
__NVIC_GetPriorityGrouping(void)2311 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2312 {
2313 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2314 }
2315
2316
2317 /**
2318 \brief Enable Interrupt
2319 \details Enables a device specific interrupt in the NVIC interrupt controller.
2320 \param [in] IRQn Device specific interrupt number.
2321 \note IRQn must not be negative.
2322 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2323 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2324 {
2325 if ((int32_t)(IRQn) >= 0)
2326 {
2327 __COMPILER_BARRIER();
2328 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2329 __COMPILER_BARRIER();
2330 }
2331 }
2332
2333
2334 /**
2335 \brief Get Interrupt Enable status
2336 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2337 \param [in] IRQn Device specific interrupt number.
2338 \return 0 Interrupt is not enabled.
2339 \return 1 Interrupt is enabled.
2340 \note IRQn must not be negative.
2341 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2342 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2343 {
2344 if ((int32_t)(IRQn) >= 0)
2345 {
2346 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2347 }
2348 else
2349 {
2350 return(0U);
2351 }
2352 }
2353
2354
2355 /**
2356 \brief Disable Interrupt
2357 \details Disables a device specific interrupt in the NVIC interrupt controller.
2358 \param [in] IRQn Device specific interrupt number.
2359 \note IRQn must not be negative.
2360 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2361 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2362 {
2363 if ((int32_t)(IRQn) >= 0)
2364 {
2365 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2366 __DSB();
2367 __ISB();
2368 }
2369 }
2370
2371
2372 /**
2373 \brief Get Pending Interrupt
2374 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2375 \param [in] IRQn Device specific interrupt number.
2376 \return 0 Interrupt status is not pending.
2377 \return 1 Interrupt status is pending.
2378 \note IRQn must not be negative.
2379 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2380 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2381 {
2382 if ((int32_t)(IRQn) >= 0)
2383 {
2384 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2385 }
2386 else
2387 {
2388 return(0U);
2389 }
2390 }
2391
2392
2393 /**
2394 \brief Set Pending Interrupt
2395 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2396 \param [in] IRQn Device specific interrupt number.
2397 \note IRQn must not be negative.
2398 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2399 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2400 {
2401 if ((int32_t)(IRQn) >= 0)
2402 {
2403 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2404 }
2405 }
2406
2407
2408 /**
2409 \brief Clear Pending Interrupt
2410 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2411 \param [in] IRQn Device specific interrupt number.
2412 \note IRQn must not be negative.
2413 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2414 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2415 {
2416 if ((int32_t)(IRQn) >= 0)
2417 {
2418 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2419 }
2420 }
2421
2422
2423 /**
2424 \brief Get Active Interrupt
2425 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2426 \param [in] IRQn Device specific interrupt number.
2427 \return 0 Interrupt status is not active.
2428 \return 1 Interrupt status is active.
2429 \note IRQn must not be negative.
2430 */
__NVIC_GetActive(IRQn_Type IRQn)2431 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2432 {
2433 if ((int32_t)(IRQn) >= 0)
2434 {
2435 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2436 }
2437 else
2438 {
2439 return(0U);
2440 }
2441 }
2442
2443
2444 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2445 /**
2446 \brief Get Interrupt Target State
2447 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2448 \param [in] IRQn Device specific interrupt number.
2449 \return 0 if interrupt is assigned to Secure
2450 \return 1 if interrupt is assigned to Non Secure
2451 \note IRQn must not be negative.
2452 */
NVIC_GetTargetState(IRQn_Type IRQn)2453 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2454 {
2455 if ((int32_t)(IRQn) >= 0)
2456 {
2457 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2458 }
2459 else
2460 {
2461 return(0U);
2462 }
2463 }
2464
2465
2466 /**
2467 \brief Set Interrupt Target State
2468 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2469 \param [in] IRQn Device specific interrupt number.
2470 \return 0 if interrupt is assigned to Secure
2471 1 if interrupt is assigned to Non Secure
2472 \note IRQn must not be negative.
2473 */
NVIC_SetTargetState(IRQn_Type IRQn)2474 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2475 {
2476 if ((int32_t)(IRQn) >= 0)
2477 {
2478 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2479 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2480 }
2481 else
2482 {
2483 return(0U);
2484 }
2485 }
2486
2487
2488 /**
2489 \brief Clear Interrupt Target State
2490 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2491 \param [in] IRQn Device specific interrupt number.
2492 \return 0 if interrupt is assigned to Secure
2493 1 if interrupt is assigned to Non Secure
2494 \note IRQn must not be negative.
2495 */
NVIC_ClearTargetState(IRQn_Type IRQn)2496 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2497 {
2498 if ((int32_t)(IRQn) >= 0)
2499 {
2500 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2501 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2502 }
2503 else
2504 {
2505 return(0U);
2506 }
2507 }
2508 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2509
2510
2511 /**
2512 \brief Set Interrupt Priority
2513 \details Sets the priority of a device specific interrupt or a processor exception.
2514 The interrupt number can be positive to specify a device specific interrupt,
2515 or negative to specify a processor exception.
2516 \param [in] IRQn Interrupt number.
2517 \param [in] priority Priority to set.
2518 \note The priority cannot be set for every processor exception.
2519 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2520 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2521 {
2522 if ((int32_t)(IRQn) >= 0)
2523 {
2524 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2525 }
2526 else
2527 {
2528 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2529 }
2530 }
2531
2532
2533 /**
2534 \brief Get Interrupt Priority
2535 \details Reads the priority of a device specific interrupt or a processor exception.
2536 The interrupt number can be positive to specify a device specific interrupt,
2537 or negative to specify a processor exception.
2538 \param [in] IRQn Interrupt number.
2539 \return Interrupt Priority.
2540 Value is aligned automatically to the implemented priority bits of the microcontroller.
2541 */
__NVIC_GetPriority(IRQn_Type IRQn)2542 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2543 {
2544
2545 if ((int32_t)(IRQn) >= 0)
2546 {
2547 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2548 }
2549 else
2550 {
2551 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2552 }
2553 }
2554
2555
2556 /**
2557 \brief Encode Priority
2558 \details Encodes the priority for an interrupt with the given priority group,
2559 preemptive priority value, and subpriority value.
2560 In case of a conflict between priority grouping and available
2561 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2562 \param [in] PriorityGroup Used priority group.
2563 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2564 \param [in] SubPriority Subpriority value (starting from 0).
2565 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2566 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2567 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2568 {
2569 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2570 uint32_t PreemptPriorityBits;
2571 uint32_t SubPriorityBits;
2572
2573 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2574 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2575
2576 return (
2577 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2578 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2579 );
2580 }
2581
2582
2583 /**
2584 \brief Decode Priority
2585 \details Decodes an interrupt priority value with a given priority group to
2586 preemptive priority value and subpriority value.
2587 In case of a conflict between priority grouping and available
2588 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2589 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2590 \param [in] PriorityGroup Used priority group.
2591 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2592 \param [out] pSubPriority Subpriority value (starting from 0).
2593 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2594 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2595 {
2596 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2597 uint32_t PreemptPriorityBits;
2598 uint32_t SubPriorityBits;
2599
2600 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2601 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2602
2603 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2604 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2605 }
2606
2607
2608 /**
2609 \brief Set Interrupt Vector
2610 \details Sets an interrupt vector in SRAM based interrupt vector table.
2611 The interrupt number can be positive to specify a device specific interrupt,
2612 or negative to specify a processor exception.
2613 VTOR must been relocated to SRAM before.
2614 \param [in] IRQn Interrupt number
2615 \param [in] vector Address of interrupt handler function
2616 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2617 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2618 {
2619 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2620 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2621 __DSB();
2622 }
2623
2624
2625 /**
2626 \brief Get Interrupt Vector
2627 \details Reads an interrupt vector from interrupt vector table.
2628 The interrupt number can be positive to specify a device specific interrupt,
2629 or negative to specify a processor exception.
2630 \param [in] IRQn Interrupt number.
2631 \return Address of interrupt handler function
2632 */
__NVIC_GetVector(IRQn_Type IRQn)2633 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2634 {
2635 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2636 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2637 }
2638
2639
2640 /**
2641 \brief System Reset
2642 \details Initiates a system reset request to reset the MCU.
2643 */
__NVIC_SystemReset(void)2644 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2645 {
2646 __DSB(); /* Ensure all outstanding memory accesses included
2647 buffered write are completed before reset */
2648 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2649 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2650 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2651 __DSB(); /* Ensure completion of memory access */
2652
2653 for(;;) /* wait until reset */
2654 {
2655 __NOP();
2656 }
2657 }
2658
2659 /**
2660 \brief Software Reset
2661 \details Initiates a system reset request to reset the CPU.
2662 */
__SW_SystemReset(void)2663 __NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)
2664 {
2665 __DSB(); /* Ensure all outstanding memory accesses including
2666 buffered write are completed before reset */
2667 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2668 (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */
2669 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */
2670 SCB_AIRCR_SYSRESETREQ_Msk );
2671 __DSB(); /* Ensure completion of memory access */
2672
2673 for(;;) /* wait until reset */
2674 {
2675 __NOP();
2676 }
2677 }
2678
2679
2680 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2681 /**
2682 \brief Set Priority Grouping (non-secure)
2683 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2684 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2685 Only values from 0..7 are used.
2686 In case of a conflict between priority grouping and available
2687 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2688 \param [in] PriorityGroup Priority grouping field.
2689 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2690 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2691 {
2692 uint32_t reg_value;
2693 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2694
2695 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2696 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2697 reg_value = (reg_value |
2698 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2699 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2700 SCB_NS->AIRCR = reg_value;
2701 }
2702
2703
2704 /**
2705 \brief Get Priority Grouping (non-secure)
2706 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2707 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2708 */
TZ_NVIC_GetPriorityGrouping_NS(void)2709 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2710 {
2711 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2712 }
2713
2714
2715 /**
2716 \brief Enable Interrupt (non-secure)
2717 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2718 \param [in] IRQn Device specific interrupt number.
2719 \note IRQn must not be negative.
2720 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2721 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2722 {
2723 if ((int32_t)(IRQn) >= 0)
2724 {
2725 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2726 }
2727 }
2728
2729
2730 /**
2731 \brief Get Interrupt Enable status (non-secure)
2732 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2733 \param [in] IRQn Device specific interrupt number.
2734 \return 0 Interrupt is not enabled.
2735 \return 1 Interrupt is enabled.
2736 \note IRQn must not be negative.
2737 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2738 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2739 {
2740 if ((int32_t)(IRQn) >= 0)
2741 {
2742 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2743 }
2744 else
2745 {
2746 return(0U);
2747 }
2748 }
2749
2750
2751 /**
2752 \brief Disable Interrupt (non-secure)
2753 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2754 \param [in] IRQn Device specific interrupt number.
2755 \note IRQn must not be negative.
2756 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2757 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2758 {
2759 if ((int32_t)(IRQn) >= 0)
2760 {
2761 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2762 }
2763 }
2764
2765
2766 /**
2767 \brief Get Pending Interrupt (non-secure)
2768 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2769 \param [in] IRQn Device specific interrupt number.
2770 \return 0 Interrupt status is not pending.
2771 \return 1 Interrupt status is pending.
2772 \note IRQn must not be negative.
2773 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2774 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2775 {
2776 if ((int32_t)(IRQn) >= 0)
2777 {
2778 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2779 }
2780 else
2781 {
2782 return(0U);
2783 }
2784 }
2785
2786
2787 /**
2788 \brief Set Pending Interrupt (non-secure)
2789 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2790 \param [in] IRQn Device specific interrupt number.
2791 \note IRQn must not be negative.
2792 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2793 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2794 {
2795 if ((int32_t)(IRQn) >= 0)
2796 {
2797 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2798 }
2799 }
2800
2801
2802 /**
2803 \brief Clear Pending Interrupt (non-secure)
2804 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2805 \param [in] IRQn Device specific interrupt number.
2806 \note IRQn must not be negative.
2807 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2808 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2809 {
2810 if ((int32_t)(IRQn) >= 0)
2811 {
2812 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2813 }
2814 }
2815
2816
2817 /**
2818 \brief Get Active Interrupt (non-secure)
2819 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2820 \param [in] IRQn Device specific interrupt number.
2821 \return 0 Interrupt status is not active.
2822 \return 1 Interrupt status is active.
2823 \note IRQn must not be negative.
2824 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2825 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2826 {
2827 if ((int32_t)(IRQn) >= 0)
2828 {
2829 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2830 }
2831 else
2832 {
2833 return(0U);
2834 }
2835 }
2836
2837
2838 /**
2839 \brief Set Interrupt Priority (non-secure)
2840 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2841 The interrupt number can be positive to specify a device specific interrupt,
2842 or negative to specify a processor exception.
2843 \param [in] IRQn Interrupt number.
2844 \param [in] priority Priority to set.
2845 \note The priority cannot be set for every non-secure processor exception.
2846 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2847 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2848 {
2849 if ((int32_t)(IRQn) >= 0)
2850 {
2851 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2852 }
2853 else
2854 {
2855 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2856 }
2857 }
2858
2859
2860 /**
2861 \brief Get Interrupt Priority (non-secure)
2862 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2863 The interrupt number can be positive to specify a device specific interrupt,
2864 or negative to specify a processor exception.
2865 \param [in] IRQn Interrupt number.
2866 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2867 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2868 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2869 {
2870
2871 if ((int32_t)(IRQn) >= 0)
2872 {
2873 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2874 }
2875 else
2876 {
2877 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2878 }
2879 }
2880 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2881
2882 /*@} end of CMSIS_Core_NVICFunctions */
2883
2884 /* ########################## MPU functions #################################### */
2885
2886 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2887
2888 #include "m-profile/armv8m_mpu.h"
2889
2890 #endif
2891
2892
2893 /* ########################## FPU functions #################################### */
2894 /**
2895 \ingroup CMSIS_Core_FunctionInterface
2896 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2897 \brief Function that provides FPU type.
2898 @{
2899 */
2900
2901 /**
2902 \brief get FPU type
2903 \details returns the FPU type
2904 \returns
2905 - \b 0: No FPU
2906 - \b 1: Single precision FPU
2907 - \b 2: Double + Single precision FPU
2908 */
SCB_GetFPUType(void)2909 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2910 {
2911 uint32_t mvfr0;
2912
2913 mvfr0 = FPU->MVFR0;
2914 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
2915 {
2916 return 2U; /* Double + Single precision FPU */
2917 }
2918 else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
2919 {
2920 return 1U; /* Single precision FPU */
2921 }
2922 else
2923 {
2924 return 0U; /* No FPU */
2925 }
2926 }
2927
2928 /*@} end of CMSIS_Core_FpuFunctions */
2929
2930
2931
2932 /* ########################## SAU functions #################################### */
2933 /**
2934 \ingroup CMSIS_Core_FunctionInterface
2935 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2936 \brief Functions that configure the SAU.
2937 @{
2938 */
2939
2940 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2941
2942 /**
2943 \brief Enable SAU
2944 \details Enables the Security Attribution Unit (SAU).
2945 */
TZ_SAU_Enable(void)2946 __STATIC_INLINE void TZ_SAU_Enable(void)
2947 {
2948 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2949 }
2950
2951
2952
2953 /**
2954 \brief Disable SAU
2955 \details Disables the Security Attribution Unit (SAU).
2956 */
TZ_SAU_Disable(void)2957 __STATIC_INLINE void TZ_SAU_Disable(void)
2958 {
2959 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2960 }
2961
2962 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2963
2964 /*@} end of CMSIS_Core_SAUFunctions */
2965
2966
2967
2968
2969 /* ################################## Debug Control function ############################################ */
2970 /**
2971 \ingroup CMSIS_Core_FunctionInterface
2972 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
2973 \brief Functions that access the Debug Control Block.
2974 @{
2975 */
2976
2977
2978 /**
2979 \brief Set Debug Authentication Control Register
2980 \details writes to Debug Authentication Control register.
2981 \param [in] value value to be writen.
2982 */
DCB_SetAuthCtrl(uint32_t value)2983 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2984 {
2985 __DSB();
2986 __ISB();
2987 DCB->DAUTHCTRL = value;
2988 __DSB();
2989 __ISB();
2990 }
2991
2992
2993 /**
2994 \brief Get Debug Authentication Control Register
2995 \details Reads Debug Authentication Control register.
2996 \return Debug Authentication Control Register.
2997 */
DCB_GetAuthCtrl(void)2998 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2999 {
3000 return (DCB->DAUTHCTRL);
3001 }
3002
3003
3004 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3005 /**
3006 \brief Set Debug Authentication Control Register (non-secure)
3007 \details writes to non-secure Debug Authentication Control register when in secure state.
3008 \param [in] value value to be writen
3009 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)3010 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3011 {
3012 __DSB();
3013 __ISB();
3014 DCB_NS->DAUTHCTRL = value;
3015 __DSB();
3016 __ISB();
3017 }
3018
3019
3020 /**
3021 \brief Get Debug Authentication Control Register (non-secure)
3022 \details Reads non-secure Debug Authentication Control register when in secure state.
3023 \return Debug Authentication Control Register.
3024 */
TZ_DCB_GetAuthCtrl_NS(void)3025 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3026 {
3027 return (DCB_NS->DAUTHCTRL);
3028 }
3029 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3030
3031 /*@} end of CMSIS_Core_DCBFunctions */
3032
3033
3034
3035
3036 /* ################################## Debug Identification function ############################################ */
3037 /**
3038 \ingroup CMSIS_Core_FunctionInterface
3039 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
3040 \brief Functions that access the Debug Identification Block.
3041 @{
3042 */
3043
3044
3045 /**
3046 \brief Get Debug Authentication Status Register
3047 \details Reads Debug Authentication Status register.
3048 \return Debug Authentication Status Register.
3049 */
DIB_GetAuthStatus(void)3050 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3051 {
3052 return (DIB->DAUTHSTATUS);
3053 }
3054
3055
3056 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3057 /**
3058 \brief Get Debug Authentication Status Register (non-secure)
3059 \details Reads non-secure Debug Authentication Status register when in secure state.
3060 \return Debug Authentication Status Register.
3061 */
TZ_DIB_GetAuthStatus_NS(void)3062 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3063 {
3064 return (DIB_NS->DAUTHSTATUS);
3065 }
3066 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3067
3068 /*@} end of CMSIS_Core_DCBFunctions */
3069
3070
3071 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
3072 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
3073
3074 /* ########################## Cache functions #################################### */
3075 /**
3076 \ingroup CMSIS_Core_FunctionInterface
3077 \defgroup CMSIS_Core_CacheFunctions Cache Functions
3078 \brief Functions that configure Instruction and Data cache.
3079 @{
3080 */
3081
3082 /* Cache Size ID Register Macros */
3083 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
3084 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
3085
3086 #define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
3087 #define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
3088
3089 /**
3090 \brief Enable I-Cache
3091 \details Turns on I-Cache
3092 */
SCB_EnableICache(void)3093 __STATIC_FORCEINLINE void SCB_EnableICache (void)
3094 {
3095 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3096 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
3097
3098 __DSB();
3099 __ISB();
3100 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3101 __DSB();
3102 __ISB();
3103 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
3104 __DSB();
3105 __ISB();
3106 #endif
3107 }
3108
3109
3110 /**
3111 \brief Disable I-Cache
3112 \details Turns off I-Cache
3113 */
SCB_DisableICache(void)3114 __STATIC_FORCEINLINE void SCB_DisableICache (void)
3115 {
3116 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3117 __DSB();
3118 __ISB();
3119 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
3120 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3121 __DSB();
3122 __ISB();
3123 #endif
3124 }
3125
3126
3127 /**
3128 \brief Invalidate I-Cache
3129 \details Invalidates I-Cache
3130 */
SCB_InvalidateICache(void)3131 __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
3132 {
3133 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3134 __DSB();
3135 __ISB();
3136 SCB->ICIALLU = 0UL;
3137 __DSB();
3138 __ISB();
3139 #endif
3140 }
3141
3142
3143 /**
3144 \brief I-Cache Invalidate by address
3145 \details Invalidates I-Cache for the given address.
3146 I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
3147 I-Cache memory blocks which are part of given address + given size are invalidated.
3148 \param[in] addr address
3149 \param[in] isize size of memory block (in number of bytes)
3150 */
SCB_InvalidateICache_by_Addr(void * addr,int32_t isize)3151 __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
3152 {
3153 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3154 if ( isize > 0 ) {
3155 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
3156 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
3157
3158 __DSB();
3159
3160 do {
3161 SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3162 op_addr += __SCB_ICACHE_LINE_SIZE;
3163 op_size -= __SCB_ICACHE_LINE_SIZE;
3164 } while ( op_size > 0 );
3165
3166 __DSB();
3167 __ISB();
3168 }
3169 #endif
3170 }
3171
3172
3173 /**
3174 \brief Enable D-Cache
3175 \details Turns on D-Cache
3176 */
SCB_EnableDCache(void)3177 __STATIC_FORCEINLINE void SCB_EnableDCache (void)
3178 {
3179 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3180 uint32_t ccsidr;
3181 uint32_t sets;
3182 uint32_t ways;
3183
3184 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
3185
3186 SCB->CSSELR = 0U; /* select Level 1 data cache */
3187 __DSB();
3188
3189 ccsidr = SCB->CCSIDR;
3190
3191 /* invalidate D-Cache */
3192 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3193 do {
3194 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3195 do {
3196 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3197 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3198 #if defined ( __CC_ARM )
3199 __schedule_barrier();
3200 #endif
3201 } while (ways-- != 0U);
3202 } while(sets-- != 0U);
3203 __DSB();
3204
3205 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
3206
3207 __DSB();
3208 __ISB();
3209 #endif
3210 }
3211
3212
3213 /**
3214 \brief Disable D-Cache
3215 \details Turns off D-Cache
3216 */
SCB_DisableDCache(void)3217 __STATIC_FORCEINLINE void SCB_DisableDCache (void)
3218 {
3219 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3220 uint32_t ccsidr;
3221 uint32_t sets;
3222 uint32_t ways;
3223
3224 SCB->CSSELR = 0U; /* select Level 1 data cache */
3225 __DSB();
3226
3227 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
3228 __DSB();
3229
3230 ccsidr = SCB->CCSIDR;
3231
3232 /* clean & invalidate D-Cache */
3233 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3234 do {
3235 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3236 do {
3237 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3238 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3239 #if defined ( __CC_ARM )
3240 __schedule_barrier();
3241 #endif
3242 } while (ways-- != 0U);
3243 } while(sets-- != 0U);
3244
3245 __DSB();
3246 __ISB();
3247 #endif
3248 }
3249
3250
3251 /**
3252 \brief Invalidate D-Cache
3253 \details Invalidates D-Cache
3254 */
SCB_InvalidateDCache(void)3255 __STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
3256 {
3257 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3258 uint32_t ccsidr;
3259 uint32_t sets;
3260 uint32_t ways;
3261
3262 SCB->CSSELR = 0U; /* select Level 1 data cache */
3263 __DSB();
3264
3265 ccsidr = SCB->CCSIDR;
3266
3267 /* invalidate D-Cache */
3268 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3269 do {
3270 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3271 do {
3272 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3273 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3274 #if defined ( __CC_ARM )
3275 __schedule_barrier();
3276 #endif
3277 } while (ways-- != 0U);
3278 } while(sets-- != 0U);
3279
3280 __DSB();
3281 __ISB();
3282 #endif
3283 }
3284
3285
3286 /**
3287 \brief Clean D-Cache
3288 \details Cleans D-Cache
3289 */
SCB_CleanDCache(void)3290 __STATIC_FORCEINLINE void SCB_CleanDCache (void)
3291 {
3292 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3293 uint32_t ccsidr;
3294 uint32_t sets;
3295 uint32_t ways;
3296
3297 SCB->CSSELR = 0U; /* select Level 1 data cache */
3298 __DSB();
3299
3300 ccsidr = SCB->CCSIDR;
3301
3302 /* clean D-Cache */
3303 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3304 do {
3305 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3306 do {
3307 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
3308 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
3309 #if defined ( __CC_ARM )
3310 __schedule_barrier();
3311 #endif
3312 } while (ways-- != 0U);
3313 } while(sets-- != 0U);
3314
3315 __DSB();
3316 __ISB();
3317 #endif
3318 }
3319
3320
3321 /**
3322 \brief Clean & Invalidate D-Cache
3323 \details Cleans and Invalidates D-Cache
3324 */
SCB_CleanInvalidateDCache(void)3325 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
3326 {
3327 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3328 uint32_t ccsidr;
3329 uint32_t sets;
3330 uint32_t ways;
3331
3332 SCB->CSSELR = 0U; /* select Level 1 data cache */
3333 __DSB();
3334
3335 ccsidr = SCB->CCSIDR;
3336
3337 /* clean & invalidate D-Cache */
3338 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3339 do {
3340 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3341 do {
3342 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3343 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3344 #if defined ( __CC_ARM )
3345 __schedule_barrier();
3346 #endif
3347 } while (ways-- != 0U);
3348 } while(sets-- != 0U);
3349
3350 __DSB();
3351 __ISB();
3352 #endif
3353 }
3354
3355
3356 /**
3357 \brief D-Cache Invalidate by address
3358 \details Invalidates D-Cache for the given address.
3359 D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
3360 D-Cache memory blocks which are part of given address + given size are invalidated.
3361 \param[in] addr address
3362 \param[in] dsize size of memory block (in number of bytes)
3363 */
SCB_InvalidateDCache_by_Addr(void * addr,int32_t dsize)3364 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
3365 {
3366 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3367 if ( dsize > 0 ) {
3368 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3369 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3370
3371 __DSB();
3372
3373 do {
3374 SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3375 op_addr += __SCB_DCACHE_LINE_SIZE;
3376 op_size -= __SCB_DCACHE_LINE_SIZE;
3377 } while ( op_size > 0 );
3378
3379 __DSB();
3380 __ISB();
3381 }
3382 #endif
3383 }
3384
3385
3386 /**
3387 \brief D-Cache Clean by address
3388 \details Cleans D-Cache for the given address
3389 D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
3390 D-Cache memory blocks which are part of given address + given size are cleaned.
3391 \param[in] addr address
3392 \param[in] dsize size of memory block (in number of bytes)
3393 */
SCB_CleanDCache_by_Addr(uint32_t * addr,int32_t dsize)3394 __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
3395 {
3396 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3397 if ( dsize > 0 ) {
3398 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3399 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3400
3401 __DSB();
3402
3403 do {
3404 SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3405 op_addr += __SCB_DCACHE_LINE_SIZE;
3406 op_size -= __SCB_DCACHE_LINE_SIZE;
3407 } while ( op_size > 0 );
3408
3409 __DSB();
3410 __ISB();
3411 }
3412 #endif
3413 }
3414
3415
3416 /**
3417 \brief D-Cache Clean and Invalidate by address
3418 \details Cleans and invalidates D_Cache for the given address
3419 D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
3420 D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
3421 \param[in] addr address (aligned to 32-byte boundary)
3422 \param[in] dsize size of memory block (in number of bytes)
3423 */
SCB_CleanInvalidateDCache_by_Addr(uint32_t * addr,int32_t dsize)3424 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
3425 {
3426 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3427 if ( dsize > 0 ) {
3428 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3429 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3430
3431 __DSB();
3432
3433 do {
3434 SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3435 op_addr += __SCB_DCACHE_LINE_SIZE;
3436 op_size -= __SCB_DCACHE_LINE_SIZE;
3437 } while ( op_size > 0 );
3438
3439 __DSB();
3440 __ISB();
3441 }
3442 #endif
3443 }
3444
3445 /*@} end of CMSIS_Core_CacheFunctions */
3446 #endif
3447
3448
3449 /* ################################## SysTick function ############################################ */
3450 /**
3451 \ingroup CMSIS_Core_FunctionInterface
3452 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
3453 \brief Functions that configure the System.
3454 @{
3455 */
3456
3457 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3458
3459 /**
3460 \brief System Tick Configuration
3461 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
3462 Counter is in free running mode to generate periodic interrupts.
3463 \param [in] ticks Number of ticks between two interrupts.
3464 \return 0 Function succeeded.
3465 \return 1 Function failed.
3466 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3467 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
3468 must contain a vendor-specific implementation of this function.
3469 */
SysTick_Config(uint32_t ticks)3470 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3471 {
3472 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3473 {
3474 return (1UL); /* Reload value impossible */
3475 }
3476
3477 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3478 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3479 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3480 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3481 SysTick_CTRL_TICKINT_Msk |
3482 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3483 return (0UL); /* Function successful */
3484 }
3485
3486 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3487 /**
3488 \brief System Tick Configuration (non-secure)
3489 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
3490 Counter is in free running mode to generate periodic interrupts.
3491 \param [in] ticks Number of ticks between two interrupts.
3492 \return 0 Function succeeded.
3493 \return 1 Function failed.
3494 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3495 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
3496 must contain a vendor-specific implementation of this function.
3497
3498 */
TZ_SysTick_Config_NS(uint32_t ticks)3499 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3500 {
3501 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3502 {
3503 return (1UL); /* Reload value impossible */
3504 }
3505
3506 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3507 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3508 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3509 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3510 SysTick_CTRL_TICKINT_Msk |
3511 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3512 return (0UL); /* Function successful */
3513 }
3514 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3515
3516 #endif
3517
3518 /*@} end of CMSIS_Core_SysTickFunctions */
3519
3520
3521
3522 /* ##################################### Debug In/Output function ########################################### */
3523 /**
3524 \ingroup CMSIS_Core_FunctionInterface
3525 \defgroup CMSIS_core_DebugFunctions ITM Functions
3526 \brief Functions that access the ITM debug interface.
3527 @{
3528 */
3529
3530 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
3531 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
3532
3533
3534 /**
3535 \brief ITM Send Character
3536 \details Transmits a character via the ITM channel 0, and
3537 \li Just returns when no debugger is connected that has booked the output.
3538 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
3539 \param [in] ch Character to transmit.
3540 \returns Character to transmit.
3541 */
ITM_SendChar(uint32_t ch)3542 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3543 {
3544 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3545 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3546 {
3547 while (ITM->PORT[0U].u32 == 0UL)
3548 {
3549 __NOP();
3550 }
3551 ITM->PORT[0U].u8 = (uint8_t)ch;
3552 }
3553 return (ch);
3554 }
3555
3556
3557 /**
3558 \brief ITM Receive Character
3559 \details Inputs a character via the external variable \ref ITM_RxBuffer.
3560 \return Received character.
3561 \return -1 No character pending.
3562 */
ITM_ReceiveChar(void)3563 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3564 {
3565 int32_t ch = -1; /* no character available */
3566
3567 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3568 {
3569 ch = ITM_RxBuffer;
3570 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3571 }
3572
3573 return (ch);
3574 }
3575
3576
3577 /**
3578 \brief ITM Check Character
3579 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
3580 \return 0 No character available.
3581 \return 1 Character available.
3582 */
ITM_CheckChar(void)3583 __STATIC_INLINE int32_t ITM_CheckChar (void)
3584 {
3585
3586 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3587 {
3588 return (0); /* no character available */
3589 }
3590 else
3591 {
3592 return (1); /* character available */
3593 }
3594 }
3595
3596 /*@} end of CMSIS_core_DebugFunctions */
3597
3598
3599
3600
3601 #ifdef __cplusplus
3602 }
3603 #endif
3604
3605 #endif /* __CORE_STAR_H_DEPENDANT */
3606
3607 #endif /* __CMSIS_GENERIC */
3608