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1 /*
2  * Copyright © 2014 NVIDIA Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #ifndef TEGRA_DRM_TEST_TEGRA_H
24 #define TEGRA_DRM_TEST_TEGRA_H
25 
26 #include "drm-test.h"
27 #include "tegra.h"
28 
29 #define HOST1X_OPCODE_SETCL(offset, classid, mask) \
30     ((0x0 << 28) | (((offset) & 0xfff) << 16) | (((classid) & 0x3ff) << 6) | ((mask) & 0x3f))
31 #define HOST1X_OPCODE_INCR(offset, count) \
32     ((0x1 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
33 #define HOST1X_OPCODE_NONINCR(offset, count) \
34     ((0x2 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
35 #define HOST1X_OPCODE_MASK(offset, mask) \
36     ((0x3 << 28) | (((offset) & 0xfff) << 16) | ((mask) & 0xffff))
37 #define HOST1X_OPCODE_IMM(offset, data) \
38     ((0x4 << 28) | (((offset) & 0xfff) << 16) | ((data) & 0xffff))
39 #define HOST1X_OPCODE_EXTEND(subop, value) \
40     ((0xe << 28) | (((subop) & 0xf) << 24) | ((value) & 0xffffff))
41 
42 #define HOST1X_CLASS_GR2D 0x51
43 
44 struct drm_tegra_gr2d {
45     struct drm_tegra *drm;
46     struct drm_tegra_channel *channel;
47 };
48 
49 int drm_tegra_gr2d_open(struct drm_tegra *drm, struct drm_tegra_gr2d **gr2dp);
50 int drm_tegra_gr2d_close(struct drm_tegra_gr2d *gr2d);
51 int drm_tegra_gr2d_fill(struct drm_tegra_gr2d *gr2d, struct drm_framebuffer *fb,
52                         unsigned int x, unsigned int y, unsigned int width,
53                         unsigned int height, uint32_t color);
54 
55 #endif
56