1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8the rights to use, copy, modify, merge, publish, distribute, sublicense, 9and/or sell copies of the Software, and to permit persons to whom the 10Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22SOFTWARE. 23 --> 24 25<!-- 26The basic idea is to define a hierarchy of encodings, where various 27ranges of bits can be either: 28 29* patterns to match to select a sub-encoding (0, 1, x (dontcare)) 30* instruction parameters (ie. dst register, type, etc) 31* range of bits that delegates to another hierarchy (ie. src reg 32 encoding which has multiple sub-encodings depending on gpr/const/ 33 relative) 34 35The root of the encoding hierarchy defines the size. By the concrete 36leaf nodes of an encoding hierarchy all bits should be accounted for 37(ie. either defined fields or as 0/1/x). 38 39TODO: 40* add optional min/max gen fields for cases where same binary maps 41 to different instructions and/or encodings on later gens 42* schema 43 --> 44 45 46<isa> 47 48<import file="ir3-common.xml"/> 49 50<bitset name="#instruction" size="64"> 51 <doc> 52 Encoding of an ir3 instruction. All instructions are 64b. 53 </doc> 54 <gen min="300"/> 55 <encode type="struct ir3_instruction *" case-prefix="OPC_"> 56 <!-- 57 Define mapping from encode src to individual fields, 58 which are common across all instruction categories 59 at the root instruction level 60 61 Not all of these apply to all instructions, but we 62 can define mappings here for anything that is used 63 in more than one instruction category. For things 64 that are specific to a single instruction category, 65 mappings should be defined at that level instead. 66 --> 67 <map name="DST">src->dsts[0]</map> 68 <map name="SRC1">src->srcs[0]</map> 69 <map name="SRC2">src->srcs[1]</map> 70 <map name="SRC3">src->srcs[2]</map> 71 <map name="REPEAT">src->repeat</map> 72 <map name="SS">!!(src->flags & IR3_INSTR_SS)</map> 73 <map name="JP">!!(src->flags & IR3_INSTR_JP)</map> 74 <map name="SY">!!(src->flags & IR3_INSTR_SY)</map> 75 <map name="UL">!!(src->flags & IR3_INSTR_UL)</map> 76 <map name="EQ">0</map> <!-- We don't use this (yet) --> 77 <map name="SAT">!!(src->flags & IR3_INSTR_SAT)</map> 78 </encode> 79</bitset> 80 81<import file="ir3-cat0.xml"/> 82<import file="ir3-cat1.xml"/> 83<import file="ir3-cat2.xml"/> 84<import file="ir3-cat3.xml"/> 85<import file="ir3-cat4.xml"/> 86<import file="ir3-cat5.xml"/> 87<import file="ir3-cat6.xml"/> 88<import file="ir3-cat7.xml"/> 89 90</isa> 91