1 2template = """\ 3/* 4 * Copyright (c) 2019 Valve Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * This file was generated by aco_builder_h.py 26 */ 27 28#ifndef _ACO_BUILDER_ 29#define _ACO_BUILDER_ 30 31#include "aco_ir.h" 32 33namespace aco { 34enum dpp_ctrl { 35 _dpp_quad_perm = 0x000, 36 _dpp_row_sl = 0x100, 37 _dpp_row_sr = 0x110, 38 _dpp_row_rr = 0x120, 39 dpp_wf_sl1 = 0x130, 40 dpp_wf_rl1 = 0x134, 41 dpp_wf_sr1 = 0x138, 42 dpp_wf_rr1 = 0x13C, 43 dpp_row_mirror = 0x140, 44 dpp_row_half_mirror = 0x141, 45 dpp_row_bcast15 = 0x142, 46 dpp_row_bcast31 = 0x143 47}; 48 49inline dpp_ctrl 50dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3) 51{ 52 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4); 53 return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6)); 54} 55 56inline dpp_ctrl 57dpp_row_sl(unsigned amount) 58{ 59 assert(amount > 0 && amount < 16); 60 return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount); 61} 62 63inline dpp_ctrl 64dpp_row_sr(unsigned amount) 65{ 66 assert(amount > 0 && amount < 16); 67 return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount); 68} 69 70inline dpp_ctrl 71dpp_row_rr(unsigned amount) 72{ 73 assert(amount > 0 && amount < 16); 74 return (dpp_ctrl)(((unsigned) _dpp_row_rr) | amount); 75} 76 77inline unsigned 78ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask) 79{ 80 assert(and_mask < 32 && or_mask < 32 && xor_mask < 32); 81 return and_mask | (or_mask << 5) | (xor_mask << 10); 82} 83 84aco_ptr<Instruction> create_s_mov(Definition dst, Operand src); 85 86enum sendmsg { 87 sendmsg_none = 0, 88 _sendmsg_gs = 2, 89 _sendmsg_gs_done = 3, 90 sendmsg_save_wave = 4, 91 sendmsg_stall_wave_gen = 5, 92 sendmsg_halt_waves = 6, 93 sendmsg_ordered_ps_done = 7, 94 sendmsg_early_prim_dealloc = 8, 95 sendmsg_gs_alloc_req = 9, 96 sendmsg_id_mask = 0xf, 97}; 98 99inline sendmsg 100sendmsg_gs(bool cut, bool emit, unsigned stream) 101{ 102 assert(stream < 4); 103 return (sendmsg)((unsigned)_sendmsg_gs | (cut << 4) | (emit << 5) | (stream << 8)); 104} 105 106inline sendmsg 107sendmsg_gs_done(bool cut, bool emit, unsigned stream) 108{ 109 assert(stream < 4); 110 return (sendmsg)((unsigned)_sendmsg_gs_done | (cut << 4) | (emit << 5) | (stream << 8)); 111} 112 113enum bperm_swiz { 114 bperm_b1_sign = 8, 115 bperm_b3_sign = 9, 116 bperm_b5_sign = 10, 117 bperm_b7_sign = 11, 118 bperm_0 = 12, 119 bperm_255 = 13, 120}; 121 122class Builder { 123public: 124 struct Result { 125 Instruction *instr; 126 127 Result(Instruction *instr_) : instr(instr_) {} 128 129 operator Instruction *() const { 130 return instr; 131 } 132 133 operator Temp() const { 134 return instr->definitions[0].getTemp(); 135 } 136 137 operator Operand() const { 138 return Operand((Temp)*this); 139 } 140 141 Definition& def(unsigned index) const { 142 return instr->definitions[index]; 143 } 144 145 aco_ptr<Instruction> get_ptr() const { 146 return aco_ptr<Instruction>(instr); 147 } 148 }; 149 150 struct Op { 151 Operand op; 152 Op(Temp tmp) : op(tmp) {} 153 Op(Operand op_) : op(op_) {} 154 Op(Result res) : op((Temp)res) {} 155 }; 156 157 enum WaveSpecificOpcode { 158 s_cselect = (unsigned) aco_opcode::s_cselect_b64, 159 s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64, 160 s_and = (unsigned) aco_opcode::s_and_b64, 161 s_andn2 = (unsigned) aco_opcode::s_andn2_b64, 162 s_or = (unsigned) aco_opcode::s_or_b64, 163 s_orn2 = (unsigned) aco_opcode::s_orn2_b64, 164 s_not = (unsigned) aco_opcode::s_not_b64, 165 s_mov = (unsigned) aco_opcode::s_mov_b64, 166 s_wqm = (unsigned) aco_opcode::s_wqm_b64, 167 s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64, 168 s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64, 169 s_xnor = (unsigned) aco_opcode::s_xnor_b64, 170 s_xor = (unsigned) aco_opcode::s_xor_b64, 171 s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64, 172 s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64, 173 s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64, 174 s_flbit_i32 = (unsigned) aco_opcode::s_flbit_i32_b64, 175 s_lshl = (unsigned) aco_opcode::s_lshl_b64, 176 }; 177 178 Program *program; 179 bool use_iterator; 180 bool start; // only when use_iterator == false 181 RegClass lm; 182 183 std::vector<aco_ptr<Instruction>> *instructions; 184 std::vector<aco_ptr<Instruction>>::iterator it; 185 bool is_precise = false; 186 bool is_nuw = false; 187 188 Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(NULL) {} 189 Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {} 190 Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {} 191 192 Builder precise() const { 193 Builder res = *this; 194 res.is_precise = true; 195 return res; 196 }; 197 198 Builder nuw() const { 199 Builder res = *this; 200 res.is_nuw = true; 201 return res; 202 } 203 204 void moveEnd(Block *block) { 205 instructions = &block->instructions; 206 } 207 208 void reset() { 209 use_iterator = false; 210 start = false; 211 instructions = NULL; 212 } 213 214 void reset(Block *block) { 215 use_iterator = false; 216 start = false; 217 instructions = &block->instructions; 218 } 219 220 void reset(std::vector<aco_ptr<Instruction>> *instrs) { 221 use_iterator = false; 222 start = false; 223 instructions = instrs; 224 } 225 226 void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) { 227 use_iterator = true; 228 start = false; 229 instructions = instrs; 230 it = instr_it; 231 } 232 233 Result insert(aco_ptr<Instruction> instr) { 234 Instruction *instr_ptr = instr.get(); 235 if (instructions) { 236 if (use_iterator) { 237 it = instructions->emplace(it, std::move(instr)); 238 it = std::next(it); 239 } else if (!start) { 240 instructions->emplace_back(std::move(instr)); 241 } else { 242 instructions->emplace(instructions->begin(), std::move(instr)); 243 } 244 } 245 return Result(instr_ptr); 246 } 247 248 Result insert(Instruction* instr) { 249 if (instructions) { 250 if (use_iterator) { 251 it = instructions->emplace(it, aco_ptr<Instruction>(instr)); 252 it = std::next(it); 253 } else if (!start) { 254 instructions->emplace_back(aco_ptr<Instruction>(instr)); 255 } else { 256 instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr)); 257 } 258 } 259 return Result(instr); 260 } 261 262 Temp tmp(RegClass rc) { 263 return program->allocateTmp(rc); 264 } 265 266 Temp tmp(RegType type, unsigned size) { 267 return tmp(RegClass(type, size)); 268 } 269 270 Definition def(RegClass rc) { 271 return Definition(program->allocateTmp(rc)); 272 } 273 274 Definition def(RegType type, unsigned size) { 275 return def(RegClass(type, size)); 276 } 277 278 Definition def(RegClass rc, PhysReg reg) { 279 return Definition(program->allocateId(rc), reg, rc); 280 } 281 282 inline aco_opcode w64or32(WaveSpecificOpcode opcode) const { 283 if (program->wave_size == 64) 284 return (aco_opcode) opcode; 285 286 switch (opcode) { 287 case s_cselect: 288 return aco_opcode::s_cselect_b32; 289 case s_cmp_lg: 290 return aco_opcode::s_cmp_lg_u32; 291 case s_and: 292 return aco_opcode::s_and_b32; 293 case s_andn2: 294 return aco_opcode::s_andn2_b32; 295 case s_or: 296 return aco_opcode::s_or_b32; 297 case s_orn2: 298 return aco_opcode::s_orn2_b32; 299 case s_not: 300 return aco_opcode::s_not_b32; 301 case s_mov: 302 return aco_opcode::s_mov_b32; 303 case s_wqm: 304 return aco_opcode::s_wqm_b32; 305 case s_and_saveexec: 306 return aco_opcode::s_and_saveexec_b32; 307 case s_or_saveexec: 308 return aco_opcode::s_or_saveexec_b32; 309 case s_xnor: 310 return aco_opcode::s_xnor_b32; 311 case s_xor: 312 return aco_opcode::s_xor_b32; 313 case s_bcnt1_i32: 314 return aco_opcode::s_bcnt1_i32_b32; 315 case s_bitcmp1: 316 return aco_opcode::s_bitcmp1_b32; 317 case s_ff1_i32: 318 return aco_opcode::s_ff1_i32_b32; 319 case s_flbit_i32: 320 return aco_opcode::s_flbit_i32_b32; 321 case s_lshl: 322 return aco_opcode::s_lshl_b32; 323 default: 324 unreachable("Unsupported wave specific opcode."); 325 } 326 } 327 328% for fixed in ['m0', 'vcc', 'exec', 'scc']: 329 Operand ${fixed}(Temp tmp) { 330 % if fixed == 'vcc' or fixed == 'exec': 331 //vcc_hi and exec_hi can still be used in wave32 332 assert(tmp.type() == RegType::sgpr && tmp.bytes() <= 8); 333 % endif 334 Operand op(tmp); 335 op.setFixed(aco::${fixed}); 336 return op; 337 } 338 339 Definition ${fixed}(Definition def) { 340 % if fixed == 'vcc' or fixed == 'exec': 341 //vcc_hi and exec_hi can still be used in wave32 342 assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8); 343 % endif 344 def.setFixed(aco::${fixed}); 345 return def; 346 } 347 348% endfor 349 350 Operand set16bit(Operand op) { 351 op.set16bit(true); 352 return op; 353 } 354 355 Operand set24bit(Operand op) { 356 op.set24bit(true); 357 return op; 358 } 359 360 /* hand-written helpers */ 361 Temp as_uniform(Op op) 362 { 363 assert(op.op.isTemp()); 364 if (op.op.getTemp().type() == RegType::vgpr) 365 return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op); 366 else 367 return op.op.getTemp(); 368 } 369 370 Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false) 371 { 372 assert(tmp.type() == RegType::vgpr); 373 bool has_lshl_add = program->gfx_level >= GFX9; 374 /* v_mul_lo_u32 has 1.6x the latency of most VALU on GFX10 (8 vs 5 cycles), 375 * compared to 4x the latency on <GFX10. */ 376 unsigned mul_cost = program->gfx_level >= GFX10 ? 1 : (4 + Operand::c32(imm).isLiteral()); 377 if (imm == 0) { 378 return copy(dst, Operand::zero()); 379 } else if (imm == 1) { 380 return copy(dst, Operand(tmp)); 381 } else if (util_is_power_of_two_or_zero(imm)) { 382 return vop2(aco_opcode::v_lshlrev_b32, dst, Operand::c32(ffs(imm) - 1u), tmp); 383 } else if (bits24) { 384 return vop2(aco_opcode::v_mul_u32_u24, dst, Operand::c32(imm), tmp); 385 } else if (util_is_power_of_two_nonzero(imm - 1u)) { 386 return vadd32(dst, vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(ffs(imm - 1u) - 1u), tmp), tmp); 387 } else if (mul_cost > 2 && util_is_power_of_two_nonzero(imm + 1u)) { 388 return vsub32(dst, vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(ffs(imm + 1u) - 1u), tmp), tmp); 389 } 390 391 unsigned instrs_required = util_bitcount(imm); 392 if (!has_lshl_add) { 393 instrs_required = util_bitcount(imm) - (imm & 0x1); /* shifts */ 394 instrs_required += util_bitcount(imm) - 1; /* additions */ 395 } 396 if (instrs_required < mul_cost) { 397 Result res(NULL); 398 Temp cur; 399 while (imm) { 400 unsigned shift = u_bit_scan(&imm); 401 Definition tmp_dst = imm ? def(v1) : dst; 402 403 if (shift && cur.id()) 404 res = vadd32(Definition(tmp_dst), vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(shift), tmp), cur); 405 else if (shift) 406 res = vop2(aco_opcode::v_lshlrev_b32, Definition(tmp_dst), Operand::c32(shift), tmp); 407 else if (cur.id()) 408 res = vadd32(Definition(tmp_dst), tmp, cur); 409 else 410 tmp_dst = Definition(tmp); 411 412 cur = tmp_dst.getTemp(); 413 } 414 return res; 415 } 416 417 Temp imm_tmp = copy(def(s1), Operand::c32(imm)); 418 return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp); 419 } 420 421 Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm) 422 { 423 return v_mul_imm(dst, tmp, imm, true); 424 } 425 426 Result copy(Definition dst, Op op) { 427 return pseudo(aco_opcode::p_parallelcopy, dst, op); 428 } 429 430 Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) { 431 if (b.op.isConstant() || b.op.regClass().type() != RegType::vgpr) 432 std::swap(a, b); 433 if (!post_ra && (!b.op.hasRegClass() || b.op.regClass().type() == RegType::sgpr)) 434 b = copy(def(v1), b); 435 436 if (!carry_in.op.isUndefined()) 437 return vop2(aco_opcode::v_addc_co_u32, Definition(dst), def(lm), a, b, carry_in); 438 else if (program->gfx_level >= GFX10 && carry_out) 439 return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b); 440 else if (program->gfx_level < GFX9 || carry_out) 441 return vop2(aco_opcode::v_add_co_u32, Definition(dst), def(lm), a, b); 442 else 443 return vop2(aco_opcode::v_add_u32, Definition(dst), a, b); 444 } 445 446 Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2))) 447 { 448 if (!borrow.op.isUndefined() || program->gfx_level < GFX9) 449 carry_out = true; 450 451 bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr; 452 if (reverse) 453 std::swap(a, b); 454 if (!b.op.hasRegClass() || b.op.regClass().type() == RegType::sgpr) 455 b = copy(def(v1), b); 456 457 aco_opcode op; 458 Temp carry; 459 if (carry_out) { 460 carry = tmp(s2); 461 if (borrow.op.isUndefined()) 462 op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32; 463 else 464 op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32; 465 } else { 466 op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32; 467 } 468 bool vop3 = false; 469 if (program->gfx_level >= GFX10 && op == aco_opcode::v_subrev_co_u32) { 470 vop3 = true; 471 op = aco_opcode::v_subrev_co_u32_e64; 472 } else if (program->gfx_level >= GFX10 && op == aco_opcode::v_sub_co_u32) { 473 vop3 = true; 474 op = aco_opcode::v_sub_co_u32_e64; 475 } 476 477 int num_ops = borrow.op.isUndefined() ? 2 : 3; 478 int num_defs = carry_out ? 2 : 1; 479 aco_ptr<Instruction> sub; 480 if (vop3) 481 sub.reset(create_instruction<VOP3_instruction>(op, Format::VOP3, num_ops, num_defs)); 482 else 483 sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs)); 484 sub->operands[0] = a.op; 485 sub->operands[1] = b.op; 486 if (!borrow.op.isUndefined()) 487 sub->operands[2] = borrow.op; 488 sub->definitions[0] = dst; 489 if (carry_out) 490 sub->definitions[1] = Definition(carry); 491 492 return insert(std::move(sub)); 493 } 494 495 Result readlane(Definition dst, Op vsrc, Op lane) 496 { 497 if (program->gfx_level >= GFX8) 498 return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane); 499 else 500 return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane); 501 } 502 Result writelane(Definition dst, Op val, Op lane, Op vsrc) { 503 if (program->gfx_level >= GFX8) 504 return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc); 505 else 506 return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc); 507 } 508<% 509import itertools 510formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(6))) + [(8, 1), (1, 8)]), 511 ("sop1", [Format.SOP1], 'SOP1_instruction', [(0, 1), (1, 0), (1, 1), (2, 1), (3, 2)]), 512 ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])), 513 ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])), 514 ("sopp", [Format.SOPP], 'SOPP_instruction', itertools.product([0, 1], [0, 1])), 515 ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]), 516 ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]), 517 ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]), 518 ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]), 519 ("mtbuf", [Format.MTBUF], 'MTBUF_instruction', [(0, 4), (1, 3)]), 520 ("mimg", [Format.MIMG], 'MIMG_instruction', itertools.product([0, 1], [3, 4, 5, 6, 7])), 521 ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]), 522 ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([1], [0, 1])), 523 ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]), 524 ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]), 525 ("vop1", [Format.VOP1], 'VOP1_instruction', [(0, 0), (1, 1), (2, 2)]), 526 ("vop1_sdwa", [Format.VOP1, Format.SDWA], 'SDWA_instruction', [(1, 1)]), 527 ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])), 528 ("vop2_sdwa", [Format.VOP2, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2, 3])), 529 ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])), 530 ("vopc_sdwa", [Format.VOPC, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2])), 531 ("vop3", [Format.VOP3], 'VOP3_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]), 532 ("vop3p", [Format.VOP3P], 'VOP3P_instruction', [(1, 2), (1, 3)]), 533 ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]), 534 ("vop1_dpp", [Format.VOP1, Format.DPP16], 'DPP16_instruction', [(1, 1)]), 535 ("vop2_dpp", [Format.VOP2, Format.DPP16], 'DPP16_instruction', itertools.product([1, 2], [2, 3])), 536 ("vopc_dpp", [Format.VOPC, Format.DPP16], 'DPP16_instruction', itertools.product([1, 2], [2])), 537 ("vop1_dpp8", [Format.VOP1, Format.DPP8], 'DPP8_instruction', [(1, 1)]), 538 ("vop2_dpp8", [Format.VOP2, Format.DPP8], 'DPP8_instruction', itertools.product([1, 2], [2, 3])), 539 ("vopc_dpp8", [Format.VOPC, Format.DPP8], 'DPP8_instruction', itertools.product([1, 2], [2])), 540 ("vop1_e64", [Format.VOP1, Format.VOP3], 'VOP3_instruction', itertools.product([1], [1])), 541 ("vop2_e64", [Format.VOP2, Format.VOP3], 'VOP3_instruction', itertools.product([1, 2], [2, 3])), 542 ("vopc_e64", [Format.VOPC, Format.VOP3], 'VOP3_instruction', itertools.product([1, 2], [2])), 543 ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]), 544 ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)]), 545 ("scratch", [Format.SCRATCH], 'FLAT_instruction', [(0, 3), (1, 2)])] 546formats = [(f if len(f) == 5 else f + ('',)) for f in formats] 547%>\\ 548% for name, formats, struct, shapes, extra_field_setup in formats: 549 % for num_definitions, num_operands in shapes: 550 <% 551 args = ['aco_opcode opcode'] 552 for i in range(num_definitions): 553 args.append('Definition def%d' % i) 554 for i in range(num_operands): 555 args.append('Op op%d' % i) 556 for f in formats: 557 args += f.get_builder_field_decls() 558 %>\\ 559 560 Result ${name}(${', '.join(args)}) 561 { 562 ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions}); 563 % for i in range(num_definitions): 564 instr->definitions[${i}] = def${i}; 565 instr->definitions[${i}].setPrecise(is_precise); 566 instr->definitions[${i}].setNUW(is_nuw); 567 % endfor 568 % for i in range(num_operands): 569 instr->operands[${i}] = op${i}.op; 570 % endfor 571 % for f in formats: 572 % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()): 573 instr->${dest} = ${field_name}; 574 % endfor 575 ${f.get_builder_initialization(num_operands)} 576 % endfor 577 ${extra_field_setup} 578 return insert(instr); 579 } 580 581 % if name == 'sop1' or name == 'sop2' or name == 'sopc': 582 <% 583 args[0] = 'WaveSpecificOpcode opcode' 584 params = [] 585 for i in range(num_definitions): 586 params.append('def%d' % i) 587 for i in range(num_operands): 588 params.append('op%d' % i) 589 %>\\ 590 591 inline Result ${name}(${', '.join(args)}) 592 { 593 return ${name}(w64or32(opcode), ${', '.join(params)}); 594 } 595 596 % endif 597 % endfor 598% endfor 599}; 600 601} // namespace aco 602 603#endif /* _ACO_BUILDER_ */""" 604 605from aco_opcodes import opcodes, Format 606from mako.template import Template 607 608print(Template(template).render(opcodes=opcodes, Format=Format)) 609