1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8the rights to use, copy, modify, merge, publish, distribute, sublicense, 9and/or sell copies of the Software, and to permit persons to whom the 10Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22SOFTWARE. 23 --> 24 25<isa> 26 27<!-- 28 Cat4 Instructions: SFU (aka EFU) instructions 29 --> 30 31<bitset name="#instruction-cat4" extends="#instruction"> 32 <display> 33 {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC} 34 </display> 35 <field name="SRC" low="0" high="15" type="#multisrc"> 36 <param name="SRC_R"/> 37 <param name="FULL"/> 38 </field> 39 <pattern low="16" high="31">xxxxxxxxxxxxxxxx</pattern> 40 <field name="DST" low="32" high="39" type="#reg-gpr"/> 41 <field name="REPEAT" low="40" high="41" type="#rptN"/> 42 <field name="SAT" pos="42" type="bool" display="(sat)"/> 43 <field name="SRC_R" pos="43" type="bool" display="(r)"/> 44 <field name="SS" pos="44" type="bool" display="(ss)"/> 45 <field name="UL" pos="45" type="bool" display="(ul)"/> 46 <field name="DST_CONV" pos="46" type="bool"> 47 <doc> 48 Destination register is opposite precision as source, ie. 49 if {FULL} is true then destination is half precision, and 50 visa versa. 51 </doc> 52 </field> 53 <derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/> 54 <pattern low="47" high="51">xxxxx</pattern> 55 <field name="FULL" pos="52" type="bool"> 56 <doc>Full precision source registers</doc> 57 </field> 58 <!-- 6b opc --> 59 <field name="JP" pos="59" type="bool" display="(jp)"/> 60 <field name="SY" pos="60" type="bool" display="(sy)"/> 61 <pattern low="61" high="63">100</pattern> <!-- cat4 --> 62 <encode> 63 <map name="SRC">src->srcs[0]</map> 64 <map name="DST_CONV"> 65 ((src->dsts[0]->num >> 2) == 62) ? 0 : 66 !!((src->srcs[0]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) 67 </map> 68 <map name="FULL">!(src->srcs[0]->flags & IR3_REG_HALF)</map> 69 <map name="SRC_R">!!(src->srcs[0]->flags & IR3_REG_R)</map> 70 </encode> 71</bitset> 72 73<bitset name="rcp" extends="#instruction-cat4"> 74 <pattern low="53" high="58">000000</pattern> <!-- OPC --> 75</bitset> 76 77<bitset name="rsq" extends="#instruction-cat4"> 78 <pattern low="53" high="58">000001</pattern> <!-- OPC --> 79</bitset> 80 81<bitset name="log2" extends="#instruction-cat4"> 82 <pattern low="53" high="58">000010</pattern> <!-- OPC --> 83</bitset> 84 85<bitset name="exp2" extends="#instruction-cat4"> 86 <pattern low="53" high="58">000011</pattern> <!-- OPC --> 87</bitset> 88 89<bitset name="sin" extends="#instruction-cat4"> 90 <pattern low="53" high="58">000100</pattern> <!-- OPC --> 91</bitset> 92 93<bitset name="cos" extends="#instruction-cat4"> 94 <pattern low="53" high="58">000101</pattern> <!-- OPC --> 95</bitset> 96 97<bitset name="sqrt" extends="#instruction-cat4"> 98 <pattern low="53" high="58">000110</pattern> <!-- OPC --> 99</bitset> 100 101<!-- 102 NOTE that these are 8+opc from their highp equivs, so it's possible 103 that the high order bit in the opc field has been repurposed for 104 half-precision use? But note that other ops (rcp/lsin/cos/sqrt) 105 still use the same opc as highp 106 --> 107 108<bitset name="hrsq" extends="#instruction-cat4"> 109 <pattern low="53" high="58">001001</pattern> <!-- OPC --> 110</bitset> 111 112<bitset name="hlog2" extends="#instruction-cat4"> 113 <pattern low="53" high="58">001010</pattern> <!-- OPC --> 114</bitset> 115 116<bitset name="hexp2" extends="#instruction-cat4"> 117 <pattern low="53" high="58">001011</pattern> <!-- OPC --> 118</bitset> 119 120</isa> 121