1 /* 2 * Copyright (c) 2017-2020 ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 /* 20 * CMSIS-Core(A) Interrupt Controller API Header File 21 */ 22 23 #ifndef IRQ_CTRL_H_ 24 #define IRQ_CTRL_H_ 25 26 #if defined ( __ICCARM__ ) 27 #pragma system_include /* treat file as system include file for MISRA check */ 28 #elif defined (__clang__) 29 #pragma clang system_header /* treat file as system include file */ 30 #endif 31 32 #include <stdint.h> 33 34 #ifndef IRQHANDLER_T 35 #define IRQHANDLER_T 36 /// Interrupt handler data type 37 typedef void (*IRQHandler_t) (void); 38 #endif 39 40 #ifndef IRQN_ID_T 41 #define IRQN_ID_T 42 /// Interrupt ID number data type 43 typedef int32_t IRQn_ID_t; 44 #endif 45 46 /* Interrupt mode bit-masks */ 47 #define IRQ_MODE_TRIG_Pos (0U) 48 #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) 49 #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt 50 #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt 51 #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt 52 #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt 53 #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt 54 #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt 55 #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt 56 57 #define IRQ_MODE_TYPE_Pos (3U) 58 #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) 59 #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line 60 #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line 61 62 #define IRQ_MODE_DOMAIN_Pos (4U) 63 #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) 64 #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain 65 #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain 66 67 #define IRQ_MODE_CPU_Pos (5U) 68 #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) 69 #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs 70 #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 71 #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 72 #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 73 #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 74 #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 75 #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 76 #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 77 #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 78 79 // Encoding in some early GIC implementations 80 #define IRQ_MODE_MODEL_Pos (13U) 81 #define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) 82 #define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model 83 #define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model 84 85 #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error 86 87 /* Interrupt priority bit-masks */ 88 #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask 89 #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error 90 91 /// Initialize interrupt controller. 92 /// \return 0 on success, -1 on error. 93 int32_t IRQ_Initialize (void); 94 95 /// Register interrupt handler. 96 /// \param[in] irqn interrupt ID number 97 /// \param[in] handler interrupt handler function address 98 /// \return 0 on success, -1 on error. 99 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); 100 101 /// Get the registered interrupt handler. 102 /// \param[in] irqn interrupt ID number 103 /// \return registered interrupt handler function address. 104 IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); 105 106 /// Enable interrupt. 107 /// \param[in] irqn interrupt ID number 108 /// \return 0 on success, -1 on error. 109 int32_t IRQ_Enable (IRQn_ID_t irqn); 110 111 /// Disable interrupt. 112 /// \param[in] irqn interrupt ID number 113 /// \return 0 on success, -1 on error. 114 int32_t IRQ_Disable (IRQn_ID_t irqn); 115 116 /// Get interrupt enable state. 117 /// \param[in] irqn interrupt ID number 118 /// \return 0 - interrupt is disabled, 1 - interrupt is enabled. 119 uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); 120 121 /// Configure interrupt request mode. 122 /// \param[in] irqn interrupt ID number 123 /// \param[in] mode mode configuration 124 /// \return 0 on success, -1 on error. 125 int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); 126 127 /// Get interrupt mode configuration. 128 /// \param[in] irqn interrupt ID number 129 /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. 130 uint32_t IRQ_GetMode (IRQn_ID_t irqn); 131 132 /// Get ID number of current interrupt request (IRQ). 133 /// \return interrupt ID number. 134 IRQn_ID_t IRQ_GetActiveIRQ (void); 135 136 /// Get ID number of current fast interrupt request (FIQ). 137 /// \return interrupt ID number. 138 IRQn_ID_t IRQ_GetActiveFIQ (void); 139 140 /// Signal end of interrupt processing. 141 /// \param[in] irqn interrupt ID number 142 /// \return 0 on success, -1 on error. 143 int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); 144 145 /// Set interrupt pending flag. 146 /// \param[in] irqn interrupt ID number 147 /// \return 0 on success, -1 on error. 148 int32_t IRQ_SetPending (IRQn_ID_t irqn); 149 150 /// Get interrupt pending flag. 151 /// \param[in] irqn interrupt ID number 152 /// \return 0 - interrupt is not pending, 1 - interrupt is pending. 153 uint32_t IRQ_GetPending (IRQn_ID_t irqn); 154 155 /// Clear interrupt pending flag. 156 /// \param[in] irqn interrupt ID number 157 /// \return 0 on success, -1 on error. 158 int32_t IRQ_ClearPending (IRQn_ID_t irqn); 159 160 /// Set interrupt priority value. 161 /// \param[in] irqn interrupt ID number 162 /// \param[in] priority interrupt priority value 163 /// \return 0 on success, -1 on error. 164 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); 165 166 /// Get interrupt priority. 167 /// \param[in] irqn interrupt ID number 168 /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. 169 uint32_t IRQ_GetPriority (IRQn_ID_t irqn); 170 171 /// Set priority masking threshold. 172 /// \param[in] priority priority masking threshold value 173 /// \return 0 on success, -1 on error. 174 int32_t IRQ_SetPriorityMask (uint32_t priority); 175 176 /// Get priority masking threshold 177 /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. 178 uint32_t IRQ_GetPriorityMask (void); 179 180 /// Set priority grouping field split point 181 /// \param[in] bits number of MSB bits included in the group priority field comparison 182 /// \return 0 on success, -1 on error. 183 int32_t IRQ_SetPriorityGroupBits (uint32_t bits); 184 185 /// Get priority grouping field split point 186 /// \return current number of MSB bits included in the group priority field comparison with 187 /// optional IRQ_PRIORITY_ERROR bit set. 188 uint32_t IRQ_GetPriorityGroupBits (void); 189 190 #endif // IRQ_CTRL_H_ 191