| /kernel/linux/linux-5.10/drivers/staging/kpc2000/kpc_dma/ |
| D | kpc_dma_driver.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #include <linux/dma-mapping.h>
70 #define ENG_CTL_IRQ_ACTIVE BIT(1)
98 #define ACD_FLAG_ABORT 1
129 #define DMA_DESC_CTL_IRQONERR BIT(1)
137 #define DMA_DESC_STS_SHORT BIT(1)
141 #define DMA_DESC_ESTS_POISON BIT(1)
147 u32 GetEngineCapabilities(struct kpc_dma_device *eng) in GetEngineCapabilities() argument
149 return readl(eng->eng_regs + 0); in GetEngineCapabilities()
153 void WriteEngineControl(struct kpc_dma_device *eng, u32 value) in WriteEngineControl() argument
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| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0+
19 …if ((GetEngineControl(ldev) & ENG_CTL_IRQ_ACTIVE) || (ldev->desc_completed->MyDMAAddr != GetEngine… in ndd_irq_handler()
20 schedule_work(&ldev->irq_work); in ndd_irq_handler()
29 struct kpc_dma_device *eng = container_of(ws, struct kpc_dma_device, irq_work); in ndd_irq_worker() local
31 lock_engine(eng); in ndd_irq_worker()
33 if (GetEngineCompletePtr(eng) == 0) in ndd_irq_worker()
36 if (eng->desc_completed->MyDMAAddr == GetEngineCompletePtr(eng)) in ndd_irq_worker()
39 cur = eng->desc_completed; in ndd_irq_worker()
41 cur = cur->Next; in ndd_irq_worker()
42 dev_dbg(&eng->pldev->dev, "Handling completed descriptor %p (acd = %p)\n", cur, cur->acd); in ndd_irq_worker()
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| D | fileops.c | 1 // SPDX-License-Identifier: GPL-2.0+
22 unsigned long last = ((iov_base + iov_len - 1) & PAGE_MASK) >> PAGE_SHIFT; in count_pages()
24 return last - first + 1; in count_pages()
52 ldev = priv->ldev; in kpc_dma_transfer()
56 dev_err(&priv->ldev->pldev->dev, "Couldn't kmalloc space for the aio data\n"); in kpc_dma_transfer()
57 return -ENOMEM; in kpc_dma_transfer()
61 acd->priv = priv; in kpc_dma_transfer()
62 acd->ldev = priv->ldev; in kpc_dma_transfer()
63 acd->cpl = &done; in kpc_dma_transfer()
64 acd->flags = 0; in kpc_dma_transfer()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | chang84.c | 39 *pevent = &chan->fifo->uevent; in g84_fifo_chan_ntfy()
44 return -EINVAL; in g84_fifo_chan_ntfy()
50 switch (engine->subdev.index) { in g84_fifo_chan_engine()
53 case NVKM_ENGINE_MSPPP : return 1; in g84_fifo_chan_engine()
62 WARN_ON(1); in g84_fifo_chan_engine()
70 switch (engine->subdev.index) { in g84_fifo_chan_engine_addr()
72 case NVKM_ENGINE_SW : return -1; in g84_fifo_chan_engine_addr()
84 WARN_ON(1); in g84_fifo_chan_engine_addr()
85 return -1; in g84_fifo_chan_engine_addr()
94 struct nv50_fifo *fifo = chan->fifo; in g84_fifo_chan_engine_fini()
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| D | channv50.c | 34 switch (engine->subdev.index) { in nv50_fifo_chan_engine_addr()
36 case NVKM_ENGINE_SW : return -1; in nv50_fifo_chan_engine_addr()
40 WARN_ON(1); in nv50_fifo_chan_engine_addr()
41 return -1; in nv50_fifo_chan_engine_addr()
50 struct nv50_fifo *fifo = chan->fifo; in nv50_fifo_chan_engine_fini()
51 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; in nv50_fifo_chan_engine_fini()
52 struct nvkm_device *device = subdev->device; in nv50_fifo_chan_engine_fini()
75 nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); in nv50_fifo_chan_engine_fini()
81 chan->base.chid, chan->base.object.client->name); in nv50_fifo_chan_engine_fini()
83 ret = -EBUSY; in nv50_fifo_chan_engine_fini()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | g84.c | 37 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in g84_chan_bind()
39 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 8); in g84_chan_bind()
45 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in g84_chan_ramfc_write()
49 ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->inst, &chan->eng); in g84_chan_ramfc_write()
53 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->inst, &chan->pgd); in g84_chan_ramfc_write()
57 ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->inst, &chan->cache); in g84_chan_ramfc_write()
61 ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->inst, &chan->ramfc); in g84_chan_ramfc_write()
65 ret = nvkm_ramht_new(device, 0x8000, 16, chan->inst, &chan->ramht); in g84_chan_ramfc_write()
69 nvkm_kmap(chan->ramfc); in g84_chan_ramfc_write()
70 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_chan_ramfc_write()
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| D | nv50.c | 38 nvkm_ramht_remove(chan->ramht, hash); in nv50_eobj_ramht_del()
44 return nvkm_ramht_insert(chan->ramht, eobj, 0, 4, eobj->handle, engn->id << 20); in nv50_eobj_ramht_add()
50 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_stop()
52 nvkm_mask(device, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000); in nv50_chan_stop()
58 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_start()
60 nvkm_mask(device, 0x002600 + (chan->id * 4), 0x80000000, 0x80000000); in nv50_chan_start()
66 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_unbind()
68 nvkm_wr32(device, 0x002600 + (chan->id * 4), 0x00000000); in nv50_chan_unbind()
74 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_bind()
76 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 12); in nv50_chan_bind()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk104.c | 43 struct gk104_clk_info eng[16]; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
77 sclk = device->crystal; in read_pll()
78 P = 1; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
99 P = 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
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| D | gf100.c | 43 struct gf100_clk_info eng[16]; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
76 P = 1; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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| D | gt215.c | 36 struct gt215_clk_info eng[nv_clk_src_max]; member
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll()
122 /* no post-divider on these.. in read_pll()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk104.c | 43 struct gk104_clk_info eng[16]; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
77 sclk = device->crystal; in read_pll()
78 P = 1; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
99 P = 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
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| D | gf100.c | 43 struct gf100_clk_info eng[16]; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
76 P = 1; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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| D | gt215.c | 36 struct gt215_clk_info eng[nv_clk_src_max]; member
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll()
122 /* no post-divider on these.. in read_pll()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gmc_v10_0.c | 96 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
100 addr = (u64)entry->src_data[0] << 12; in gmc_v10_0_process_interrupt()
101 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v10_0_process_interrupt()
109 if (entry->vmid_src == AMDGPU_GFXHUB_0) in gmc_v10_0_process_interrupt()
110 RREG32(hub->vm_l2_pro_fault_status); in gmc_v10_0_process_interrupt()
112 status = RREG32(hub->vm_l2_pro_fault_status); in gmc_v10_0_process_interrupt()
113 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); in gmc_v10_0_process_interrupt()
120 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v10_0_process_interrupt()
122 dev_err(adev->dev, in gmc_v10_0_process_interrupt()
125 entry->vmid_src ? "mmhub" : "gfxhub", in gmc_v10_0_process_interrupt()
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| /kernel/linux/linux-6.6/drivers/mtd/nand/ |
| D | ecc-mxic.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
33 #define SDMA_MAIN BIT(1)
68 #define READ_NAND BIT(1)
114 static struct mxic_ecc_engine *ext_ecc_eng_to_mxic(struct nand_ecc_engine *eng) in ext_ecc_eng_to_mxic() argument
116 return container_of(eng, struct mxic_ecc_engine, external_engine); in ext_ecc_eng_to_mxic()
119 static struct mxic_ecc_engine *pip_ecc_eng_to_mxic(struct nand_ecc_engine *eng) in pip_ecc_eng_to_mxic() argument
121 return container_of(eng, struct mxic_ecc_engine, pipelined_engine); in pip_ecc_eng_to_mxic()
126 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_mxic() local
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | gmc_v11_0.c | 74 if (!adev->in_s0ix) in gmc_v11_0_vm_fault_interrupt_state()
86 if (!adev->in_s0ix) in gmc_v11_0_vm_fault_interrupt_state()
100 uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ? in gmc_v11_0_process_interrupt()
102 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; in gmc_v11_0_process_interrupt()
106 addr = (u64)entry->src_data[0] << 12; in gmc_v11_0_process_interrupt()
107 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v11_0_process_interrupt()
115 if (entry->vmid_src == AMDGPU_GFXHUB(0)) in gmc_v11_0_process_interrupt()
116 RREG32(hub->vm_l2_pro_fault_status); in gmc_v11_0_process_interrupt()
118 status = RREG32(hub->vm_l2_pro_fault_status); in gmc_v11_0_process_interrupt()
119 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); in gmc_v11_0_process_interrupt()
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| D | gmc_v10_0.c | 79 if (!adev->in_s0ix) in gmc_v10_0_vm_fault_interrupt_state()
91 if (!adev->in_s0ix) in gmc_v10_0_vm_fault_interrupt_state()
105 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? in gmc_v10_0_process_interrupt()
107 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; in gmc_v10_0_process_interrupt()
108 bool retry_fault = !!(entry->src_data[1] & 0x80); in gmc_v10_0_process_interrupt()
109 bool write_fault = !!(entry->src_data[1] & 0x20); in gmc_v10_0_process_interrupt()
114 addr = (u64)entry->src_data[0] << 12; in gmc_v10_0_process_interrupt()
115 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v10_0_process_interrupt()
118 /* Returning 1 here also prevents sending the IV to the KFD */ in gmc_v10_0_process_interrupt()
121 if (entry->ih != &adev->irq.ih_soft && in gmc_v10_0_process_interrupt()
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| /kernel/linux/linux-5.10/include/linux/ |
| D | via-core.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
112 #define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
113 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
114 #define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */
118 #define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */
119 #define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */
120 #define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */
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| /kernel/linux/linux-6.6/include/linux/ |
| D | via-core.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
112 #define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
113 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
114 #define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */
118 #define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */
119 #define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */
120 #define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-mxic.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/mtd/nand-ecc-mxic.h>
20 #include <linux/spi/spi-mem.h>
29 #define HC_CFG_TYPE_SPI_NAND 1
40 #define HC_CFG_MAN_CS_EN BIT(1)
58 #define INT_TX_NOT_FULL BIT(1)
74 #define OP_CMD_BYTES(x) (((x) - 1) << 13)
86 #define OP_BUSW_2 1
92 #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
117 #define DMAC_CFG_QE(x) (((x) + 1) << 16)
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | sti-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Match running platform with pre-defined OPP values for CPUFreq
24 #define HW_INFO_INDEX 1
25 #define MAJOR_ID_INDEX 1
43 * struct sti_cpufreq_ddata - ST CPUFreq Driver Data
56 struct device_node *np = ddata.cpu->of_node; in sti_cpufreq_fetch_major()
77 return ((socid >> VERSION_SHIFT) & 0xf) + 1; in sti_cpufreq_fetch_major()
83 struct device_node *np = dev->of_node; in sti_cpufreq_fetch_minor()
88 ret = of_property_read_u32_index(np, "st,syscfg-eng", in sti_cpufreq_fetch_minor()
154 struct device_node *np = dev->of_node; in sti_cpufreq_set_opp_info()
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| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| D | sti-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Match running platform with pre-defined OPP values for CPUFreq
24 #define HW_INFO_INDEX 1
25 #define MAJOR_ID_INDEX 1
43 * struct sti_cpufreq_ddata - ST CPUFreq Driver Data
56 struct device_node *np = ddata.cpu->of_node; in sti_cpufreq_fetch_major()
77 return ((socid >> VERSION_SHIFT) & 0xf) + 1; in sti_cpufreq_fetch_major()
83 struct device_node *np = dev->of_node; in sti_cpufreq_fetch_minor()
88 ret = of_property_read_u32_index(np, "st,syscfg-eng", in sti_cpufreq_fetch_minor()
154 struct device_node *np = dev->of_node; in sti_cpufreq_set_opp_info()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_capture.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2022 Intel Corporation
27 * NOTE: For engine-registers, GuC only needs the register offsets
28 * from the engine-mmio-base
76 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \
77 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \
95 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \
106 /* XE_LP Render / Compute Per-Class */
113 /* GEN8+ Render / Compute Per-Engine-Instance */
118 /* GEN8+ Media Decode/Encode Per-Engine-Instance */
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| /kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/af/ |
| D | rvu_cpt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #define CPT_CTX_ILEN 1ULL
31 busy_sts |= 1ULL << i; \
34 free_sts |= 1ULL << i; \
36 (_rsp)->busy_sts_##etype = busy_sts; \
37 (_rsp)->free_sts_##etype = free_sts; \
43 struct rvu *rvu = block->rvu; in cpt_af_flt_intr_handler()
44 int blkaddr = block->addr; in cpt_af_flt_intr_handler()
46 int i, eng; in cpt_af_flt_intr_handler() local
50 dev_err_ratelimited(rvu->dev, "Received CPTAF FLT%d irq : 0x%llx", vec, reg); in cpt_af_flt_intr_handler()
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| /kernel/linux/linux-6.6/drivers/infiniband/hw/hfi1/ |
| D | sdma.h | 1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
3 * Copyright(c) 2015 - 2018 Intel Corporation.
22 #define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1)
25 #define SDMA_MAP_SINGLE 1
48 #define SDMA_AHG_COPY 1
61 ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1)
67 ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1)
74 ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1)
80 ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1)
86 ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1)
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