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/arkcompiler/runtime_core/docs/changelogs/
D2022-08-18-isa-changelog.md1 # 2022-08-18-isa-changelog
15 3. We add prefix "deprecated" and keep the many old isa as "deprecated"-prefixed opcodes (for compa…
20 8. We add 8-bit or 16-bit imm as inline cache slot for some specific opcodes.
23 As we merge some "define-function" opcodes as one opcode, in function we add one field which record…
24 such that runtime can distinguish the "define-function" operations of different kinds.
26 We reuse the field 32-bit field `access_flags_` to encode Function Kind and Header index.
27 This will not introduce compatibility issue because the later 24-bit of `access_flags_` is unused i…
30 |<- 16-bit header index ->|<- 8-bit function kind ->|<- 8-bit original access flag ->|
39 As we use 16-bit to encode methodId, stringId and literalarrayId, the number of these Ids in one me…
45 3. In bytecode, we still use 16-bit literalarrayId rather than offset.
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/arkcompiler/runtime_core/static_core/plugins/ets/templates/stdlib/
DDataView.sts.j22 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
47 this(buffer, byteOffset, (buffer as Buffer).getByteLength() - byteOffset)
79 {%- for bit in [8, 16, 32, 64] %}
80 {%- for mode in ["Int", "Uint", "Float"] %}
81 {%- if mode != "Float" or bit >= 32 %}
82 // === {{mode}}{{bit}} ===
83 {%- set impls = ['Little', 'Big'] if bit != 8 else ['Big'] %}
85 {%- set type2nameBits = {8: "byte", 16: "short", 32: "int", 64: "long"} %}
86 {%- set type2nameCompat = {8: "number", 16: "number", 32: "number", 64: "bigint"} %}
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/arkcompiler/ets_runtime/ecmascript/
Djs_tagged_value_internals.h7 * http://www.apache.org/licenses/LICENSE-2.0
25 // Every double with all of its exponent bits set and its highest mantissa bit set is a quiet NaN.
27 // “QNaN Floating-Point Indefinite” value, leaving us 50 bits. Those remaining bits can be anythin…
28 // so we use a special quietNaN as TaggedInt tag(highest 16bits as 0xFFFF), and need to encode dou…
29 // to the value will begin with a 16-bit pattern within the range 0x0001..0xFFFE.
31 // Nan-boxing pointer is used and the first four bytes are used as tag:
32 // Object: [0x0000] [48 bit direct pointer]
34 // / [0x0001] [48 bit any value]
36 // \ [0xFFFE] [48 bit any value]
37 // TaggedInt: [0xFFFF] [0x0000] [32 bit signed integer]
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/
Dx64_int_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
17 * Registers in x86-64
19 * - caller-save registers: %rax, %rcx, %rdx, %rdi, %rsi, %rsp, and %r8-r11
20 * - callee-saved registers: %r12, %r13, %r14, %r15, %rbx, %rsp, %rbp.
21 * - In contrast to the Intel386 ABI, %rdi, and %rsi in x86-64 belong to the called function, not
22 * the caller. So, It's caller-save registers
23 …* - User-level applications use as integer registers for passing the sequence %rdi, %rsi, %rdx, %r…
25 * - the sequence %rax, %rdx is used to return INTEGER,
26 * - rdx is used to pass 3rd argument to functions; 2nd return register
27 * - %r11 is neither required to be preserved, nor is it used to pass arguments
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Dx64_fp_simd_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
17 * - %xmm0–%xmm1 used to pass and return floating point arguments
18 - %xmm2–%xmm7 used to pass floating point arguments
23 …* ID, prefixes: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, canBeAssigned, isCalleeSave, isParam, isSp…
/arkcompiler/runtime_core/static_core/plugins/ets/tests/checked/
Dets_static_lookup_16bit.pa6 # http://www.apache.org/licenses/LICENSE-2.0
14 #! CHECKER Static lookup for 16-bit StObjByName JIT
15 #! RUN force_jit: true, options: "--compiler-regex='.*test_store.*'", entry: "_GLOBAL::tes…
24 #! CHECKER Static lookup for 16-bit StObjByName AOT
26 #! RUN_PAOC options: "--compiler-regex='.*test_store.*'"
36 #! CHECKER Static lookup for 16-bit LdObjByName JIT
37 #! RUN force_jit: true, options: "--compiler-regex='.*test_load.*'", entry: "_GLOBAL::test…
46 #! CHECKER Static lookup for 16-bit LdObjByName AOT
48 #! RUN_PAOC options: "--compiler-regex='.*test_load.*'"
89 ldai -1
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/arkcompiler/runtime_core/static_core/runtime/bridge/arch/x86/
Dinterpreter_to_compiled_code_bridge_x86.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
27 cmpl $(SHORTY_NUM_64BIT_TYPES - 1), %ecx
30 // it is a 32bit value
36 // it is a 64bit value
55 addl $16, \stack_ptr
62 // %eax - SHORTY_PTR_REG
63 // %edx - SHORTY_REG
64 // %ecx - shorty value (no initialization needed)
65 // %ebx - method
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Dcompiled_code_to_interpreter_bridge_x86.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
32 // %esp % 16 == 12 here (-4 == 12 (mod 16))
62 // %esp % 16 == 8 here
65 leal -8(%ebp), %ecx // prev*
69 // %esp should be 16-byte aligned here
76 …// %eax - SHORTY_PTR_REG, %edx - SHORTY_REG, %ecx - shorty value, %edi - iframe.vregs_ + num_vregs…
77 // %esi - args, (%esp) - iframe*
116 cmpl $(SHORTY_NUM_64BIT_TYPES - 1), %ecx
119 // it is a 32bit value or reference
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/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
39 - equal_common_types
40 - float_src_eq_dst_size
41 - integer_src_ge_dst_size
43 - equal_common_types
44 - integer_src_ge_dst_size
46 - equal_common_types
47 - integer_src_ge_dst_size
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/arkcompiler/ets_runtime/ecmascript/snapshot/mem/
Dencode_bit.h7 * http://www.apache.org/licenses/LICENSE-2.0
29 * 16bit 8bit 1bit 1bit 1bit 8bit 1bit 18bit 10bit
44 // encode bit
52 static constexpr int UNUSED_BIT_NUMBER = 8; // unused bit number
53 static constexpr int IS_REFERENCE_BIT_NUMBER = 16; // [0x0000] is reference
/arkcompiler/runtime_core/bytecode_optimizer/
Dtagged_value.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
27 // Every double with all of its exponent bits set and its highest mantissa bit set is a quiet NaN.
29 // “QNaN Floating-Point Indefinite” value, leaving us 50 bits. Those remaining bits can be anythin…
30 // so we use a special quietNaN as TaggedInt tag(highest 16bits as 0xFFFF), and need to encode dou…
31 // to the value will begin with a 16-bit pattern within the range 0x0001..0xFFFE.
33 // Nan-boxing pointer is used and the first four bytes are used as tag:
34 // Object: [0x0000] [48 bit direct pointer]
35 // WeakRef: [0x0000] [47 bits direct pointer] | 1 bit 1
36 // / [0x0001] [48 bit any value]
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
Daarch64_imm_valid.h7 * http://www.apache.org/licenses/LICENSE-2.0
27 uint64 mask2 = (1UL << static_cast<uint64>(nLowerZeroBits)) - 1UL; in IsBitSizeImmediate()
65 // When value & ffffffff00000000 is 0, all high 32-bits are 0. in IsSingleInstructionMovable32()
66 // When value & ffffffff00000000 is ffffffff00000000, all high 32-bits are 1. in IsSingleInstructionMovable32()
67 // High 32-bits should be all 0 or all 1, when it comes to mov w0, #imm. in IsSingleInstructionMovable32()
89 // for target linux-aarch64-gnu in Imm12BitValid()
94 // For the 32-bit variant: is the bitmask immediate
97 if (value == 0 || static_cast<int64>(value) == -1) { in Imm12BitMaskValid()
106 // for target linux-aarch64-gnu in Imm13BitValid()
111 // For the 64-bit variant: is the bitmask immediate
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Daarch64_fp_simd_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
22 * ID, 128 bit vector prefix, followed by scalar prefixes
23 …* scalar prefixes: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, canBeAssigned, isCalleeSave, isParam, i…
24 * (e.g., we use D0 when V0 contains a 64-bit scalar FP number (aka, double))
42 FP_SIMD_REG(16, "V", "B", "H", "S", "D", "Q", true, false, false, false, false)
Daarch64_isa.h7 * http://www.apache.org/licenses/LICENSE-2.0
34 constexpr int kAarch64StackPtrAlignment = 16;
37 constexpr uint32 kAarch64IntregBytelen = 8; /* 64-bit */
39 constexpr int kAarch64SizeOfFplr = 16;
42 kStpLdpImm64LowerBound = -512,
44 kStpLdpImm32LowerBound = -256,
48 enum StrLdrPerPostBound : int64 { kStrLdrPerPostLowerBound = -256, kStrLdrPerPostUpperBound = 255 };
64 * ...When you use the 32-bit form of an instruction, the upper
73 * to it as WZR in a 32-bit context or XZR in a 64-bit context.
85 /* fp-simd registers */
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Daarch64_int_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
27 * to it as WZR in a 32-bit context or XZR in a 64-bit context.
31 /* ID, 32-bit prefix, 64-bit prefix, canBeAssigned, isCalleeSave, isParam, isSpill, isExtraSpill */
48 INT_REG(16, "W", "X", true, false, false, false, false)
66 * We should not use "W" prefix in 64-bit context, though!!
71 /* Alias ID, ID, 32-bit prefix, 64-bit prefix */
/arkcompiler/runtime_core/static_core/runtime/bridge/arch/arm/
Dcompiled_code_to_interpreter_bridge_armhf.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
37 sub sp, sp, #16
38 CFI_ADJUST_CFA_OFFSET(16)
53 push {r4 - r10}
54 CFI_REL_OFFSET(r10, -(2 * 4))
55 CFI_REL_OFFSET(r9, -(3 * 4))
56 CFI_REL_OFFSET(r8, -(4 * 4))
57 CFI_REL_OFFSET(r7, -(5 * 4))
58 CFI_REL_OFFSET(r6, -(6 * 4))
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Dcompiled_code_to_interpreter_bridge_arm.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
36 // store r0-r3 before the frame to make arg array continuos with stack args
37 push {r0-r3}
38 CFI_ADJUST_CFA_OFFSET(16)
49 CFI_ADJUST_CFA_OFFSET(-4)
57 push {r4 - r10}
58 CFI_REL_OFFSET(r10, -(2 * 4))
59 CFI_REL_OFFSET(r9, -(3 * 4))
60 CFI_REL_OFFSET(r8, -(4 * 4))
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/arkcompiler/runtime_core/static_core/runtime/fibers/arch/aarch64/
Dcontext_layout.h2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
19 // NOLINTBEGIN(cppcoreguidelines-macro-usage)
24 * GPRs: 14 x 8 = 112 bytes (r0, r18-r30)
25 * Special GPRs: 2 x 8 = 16 bytes (PC, SP)
28 * FP regs: 8 x 16 = 128 bytes (Q8-Q15)
32 * -----------------------------------------
35 * 0x10 | 16 | 8 | R20
50 * 0x80 | 128 | 16 | Q8
51 * 0x90 | 144 | 16 | Q9
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/arkcompiler/runtime_core/static_core/runtime/include/coretypes/
Dtagged_value.h2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
45 static constexpr size_t INT16_BITS = 16;
48 // Every double with all of its exponent bits set and its highest mantissa bit set is a quiet NaN.
50 // “QNaN Floating-Point Indefinite” value, leaving us 50 bits. Those remaining bits can be anythin…
51 // so we use a special quietNaN as TaggedInt tag(highest 16bits as 0xFFFF), and need to encode dou…
52 // to the value will begin with a 16-bit pattern within the range 0x0001..0xFFFE.
54 // Nan-boxing pointer is used and the first four bytes are used as tag:
55 // Object: [0x0000] [48 bit direct pointer]
56 // WeakRef: [0x0000] [47 bits direct pointer] | 1 bit 1
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/arkcompiler/ets_frontend/es2panda/util/
Dbase64.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
28 // 2: the index do not exceed the range of encodedRes and form a complete four-character block in Base64Encode()
29 …for (size_t i = 0, j = 0; i < encodedRes.length() - 2; i += TRANSFORMED_CHAR_NUM, j += TO_TRANSFOR… in Base64Encode()
30 // convert three 8bit into four 6bit; then add two 0 bit in each 6 bit in Base64Encode()
46 encodedRes[encodedRes.length() - 2] = '='; in Base64Encode()
47 encodedRes[encodedRes.length() - 1] = '='; in Base64Encode()
51 encodedRes[encodedRes.length() - 1] = '='; in Base64Encode()
62 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode()
63 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode()
64 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/assembler/
Doperand.h7 * http://www.apache.org/licenses/LICENSE-2.0
27 /* Use 16 bits to represent a register:
30 …The fifth bit from right to left is used to identity register rip, the bit equals 1 represents the…
31 …The sixth bit from right to left is used to identity float register, the bit equals 1 represents t…
32 The eighth bit from right to left is used to determine whether
33 …it is the high 8-bit register or the lower 8-bit register, the bit equals 1 represents the lower 8…
34 The specific distribution of the 16 bits is shown below:
35 +-----------------------------------+-----------+-------+---------+-------+-------------------+
37 +-----------------------------------+-----------+-------+---------+-------+-------------------+
38 | Reg's size in bits | H/L8-reg | unuse | IsFloat | IsRIP | Reg's id |
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_ir/include/
Dcmpl.h7 * http://www.apache.org/licenses/LICENSE-2.0
37 uint8 *formalWordsTypetagged; // bit vector where the Nth bit tells whether
44 uint8 *localWordsTypetagged; // bit vector where the Nth bit tells whether
47 // the word at location (%%FP - N*4)) has
49 // at (%%FP - N*4 + 4); the bitvector's size
51 uint8 *formalWordsRefCounted; // bit vector where the Nth bit tells whether
58 uint8 *localWordsRefCounted; // bit vector where the Nth bit tells whether
61 // the word at location (%%FP - N*4)) points to
77 return funcSize - (kTwoBitVectors * BlockSize2BitVectorSize(upFormalSize)) - in FuncCodeSize()
90 uint8 *globalWordsTypetagged; // bit vector where the Nth bit tells whether
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/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
Dassembler_aarch64.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
27 … ((width != RegXSize) && (((imm >> width) != 0) || (imm == (~0ULL >> (RegXSize - width)))))) { in Create()
35 uint64_t mask = (1ULL << size) - 1; in Create()
46 uint64_t mask = ((uint64_t)-1LL) >> (RegXSize - size); in Create()
60 i = static_cast<uint32_t>(RegXSize) - clo; in Create()
61 cto = clo + CountTrailingOnes64(imm) - (static_cast<uint32_t>(RegXSize) - size); in Create()
68 unsigned immr = (size - i) & (size - 1); in Create()
70 // If size has a 1 in the n'th bit, create a value that has zeroes in in Create()
72 uint64_t nImms = ~(size - 1) << 1; in Create()
74 // Or the CTO value into the low bits, which must be below the Nth bit in Create()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/
Delf_types.h7 * http://www.apache.org/licenses/LICENSE-2.0
22 #define EI_NIDENT (16)
33 #define ELFCLASS64 2 /* 64-bit objects */
42 #define EM_X86_64 62 /* AMD x86-64 architecture */
45 #define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page-rel. ADRP imm. from 32:12. */
48 #define R_X86_64_32 10 /* Direct 32 bit zero extended */
49 #define R_X86_64_64 1 /* Direct 64 bit */
51 #define R_X86_64_PC32 2 /* PC relative 32 bit signed */
52 #define R_X86_64_PC64 24 /* PC relative 64 bit */
53 #define R_X86_64_PLT32 4 /* 32 bit PLT address */
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/arkcompiler/runtime_core/static_core/plugins/ets/irtoc_scripts/
Dstring.irt7 # http://www.apache.org/licenses/LICENSE-2.0
19 MEM_BLOCK_16_BYTES = "16"
95 # 0x000E..0x009F -- common non-whitespace chars
101 # 0x0009 -- horizontal tab
102 # 0x000A -- line feed or new line
103 # 0x000B -- vertical tab
104 # 0x000C -- formfeed
105 # 0x000D -- carriage return
112 # 0x00A0 -- non-breaking space
116 # 0x1680 -- Ogham space mark
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