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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
Daarch64_imm_valid.h7 * http://www.apache.org/licenses/LICENSE-2.0
27 uint64 mask2 = (1UL << static_cast<uint64>(nLowerZeroBits)) - 1UL; in IsBitSizeImmediate()
47 // get lower 32 bits in IsMoveWidableImmediateCopy()
49 …// If lower 32 bits are all 0, but higher 32 bits have 1, val will be 1 and return true, but it is… in IsMoveWidableImmediateCopy()
65 // When value & ffffffff00000000 is 0, all high 32-bits are 0. in IsSingleInstructionMovable32()
66 // When value & ffffffff00000000 is ffffffff00000000, all high 32-bits are 1. in IsSingleInstructionMovable32()
67 // High 32-bits should be all 0 or all 1, when it comes to mov w0, #imm. in IsSingleInstructionMovable32()
72 constexpr uint32 bitLen = 32; in IsSingleInstructionMovable32()
89 // for target linux-aarch64-gnu in Imm12BitValid()
94 // For the 32-bit variant: is the bitmask immediate
[all …]
Daarch64_int_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
27 * to it as WZR in a 32-bit context or XZR in a 64-bit context.
31 /* ID, 32-bit prefix, 64-bit prefix, canBeAssigned, isCalleeSave, isParam, isSpill, isExtraSpill */
66 * We should not use "W" prefix in 64-bit context, though!!
71 /* Alias ID, ID, 32-bit prefix, 64-bit prefix */
Daarch64_isa.h7 * http://www.apache.org/licenses/LICENSE-2.0
37 constexpr uint32 kAarch64IntregBytelen = 8; /* 64-bit */
42 kStpLdpImm64LowerBound = -512,
44 kStpLdpImm32LowerBound = -256,
48 enum StrLdrPerPostBound : int64 { kStrLdrPerPostLowerBound = -256, kStrLdrPerPostUpperBound = 255 };
64 * ...When you use the 32-bit form of an instruction, the upper
65 * 32 bits of the source registers are ignored and
66 * the upper 32 bits of the destination register are set to zero.
73 * to it as WZR in a 32-bit context or XZR in a 64-bit context.
85 /* fp-simd registers */
[all …]
/arkcompiler/runtime_core/static_core/plugins/ets/templates/stdlib/
DDataView.sts.j22 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
47 this(buffer, byteOffset, (buffer as Buffer).getByteLength() - byteOffset)
79 {%- for bit in [8, 16, 32, 64] %}
80 {%- for mode in ["Int", "Uint", "Float"] %}
81 {%- if mode != "Float" or bit >= 32 %}
82 // === {{mode}}{{bit}} ===
83 {%- set impls = ['Little', 'Big'] if bit != 8 else ['Big'] %}
85 {%- set type2nameBits = {8: "byte", 16: "short", 32: "int", 64: "long"} %}
86 {%- set type2nameCompat = {8: "number", 16: "number", 32: "number", 64: "bigint"} %}
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/arkcompiler/runtime_core/compiler/docs/
Dinterface_inline_cache.md11 * There is a 90% - 95% chance that the same method will be used in real-world application test.
20 * must be 64bit system
27 Cache structure:（offset addr)/(class addr) 32bit/32bit
28 -----------------------------------------------
31 cache:offset/class ---------->| <-|
35 --> call runtime irtoc function | |
36 read cache <-----------------------| |
41 save method‘s offset to cache >------|
42 <-- return to (.text)
44 -----------------------------------------------
[all …]
/arkcompiler/runtime_core/static_core/compiler/docs/
Dinterface_inline_cache.md11 * There is a 90% - 95% chance that the same method will be used in real-world application test.
20 * must be 64bit system
27 Cache structure:（offset addr)/(class addr) 32bit/32bit
28 -----------------------------------------------
31 cache:offset/class ---------->| <-|
35 --> call runtime irtoc function | |
36 read cache <-----------------------| |
41 save method‘s offset to cache >------|
42 <-- return to (.text)
44 -----------------------------------------------
[all …]
/arkcompiler/runtime_core/static_core/libpandabase/utils/
Dregmask.h2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
44 size_t res = (1ULL << width) - 1; in MakeMaskByExcluding()
50 * Base struct for registers mask, template-parametrized by number of registers.
51 * Currently we don't support registers number greater than 32.
59 // We don't support architectures with CPU registers number, greater than 32.
67 // NOLINTNEXTLINE(google-explicit-constructor)
90 constexpr bool Test(size_t bit) const in Test() argument
92 ASSERT(bit < Size()); in Test()
93 return ((value_ >> static_cast<ValueType>(bit)) & 1U) != 0; in Test()
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/arkcompiler/runtime_core/libpandabase/utils/
Dregmask.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
44 size_t res = (1ULL << width) - 1; in MakeMaskByExcluding()
50 * Base struct for registers mask, template-parametrized by number of registers.
51 * Currently we don't support registers number greater than 32.
59 // We don't support architectures with CPU registers number, greater than 32.
67 // NOLINTNEXTLINE(google-explicit-constructor)
90 constexpr bool Test(size_t bit) const in Test() argument
92 ASSERT(bit < Size()); in Test()
93 return ((value_ >> static_cast<ValueType>(bit)) & 1U) != 0; in Test()
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/arkcompiler/runtime_core/static_core/verification/util/
Dmem.h2 * Copyright (c) 2022-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
24 is unavailable for allocation -- for example, it may be reserved for kernel memory.
27 https://linux-kernel-labs.github.io/refs/heads/master/lectures/address-space.html
29 Linux is using a split address space for 32 bit systems, although in the past there
31 …architecture that supports it, e.g. x86). Linux always uses split address space for 64 bit systems.
33 [For 32-bit Linux, the split is usually 3/1, i.e. 0x00000000-0xc0000000 is user space,
34 0xc0000000-0xffffffff is kernel space]
36 …For Windows: https://learn.microsoft.com/en-us/windows-hardware/drivers/gettingstarted/virtual-add…
38 For a 32-bit process, the virtual address space is usually the 2-gigabyte range 0x00000000
[all …]
/arkcompiler/ets_runtime/ecmascript/jspandafile/
Dconstpool_value.h7 * http://www.apache.org/licenses/LICENSE-2.0
64 // NOLINTNEXTLINE(readability-magic-numbers)
65 using ConstPoolIndexField = BitField<uint32_t, 0, 32>; // 32: 32 bit
66 // NOLINTNEXTLINE(readability-magic-numbers)
67 using ConstPoolTypeField = BitField<ConstPoolType, 32, 4>; // 32: offset, 4: 4bit
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_ir/include/
Dcmpl.h7 * http://www.apache.org/licenses/LICENSE-2.0
37 uint8 *formalWordsTypetagged; // bit vector where the Nth bit tells whether
44 uint8 *localWordsTypetagged; // bit vector where the Nth bit tells whether
47 // the word at location (%%FP - N*4)) has
49 // at (%%FP - N*4 + 4); the bitvector's size
51 uint8 *formalWordsRefCounted; // bit vector where the Nth bit tells whether
58 uint8 *localWordsRefCounted; // bit vector where the Nth bit tells whether
61 // the word at location (%%FP - N*4)) points to
77 return funcSize - (kTwoBitVectors * BlockSize2BitVectorSize(upFormalSize)) - in FuncCodeSize()
90 uint8 *globalWordsTypetagged; // bit vector where the Nth bit tells whether
[all …]
/arkcompiler/runtime_core/static_core/runtime/mem/gc/g1/
Dg1-helpers.cpp2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
19 #include "runtime/mem/gc/g1/g1-helpers.h"
20 #include "runtime/mem/gc/card_table-inl.h"
28 GCBarrierSet *barrierSet = thread->GetBarrierSet(); in GetG1BarrierSet()
35 // The cast below is needed to truncate high 32bits from 64bit pointer in PreWrbFuncEntrypoint()
36 // in case object pointers have 32bit. in PreWrbFuncEntrypoint()
39 … ASSERT(IsAddressInObjectsHeap(static_cast<const ObjectHeader *>(oldval)->ClassAddr<BaseClass>())); in PreWrbFuncEntrypoint()
42 …// thread can't be null here because pre-barrier is called only in concurrent-mark, but we don't p… in PreWrbFuncEntrypoint()
43 // weak-references in concurrent mark in PreWrbFuncEntrypoint()
[all …]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/
Delf_types.h7 * http://www.apache.org/licenses/LICENSE-2.0
33 #define ELFCLASS64 2 /* 64-bit objects */
42 #define EM_X86_64 62 /* AMD x86-64 architecture */
45 #define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page-rel. ADRP imm. from 32:12. */
48 #define R_X86_64_32 10 /* Direct 32 bit zero extended */
49 #define R_X86_64_64 1 /* Direct 64 bit */
51 #define R_X86_64_PC32 2 /* PC relative 32 bit signed */
52 #define R_X86_64_PC64 24 /* PC relative 64 bit */
53 #define R_X86_64_PLT32 4 /* 32 bit PLT address */
58 #define SHF_MASKPROC 0xf0000000 /* Processor-specific */
/arkcompiler/runtime_core/static_core/docs/
Dcode_metainfo.md5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
14 +-------------+
16 | +-------------------+
20 +-------------+-------------------+
21 | | <-- Method::CompiledCodeEntrypoint
24 +-------------+-----------------+
26 | |-----------------+----------------------+
31 | | Bit Tables | Method indexes |
37 |-------------+-----------------+----------------------+
40 ## Bit table
[all …]
/arkcompiler/runtime_core/docs/
Dcode_metainfo.md5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
14 +-------------+
16 | +-------------------+
20 +-------------+-------------------+
21 | | <-- Method::CompiledCodeEntrypoint
24 +-------------+-----------------+
26 | |-----------------+----------------------+
31 | | Bit Tables | Method indexes |
37 |-------------+-----------------+----------------------+
40 ## Bit table
[all …]
/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
39 - equal_common_types
40 - float_src_eq_dst_size
41 - integer_src_ge_dst_size
43 - equal_common_types
44 - integer_src_ge_dst_size
46 - equal_common_types
47 - integer_src_ge_dst_size
[all …]
/arkcompiler/runtime_core/static_core/libpandabase/tests/
Dregmask_test.cpp2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
29 …ASSERT_EQ(mask.GetMaxRegister(), base.size() - Clz(static_cast<RegMask::ValueType>(base.to_ulong()… in CompareWithBitset()
61 void TestDistance(RegMask mask, size_t bit, size_t bitsBefore, size_t bitsAfter) in TestDistance() argument
63 ASSERT_EQ(mask.GetDistanceFromTail(bit), bitsBefore); in TestDistance()
64 ASSERT_EQ(mask.GetDistanceFromHead(bit), bitsAfter); in TestDistance()
69 // NOLINTBEGIN(readability-magic-numbers) in TEST()
72 TestRegMask(MakeMaskByExcluding(32U, 0U)); in TEST()
73 TestRegMask(MakeMaskByExcluding(32U, 31U)); in TEST()
74 TestRegMask(MakeMaskByExcluding(32U, 0U, 31U)); in TEST()
[all …]
/arkcompiler/runtime_core/libpandabase/tests/
Dregmask_test.cpp2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
29 …ASSERT_EQ(mask.GetMaxRegister(), base.size() - Clz(static_cast<RegMask::ValueType>(base.to_ulong()… in CompareWithBitset()
61 void TestDistance(RegMask mask, size_t bit, size_t bits_before, size_t bits_after) in TestDistance() argument
63 ASSERT_EQ(mask.GetDistanceFromTail(bit), bits_before); in TestDistance()
64 ASSERT_EQ(mask.GetDistanceFromHead(bit), bits_after); in TestDistance()
71 TestRegMask(MakeMaskByExcluding(32, 0));
72 TestRegMask(MakeMaskByExcluding(32, 31));
73 TestRegMask(MakeMaskByExcluding(32, 0, 31));
74 TestRegMask(MakeMaskByExcluding(32, 0, 15, 31));
/arkcompiler/runtime_core/docs/changelogs/
D2022-08-18-isa-changelog.md1 # 2022-08-18-isa-changelog
15 3. We add prefix "deprecated" and keep the many old isa as "deprecated"-prefixed opcodes (for compa…
20 8. We add 8-bit or 16-bit imm as inline cache slot for some specific opcodes.
23 As we merge some "define-function" opcodes as one opcode, in function we add one field which record…
24 such that runtime can distinguish the "define-function" operations of different kinds.
26 We reuse the field 32-bit field `access_flags_` to encode Function Kind and Header index.
27 This will not introduce compatibility issue because the later 24-bit of `access_flags_` is unused i…
30 |<- 16-bit header index ->|<- 8-bit function kind ->|<- 8-bit original access flag ->|
39 As we use 16-bit to encode methodId, stringId and literalarrayId, the number of these Ids in one me…
45 3. In bytecode, we still use 16-bit literalarrayId rather than offset.
[all …]
/arkcompiler/runtime_core/static_core/isa/
Disa.yaml1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
14 ---
17 - name: General design
21 - name: Registers
31 - name: Accumulator
40 register-to-register moves.
42 - name: Calling sequence
48 …On return, callee frame is destroyed. If function return value is non-void, it is passed to caller…
52 - name: Supported primitive types
[all …]
/arkcompiler/runtime_core/static_core/runtime/bridge/arch/arm/
Dcompiled_code_to_interpreter_bridge_arm.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
36 // store r0-r3 before the frame to make arg array continuos with stack args
37 push {r0-r3}
49 CFI_ADJUST_CFA_OFFSET(-4)
57 push {r4 - r10}
58 CFI_REL_OFFSET(r10, -(2 * 4))
59 CFI_REL_OFFSET(r9, -(3 * 4))
60 CFI_REL_OFFSET(r8, -(4 * 4))
61 CFI_REL_OFFSET(r7, -(5 * 4))
[all …]
/arkcompiler/runtime_core/tests/verifier-tests/
Dbug_2107_2.pa1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 #---
17 #- title: Integer truncations and extensions.
19 # Truncations discard all but N lowest-order bits, where N is the bit size of destination
24 # - x_none
26 # - sig: i64toi32
27 # acc: inout:i64->i32
29 # - op_none
31 # - acc_type
[all …]
/arkcompiler/runtime_core/static_core/tests/verifier-tests/
Dbug_2107_2.pa1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 #---
17 #- title: Integer truncations and extensions.
19 # Truncations discard all but N lowest-order bits, where N is the bit size of destination
24 # - x_none
26 # - sig: i64toi32
27 # acc: inout:i64->i32
29 # - op_none
31 # - acc_type
[all …]
/arkcompiler/ets_runtime/ecmascript/base/
Dmath_helper.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
24 #define panda_bit_utils_ctz __builtin_ctz // NOLINT(cppcoreguidelines-macro-usage)
25 #define panda_bit_utils_ctzll __builtin_ctzll // NOLINT(cppcoreguidelines-macro-usage)
55 … // -0.0(double) is the special case for std::atanh() function compiled in linux for windows. in Atanh()
56 return -0.0; in Atanh()
68 // Use __builtin_ctzll for 8 bytes (64 bits) and __builtin_ctz for 32-bit integers. in WhichPowerOfTwo()
78 if (rhs == -1) { in SignedDiv32()
79 return lhs == std::numeric_limits<int32_t>::min() ? lhs : -lhs; in SignedDiv32()
89 if (rhs == -1) { in SignedDiv64()
[all …]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/
Dx64_fp_simd_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
17 * - %xmm0–%xmm1 used to pass and return floating point arguments
18 - %xmm2–%xmm7 used to pass floating point arguments
23 …* ID, prefixes: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, canBeAssigned, isCalleeSave, isParam, isSp…

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