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/arkcompiler/runtime_core/static_core/plugins/ets/templates/stdlib/
DDataView.sts.j22 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
47 this(buffer, byteOffset, (buffer as Buffer).getByteLength() - byteOffset)
79 {%- for bit in [8, 16, 32, 64] %}
80 {%- for mode in ["Int", "Uint", "Float"] %}
81 {%- if mode != "Float" or bit >= 32 %}
82 // === {{mode}}{{bit}} ===
83 {%- set impls = ['Little', 'Big'] if bit != 8 else ['Big'] %}
85 {%- set type2nameBits = {8: "byte", 16: "short", 32: "int", 64: "long"} %}
86 {%- set type2nameCompat = {8: "number", 16: "number", 32: "number", 64: "bigint"} %}
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/arkcompiler/runtime_core/docs/changelogs/
D2022-08-18-isa-changelog.md1 # 2022-08-18-isa-changelog
15 3. We add prefix "deprecated" and keep the many old isa as "deprecated"-prefixed opcodes (for compa…
20 8. We add 8-bit or 16-bit imm as inline cache slot for some specific opcodes.
23 As we merge some "define-function" opcodes as one opcode, in function we add one field which record…
24 such that runtime can distinguish the "define-function" operations of different kinds.
26 We reuse the field 32-bit field `access_flags_` to encode Function Kind and Header index.
27 This will not introduce compatibility issue because the later 24-bit of `access_flags_` is unused i…
30 |<- 16-bit header index ->|<- 8-bit function kind ->|<- 8-bit original access flag ->|
39 As we use 16-bit to encode methodId, stringId and literalarrayId, the number of these Ids in one me…
45 3. In bytecode, we still use 16-bit literalarrayId rather than offset.
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_ir/include/
Dcmpl.h7 * http://www.apache.org/licenses/LICENSE-2.0
37 uint8 *formalWordsTypetagged; // bit vector where the Nth bit tells whether
44 uint8 *localWordsTypetagged; // bit vector where the Nth bit tells whether
47 // the word at location (%%FP - N*4)) has
49 // at (%%FP - N*4 + 4); the bitvector's size
51 uint8 *formalWordsRefCounted; // bit vector where the Nth bit tells whether
58 uint8 *localWordsRefCounted; // bit vector where the Nth bit tells whether
61 // the word at location (%%FP - N*4)) points to
77 return funcSize - (kTwoBitVectors * BlockSize2BitVectorSize(upFormalSize)) - in FuncCodeSize()
90 uint8 *globalWordsTypetagged; // bit vector where the Nth bit tells whether
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/arkcompiler/ets_runtime/ecmascript/snapshot/mem/
Dencode_bit.h7 * http://www.apache.org/licenses/LICENSE-2.0
29 * 16bit 8bit 1bit 1bit 1bit 8bit 1bit 18bit 10bit
44 // encode bit
48 static constexpr int OBJECT_TYPE_BIT_NUMBER = 8; // js_type
52 static constexpr int UNUSED_BIT_NUMBER = 8; // unused bit number
/arkcompiler/runtime_core/static_core/verification/util/
Dmem.h2 * Copyright (c) 2022-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
24 is unavailable for allocation -- for example, it may be reserved for kernel memory.
27 https://linux-kernel-labs.github.io/refs/heads/master/lectures/address-space.html
29 Linux is using a split address space for 32 bit systems, although in the past there
31 …architecture that supports it, e.g. x86). Linux always uses split address space for 64 bit systems.
33 [For 32-bit Linux, the split is usually 3/1, i.e. 0x00000000-0xc0000000 is user space,
34 0xc0000000-0xffffffff is kernel space]
36 …For Windows: https://learn.microsoft.com/en-us/windows-hardware/drivers/gettingstarted/virtual-add…
38 For a 32-bit process, the virtual address space is usually the 2-gigabyte range 0x00000000
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/
Dx64_fp_simd_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
17 * - %xmm0–%xmm1 used to pass and return floating point arguments
18 - %xmm2–%xmm7 used to pass floating point arguments
23 …* ID, prefixes: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, canBeAssigned, isCalleeSave, isParam, isSp…
34 FP_SIMD_REG(8 , "B", "H", "S", "D", "Q", true, false, false, true, false)
Dx64_int_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
17 * Registers in x86-64
19 * - caller-save registers: %rax, %rcx, %rdx, %rdi, %rsi, %rsp, and %r8-r11
20 * - callee-saved registers: %r12, %r13, %r14, %r15, %rbx, %rsp, %rbp.
21 * - In contrast to the Intel386 ABI, %rdi, and %rsi in x86-64 belong to the called function, not
22 * the caller. So, It's caller-save registers
23 …* - User-level applications use as integer registers for passing the sequence %rdi, %rsi, %rdx, %r…
25 * - the sequence %rax, %rdx is used to return INTEGER,
26 * - rdx is used to pass 3rd argument to functions; 2nd return register
27 * - %r11 is neither required to be preserved, nor is it used to pass arguments
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/arkcompiler/runtime_core/static_core/plugins/ets/tests/checked/
Dets_static_lookup_8bit.pa6 # http://www.apache.org/licenses/LICENSE-2.0
14 #! CHECKER Static lookup for 8-bit StObjByName JIT
15 #! RUN force_jit: true, options: "--compiler-regex='.*test_store.*'", entry: "_GLOBAL::tes…
24 #! CHECKER Static lookup for 8-bit StObjByName AOT
26 #! RUN_PAOC options: "--compiler-regex='.*test_store.*'"
36 #! CHECKER Static lookup for 8-bit LdObjByName JIT
37 #! RUN force_jit: true, options: "--compiler-regex='.*test_load.*'", entry: "_GLOBAL::test…
46 #! CHECKER Static lookup for 8-bit LdObjByName AOT
48 #! RUN_PAOC options: "--compiler-regex='.*test_load.*'"
89 ldai -1
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/arkcompiler/ets_runtime/ecmascript/
Dproperty_attributes.h7 * http://www.apache.org/licenses/LICENSE-2.0
66 * Common | WritableField (bit 1)
67 * | EnumerableField (bit 2)
68 * | ConfigurableField (bit 3)
69 * | IsAccessorField (bit 4)
70 * | IsInlinedPropsField(bit 5)
71 * | RepresentationField(bit 6...7)
72 * --------------------------------
73 * Fast | OffsetField(bit 8...17)
74 * | TrackTypeField(bit 18...20)
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/arkcompiler/runtime_core/static_core/runtime/bridge/arch/x86/
Dcompiled_code_to_interpreter_bridge_x86.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
32 // %esp % 16 == 12 here (-4 == 12 (mod 16))
62 // %esp % 16 == 8 here
65 leal -8(%ebp), %ecx // prev*
69 // %esp should be 16-byte aligned here
71 addl $8, %esp // cleanup
76 …// %eax - SHORTY_PTR_REG, %edx - SHORTY_REG, %ecx - shorty value, %edi - iframe.vregs_ + num_vregs…
77 // %esi - args, (%esp) - iframe*
84 leal 8(%ebp), %esi // args
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Dinterpreter_to_compiled_code_bridge_x86.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
27 cmpl $(SHORTY_NUM_64BIT_TYPES - 1), %ecx
30 // it is a 32bit value
36 // it is a 64bit value
41 addl $8, \stack_ptr
51 movl 8(\arg_ptr), \tmp1
53 movl \tmp1, 8(\stack_ptr)
62 // %eax - SHORTY_PTR_REG
63 // %edx - SHORTY_REG
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/arkcompiler/ets_runtime/ecmascript/base/
Dmath_helper.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
24 #define panda_bit_utils_ctz __builtin_ctz // NOLINT(cppcoreguidelines-macro-usage)
25 #define panda_bit_utils_ctzll __builtin_ctzll // NOLINT(cppcoreguidelines-macro-usage)
55 … // -0.0(double) is the special case for std::atanh() function compiled in linux for windows. in Atanh()
56 return -0.0; in Atanh()
66 // Ensure the size of the integer is no more than 8 bytes (64 bits). in WhichPowerOfTwo()
67 static_assert(sizeof(T) <= 8); in WhichPowerOfTwo()
68 // Use __builtin_ctzll for 8 bytes (64 bits) and __builtin_ctz for 32-bit integers. in WhichPowerOfTwo()
69 …return sizeof(T) == 8 ? __builtin_ctzll(static_cast<uint64_t>(value)) : __builtin_ctz(static_cast<… in WhichPowerOfTwo()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/assembler/
Doperand.h7 * http://www.apache.org/licenses/LICENSE-2.0
28 The high 8 bits is register's size.
30 …The fifth bit from right to left is used to identity register rip, the bit equals 1 represents the…
31 …The sixth bit from right to left is used to identity float register, the bit equals 1 represents t…
32 The eighth bit from right to left is used to determine whether
33 …it is the high 8-bit register or the lower 8-bit register, the bit equals 1 represents the lower 8…
35 +-----------------------------------+-----------+-------+---------+-------+-------------------+
36 | 15 14 13 12 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
37 +-----------------------------------+-----------+-------+---------+-------+-------------------+
38 | Reg's size in bits | H/L8-reg | unuse | IsFloat | IsRIP | Reg's id |
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/arkcompiler/runtime_core/static_core/docs/
Dcode_metainfo.md5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
14 +-------------+
16 | +-------------------+
20 +-------------+-------------------+
21 | | <-- Method::CompiledCodeEntrypoint
24 +-------------+-----------------+
26 | |-----------------+----------------------+
31 | | Bit Tables | Method indexes |
37 |-------------+-----------------+----------------------+
40 ## Bit table
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/arkcompiler/runtime_core/docs/
Dcode_metainfo.md5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
14 +-------------+
16 | +-------------------+
20 +-------------+-------------------+
21 | | <-- Method::CompiledCodeEntrypoint
24 +-------------+-----------------+
26 | |-----------------+----------------------+
31 | | Bit Tables | Method indexes |
37 |-------------+-----------------+----------------------+
40 ## Bit table
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/arkcompiler/ets_frontend/es2panda/util/
Dbase64.cpp7 * http://www.apache.org/licenses/LICENSE-2.0
28 // 2: the index do not exceed the range of encodedRes and form a complete four-character block in Base64Encode()
29 …for (size_t i = 0, j = 0; i < encodedRes.length() - 2; i += TRANSFORMED_CHAR_NUM, j += TO_TRANSFOR… in Base64Encode()
30 // convert three 8bit into four 6bit; then add two 0 bit in each 6 bit in Base64Encode()
46 encodedRes[encodedRes.length() - 2] = '='; in Base64Encode()
47 encodedRes[encodedRes.length() - 1] = '='; in Base64Encode()
51 encodedRes[encodedRes.length() - 1] = '='; in Base64Encode()
62 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode()
63 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode()
64 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode()
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/arkcompiler/runtime_core/static_core/runtime/bridge/arch/arm/
Dinterpreter_to_compiled_code_bridge_arm.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
28 cmp r2, #(SHORTY_NUM_64BIT_TYPES - 1)
30 // it is a 32bit value
34 1: // it is a 64bit value
36 add \stack_ptr, \stack_ptr, #7 // round the address up to 8 byte boundary
42 add \stack_ptr, \stack_ptr, #7 // round the address up to 8 byte boundary
67 bic sp, sp, #7 // round downd sp to 8byte boundary
72 // r0 - SHORTY_PTR_REG
73 // r1 - SHORTY_REG
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Dcompiled_code_to_interpreter_bridge_arm.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
36 // store r0-r3 before the frame to make arg array continuos with stack args
37 push {r0-r3}
43 CFI_ADJUST_CFA_OFFSET(8)
46 CFI_ADJUST_CFA_OFFSET(8)
49 CFI_ADJUST_CFA_OFFSET(-4)
57 push {r4 - r10}
58 CFI_REL_OFFSET(r10, -(2 * 4))
59 CFI_REL_OFFSET(r9, -(3 * 4))
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Dinterpreter_to_compiled_code_bridge_armhf.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
24 // load arguments into r0-r4 while begin_ptr != end_ptr
25 ldr r0, [\begin_ptr, #-4]!
28 ldr r1, [\begin_ptr, #-4]!
31 ldr r2, [\begin_ptr, #-4]!
34 ldr r3, [\begin_ptr, #-4]!
39 // load arguments into d0-d7 while \begin_ptr != \end_ptr
80 // it is a 32bit int or reference
85 strlt \tmp1, [\gpr_ptr, #-4]!
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/arkcompiler/runtime_core/static_core/libpandabase/utils/
Dbit_field.h2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
29 static constexpr unsigned BITS_PER_BYTE = 8;
52 * Make BitField type that follows right after current bit range.
67 * Make Flag field that follows right after current bit range.
74 * Return maximum value that fits bit range [START_BIT : START_BIT+END_BIT]
78 return (1LLU << BITS_NUM) - 1; in MaxValue()
82 * Return mask of bit range, f.e. 0b1110 for BitField<T, 1, 3>
90 * Check if given value fits into the bit field
98 * Set 'value' to current bit range [START_BIT : START_BIT+END_BIT] within the 'stor' parameter.
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
Daarch64_fp_simd_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
22 * ID, 128 bit vector prefix, followed by scalar prefixes
23 …* scalar prefixes: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, canBeAssigned, isCalleeSave, isParam, i…
24 * (e.g., we use D0 when V0 contains a 64-bit scalar FP number (aka, double))
34 FP_SIMD_REG(8 , "V", "B", "H", "S", "D", "Q", true, true, false, false, false)
Daarch64_isa.h7 * http://www.apache.org/licenses/LICENSE-2.0
36 constexpr int32 kAarch64OffsetAlign = 8;
37 constexpr uint32 kAarch64IntregBytelen = 8; /* 64-bit */
38 constexpr uint32 kAarch64FpregBytelen = 8; /* only lower 64 bits are used */
42 kStpLdpImm64LowerBound = -512,
44 kStpLdpImm32LowerBound = -256,
48 enum StrLdrPerPostBound : int64 { kStrLdrPerPostLowerBound = -256, kStrLdrPerPostUpperBound = 255 };
53 kStrLdrImm64UpperBound = 32760, /* must be a multiple of 8 */
64 * ...When you use the 32-bit form of an instruction, the upper
73 * to it as WZR in a 32-bit context or XZR in a 64-bit context.
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/arkcompiler/runtime_core/libpandabase/utils/
Dbit_field.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
29 static constexpr unsigned BITS_PER_BYTE = 8;
53 * Make BitField type that follows right after current bit range.
68 * Make Flag field that follows right after current bit range.
75 * Return maximum value that fits bit range [START_BIT : START_BIT+END_BIT]
79 return (1LLU << bits_num) - 1; in MaxValue()
83 * Return mask of bit range, f.e. 0b1110 for BitField<T, 1, 3>
91 * Check if given value fits into the bit field
99 * Set 'value' to current bit range [START_BIT : START_BIT+END_BIT] within the 'stor' parameter.
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/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
39 - equal_common_types
40 - float_src_eq_dst_size
41 - integer_src_ge_dst_size
43 - equal_common_types
44 - integer_src_ge_dst_size
46 - equal_common_types
47 - integer_src_ge_dst_size
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/arkcompiler/runtime_core/compiler/docs/
Dinterface_inline_cache.md11 * There is a 90% - 95% chance that the same method will be used in real-world application test.
20 * must be 64bit system
27 Cache structure:（offset addr)/(class addr) 32bit/32bit
28 -----------------------------------------------
31 cache:offset/class ---------->| <-|
35 --> call runtime irtoc function | |
36 read cache <-----------------------| |
41 save method‘s offset to cache >------|
42 <-- return to (.text)
44 -----------------------------------------------
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