| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | qcom,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5332-dwc3
18 - qcom,ipq6018-dwc3
19 - qcom,ipq8064-dwc3
20 - qcom,ipq8074-dwc3
21 - qcom,ipq9574-dwc3
22 - qcom,msm8953-dwc3
23 - qcom,msm8994-dwc3
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| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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| D | rockchip,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
13 The common content of the node is defined in snps,dwc3.yaml.
24 - $ref: snps,dwc3.yaml#
31 - rockchip,rk3328-dwc3
32 - rockchip,rk3568-dwc3
40 - rockchip,rk3328-dwc3
41 - rockchip,rk3568-dwc3
42 - const: snps,dwc3
99 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
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| D | omap-usb.txt | 46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
71 compatible = "ti,dwc3";
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| D | fsl,imx8mq-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
18 - fsl,imx8mq-dwc3
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
29 - $ref: snps,dwc3.yaml#
39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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| /kernel/linux/linux-6.6/drivers/usb/dwc3/ |
| D | Makefile | 5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o
46 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
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| D | dwc3-haps.c | 3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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| D | dwc3-imx8mp.c | 3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
53 struct platform_device *dwc3; member
101 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_wakeup_enable() local
104 if (!dwc3) in dwc3_imx8mp_wakeup_enable()
109 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) in dwc3_imx8mp_wakeup_enable()
112 else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) in dwc3_imx8mp_wakeup_enable()
131 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt()
222 dwc3_np = of_get_compatible_child(node, "snps,dwc3"); in dwc3_imx8mp_probe()
225 dev_err(dev, "failed to find dwc3 core child\n"); in dwc3_imx8mp_probe()
231 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in dwc3_imx8mp_probe()
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| D | dwc3-pci.c | 3 * dwc3-pci.c - PCI Specific glue layer
74 * @dwc3: child dwc3 platform_device
81 struct platform_device *dwc3; member
273 * Make the pdev name predictable (only 1 DWC3 on BYT) in dwc3_pci_quirks()
277 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
278 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; in dwc3_pci_quirks()
298 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
305 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
308 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
310 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
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| D | dwc3-qcom.c | 4 * Inspired by dwc3-of-simple.c
70 struct platform_device *dwc3; member
267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); in dwc3_qcom_interconnect_init()
310 struct dwc3 *dwc; in dwc3_qcom_is_host()
315 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
326 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_read_usb2_speed()
337 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code in dwc3_qcom_read_usb2_speed()
489 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
507 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
675 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_qcom_acpi_register_core()
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| /kernel/linux/linux-5.10/drivers/usb/dwc3/ |
| D | Makefile | 5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
46 obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
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| D | dwc3-haps.c | 3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
56 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
57 if (!dwc->dwc3) in dwc3_haps_probe()
71 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
73 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
78 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
80 ret = platform_device_add_properties(dwc->dwc3, initial_properties); in dwc3_haps_probe()
84 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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| D | dwc3-qcom.c | 4 * Inspired by dwc3-of-simple.c
69 struct platform_device *dwc3; member
265 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER || in dwc3_qcom_interconnect_init()
266 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN) in dwc3_qcom_interconnect_init()
309 struct dwc3 *dwc; in dwc3_qcom_is_host()
314 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
432 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
450 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
614 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_qcom_acpi_register_core()
615 if (!qcom->dwc3) in dwc3_qcom_acpi_register_core()
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| D | dwc3-pci.c | 3 * dwc3-pci.c - PCI Specific glue layer
56 * @dwc3: child dwc3 platform_device
63 struct platform_device *dwc3; member
214 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
217 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
219 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
223 pm_runtime_mark_last_busy(&dwc3->dev); in dwc3_pci_resume_work()
224 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
248 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_pci_probe()
249 if (!dwc->dwc3) in dwc3_pci_probe()
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| D | core.c | 47 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
90 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) in dwc3_set_prtcap()
119 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
167 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || in __dwc3_set_mode()
238 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
254 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
270 int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
277 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
324 * @dwc3: Pointer to our controller context structure
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/dwc3.txt
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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| D | qcom,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,msm8996-dwc3
17 - qcom,msm8998-dwc3
18 - qcom,sc7180-dwc3
19 - qcom,sdm845-dwc3
20 - const: qcom,dwc3
99 Used when dwc3 operates without SSPHY and only
106 "^dwc3@[0-9a-f]+$":
109 A child node must exist to represent the core DWC3 IP block
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| D | dwc3.txt | 1 synopsys DWC3 CORE
3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
9 - interrupts: Interrupts used by the dwc3 controller.
19 "qcom,dwc3"
23 "sprd,sc9860-dwc3"
24 "st,stih407-dwc3"
25 "ti,am437x-dwc3"
26 "ti,dwc3"
27 "ti,keystone-dwc3"
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| D | rockchip,dwc3.txt | 1 Rockchip SuperSpeed DWC3 USB SoC controller
4 - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
15 A child node must exist to represent the core DWC3 IP block. The name of
16 the node is not important. The content of the node is defined in dwc3.txt.
25 compatible = "rockchip,rk3399-dwc3";
33 usbdrd_dwc3_0: dwc3@fe800000 {
34 compatible = "snps,dwc3";
42 compatible = "rockchip,rk3399-dwc3";
50 usbdrd_dwc3_1: dwc3@fe900000 {
51 compatible = "snps,dwc3";
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| D | intel,keembay-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
7 title: Intel Keem Bay DWC3 USB controller
14 const: intel,keembay-dwc3
37 "^dwc3@[0-9a-f]+$":
40 A child node must exist to represent the core DWC3 IP block.
41 The content of the node is defined in dwc3.txt.
61 compatible = "intel,keembay-dwc3";
71 dwc3@34000000 {
72 compatible = "snps,dwc3";
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| D | omap-usb.txt | 46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/dwc3.txt
71 compatible = "ti,dwc3";
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| D | exynos-usb.txt | 68 DWC3
71 "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
73 "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
75 "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
93 The dwc3 core should be added as subnode to Exynos dwc3 glue.
94 - dwc3 :
95 The binding details of dwc3 can be found in:
96 Documentation/devicetree/bindings/usb/dwc3.txt
109 dwc3 {
110 compatible = "synopsys,dwc3";
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| D | dwc3-xilinx.txt | 1 Xilinx SuperSpeed DWC3 USB SoC controller
4 - compatible: Should contain "xlnx,zynqmp-dwc3"
13 A child node must exist to represent the core DWC3 IP block. The name of
14 the node is not important. The content of the node is defined in dwc3.txt.
21 compatible = "xlnx,zynqmp-dwc3";
26 dwc3@fe200000 {
27 compatible = "snps,dwc3";
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| D | ti,keystone-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
68 description: This is the node representing the DWC3 controller instance
69 Documentation/devicetree/bindings/usb/dwc3.txt
85 dwc3@2680000 {
86 compatible = "ti,keystone-dwc3";
95 compatible = "synopsys,dwc3";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-dwc3-glue.yaml | 4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
[all …]
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