1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
dwc3_get_dr_mode(struct dwc3 * dwc)47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103 }
104
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106 {
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115 }
116
__dwc3_set_mode(struct work_struct * work)117 static void __dwc3_set_mode(struct work_struct *work)
118 {
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
122 u32 reg;
123 u32 desired_dr_role;
124
125 mutex_lock(&dwc->mutex);
126 spin_lock_irqsave(&dwc->lock, flags);
127 desired_dr_role = dwc->desired_dr_role;
128 spin_unlock_irqrestore(&dwc->lock, flags);
129
130 pm_runtime_get_sync(dwc->dev);
131
132 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
133 dwc3_otg_update(dwc, 0);
134
135 if (!desired_dr_role)
136 goto out;
137
138 if (desired_dr_role == dwc->current_dr_role)
139 goto out;
140
141 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
142 goto out;
143
144 switch (dwc->current_dr_role) {
145 case DWC3_GCTL_PRTCAP_HOST:
146 dwc3_host_exit(dwc);
147 break;
148 case DWC3_GCTL_PRTCAP_DEVICE:
149 dwc3_gadget_exit(dwc);
150 dwc3_event_buffers_cleanup(dwc);
151 break;
152 case DWC3_GCTL_PRTCAP_OTG:
153 dwc3_otg_exit(dwc);
154 spin_lock_irqsave(&dwc->lock, flags);
155 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
156 spin_unlock_irqrestore(&dwc->lock, flags);
157 dwc3_otg_update(dwc, 1);
158 break;
159 default:
160 break;
161 }
162
163 /*
164 * When current_dr_role is not set, there's no role switching.
165 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
166 */
167 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
168 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
169 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
170 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
171 reg |= DWC3_GCTL_CORESOFTRESET;
172 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
173
174 /*
175 * Wait for internal clocks to synchronized. DWC_usb31 and
176 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
177 * keep it consistent across different IPs, let's wait up to
178 * 100ms before clearing GCTL.CORESOFTRESET.
179 */
180 msleep(100);
181
182 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
183 reg &= ~DWC3_GCTL_CORESOFTRESET;
184 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
185 }
186
187 spin_lock_irqsave(&dwc->lock, flags);
188
189 dwc3_set_prtcap(dwc, desired_dr_role);
190
191 spin_unlock_irqrestore(&dwc->lock, flags);
192
193 switch (desired_dr_role) {
194 case DWC3_GCTL_PRTCAP_HOST:
195 ret = dwc3_host_init(dwc);
196 if (ret) {
197 dev_err(dwc->dev, "failed to initialize host\n");
198 } else {
199 if (dwc->usb2_phy)
200 otg_set_vbus(dwc->usb2_phy->otg, true);
201 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
202 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
203 if (dwc->dis_split_quirk) {
204 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
205 reg |= DWC3_GUCTL3_SPLITDISABLE;
206 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
207 }
208 }
209 break;
210 case DWC3_GCTL_PRTCAP_DEVICE:
211 dwc3_core_soft_reset(dwc);
212
213 dwc3_event_buffers_setup(dwc);
214
215 if (dwc->usb2_phy)
216 otg_set_vbus(dwc->usb2_phy->otg, false);
217 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
218 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
219
220 ret = dwc3_gadget_init(dwc);
221 if (ret)
222 dev_err(dwc->dev, "failed to initialize peripheral\n");
223 break;
224 case DWC3_GCTL_PRTCAP_OTG:
225 dwc3_otg_init(dwc);
226 dwc3_otg_update(dwc, 0);
227 break;
228 default:
229 break;
230 }
231
232 out:
233 pm_runtime_mark_last_busy(dwc->dev);
234 pm_runtime_put_autosuspend(dwc->dev);
235 mutex_unlock(&dwc->mutex);
236 }
237
dwc3_set_mode(struct dwc3 * dwc,u32 mode)238 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
239 {
240 unsigned long flags;
241
242 if (dwc->dr_mode != USB_DR_MODE_OTG)
243 return;
244
245 spin_lock_irqsave(&dwc->lock, flags);
246 dwc->desired_dr_role = mode;
247 spin_unlock_irqrestore(&dwc->lock, flags);
248
249 queue_work(system_freezable_wq, &dwc->drd_work);
250 }
251
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)252 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
253 {
254 struct dwc3 *dwc = dep->dwc;
255 u32 reg;
256
257 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
258 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
259 DWC3_GDBGFIFOSPACE_TYPE(type));
260
261 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
262
263 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
264 }
265
266 /**
267 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
268 * @dwc: pointer to our context structure
269 */
dwc3_core_soft_reset(struct dwc3 * dwc)270 int dwc3_core_soft_reset(struct dwc3 *dwc)
271 {
272 u32 reg;
273 int retries = 1000;
274
275 /*
276 * We're resetting only the device side because, if we're in host mode,
277 * XHCI driver will reset the host block. If dwc3 was configured for
278 * host-only mode, then we can return early.
279 */
280 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
281 return 0;
282
283 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
284 reg |= DWC3_DCTL_CSFTRST;
285 reg &= ~DWC3_DCTL_RUN_STOP;
286 dwc3_gadget_dctl_write_safe(dwc, reg);
287
288 /*
289 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
290 * is cleared only after all the clocks are synchronized. This can
291 * take a little more than 50ms. Set the polling rate at 20ms
292 * for 10 times instead.
293 */
294 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
295 retries = 10;
296
297 do {
298 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
299 if (!(reg & DWC3_DCTL_CSFTRST))
300 goto done;
301
302 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
303 msleep(20);
304 else
305 udelay(1);
306 } while (--retries);
307
308 return -ETIMEDOUT;
309
310 done:
311 /*
312 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
313 * is cleared, we must wait at least 50ms before accessing the PHY
314 * domain (synchronization delay).
315 */
316 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
317 msleep(50);
318
319 return 0;
320 }
321
322 /*
323 * dwc3_frame_length_adjustment - Adjusts frame length if required
324 * @dwc3: Pointer to our controller context structure
325 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)326 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
327 {
328 u32 reg;
329 u32 dft;
330
331 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
332 return;
333
334 if (dwc->fladj == 0)
335 return;
336
337 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
338 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
339 if (dft != dwc->fladj) {
340 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
341 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
342 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
343 }
344 }
345
346 /**
347 * dwc3_free_one_event_buffer - Frees one event buffer
348 * @dwc: Pointer to our controller context structure
349 * @evt: Pointer to event buffer to be freed
350 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)351 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
352 struct dwc3_event_buffer *evt)
353 {
354 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
355 }
356
357 /**
358 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
359 * @dwc: Pointer to our controller context structure
360 * @length: size of the event buffer
361 *
362 * Returns a pointer to the allocated event buffer structure on success
363 * otherwise ERR_PTR(errno).
364 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)365 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
366 unsigned length)
367 {
368 struct dwc3_event_buffer *evt;
369
370 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
371 if (!evt)
372 return ERR_PTR(-ENOMEM);
373
374 evt->dwc = dwc;
375 evt->length = length;
376 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
377 if (!evt->cache)
378 return ERR_PTR(-ENOMEM);
379
380 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
381 &evt->dma, GFP_KERNEL);
382 if (!evt->buf)
383 return ERR_PTR(-ENOMEM);
384
385 return evt;
386 }
387
388 /**
389 * dwc3_free_event_buffers - frees all allocated event buffers
390 * @dwc: Pointer to our controller context structure
391 */
dwc3_free_event_buffers(struct dwc3 * dwc)392 static void dwc3_free_event_buffers(struct dwc3 *dwc)
393 {
394 struct dwc3_event_buffer *evt;
395
396 evt = dwc->ev_buf;
397 if (evt)
398 dwc3_free_one_event_buffer(dwc, evt);
399 }
400
401 /**
402 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
403 * @dwc: pointer to our controller context structure
404 * @length: size of event buffer
405 *
406 * Returns 0 on success otherwise negative errno. In the error case, dwc
407 * may contain some buffers allocated but not all which were requested.
408 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)409 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
410 {
411 struct dwc3_event_buffer *evt;
412 unsigned int hw_mode;
413
414 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
415 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
416 dwc->ev_buf = NULL;
417 return 0;
418 }
419
420 evt = dwc3_alloc_one_event_buffer(dwc, length);
421 if (IS_ERR(evt)) {
422 dev_err(dwc->dev, "can't allocate event buffer\n");
423 return PTR_ERR(evt);
424 }
425 dwc->ev_buf = evt;
426
427 return 0;
428 }
429
430 /**
431 * dwc3_event_buffers_setup - setup our allocated event buffers
432 * @dwc: pointer to our controller context structure
433 *
434 * Returns 0 on success otherwise negative errno.
435 */
dwc3_event_buffers_setup(struct dwc3 * dwc)436 int dwc3_event_buffers_setup(struct dwc3 *dwc)
437 {
438 struct dwc3_event_buffer *evt;
439
440 if (!dwc->ev_buf)
441 return 0;
442
443 evt = dwc->ev_buf;
444 evt->lpos = 0;
445 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
446 lower_32_bits(evt->dma));
447 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
448 upper_32_bits(evt->dma));
449 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
450 DWC3_GEVNTSIZ_SIZE(evt->length));
451 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
452
453 return 0;
454 }
455
dwc3_event_buffers_cleanup(struct dwc3 * dwc)456 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
457 {
458 struct dwc3_event_buffer *evt;
459 u32 reg;
460
461 if (!dwc->ev_buf)
462 return;
463 /*
464 * Exynos platforms may not be able to access event buffer if the
465 * controller failed to halt on dwc3_core_exit().
466 */
467 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
468 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
469 return;
470
471 evt = dwc->ev_buf;
472
473 evt->lpos = 0;
474
475 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
476 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
477 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
478 | DWC3_GEVNTSIZ_SIZE(0));
479 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
480 }
481
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)482 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
483 {
484 if (!dwc->has_hibernation)
485 return 0;
486
487 if (!dwc->nr_scratch)
488 return 0;
489
490 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
491 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
492 if (!dwc->scratchbuf)
493 return -ENOMEM;
494
495 return 0;
496 }
497
dwc3_setup_scratch_buffers(struct dwc3 * dwc)498 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
499 {
500 dma_addr_t scratch_addr;
501 u32 param;
502 int ret;
503
504 if (!dwc->has_hibernation)
505 return 0;
506
507 if (!dwc->nr_scratch)
508 return 0;
509
510 /* should never fall here */
511 if (!WARN_ON(dwc->scratchbuf))
512 return 0;
513
514 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
515 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
516 DMA_BIDIRECTIONAL);
517 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
518 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
519 ret = -EFAULT;
520 goto err0;
521 }
522
523 dwc->scratch_addr = scratch_addr;
524
525 param = lower_32_bits(scratch_addr);
526
527 ret = dwc3_send_gadget_generic_command(dwc,
528 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
529 if (ret < 0)
530 goto err1;
531
532 param = upper_32_bits(scratch_addr);
533
534 ret = dwc3_send_gadget_generic_command(dwc,
535 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
536 if (ret < 0)
537 goto err1;
538
539 return 0;
540
541 err1:
542 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
543 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
544
545 err0:
546 return ret;
547 }
548
dwc3_free_scratch_buffers(struct dwc3 * dwc)549 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
550 {
551 if (!dwc->has_hibernation)
552 return;
553
554 if (!dwc->nr_scratch)
555 return;
556
557 /* should never fall here */
558 if (!WARN_ON(dwc->scratchbuf))
559 return;
560
561 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
562 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
563 kfree(dwc->scratchbuf);
564 }
565
dwc3_core_num_eps(struct dwc3 * dwc)566 static void dwc3_core_num_eps(struct dwc3 *dwc)
567 {
568 struct dwc3_hwparams *parms = &dwc->hwparams;
569
570 dwc->num_eps = DWC3_NUM_EPS(parms);
571 }
572
dwc3_cache_hwparams(struct dwc3 * dwc)573 static void dwc3_cache_hwparams(struct dwc3 *dwc)
574 {
575 struct dwc3_hwparams *parms = &dwc->hwparams;
576
577 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
578 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
579 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
580 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
581 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
582 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
583 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
584 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
585 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
586 }
587
dwc3_core_ulpi_init(struct dwc3 * dwc)588 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
589 {
590 int intf;
591 int ret = 0;
592
593 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
594
595 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
596 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
597 dwc->hsphy_interface &&
598 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
599 ret = dwc3_ulpi_init(dwc);
600
601 return ret;
602 }
603
604 /**
605 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
606 * @dwc: Pointer to our controller context structure
607 *
608 * Returns 0 on success. The USB PHY interfaces are configured but not
609 * initialized. The PHY interfaces and the PHYs get initialized together with
610 * the core in dwc3_core_init.
611 */
dwc3_phy_setup(struct dwc3 * dwc)612 static int dwc3_phy_setup(struct dwc3 *dwc)
613 {
614 unsigned int hw_mode;
615 u32 reg;
616
617 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
618
619 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
620
621 /*
622 * Make sure UX_EXIT_PX is cleared as that causes issues with some
623 * PHYs. Also, this bit is not supposed to be used in normal operation.
624 */
625 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
626
627 /*
628 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
629 * to '0' during coreConsultant configuration. So default value
630 * will be '0' when the core is reset. Application needs to set it
631 * to '1' after the core initialization is completed.
632 */
633 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
634 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
635
636 /*
637 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
638 * power-on reset, and it can be set after core initialization, which is
639 * after device soft-reset during initialization.
640 */
641 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
642 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
643
644 if (dwc->u2ss_inp3_quirk)
645 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
646
647 if (dwc->dis_rxdet_inp3_quirk)
648 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
649
650 if (dwc->req_p1p2p3_quirk)
651 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
652
653 if (dwc->del_p1p2p3_quirk)
654 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
655
656 if (dwc->del_phy_power_chg_quirk)
657 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
658
659 if (dwc->lfps_filter_quirk)
660 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
661
662 if (dwc->rx_detect_poll_quirk)
663 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
664
665 if (dwc->tx_de_emphasis_quirk)
666 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
667
668 if (dwc->dis_u3_susphy_quirk)
669 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
670
671 if (dwc->dis_del_phy_power_chg_quirk)
672 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
673
674 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
675
676 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
677
678 /* Select the HS PHY interface */
679 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
680 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
681 if (dwc->hsphy_interface &&
682 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
683 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
684 break;
685 } else if (dwc->hsphy_interface &&
686 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
687 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
688 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
689 } else {
690 /* Relying on default value. */
691 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
692 break;
693 }
694 fallthrough;
695 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
696 default:
697 break;
698 }
699
700 switch (dwc->hsphy_mode) {
701 case USBPHY_INTERFACE_MODE_UTMI:
702 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
703 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
704 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
705 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
706 break;
707 case USBPHY_INTERFACE_MODE_UTMIW:
708 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
709 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
710 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
711 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
712 break;
713 default:
714 break;
715 }
716
717 /*
718 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
719 * '0' during coreConsultant configuration. So default value will
720 * be '0' when the core is reset. Application needs to set it to
721 * '1' after the core initialization is completed.
722 */
723 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
724 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
725
726 /*
727 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
728 * power-on reset, and it can be set after core initialization, which is
729 * after device soft-reset during initialization.
730 */
731 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
732 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
733
734 if (dwc->dis_u2_susphy_quirk)
735 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
736
737 if (dwc->dis_enblslpm_quirk)
738 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
739 else
740 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
741
742 if (dwc->dis_u2_freeclk_exists_quirk)
743 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
744
745 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
746
747 return 0;
748 }
749
dwc3_core_exit(struct dwc3 * dwc)750 static void dwc3_core_exit(struct dwc3 *dwc)
751 {
752 dwc3_event_buffers_cleanup(dwc);
753
754 usb_phy_set_suspend(dwc->usb2_phy, 1);
755 usb_phy_set_suspend(dwc->usb3_phy, 1);
756 phy_power_off(dwc->usb2_generic_phy);
757 phy_power_off(dwc->usb3_generic_phy);
758
759 usb_phy_shutdown(dwc->usb2_phy);
760 usb_phy_shutdown(dwc->usb3_phy);
761 phy_exit(dwc->usb2_generic_phy);
762 phy_exit(dwc->usb3_generic_phy);
763
764 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
765 reset_control_assert(dwc->reset);
766 }
767
dwc3_core_is_valid(struct dwc3 * dwc)768 static bool dwc3_core_is_valid(struct dwc3 *dwc)
769 {
770 u32 reg;
771
772 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
773 dwc->ip = DWC3_GSNPS_ID(reg);
774
775 /* This should read as U3 followed by revision number */
776 if (DWC3_IP_IS(DWC3)) {
777 dwc->revision = reg;
778 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
779 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
780 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
781 } else {
782 return false;
783 }
784
785 return true;
786 }
787
dwc3_core_setup_global_control(struct dwc3 * dwc)788 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
789 {
790 u32 hwparams4 = dwc->hwparams.hwparams4;
791 u32 reg;
792
793 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
794 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
795
796 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
797 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
798 /**
799 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
800 * issue which would cause xHCI compliance tests to fail.
801 *
802 * Because of that we cannot enable clock gating on such
803 * configurations.
804 *
805 * Refers to:
806 *
807 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
808 * SOF/ITP Mode Used
809 */
810 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
811 dwc->dr_mode == USB_DR_MODE_OTG) &&
812 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
813 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
814 else
815 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
816 break;
817 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
818 /* enable hibernation here */
819 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
820
821 /*
822 * REVISIT Enabling this bit so that host-mode hibernation
823 * will work. Device-mode hibernation is not yet implemented.
824 */
825 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
826 break;
827 default:
828 /* nothing */
829 break;
830 }
831
832 /* check if current dwc3 is on simulation board */
833 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
834 dev_info(dwc->dev, "Running with FPGA optimizations\n");
835 dwc->is_fpga = true;
836 }
837
838 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
839 "disable_scramble cannot be used on non-FPGA builds\n");
840
841 if (dwc->disable_scramble_quirk && dwc->is_fpga)
842 reg |= DWC3_GCTL_DISSCRAMBLE;
843 else
844 reg &= ~DWC3_GCTL_DISSCRAMBLE;
845
846 if (dwc->u2exit_lfps_quirk)
847 reg |= DWC3_GCTL_U2EXIT_LFPS;
848
849 /*
850 * WORKAROUND: DWC3 revisions <1.90a have a bug
851 * where the device can fail to connect at SuperSpeed
852 * and falls back to high-speed mode which causes
853 * the device to enter a Connect/Disconnect loop
854 */
855 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
856 reg |= DWC3_GCTL_U2RSTECN;
857
858 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
859 }
860
861 static int dwc3_core_get_phy(struct dwc3 *dwc);
862 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
863
864 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)865 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
866 {
867 struct device *dev = dwc->dev;
868 /* incrx_mode : for INCR burst type. */
869 bool incrx_mode;
870 /* incrx_size : for size of INCRX burst. */
871 u32 incrx_size;
872 u32 *vals;
873 u32 cfg;
874 int ntype;
875 int ret;
876 int i;
877
878 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
879
880 /*
881 * Handle property "snps,incr-burst-type-adjustment".
882 * Get the number of value from this property:
883 * result <= 0, means this property is not supported.
884 * result = 1, means INCRx burst mode supported.
885 * result > 1, means undefined length burst mode supported.
886 */
887 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
888 if (ntype <= 0)
889 return;
890
891 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
892 if (!vals) {
893 dev_err(dev, "Error to get memory\n");
894 return;
895 }
896
897 /* Get INCR burst type, and parse it */
898 ret = device_property_read_u32_array(dev,
899 "snps,incr-burst-type-adjustment", vals, ntype);
900 if (ret) {
901 kfree(vals);
902 dev_err(dev, "Error to get property\n");
903 return;
904 }
905
906 incrx_size = *vals;
907
908 if (ntype > 1) {
909 /* INCRX (undefined length) burst mode */
910 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
911 for (i = 1; i < ntype; i++) {
912 if (vals[i] > incrx_size)
913 incrx_size = vals[i];
914 }
915 } else {
916 /* INCRX burst mode */
917 incrx_mode = INCRX_BURST_MODE;
918 }
919
920 kfree(vals);
921
922 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
923 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
924 if (incrx_mode)
925 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
926 switch (incrx_size) {
927 case 256:
928 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
929 break;
930 case 128:
931 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
932 break;
933 case 64:
934 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
935 break;
936 case 32:
937 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
938 break;
939 case 16:
940 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
941 break;
942 case 8:
943 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
944 break;
945 case 4:
946 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
947 break;
948 case 1:
949 break;
950 default:
951 dev_err(dev, "Invalid property\n");
952 break;
953 }
954
955 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
956 }
957
958 /**
959 * dwc3_core_init - Low-level initialization of DWC3 Core
960 * @dwc: Pointer to our controller context structure
961 *
962 * Returns 0 on success otherwise negative errno.
963 */
dwc3_core_init(struct dwc3 * dwc)964 static int dwc3_core_init(struct dwc3 *dwc)
965 {
966 unsigned int hw_mode;
967 u32 reg;
968 int ret;
969
970 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
971
972 /*
973 * Write Linux Version Code to our GUID register so it's easy to figure
974 * out which kernel version a bug was found.
975 */
976 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
977
978 ret = dwc3_phy_setup(dwc);
979 if (ret)
980 goto err0;
981
982 if (!dwc->ulpi_ready) {
983 ret = dwc3_core_ulpi_init(dwc);
984 if (ret) {
985 if (ret == -ETIMEDOUT) {
986 dwc3_core_soft_reset(dwc);
987 ret = -EPROBE_DEFER;
988 }
989 goto err0;
990 }
991 dwc->ulpi_ready = true;
992 }
993
994 if (!dwc->phys_ready) {
995 ret = dwc3_core_get_phy(dwc);
996 if (ret)
997 goto err0a;
998 dwc->phys_ready = true;
999 }
1000
1001 usb_phy_init(dwc->usb2_phy);
1002 usb_phy_init(dwc->usb3_phy);
1003 ret = phy_init(dwc->usb2_generic_phy);
1004 if (ret < 0)
1005 goto err0a;
1006
1007 ret = phy_init(dwc->usb3_generic_phy);
1008 if (ret < 0) {
1009 phy_exit(dwc->usb2_generic_phy);
1010 goto err0a;
1011 }
1012
1013 ret = dwc3_core_soft_reset(dwc);
1014 if (ret)
1015 goto err1;
1016
1017 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1018 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1019 if (!dwc->dis_u3_susphy_quirk) {
1020 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1021 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1022 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1023 }
1024
1025 if (!dwc->dis_u2_susphy_quirk) {
1026 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1027 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1028 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1029 }
1030 }
1031
1032 dwc3_core_setup_global_control(dwc);
1033 dwc3_core_num_eps(dwc);
1034
1035 ret = dwc3_setup_scratch_buffers(dwc);
1036 if (ret)
1037 goto err1;
1038
1039 /* Adjust Frame Length */
1040 dwc3_frame_length_adjustment(dwc);
1041
1042 dwc3_set_incr_burst_type(dwc);
1043
1044 usb_phy_set_suspend(dwc->usb2_phy, 0);
1045 usb_phy_set_suspend(dwc->usb3_phy, 0);
1046 ret = phy_power_on(dwc->usb2_generic_phy);
1047 if (ret < 0)
1048 goto err2;
1049
1050 ret = phy_power_on(dwc->usb3_generic_phy);
1051 if (ret < 0)
1052 goto err3;
1053
1054 ret = dwc3_event_buffers_setup(dwc);
1055 if (ret) {
1056 dev_err(dwc->dev, "failed to setup event buffers\n");
1057 goto err4;
1058 }
1059
1060 /*
1061 * ENDXFER polling is available on version 3.10a and later of
1062 * the DWC_usb3 controller. It is NOT available in the
1063 * DWC_usb31 controller.
1064 */
1065 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1066 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1067 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1068 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1069 }
1070
1071 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1072 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1073
1074 /*
1075 * Enable hardware control of sending remote wakeup
1076 * in HS when the device is in the L1 state.
1077 */
1078 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1079 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1080
1081 if (dwc->dis_tx_ipgap_linecheck_quirk)
1082 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1083
1084 if (dwc->parkmode_disable_ss_quirk)
1085 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1086
1087 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1088 }
1089
1090 /*
1091 * Must config both number of packets and max burst settings to enable
1092 * RX and/or TX threshold.
1093 */
1094 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1095 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1096 u8 rx_maxburst = dwc->rx_max_burst_prd;
1097 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1098 u8 tx_maxburst = dwc->tx_max_burst_prd;
1099
1100 if (rx_thr_num && rx_maxburst) {
1101 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1102 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1103
1104 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1105 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1106
1107 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1108 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1109
1110 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1111 }
1112
1113 if (tx_thr_num && tx_maxburst) {
1114 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1115 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1116
1117 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1118 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1119
1120 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1121 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1122
1123 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1124 }
1125 }
1126
1127 return 0;
1128
1129 err4:
1130 phy_power_off(dwc->usb3_generic_phy);
1131
1132 err3:
1133 phy_power_off(dwc->usb2_generic_phy);
1134
1135 err2:
1136 usb_phy_set_suspend(dwc->usb2_phy, 1);
1137 usb_phy_set_suspend(dwc->usb3_phy, 1);
1138
1139 err1:
1140 usb_phy_shutdown(dwc->usb2_phy);
1141 usb_phy_shutdown(dwc->usb3_phy);
1142 phy_exit(dwc->usb2_generic_phy);
1143 phy_exit(dwc->usb3_generic_phy);
1144
1145 err0a:
1146 dwc3_ulpi_exit(dwc);
1147
1148 err0:
1149 return ret;
1150 }
1151
dwc3_core_get_phy(struct dwc3 * dwc)1152 static int dwc3_core_get_phy(struct dwc3 *dwc)
1153 {
1154 struct device *dev = dwc->dev;
1155 struct device_node *node = dev->of_node;
1156 int ret;
1157
1158 if (node) {
1159 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1160 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1161 } else {
1162 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1163 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1164 }
1165
1166 if (IS_ERR(dwc->usb2_phy)) {
1167 ret = PTR_ERR(dwc->usb2_phy);
1168 if (ret == -ENXIO || ret == -ENODEV) {
1169 dwc->usb2_phy = NULL;
1170 } else if (ret == -EPROBE_DEFER) {
1171 return ret;
1172 } else {
1173 dev_err(dev, "no usb2 phy configured\n");
1174 return ret;
1175 }
1176 }
1177
1178 if (IS_ERR(dwc->usb3_phy)) {
1179 ret = PTR_ERR(dwc->usb3_phy);
1180 if (ret == -ENXIO || ret == -ENODEV) {
1181 dwc->usb3_phy = NULL;
1182 } else if (ret == -EPROBE_DEFER) {
1183 return ret;
1184 } else {
1185 dev_err(dev, "no usb3 phy configured\n");
1186 return ret;
1187 }
1188 }
1189
1190 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1191 if (IS_ERR(dwc->usb2_generic_phy)) {
1192 ret = PTR_ERR(dwc->usb2_generic_phy);
1193 if (ret == -ENOSYS || ret == -ENODEV) {
1194 dwc->usb2_generic_phy = NULL;
1195 } else if (ret == -EPROBE_DEFER) {
1196 return ret;
1197 } else {
1198 dev_err(dev, "no usb2 phy configured\n");
1199 return ret;
1200 }
1201 }
1202
1203 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1204 if (IS_ERR(dwc->usb3_generic_phy)) {
1205 ret = PTR_ERR(dwc->usb3_generic_phy);
1206 if (ret == -ENOSYS || ret == -ENODEV) {
1207 dwc->usb3_generic_phy = NULL;
1208 } else if (ret == -EPROBE_DEFER) {
1209 return ret;
1210 } else {
1211 dev_err(dev, "no usb3 phy configured\n");
1212 return ret;
1213 }
1214 }
1215
1216 return 0;
1217 }
1218
dwc3_core_init_mode(struct dwc3 * dwc)1219 static int dwc3_core_init_mode(struct dwc3 *dwc)
1220 {
1221 struct device *dev = dwc->dev;
1222 int ret;
1223
1224 switch (dwc->dr_mode) {
1225 case USB_DR_MODE_PERIPHERAL:
1226 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1227
1228 if (dwc->usb2_phy)
1229 otg_set_vbus(dwc->usb2_phy->otg, false);
1230 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1231 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1232
1233 ret = dwc3_gadget_init(dwc);
1234 if (ret) {
1235 if (ret != -EPROBE_DEFER)
1236 dev_err(dev, "failed to initialize gadget\n");
1237 return ret;
1238 }
1239 break;
1240 case USB_DR_MODE_HOST:
1241 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1242
1243 if (dwc->usb2_phy)
1244 otg_set_vbus(dwc->usb2_phy->otg, true);
1245 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1246 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1247
1248 ret = dwc3_host_init(dwc);
1249 if (ret) {
1250 if (ret != -EPROBE_DEFER)
1251 dev_err(dev, "failed to initialize host\n");
1252 return ret;
1253 }
1254 break;
1255 case USB_DR_MODE_OTG:
1256 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1257 ret = dwc3_drd_init(dwc);
1258 if (ret) {
1259 if (ret != -EPROBE_DEFER)
1260 dev_err(dev, "failed to initialize dual-role\n");
1261 return ret;
1262 }
1263 break;
1264 default:
1265 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1266 return -EINVAL;
1267 }
1268
1269 return 0;
1270 }
1271
dwc3_core_exit_mode(struct dwc3 * dwc)1272 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1273 {
1274 switch (dwc->dr_mode) {
1275 case USB_DR_MODE_PERIPHERAL:
1276 dwc3_gadget_exit(dwc);
1277 break;
1278 case USB_DR_MODE_HOST:
1279 dwc3_host_exit(dwc);
1280 break;
1281 case USB_DR_MODE_OTG:
1282 dwc3_drd_exit(dwc);
1283 break;
1284 default:
1285 /* do nothing */
1286 break;
1287 }
1288
1289 /* de-assert DRVVBUS for HOST and OTG mode */
1290 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1291 }
1292
dwc3_get_properties(struct dwc3 * dwc)1293 static void dwc3_get_properties(struct dwc3 *dwc)
1294 {
1295 struct device *dev = dwc->dev;
1296 u8 lpm_nyet_threshold;
1297 u8 tx_de_emphasis;
1298 u8 hird_threshold;
1299 u8 rx_thr_num_pkt_prd = 0;
1300 u8 rx_max_burst_prd = 0;
1301 u8 tx_thr_num_pkt_prd = 0;
1302 u8 tx_max_burst_prd = 0;
1303
1304 /* default to highest possible threshold */
1305 lpm_nyet_threshold = 0xf;
1306
1307 /* default to -3.5dB de-emphasis */
1308 tx_de_emphasis = 1;
1309
1310 /*
1311 * default to assert utmi_sleep_n and use maximum allowed HIRD
1312 * threshold value of 0b1100
1313 */
1314 hird_threshold = 12;
1315
1316 dwc->maximum_speed = usb_get_maximum_speed(dev);
1317 dwc->dr_mode = usb_get_dr_mode(dev);
1318 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1319
1320 dwc->sysdev_is_parent = device_property_read_bool(dev,
1321 "linux,sysdev_is_parent");
1322 if (dwc->sysdev_is_parent)
1323 dwc->sysdev = dwc->dev->parent;
1324 else
1325 dwc->sysdev = dwc->dev;
1326
1327 dwc->has_lpm_erratum = device_property_read_bool(dev,
1328 "snps,has-lpm-erratum");
1329 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1330 &lpm_nyet_threshold);
1331 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1332 "snps,is-utmi-l1-suspend");
1333 device_property_read_u8(dev, "snps,hird-threshold",
1334 &hird_threshold);
1335 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1336 "snps,dis-start-transfer-quirk");
1337 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1338 "snps,usb3_lpm_capable");
1339 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1340 "snps,usb2-lpm-disable");
1341 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1342 "snps,usb2-gadget-lpm-disable");
1343 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1344 &rx_thr_num_pkt_prd);
1345 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1346 &rx_max_burst_prd);
1347 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1348 &tx_thr_num_pkt_prd);
1349 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1350 &tx_max_burst_prd);
1351
1352 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1353 "snps,disable_scramble_quirk");
1354 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1355 "snps,u2exit_lfps_quirk");
1356 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1357 "snps,u2ss_inp3_quirk");
1358 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1359 "snps,req_p1p2p3_quirk");
1360 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1361 "snps,del_p1p2p3_quirk");
1362 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1363 "snps,del_phy_power_chg_quirk");
1364 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1365 "snps,lfps_filter_quirk");
1366 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1367 "snps,rx_detect_poll_quirk");
1368 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1369 "snps,dis_u3_susphy_quirk");
1370 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1371 "snps,dis_u2_susphy_quirk");
1372 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1373 "snps,dis_enblslpm_quirk");
1374 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1375 "snps,dis-u1-entry-quirk");
1376 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1377 "snps,dis-u2-entry-quirk");
1378 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1379 "snps,dis_rxdet_inp3_quirk");
1380 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1381 "snps,dis-u2-freeclk-exists-quirk");
1382 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1383 "snps,dis-del-phy-power-chg-quirk");
1384 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1385 "snps,dis-tx-ipgap-linecheck-quirk");
1386 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1387 "snps,parkmode-disable-ss-quirk");
1388
1389 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1390 "snps,tx_de_emphasis_quirk");
1391 device_property_read_u8(dev, "snps,tx_de_emphasis",
1392 &tx_de_emphasis);
1393 device_property_read_string(dev, "snps,hsphy_interface",
1394 &dwc->hsphy_interface);
1395 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1396 &dwc->fladj);
1397
1398 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1399 "snps,dis_metastability_quirk");
1400
1401 dwc->dis_split_quirk = device_property_read_bool(dev,
1402 "snps,dis-split-quirk");
1403
1404 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1405 dwc->tx_de_emphasis = tx_de_emphasis;
1406
1407 dwc->hird_threshold = hird_threshold;
1408
1409 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1410 dwc->rx_max_burst_prd = rx_max_burst_prd;
1411
1412 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1413 dwc->tx_max_burst_prd = tx_max_burst_prd;
1414
1415 dwc->imod_interval = 0;
1416 }
1417
1418 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1419 bool dwc3_has_imod(struct dwc3 *dwc)
1420 {
1421 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1422 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1423 DWC3_IP_IS(DWC32);
1424 }
1425
dwc3_check_params(struct dwc3 * dwc)1426 static void dwc3_check_params(struct dwc3 *dwc)
1427 {
1428 struct device *dev = dwc->dev;
1429 unsigned int hwparam_gen =
1430 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1431
1432 /* Check for proper value of imod_interval */
1433 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1434 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1435 dwc->imod_interval = 0;
1436 }
1437
1438 /*
1439 * Workaround for STAR 9000961433 which affects only version
1440 * 3.00a of the DWC_usb3 core. This prevents the controller
1441 * interrupt from being masked while handling events. IMOD
1442 * allows us to work around this issue. Enable it for the
1443 * affected version.
1444 */
1445 if (!dwc->imod_interval &&
1446 DWC3_VER_IS(DWC3, 300A))
1447 dwc->imod_interval = 1;
1448
1449 /* Check the maximum_speed parameter */
1450 switch (dwc->maximum_speed) {
1451 case USB_SPEED_LOW:
1452 case USB_SPEED_FULL:
1453 case USB_SPEED_HIGH:
1454 break;
1455 case USB_SPEED_SUPER:
1456 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1457 dev_warn(dev, "UDC doesn't support Gen 1\n");
1458 break;
1459 case USB_SPEED_SUPER_PLUS:
1460 if ((DWC3_IP_IS(DWC32) &&
1461 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1462 (!DWC3_IP_IS(DWC32) &&
1463 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1464 dev_warn(dev, "UDC doesn't support SSP\n");
1465 break;
1466 default:
1467 dev_err(dev, "invalid maximum_speed parameter %d\n",
1468 dwc->maximum_speed);
1469 fallthrough;
1470 case USB_SPEED_UNKNOWN:
1471 switch (hwparam_gen) {
1472 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1473 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1474 break;
1475 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1476 if (DWC3_IP_IS(DWC32))
1477 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1478 else
1479 dwc->maximum_speed = USB_SPEED_SUPER;
1480 break;
1481 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1482 dwc->maximum_speed = USB_SPEED_HIGH;
1483 break;
1484 default:
1485 dwc->maximum_speed = USB_SPEED_SUPER;
1486 break;
1487 }
1488 break;
1489 }
1490 }
1491
dwc3_probe(struct platform_device * pdev)1492 static int dwc3_probe(struct platform_device *pdev)
1493 {
1494 struct device *dev = &pdev->dev;
1495 struct resource *res, dwc_res;
1496 struct dwc3 *dwc;
1497
1498 int ret;
1499
1500 void __iomem *regs;
1501
1502 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1503 if (!dwc)
1504 return -ENOMEM;
1505
1506 dwc->dev = dev;
1507
1508 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1509 if (!res) {
1510 dev_err(dev, "missing memory resource\n");
1511 return -ENODEV;
1512 }
1513
1514 dwc->xhci_resources[0].start = res->start;
1515 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1516 DWC3_XHCI_REGS_END;
1517 dwc->xhci_resources[0].flags = res->flags;
1518 dwc->xhci_resources[0].name = res->name;
1519
1520 /*
1521 * Request memory region but exclude xHCI regs,
1522 * since it will be requested by the xhci-plat driver.
1523 */
1524 dwc_res = *res;
1525 dwc_res.start += DWC3_GLOBALS_REGS_START;
1526
1527 regs = devm_ioremap_resource(dev, &dwc_res);
1528 if (IS_ERR(regs))
1529 return PTR_ERR(regs);
1530
1531 dwc->regs = regs;
1532 dwc->regs_size = resource_size(&dwc_res);
1533
1534 dwc3_get_properties(dwc);
1535
1536 dwc->reset = devm_reset_control_array_get(dev, true, true);
1537 if (IS_ERR(dwc->reset))
1538 return PTR_ERR(dwc->reset);
1539
1540 if (dev->of_node) {
1541 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1542 if (ret == -EPROBE_DEFER)
1543 return ret;
1544 /*
1545 * Clocks are optional, but new DT platforms should support all
1546 * clocks as required by the DT-binding.
1547 */
1548 if (ret < 0)
1549 dwc->num_clks = 0;
1550 else
1551 dwc->num_clks = ret;
1552
1553 }
1554
1555 ret = reset_control_deassert(dwc->reset);
1556 if (ret)
1557 return ret;
1558
1559 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1560 if (ret)
1561 goto assert_reset;
1562
1563 if (!dwc3_core_is_valid(dwc)) {
1564 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1565 ret = -ENODEV;
1566 goto disable_clks;
1567 }
1568
1569 platform_set_drvdata(pdev, dwc);
1570 dwc3_cache_hwparams(dwc);
1571
1572 spin_lock_init(&dwc->lock);
1573 mutex_init(&dwc->mutex);
1574
1575 pm_runtime_get_noresume(dev);
1576 pm_runtime_set_active(dev);
1577 pm_runtime_use_autosuspend(dev);
1578 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1579 pm_runtime_enable(dev);
1580
1581 pm_runtime_forbid(dev);
1582
1583 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1584 if (ret) {
1585 dev_err(dwc->dev, "failed to allocate event buffers\n");
1586 ret = -ENOMEM;
1587 goto err2;
1588 }
1589
1590 ret = dwc3_get_dr_mode(dwc);
1591 if (ret)
1592 goto err3;
1593
1594 ret = dwc3_alloc_scratch_buffers(dwc);
1595 if (ret)
1596 goto err3;
1597
1598 ret = dwc3_core_init(dwc);
1599 if (ret) {
1600 if (ret != -EPROBE_DEFER)
1601 dev_err(dev, "failed to initialize core: %d\n", ret);
1602 goto err4;
1603 }
1604
1605 dwc3_check_params(dwc);
1606 dwc3_debugfs_init(dwc);
1607
1608 ret = dwc3_core_init_mode(dwc);
1609 if (ret)
1610 goto err5;
1611
1612 pm_runtime_put(dev);
1613
1614 dma_set_max_seg_size(dev, UINT_MAX);
1615
1616 return 0;
1617
1618 err5:
1619 dwc3_debugfs_exit(dwc);
1620 dwc3_event_buffers_cleanup(dwc);
1621
1622 usb_phy_set_suspend(dwc->usb2_phy, 1);
1623 usb_phy_set_suspend(dwc->usb3_phy, 1);
1624 phy_power_off(dwc->usb2_generic_phy);
1625 phy_power_off(dwc->usb3_generic_phy);
1626
1627 usb_phy_shutdown(dwc->usb2_phy);
1628 usb_phy_shutdown(dwc->usb3_phy);
1629 phy_exit(dwc->usb2_generic_phy);
1630 phy_exit(dwc->usb3_generic_phy);
1631
1632 dwc3_ulpi_exit(dwc);
1633
1634 err4:
1635 dwc3_free_scratch_buffers(dwc);
1636
1637 err3:
1638 dwc3_free_event_buffers(dwc);
1639
1640 err2:
1641 pm_runtime_allow(dev);
1642 pm_runtime_disable(dev);
1643 pm_runtime_set_suspended(dev);
1644 pm_runtime_put_noidle(dev);
1645 disable_clks:
1646 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1647 assert_reset:
1648 reset_control_assert(dwc->reset);
1649
1650 return ret;
1651 }
1652
dwc3_remove(struct platform_device * pdev)1653 static int dwc3_remove(struct platform_device *pdev)
1654 {
1655 struct dwc3 *dwc = platform_get_drvdata(pdev);
1656
1657 pm_runtime_get_sync(&pdev->dev);
1658
1659 dwc3_core_exit_mode(dwc);
1660 dwc3_debugfs_exit(dwc);
1661
1662 dwc3_core_exit(dwc);
1663 dwc3_ulpi_exit(dwc);
1664
1665 pm_runtime_allow(&pdev->dev);
1666 pm_runtime_disable(&pdev->dev);
1667 pm_runtime_put_noidle(&pdev->dev);
1668 pm_runtime_set_suspended(&pdev->dev);
1669
1670 dwc3_free_event_buffers(dwc);
1671 dwc3_free_scratch_buffers(dwc);
1672
1673 return 0;
1674 }
1675
1676 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1677 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1678 {
1679 int ret;
1680
1681 ret = reset_control_deassert(dwc->reset);
1682 if (ret)
1683 return ret;
1684
1685 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1686 if (ret)
1687 goto assert_reset;
1688
1689 ret = dwc3_core_init(dwc);
1690 if (ret)
1691 goto disable_clks;
1692
1693 return 0;
1694
1695 disable_clks:
1696 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1697 assert_reset:
1698 reset_control_assert(dwc->reset);
1699
1700 return ret;
1701 }
1702
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1703 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1704 {
1705 unsigned long flags;
1706 u32 reg;
1707
1708 switch (dwc->current_dr_role) {
1709 case DWC3_GCTL_PRTCAP_DEVICE:
1710 if (pm_runtime_suspended(dwc->dev))
1711 break;
1712 spin_lock_irqsave(&dwc->lock, flags);
1713 dwc3_gadget_suspend(dwc);
1714 spin_unlock_irqrestore(&dwc->lock, flags);
1715 synchronize_irq(dwc->irq_gadget);
1716 dwc3_core_exit(dwc);
1717 break;
1718 case DWC3_GCTL_PRTCAP_HOST:
1719 if (!PMSG_IS_AUTO(msg)) {
1720 dwc3_core_exit(dwc);
1721 break;
1722 }
1723
1724 /* Let controller to suspend HSPHY before PHY driver suspends */
1725 if (dwc->dis_u2_susphy_quirk ||
1726 dwc->dis_enblslpm_quirk) {
1727 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1728 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1729 DWC3_GUSB2PHYCFG_SUSPHY;
1730 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1731
1732 /* Give some time for USB2 PHY to suspend */
1733 usleep_range(5000, 6000);
1734 }
1735
1736 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1737 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1738 break;
1739 case DWC3_GCTL_PRTCAP_OTG:
1740 /* do nothing during runtime_suspend */
1741 if (PMSG_IS_AUTO(msg))
1742 break;
1743
1744 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1745 spin_lock_irqsave(&dwc->lock, flags);
1746 dwc3_gadget_suspend(dwc);
1747 spin_unlock_irqrestore(&dwc->lock, flags);
1748 synchronize_irq(dwc->irq_gadget);
1749 }
1750
1751 dwc3_otg_exit(dwc);
1752 dwc3_core_exit(dwc);
1753 break;
1754 default:
1755 /* do nothing */
1756 break;
1757 }
1758
1759 return 0;
1760 }
1761
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1762 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1763 {
1764 unsigned long flags;
1765 int ret;
1766 u32 reg;
1767
1768 switch (dwc->current_dr_role) {
1769 case DWC3_GCTL_PRTCAP_DEVICE:
1770 ret = dwc3_core_init_for_resume(dwc);
1771 if (ret)
1772 return ret;
1773
1774 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1775 spin_lock_irqsave(&dwc->lock, flags);
1776 dwc3_gadget_resume(dwc);
1777 spin_unlock_irqrestore(&dwc->lock, flags);
1778 break;
1779 case DWC3_GCTL_PRTCAP_HOST:
1780 if (!PMSG_IS_AUTO(msg)) {
1781 ret = dwc3_core_init_for_resume(dwc);
1782 if (ret)
1783 return ret;
1784 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1785 break;
1786 }
1787 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1788 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1789 if (dwc->dis_u2_susphy_quirk)
1790 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1791
1792 if (dwc->dis_enblslpm_quirk)
1793 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1794
1795 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1796
1797 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1798 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1799 break;
1800 case DWC3_GCTL_PRTCAP_OTG:
1801 /* nothing to do on runtime_resume */
1802 if (PMSG_IS_AUTO(msg))
1803 break;
1804
1805 ret = dwc3_core_init_for_resume(dwc);
1806 if (ret)
1807 return ret;
1808
1809 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1810
1811 dwc3_otg_init(dwc);
1812 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1813 dwc3_otg_host_init(dwc);
1814 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1815 spin_lock_irqsave(&dwc->lock, flags);
1816 dwc3_gadget_resume(dwc);
1817 spin_unlock_irqrestore(&dwc->lock, flags);
1818 }
1819
1820 break;
1821 default:
1822 /* do nothing */
1823 break;
1824 }
1825
1826 return 0;
1827 }
1828
dwc3_runtime_checks(struct dwc3 * dwc)1829 static int dwc3_runtime_checks(struct dwc3 *dwc)
1830 {
1831 switch (dwc->current_dr_role) {
1832 case DWC3_GCTL_PRTCAP_DEVICE:
1833 if (dwc->connected)
1834 return -EBUSY;
1835 break;
1836 case DWC3_GCTL_PRTCAP_HOST:
1837 default:
1838 /* do nothing */
1839 break;
1840 }
1841
1842 return 0;
1843 }
1844
dwc3_runtime_suspend(struct device * dev)1845 static int dwc3_runtime_suspend(struct device *dev)
1846 {
1847 struct dwc3 *dwc = dev_get_drvdata(dev);
1848 int ret;
1849
1850 if (dwc3_runtime_checks(dwc))
1851 return -EBUSY;
1852
1853 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1854 if (ret)
1855 return ret;
1856
1857 device_init_wakeup(dev, true);
1858
1859 return 0;
1860 }
1861
dwc3_runtime_resume(struct device * dev)1862 static int dwc3_runtime_resume(struct device *dev)
1863 {
1864 struct dwc3 *dwc = dev_get_drvdata(dev);
1865 int ret;
1866
1867 device_init_wakeup(dev, false);
1868
1869 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1870 if (ret)
1871 return ret;
1872
1873 switch (dwc->current_dr_role) {
1874 case DWC3_GCTL_PRTCAP_DEVICE:
1875 dwc3_gadget_process_pending_events(dwc);
1876 break;
1877 case DWC3_GCTL_PRTCAP_HOST:
1878 default:
1879 /* do nothing */
1880 break;
1881 }
1882
1883 pm_runtime_mark_last_busy(dev);
1884
1885 return 0;
1886 }
1887
dwc3_runtime_idle(struct device * dev)1888 static int dwc3_runtime_idle(struct device *dev)
1889 {
1890 struct dwc3 *dwc = dev_get_drvdata(dev);
1891
1892 switch (dwc->current_dr_role) {
1893 case DWC3_GCTL_PRTCAP_DEVICE:
1894 if (dwc3_runtime_checks(dwc))
1895 return -EBUSY;
1896 break;
1897 case DWC3_GCTL_PRTCAP_HOST:
1898 default:
1899 /* do nothing */
1900 break;
1901 }
1902
1903 pm_runtime_mark_last_busy(dev);
1904 pm_runtime_autosuspend(dev);
1905
1906 return 0;
1907 }
1908 #endif /* CONFIG_PM */
1909
1910 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)1911 static int dwc3_suspend(struct device *dev)
1912 {
1913 struct dwc3 *dwc = dev_get_drvdata(dev);
1914 int ret;
1915
1916 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1917 if (ret)
1918 return ret;
1919
1920 pinctrl_pm_select_sleep_state(dev);
1921
1922 return 0;
1923 }
1924
dwc3_resume(struct device * dev)1925 static int dwc3_resume(struct device *dev)
1926 {
1927 struct dwc3 *dwc = dev_get_drvdata(dev);
1928 int ret;
1929
1930 pinctrl_pm_select_default_state(dev);
1931
1932 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1933 if (ret)
1934 return ret;
1935
1936 pm_runtime_disable(dev);
1937 pm_runtime_set_active(dev);
1938 pm_runtime_enable(dev);
1939
1940 return 0;
1941 }
1942
dwc3_complete(struct device * dev)1943 static void dwc3_complete(struct device *dev)
1944 {
1945 struct dwc3 *dwc = dev_get_drvdata(dev);
1946 u32 reg;
1947
1948 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1949 dwc->dis_split_quirk) {
1950 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1951 reg |= DWC3_GUCTL3_SPLITDISABLE;
1952 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1953 }
1954 }
1955 #else
1956 #define dwc3_complete NULL
1957 #endif /* CONFIG_PM_SLEEP */
1958
1959 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1960 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1961 .complete = dwc3_complete,
1962 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1963 dwc3_runtime_idle)
1964 };
1965
1966 #ifdef CONFIG_OF
1967 static const struct of_device_id of_dwc3_match[] = {
1968 {
1969 .compatible = "snps,dwc3"
1970 },
1971 {
1972 .compatible = "synopsys,dwc3"
1973 },
1974 { },
1975 };
1976 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1977 #endif
1978
1979 #ifdef CONFIG_ACPI
1980
1981 #define ACPI_ID_INTEL_BSW "808622B7"
1982
1983 static const struct acpi_device_id dwc3_acpi_match[] = {
1984 { ACPI_ID_INTEL_BSW, 0 },
1985 { },
1986 };
1987 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1988 #endif
1989
1990 static struct platform_driver dwc3_driver = {
1991 .probe = dwc3_probe,
1992 .remove = dwc3_remove,
1993 .driver = {
1994 .name = "dwc3",
1995 .of_match_table = of_match_ptr(of_dwc3_match),
1996 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1997 .pm = &dwc3_dev_pm_ops,
1998 },
1999 };
2000
2001 module_platform_driver(dwc3_driver);
2002
2003 MODULE_ALIAS("platform:dwc3");
2004 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2005 MODULE_LICENSE("GPL v2");
2006 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2007