1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 * Description: dyn mem driver.
15 *
16 * Create: 2023-04-09
17 */
18
19 #include <stdint.h>
20
21 #include "chip_io.h"
22 #include "dyn_mem.h"
23
24 /**
25 * @brief Definition of SHARE RAM Selections.
26 */
27 typedef enum {
28 SHARE_RAM_PKT_RAM = 0,
29 SHARE_RAM_BGLE = 1,
30 SHARE_RAM_ITCM = 2,
31 SHARE_RAM_DTCM = 3,
32 } pwm_action_t;
33
34 /**
35 * @brief This union represents the bit fields in the CFG_RAM_SEL register.
36 * Read the register into the <i>d32</i> member then
37 * set/clear the bits using the <i>b</i> elements.
38 */
39 typedef union cfg_ram_sel {
40 uint32_t d32; /*!< Raw register data. */
41 struct {
42 uint32_t cfg_ram12_sel : 1; /*!< RAM12 (size:2K) configuration:
43 1'b0:pkt_ram
44 1'b1:BGLE */
45 uint32_t reserved0 : 1; /*!< reserved. */
46 uint32_t cfg_ram11_sel : 2; /*!< RAM11 (size:16K) configuration
47 2'b00:pkt_ram
48 2'b01:BGLE
49 2'b10:ITCM
50 2'b11:DTCM */
51 uint32_t cfg_ram10_sel : 2; /*!< RAM10 (size:16K) configuration */
52 uint32_t cfg_ram9_sel : 2; /*!< RAM9 (size:32K) configuration */
53 uint32_t cfg_ram8_sel : 2; /*!< RAM8 (size:32K) configuration */
54 uint32_t cfg_ram7_sel : 2; /*!< RAM7 (size:64K) configuration */
55 uint32_t cfg_ram6_sel : 2; /*!< RAM6 (size:64K) configuration */
56 uint32_t cfg_ram5_sel : 2; /*!< RAM5 (size:64K) configuration */
57 uint32_t reserved1 : 16; /*!< reserved. */
58 } b;
59 } cfg_ram_sel_t;
60
61 #define OPEN_SHARE_RAM_CLOCK_MASK 0xFFFC00
62 #define CLOSE_SHARE_RAM_CLOCK_MASK 0xFF0003FF
63 /**
64 * @brief SHARE RAM configuration.
65 */
dyn_mem_cfg(void)66 __attribute__((section(".text.runtime.init"))) void dyn_mem_cfg(void)
67 {
68 uint32_t reg_data;
69 reg_data = readl(CFG_RAM_CKEN);
70 reg_data = reg_data & CLOSE_SHARE_RAM_CLOCK_MASK;
71 writel(CFG_RAM_CKEN, reg_data);
72 reg_setbit(BT_EM_GT_MODE, 0, 0);
73
74 cfg_ram_sel_t cfg;
75 cfg.d32 = readl(SHARE_RAM_CTL_CFG_RAM_SEL);
76
77 cfg.b.cfg_ram5_sel = SHARE_RAM_PKT_RAM;
78 cfg.b.cfg_ram6_sel = SHARE_RAM_PKT_RAM;
79 cfg.b.cfg_ram7_sel = SHARE_RAM_PKT_RAM;
80
81 #if defined(CONFIG_BGLE_RAM_SIZE_16K) && defined(WIFI_TCM_OPTIMIZE)
82 // pkt_ram 512K itcm: 64K dtcm: 16K bgle: 16K
83 cfg.b.cfg_ram8_sel = SHARE_RAM_ITCM;
84 cfg.b.cfg_ram9_sel = SHARE_RAM_ITCM;
85 cfg.b.cfg_ram10_sel = SHARE_RAM_DTCM;
86 cfg.b.cfg_ram11_sel = SHARE_RAM_BGLE;
87
88 #elif defined(CONFIG_BGLE_RAM_SIZE_16K)
89 // pkt_ram 544K itcm: 16K dtcm: 32K bgle: 16K
90 cfg.b.cfg_ram8_sel = SHARE_RAM_PKT_RAM;
91 cfg.b.cfg_ram9_sel = SHARE_RAM_DTCM;
92 cfg.b.cfg_ram10_sel = SHARE_RAM_ITCM;
93 cfg.b.cfg_ram11_sel = SHARE_RAM_BGLE;
94
95 #elif defined(CONFIG_BGLE_RAM_SIZE_32K)
96 // pkt_ram 544K itcm: 16K dtcm: 16K bgle: 32K
97 cfg.b.cfg_ram8_sel = SHARE_RAM_PKT_RAM;
98 cfg.b.cfg_ram9_sel = SHARE_RAM_BGLE;
99 cfg.b.cfg_ram10_sel = SHARE_RAM_DTCM;
100 cfg.b.cfg_ram11_sel = SHARE_RAM_ITCM;
101
102 #elif defined(CONFIG_BGLE_RAM_SIZE_64K) // btc-only
103 // pkt_ram 448K itcm: 32K dtcm: 64K bgle: 64K
104 cfg.b.cfg_ram7_sel = SHARE_RAM_DTCM;
105 cfg.b.cfg_ram8_sel = SHARE_RAM_BGLE;
106 cfg.b.cfg_ram9_sel = SHARE_RAM_BGLE;
107 cfg.b.cfg_ram10_sel = SHARE_RAM_ITCM;
108 cfg.b.cfg_ram11_sel = SHARE_RAM_ITCM;
109
110 #elif defined(WIFI_TCM_OPTIMIZE) // wifi-only
111 // pkt_ram 512K itcm: 64K dtcm: 32K bgle: 0K
112 cfg.b.cfg_ram8_sel = SHARE_RAM_ITCM;
113 cfg.b.cfg_ram9_sel = SHARE_RAM_ITCM;
114 cfg.b.cfg_ram10_sel = SHARE_RAM_DTCM;
115 cfg.b.cfg_ram11_sel = SHARE_RAM_DTCM;
116
117 #else
118 // default cfg: pkt_ram 576K itcm: 16K dtcm: 16K bgle: 0K
119 cfg.b.cfg_ram8_sel = SHARE_RAM_PKT_RAM;
120 cfg.b.cfg_ram9_sel = SHARE_RAM_PKT_RAM;
121 cfg.b.cfg_ram10_sel = SHARE_RAM_DTCM;
122 cfg.b.cfg_ram11_sel = SHARE_RAM_ITCM;
123 #endif
124 writel(SHARE_RAM_CTL_CFG_RAM_SEL, cfg.d32);
125
126 reg_data = readl(CFG_RAM_CKEN);
127 reg_data = reg_data | OPEN_SHARE_RAM_CLOCK_MASK;
128 writel(CFG_RAM_CKEN, reg_data);
129 reg_clrbit(BT_EM_GT_MODE, 0, 0);
130 return;
131 }
132
133