1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: Interrupt DRIVER 15 * 16 * Create: 2021-10-13 17 */ 18 #include "stdint.h" 19 #include "chip_core_irq.h" 20 #if defined(__LITEOS__) 21 #include "los_hwi.h" 22 #elif defined(__FREERTOS__) 23 #include "FreeRTOS.h" 24 #include "hwi.h" 25 #elif defined(__ALIOS__) 26 #include "hwi_irq.h" 27 #endif 28 29 const uint8_t m_auc_int_pri[BUTT_IRQN] = { 30 #if defined(__LITEOS__) 31 LOSCFG_HWI_PRIO_LIMIT, // USER_SOFTWARE_INT_IRQn = 0, 32 LOSCFG_HWI_PRIO_LIMIT, // SUPERVISOR_SOFTWARE_INT_IRQn = 1, 33 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT2_IRQn = 2, 34 LOSCFG_HWI_PRIO_LIMIT, // MACHINE_SOFTWARE_INT_IRQn = 3, 35 LOSCFG_HWI_PRIO_LIMIT, // USER_TIMER_INT_IRQn = 4, 36 LOSCFG_HWI_PRIO_LIMIT, // SUPERVISOR_TIMER_INT_IRQn = 5, 37 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT6_IRQn = 6, 38 LOSCFG_HWI_PRIO_LIMIT, // MACHINE_TIMER_INT_IRQn = 7, 39 LOSCFG_HWI_PRIO_LIMIT, // USER_EXTERNAL_INT_IRQn = 8, 40 LOSCFG_HWI_PRIO_LIMIT, // SUPERVISOR_EXTERNAL_INT_IRQn = 9, 41 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT10_IRQn = 10, 42 OS_HWI_PRIO_LOWEST, // MACHINE_EXTERNAL_INT_IRQn = 11, 43 OS_HWI_PRIO_HIGHEST, // NON_MASKABLE_INT_IRQn = 12, 44 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT13_IRQn = 13, 45 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT14_IRQn = 14, 46 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT15_IRQn = 15, 47 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT16_IRQn = 16, 48 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT17_IRQn = 17, 49 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT18_IRQn = 18, 50 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT19_IRQn = 19, 51 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT20_IRQn = 20, 52 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT21_IRQn = 21, 53 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT22_IRQn = 22, 54 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT23_IRQn = 23, 55 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT24_IRQn = 23, 56 LOSCFG_HWI_PRIO_LIMIT, // RESERVED_INT25_IRQn = 25, 57 58 OS_HWI_PRIO_LOWEST, // RESERVED_INT0_IRQn = 0, 59 OS_HWI_PRIO_LOWEST, // RESERVED_INT1_IRQn = 1, 60 OS_HWI_PRIO_LOWEST - 1, // MCU_INT0_IRQN = 2, 61 OS_HWI_PRIO_LOWEST, // MCU_INT1_IRQN = 3, 62 OS_HWI_PRIO_LOWEST, // RESERVED_INT4_IRQn = 4, 63 OS_HWI_PRIO_LOWEST, // RESERVED_INT5_IRQn = 5, 64 OS_HWI_PRIO_LOWEST, // RESERVED_INT6_IRQn = 6, 65 OS_HWI_PRIO_LOWEST, // RESERVED_INT7_IRQn = 7, 66 OS_HWI_PRIO_LOWEST, // GPIO_0_IRQN = 8, 67 OS_HWI_PRIO_LOWEST, // GPIO_1_IRQN = 9, 68 OS_HWI_PRIO_LOWEST, // RESERVED_INT10_IRQn = 10, 69 OS_HWI_PRIO_LOWEST, // RESERVED_INT11_IRQn = 11, 70 OS_HWI_PRIO_LOWEST, // RESERVED_INT12_IRQn = 12, 71 OS_HWI_PRIO_LOWEST, // UART_L0_IRQn = 13, 72 OS_HWI_PRIO_LOWEST, // RESERVED_INT14_IRQn = 14, 73 OS_HWI_PRIO_LOWEST - 2, // UART_H0_IRQn = 15, 74 OS_HWI_PRIO_LOWEST, // UART_H1_IRQn = 16, 75 OS_HWI_PRIO_LOWEST, // QSPI0_2CS_IRQN = 17, 76 OS_HWI_PRIO_LOWEST, // QSPI1_2CS_IRQN = 18, 77 OS_HWI_PRIO_LOWEST, // SPI4_S_IRQN = 19, 78 OS_HWI_PRIO_LOWEST - 1, // KEY_SCAN_IRQN = 20, 79 OS_HWI_PRIO_LOWEST - 1, // M_WAKEUP_IRQN = 21, 80 OS_HWI_PRIO_LOWEST, // M_SLEEP_IRQN = 22, 81 OS_HWI_PRIO_LOWEST, // RTC_0_IRQN = 23, 82 OS_HWI_PRIO_LOWEST, // RTC_1_IRQN = 24, 83 OS_HWI_PRIO_LOWEST, // RTC_2_IRQN = 25, 84 OS_HWI_PRIO_LOWEST, // RTC_3_IRQN = 26, 85 OS_HWI_PRIO_LOWEST - 1, // TIMER_0_IRQN = 27, 86 OS_HWI_PRIO_LOWEST - 1, // TIMER_1_IRQN = 28, 87 OS_HWI_PRIO_LOWEST - 1, // TIMER_2_IRQN = 29, 88 OS_HWI_PRIO_LOWEST, // TIMER_3_IRQN = 30, 89 OS_HWI_PRIO_LOWEST, // M_SDMA_IRQN = 31, 90 OS_HWI_PRIO_LOWEST, // M_DMA_IRQN = 32, 91 OS_HWI_PRIO_LOWEST, // SPI_M_S_0_IRQN = 33, 92 OS_HWI_PRIO_LOWEST, // SPI_M_S_1_IRQN = 34, 93 OS_HWI_PRIO_LOWEST, // SPI_M_IRQN = 35, 94 OS_HWI_PRIO_LOWEST, // I2C_0_IRQN = 36, 95 OS_HWI_PRIO_LOWEST, // I2C_1_IRQN = 37, 96 OS_HWI_PRIO_LOWEST, // I2C_2_IRQN = 38, 97 OS_HWI_PRIO_LOWEST, // SPI3_MS_IRQN = 39, 98 OS_HWI_PRIO_LOWEST, // EFLASH_INT_IRQN = 40, 99 OS_HWI_PRIO_LOWEST, // RESERVED_INT41_IRQn = 41, 100 OS_HWI_PRIO_LOWEST - 3, // RESERVED_INT42_IRQn = 42, 101 OS_HWI_PRIO_LOWEST, // RESERVED_INT43_IRQn = 43, 102 OS_HWI_PRIO_LOWEST, // SEC_INT_IRQN = 44, 103 OS_HWI_PRIO_LOWEST, // PWM_0_IRQN = 45, 104 OS_HWI_PRIO_LOWEST, // PWM_1_IRQN = 46 105 #elif defined(__FREERTOS__) 106 configHWI_PRIO_LIMIT, // USER_SOFTWARE_INT_IRQn = 0, 107 configHWI_PRIO_LIMIT, // SUPERVISOR_SOFTWARE_INT_IRQn = 1, 108 configHWI_PRIO_LIMIT, // RESERVED_INT2_IRQn = 2, 109 configHWI_PRIO_LIMIT, // MACHINE_SOFTWARE_INT_IRQn = 3, 110 configHWI_PRIO_LIMIT, // USER_TIMER_INT_IRQn = 4, 111 configHWI_PRIO_LIMIT, // SUPERVISOR_TIMER_INT_IRQn = 5, 112 configHWI_PRIO_LIMIT, // RESERVED_INT6_IRQn = 6, 113 configHWI_PRIO_LIMIT, // MACHINE_TIMER_INT_IRQn = 7, 114 configHWI_PRIO_LIMIT, // USER_EXTERNAL_INT_IRQn = 8, 115 configHWI_PRIO_LIMIT, // SUPERVISOR_EXTERNAL_INT_IRQn = 9, 116 configHWI_PRIO_LIMIT, // RESERVED_INT10_IRQn = 10, 117 configHWI_PRIO_LOWEST, // MACHINE_EXTERNAL_INT_IRQn = 11, 118 configHWI_PRIO_HIGHEST, // NON_MASKABLE_INT_IRQn = 12, 119 configHWI_PRIO_LIMIT, // RESERVED_INT13_IRQn = 13, 120 configHWI_PRIO_LIMIT, // RESERVED_INT14_IRQn = 14, 121 configHWI_PRIO_LIMIT, // RESERVED_INT15_IRQn = 15, 122 configHWI_PRIO_LIMIT, // RESERVED_INT16_IRQn = 16, 123 configHWI_PRIO_LIMIT, // RESERVED_INT17_IRQn = 17, 124 configHWI_PRIO_LIMIT, // RESERVED_INT18_IRQn = 18, 125 configHWI_PRIO_LIMIT, // RESERVED_INT19_IRQn = 19, 126 configHWI_PRIO_LIMIT, // RESERVED_INT20_IRQn = 20, 127 configHWI_PRIO_LIMIT, // RESERVED_INT21_IRQn = 21, 128 configHWI_PRIO_LIMIT, // RESERVED_INT22_IRQn = 22, 129 configHWI_PRIO_LIMIT, // RESERVED_INT23_IRQn = 23, 130 configHWI_PRIO_LIMIT, // RESERVED_INT24_IRQn = 23, 131 configHWI_PRIO_LIMIT, // RESERVED_INT25_IRQn = 25, 132 133 configHWI_PRIO_LOWEST, // RESERVED_INT0_IRQn = 0, 134 configHWI_PRIO_LOWEST, // RESERVED_INT1_IRQn = 1, 135 configHWI_PRIO_LOWEST - 1, // MCU_INT0_IRQN = 2, 136 configHWI_PRIO_LOWEST, // MCU_INT1_IRQN = 3, 137 configHWI_PRIO_LOWEST, // RESERVED_INT4_IRQn = 4, 138 configHWI_PRIO_LOWEST, // RESERVED_INT5_IRQn = 5, 139 configHWI_PRIO_LOWEST, // RESERVED_INT6_IRQn = 6, 140 configHWI_PRIO_LOWEST, // RESERVED_INT7_IRQn = 7, 141 configHWI_PRIO_LOWEST, // GPIO_0_IRQN = 8, 142 configHWI_PRIO_LOWEST, // GPIO_1_IRQN = 9, 143 configHWI_PRIO_LOWEST, // RESERVED_INT10_IRQn = 10, 144 configHWI_PRIO_LOWEST, // RESERVED_INT11_IRQn = 11, 145 configHWI_PRIO_LOWEST, // RESERVED_INT12_IRQn = 12, 146 configHWI_PRIO_LOWEST, // UART_L0_IRQn = 13, 147 configHWI_PRIO_LOWEST, // RESERVED_INT14_IRQn = 14, 148 configHWI_PRIO_LOWEST - 2, // UART_H0_IRQn = 15, 149 configHWI_PRIO_LOWEST, // UART_H1_IRQn = 16, 150 configHWI_PRIO_LOWEST, // QSPI0_2CS_IRQN = 17, 151 configHWI_PRIO_LOWEST, // QSPI1_2CS_IRQN = 18, 152 configHWI_PRIO_LOWEST, // SPI4_S_IRQN = 19, 153 configHWI_PRIO_LOWEST - 1, // KEY_SCAN_IRQN = 20, 154 configHWI_PRIO_LOWEST - 1, // M_WAKEUP_IRQN = 21, 155 configHWI_PRIO_LOWEST, // M_SLEEP_IRQN = 22, 156 configHWI_PRIO_LOWEST, // RTC_0_IRQN = 23, 157 configHWI_PRIO_LOWEST, // RTC_1_IRQN = 24, 158 configHWI_PRIO_LOWEST, // RTC_2_IRQN = 25, 159 configHWI_PRIO_LOWEST, // RTC_3_IRQN = 26, 160 configHWI_PRIO_LOWEST - 1, // TIMER_0_IRQN = 27, 161 configHWI_PRIO_LOWEST - 1, // TIMER_1_IRQN = 28, 162 configHWI_PRIO_LOWEST - 1, // TIMER_2_IRQN = 29, 163 configHWI_PRIO_LOWEST, // TIMER_3_IRQN = 30, 164 configHWI_PRIO_LOWEST, // M_SDMA_IRQN = 31, 165 configHWI_PRIO_LOWEST, // M_DMA_IRQN = 32, 166 configHWI_PRIO_LOWEST, // SPI_M_S_0_IRQN = 33, 167 configHWI_PRIO_LOWEST, // SPI_M_S_1_IRQN = 34, 168 configHWI_PRIO_LOWEST, // SPI_M_IRQN = 35, 169 configHWI_PRIO_LOWEST, // I2C_0_IRQN = 36, 170 configHWI_PRIO_LOWEST, // I2C_1_IRQN = 37, 171 configHWI_PRIO_LOWEST, // I2C_2_IRQN = 38, 172 configHWI_PRIO_LOWEST, // SPI3_MS_IRQN = 39, 173 configHWI_PRIO_LOWEST, // EFLASH_INT_IRQN = 40, 174 configHWI_PRIO_LOWEST, // RESERVED_INT41_IRQn = 41, 175 configHWI_PRIO_LOWEST - 3, // RESERVED_INT42_IRQn = 42, 176 configHWI_PRIO_LOWEST, // RESERVED_INT43_IRQn = 43, 177 configHWI_PRIO_LOWEST, // SEC_INT_IRQN = 44, 178 configHWI_PRIO_LOWEST, // PWM_0_IRQN = 45, 179 configHWI_PRIO_LOWEST, // PWM_1_IRQN = 46 180 #elif defined(__ALIOS__) 181 HWI_PRIO_LIMIT, // USER_SOFTWARE_INT_IRQn = 0, 182 HWI_PRIO_LIMIT, // SUPERVISOR_SOFTWARE_INT_IRQn = 1, 183 HWI_PRIO_LIMIT, // RESERVED_INT2_IRQn = 2, 184 HWI_PRIO_LIMIT, // MACHINE_SOFTWARE_INT_IRQn = 3, 185 HWI_PRIO_LIMIT, // USER_TIMER_INT_IRQn = 4, 186 HWI_PRIO_LIMIT, // SUPERVISOR_TIMER_INT_IRQn = 5, 187 HWI_PRIO_LIMIT, // RESERVED_INT6_IRQn = 6, 188 HWI_PRIO_LIMIT, // MACHINE_TIMER_INT_IRQn = 7, 189 HWI_PRIO_LIMIT, // USER_EXTERNAL_INT_IRQn = 8, 190 HWI_PRIO_LIMIT, // SUPERVISOR_EXTERNAL_INT_IRQn = 9, 191 HWI_PRIO_LIMIT, // RESERVED_INT10_IRQn = 10, 192 HWI_PRIO_LOWEST, // MACHINE_EXTERNAL_INT_IRQn = 11, 193 HWI_PRIO_HIGHEST, // NON_MASKABLE_INT_IRQn = 12, 194 HWI_PRIO_LIMIT, // RESERVED_INT13_IRQn = 13, 195 HWI_PRIO_LIMIT, // RESERVED_INT14_IRQn = 14, 196 HWI_PRIO_LIMIT, // RESERVED_INT15_IRQn = 15, 197 HWI_PRIO_LIMIT, // RESERVED_INT16_IRQn = 16, 198 HWI_PRIO_LIMIT, // RESERVED_INT17_IRQn = 17, 199 HWI_PRIO_LIMIT, // RESERVED_INT18_IRQn = 18, 200 HWI_PRIO_LIMIT, // RESERVED_INT19_IRQn = 19, 201 HWI_PRIO_LIMIT, // RESERVED_INT20_IRQn = 20, 202 HWI_PRIO_LIMIT, // RESERVED_INT21_IRQn = 21, 203 HWI_PRIO_LIMIT, // RESERVED_INT22_IRQn = 22, 204 HWI_PRIO_LIMIT, // RESERVED_INT23_IRQn = 23, 205 HWI_PRIO_LIMIT, // RESERVED_INT24_IRQn = 23, 206 HWI_PRIO_LIMIT, // RESERVED_INT25_IRQn = 25, 207 208 HWI_PRIO_LOWEST, // RESERVED_INT0_IRQn = 0, 209 HWI_PRIO_LOWEST, // RESERVED_INT1_IRQn = 1, 210 HWI_PRIO_LOWEST - 1, // MCU_INT0_IRQN = 2, 211 HWI_PRIO_LOWEST, // MCU_INT1_IRQN = 3, 212 HWI_PRIO_LOWEST, // RESERVED_INT4_IRQn = 4, 213 HWI_PRIO_LOWEST, // RESERVED_INT5_IRQn = 5, 214 HWI_PRIO_LOWEST, // RESERVED_INT6_IRQn = 6, 215 HWI_PRIO_LOWEST, // RESERVED_INT7_IRQn = 7, 216 HWI_PRIO_LOWEST, // GPIO_0_IRQN = 8, 217 HWI_PRIO_LOWEST, // GPIO_1_IRQN = 9, 218 HWI_PRIO_LOWEST, // RESERVED_INT10_IRQn = 10, 219 HWI_PRIO_LOWEST, // RESERVED_INT11_IRQn = 11, 220 HWI_PRIO_LOWEST, // RESERVED_INT12_IRQn = 12, 221 HWI_PRIO_LOWEST, // UART_L0_IRQn = 13, 222 HWI_PRIO_LOWEST, // RESERVED_INT14_IRQn = 14, 223 HWI_PRIO_LOWEST - 2, // UART_H0_IRQn = 15, 224 HWI_PRIO_LOWEST, // UART_H1_IRQn = 16, 225 HWI_PRIO_LOWEST, // QSPI0_2CS_IRQN = 17, 226 HWI_PRIO_LOWEST, // QSPI1_2CS_IRQN = 18, 227 HWI_PRIO_LOWEST, // SPI4_S_IRQN = 19, 228 HWI_PRIO_LOWEST - 1, // KEY_SCAN_IRQN = 20, 229 HWI_PRIO_LOWEST - 1, // M_WAKEUP_IRQN = 21, 230 HWI_PRIO_LOWEST, // M_SLEEP_IRQN = 22, 231 HWI_PRIO_LOWEST, // RTC_0_IRQN = 23, 232 HWI_PRIO_LOWEST, // RTC_1_IRQN = 24, 233 HWI_PRIO_LOWEST, // RTC_2_IRQN = 25, 234 HWI_PRIO_LOWEST, // RTC_3_IRQN = 26, 235 HWI_PRIO_LOWEST - 1, // TIMER_0_IRQN = 27, 236 HWI_PRIO_LOWEST - 1, // TIMER_1_IRQN = 28, 237 HWI_PRIO_LOWEST - 1, // TIMER_2_IRQN = 29, 238 HWI_PRIO_LOWEST, // TIMER_3_IRQN = 30, 239 HWI_PRIO_LOWEST, // M_SDMA_IRQN = 31, 240 HWI_PRIO_LOWEST, // M_DMA_IRQN = 32, 241 HWI_PRIO_LOWEST, // SPI_M_S_0_IRQN = 33, 242 HWI_PRIO_LOWEST, // SPI_M_S_1_IRQN = 34, 243 HWI_PRIO_LOWEST, // SPI_M_IRQN = 35, 244 HWI_PRIO_LOWEST, // I2C_0_IRQN = 36, 245 HWI_PRIO_LOWEST, // I2C_1_IRQN = 37, 246 HWI_PRIO_LOWEST, // I2C_2_IRQN = 38, 247 HWI_PRIO_LOWEST, // SPI3_MS_IRQN = 39, 248 HWI_PRIO_LOWEST, // EFLASH_INT_IRQN = 40, 249 HWI_PRIO_LOWEST, // RESERVED_INT41_IRQn = 41, 250 HWI_PRIO_LOWEST - 3, // RESERVED_INT42_IRQn = 42, 251 HWI_PRIO_LOWEST, // RESERVED_INT43_IRQn = 43, 252 HWI_PRIO_LOWEST, // SEC_INT_IRQN = 44, 253 HWI_PRIO_LOWEST, // PWM_0_IRQN = 45, 254 HWI_PRIO_LOWEST, // PWM_1_IRQN = 46 255 #endif 256 }; 257