1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: Hi113X Vector Table Definitions 15 * 16 * Create: 2018-10-15 17 */ 18 #ifndef VECTORS_H 19 #define VECTORS_H 20 21 #include <stdint.h> 22 #include "core.h" 23 #include "interrupt_porting.h" 24 25 /** @addtogroup connectivity_config_vectors VECTORS 26 * @{ 27 */ 28 /** 29 * @brief Defined to be the highest ISR_VECTOR supported by the core 30 */ 31 #define ISR_VECTOR_MAX_SUPPORTED (BUTT_IRQN - 1) 32 33 #define LOCIEN_IRQ_NUM 32 34 #define LOCIPRI_IRQ_NUM 8 35 #define LOCIPRI_IRQ_BITS 4 36 #define LOCIPRI_DEFAULT_VAL 0x11111111 /* The default interrupt priority is 1. */ 37 38 /** 39 * Highest priority of a hardware interrupt. 40 */ 41 #define INTERRUPT_PRIO_HIGHEST 7 42 43 /** 44 * Lowest priority of a hardware interrupt. 45 */ 46 #define INTERRUPT_PRIO_LOWEST 1 47 48 /** 49 * Count of HimiDeer system interrupt vector. 50 */ 51 #define RISCV_SYS_VECTOR_CNT 26 52 53 /** 54 * Count of HimiDeer local interrupt vector 0 - 5, enabled by CSR mie 26 -31 bit. 55 */ 56 #define RISCV_MIE_IRQ_VECTOR_CNT 6 57 58 /** 59 * Count of HimiDeer local interrupt vector 6~76, enabled by custom CSR locie0~2. 60 */ 61 #define RISCV_CUSTOM_IRQ_VECTOR_CNT 60 62 63 /** 64 * Count of HimiDeer local IRQ interrupt vector. 65 */ 66 #define RISCV_LOCAL_IRQ_VECTOR_CNT (RISCV_MIE_IRQ_VECTOR_CNT + RISCV_SYS_VECTOR_CNT) 67 68 /** 69 * Count of himideer interrupt vector. 70 */ 71 #define RISCV_VECTOR_CNT (RISCV_LOCAL_IRQ_VECTOR_CNT + RISCV_CUSTOM_IRQ_VECTOR_CNT) 72 73 /** 74 * @brief Interrupt vector identifiers 75 */ 76 typedef enum { 77 USER_SOFTWARE_INT_IRQN = 0, // !< RISCV Trap Entry 78 SUPERVISOR_SOFTWARE_INT_IRQN = 1, 79 RESERVED_INT2_IRQN = 2, 80 MACHINE_SOFTWARE_INT_IRQN = 3, 81 USER_TIMER_INT_IRQN = 4, 82 SUPERVISOR_TIMER_INT_IRQN = 5, 83 RESERVED_INT6_IRQN = 6, 84 MACHINE_TIMER_INT_IRQN = 7, 85 USER_EXTERNAL_INT_IRQN = 8, 86 SUPERVISOR_EXTERNAL_INT_IRQN = 9, 87 RESERVED_INT10_IRQN = 10, 88 MACHINE_EXTERNAL_INT_IRQN = 11, 89 NON_MASKABLE_INT_IRQN = 12, // !< RISCV NMI vector 90 RESERVED_INT13_IRQN = 13, 91 RESERVED_INT14_IRQN = 14, 92 RESERVED_INT15_IRQN = 15, 93 #if ARCH == RISCV70 94 ISR_VECTOR_IRQ_0 = 16, // !< RISCV Local Interrupt request 0 vector 95 #else 96 RESERVED_INT16_IRQN = 16, 97 RESERVED_INT17_IRQN = 17, 98 RESERVED_INT18_IRQN = 18, 99 RESERVED_INT19_IRQN = 19, 100 RESERVED_INT20_IRQN = 20, 101 RESERVED_INT21_IRQN = 21, 102 RESERVED_INT22_IRQN = 22, 103 RESERVED_INT23_IRQN = 23, 104 RESERVED_INT24_IRQN = 24, 105 RESERVED_INT25_IRQN = 25, 106 ISR_VECTOR_IRQ_0 = 26, // !< RISCV Local Interrupt request 0 vector 107 #endif 108 ISR_VECTOR_IRQ_1, // !< RISCV Local Interrupt request 1 vector 109 ISR_VECTOR_IRQ_2, // !< RISCV Local Interrupt request 2 vector 110 ISR_VECTOR_IRQ_3, // !< RISCV Local Interrupt request 3 vector 111 ISR_VECTOR_IRQ_4, // !< RISCV Local Interrupt request 4 vector 112 ISR_VECTOR_IRQ_5, // !< RISCV Local Interrupt request 5 vector 113 ISR_VECTOR_IRQ_6, // !< RISCV Local Interrupt request 6 vector 114 ISR_VECTOR_IRQ_7, // !< RISCV Local Interrupt request 7 vector 115 ISR_VECTOR_IRQ_8, // !< RISCV Local Interrupt request 8 vector 116 ISR_VECTOR_IRQ_9, // !< RISCV Local Interrupt request 9 vector 117 ISR_VECTOR_IRQ_10, // !< RISCV Local Interrupt request 10 vector 118 ISR_VECTOR_IRQ_11, // !< RISCV Local Interrupt request 11 vector 119 ISR_VECTOR_IRQ_12, // !< RISCV Local Interrupt request 12 vector 120 ISR_VECTOR_IRQ_13, // !< RISCV Local Interrupt request 13 vector 121 ISR_VECTOR_IRQ_14, // !< RISCV Local Interrupt request 14 vector 122 ISR_VECTOR_IRQ_15, // !< RISCV Local Interrupt request 15 vector 123 ISR_VECTOR_IRQ_16, // !< RISCV Local Interrupt request 16 vector 124 ISR_VECTOR_IRQ_17, // !< RISCV Local Interrupt request 17 vector 125 ISR_VECTOR_IRQ_18, // !< RISCV Local Interrupt request 18 vector 126 ISR_VECTOR_IRQ_19, // !< RISCV Local Interrupt request 19 vector 127 ISR_VECTOR_IRQ_20, // !< RISCV Local Interrupt request 20 vector 128 ISR_VECTOR_IRQ_21, // !< RISCV Local Interrupt request 21 vector 129 ISR_VECTOR_IRQ_22, // !< RISCV Local Interrupt request 22 vector 130 ISR_VECTOR_IRQ_23, // !< RISCV Local Interrupt request 23 vector 131 ISR_VECTOR_IRQ_24, // !< RISCV Local Interrupt request 24 vector 132 ISR_VECTOR_IRQ_25, // !< RISCV Local Interrupt request 25 vector 133 134 ISR_VECTOR_IRQ_26, // !< RISCV Local Interrupt request 26 vector 135 ISR_VECTOR_IRQ_27, // !< RISCV Local Interrupt request 27 vector 136 ISR_VECTOR_IRQ_28, // !< RISCV Local Interrupt request 28 vector 137 ISR_VECTOR_IRQ_29, // !< RISCV Local Interrupt request 29 vector 138 ISR_VECTOR_IRQ_30, // !< RISCV Local Interrupt request 30 vector 139 ISR_VECTOR_IRQ_31, // !< RISCV Local Interrupt request 31 vector 140 141 ISR_VECTOR_IRQ_32, // !< RISCV External Interrupt request 32 vector 142 ISR_VECTOR_IRQ_33, // !< RISCV External Interrupt request 33 vector 143 ISR_VECTOR_IRQ_34, // !< RISCV External Interrupt request 34 vector 144 ISR_VECTOR_IRQ_35, // !< RISCV External Interrupt request 35 vector 145 ISR_VECTOR_IRQ_36, // !< RISCV External Interrupt request 36 vector 146 ISR_VECTOR_IRQ_37, // !< RISCV External Interrupt request 37 vector 147 ISR_VECTOR_IRQ_38, // !< RISCV External Interrupt request 38 vector 148 ISR_VECTOR_IRQ_39, // !< RISCV External Interrupt request 39 vector 149 ISR_VECTOR_IRQ_40, // !< RISCV External Interrupt request 40 vector 150 ISR_VECTOR_IRQ_41, // !< RISCV External Interrupt request 41 vector 151 ISR_VECTOR_IRQ_42, // !< RISCV External Interrupt request 42 vector 152 ISR_VECTOR_IRQ_43, // !< RISCV External Interrupt request 43 vector 153 ISR_VECTOR_IRQ_44, // !< RISCV External Interrupt request 44 vector 154 ISR_VECTOR_IRQ_45, // !< RISCV External Interrupt request 45 vector 155 ISR_VECTOR_IRQ_46, // !< RISCV External Interrupt request 46 vector 156 ISR_VECTOR_IRQ_47, // !< RISCV External Interrupt request 47 vector 157 ISR_VECTOR_IRQ_48, // !< RISCV External Interrupt request 48 vector 158 ISR_VECTOR_IRQ_49, // !< RISCV External Interrupt request 49 vector 159 ISR_VECTOR_IRQ_50, // !< RISCV External Interrupt request 50 vector 160 ISR_VECTOR_IRQ_51, // !< RISCV External Interrupt request 51 vector 161 ISR_VECTOR_IRQ_52, // !< RISCV External Interrupt request 52 vector 162 ISR_VECTOR_IRQ_53, // !< RISCV External Interrupt request 53 vector 163 ISR_VECTOR_IRQ_54, // !< RISCV External Interrupt request 54 vector 164 ISR_VECTOR_IRQ_55, // !< RISCV External Interrupt request 55 vector 165 ISR_VECTOR_IRQ_56, // !< RISCV External Interrupt request 56 vector 166 ISR_VECTOR_IRQ_57, // !< RISCV External Interrupt request 57 vector 167 ISR_VECTOR_IRQ_58, // !< RISCV External Interrupt request 58 vector 168 ISR_VECTOR_IRQ_59, // !< RISCV External Interrupt request 59 vector 169 ISR_VECTOR_IRQ_60, // !< RISCV External Interrupt request 60 vector 170 ISR_VECTOR_IRQ_61, // !< RISCV External Interrupt request 61 vector 171 ISR_VECTOR_IRQ_62, // !< RISCV External Interrupt request 62 vector 172 ISR_VECTOR_IRQ_63, // !< RISCV External Interrupt request 63 vector 173 ISR_VECTOR_IRQ_64, // !< RISCV External Interrupt request 64 vector 174 ISR_VECTOR_IRQ_65, // !< RISCV External Interrupt request 65 vector 175 ISR_VECTOR_IRQ_66, // !< RISCV External Interrupt request 66 vector 176 ISR_VECTOR_IRQ_67, // !< RISCV External Interrupt request 67 vector 177 ISR_VECTOR_IRQ_68, // !< RISCV External Interrupt request 68 vector 178 ISR_VECTOR_IRQ_69, // !< RISCV External Interrupt request 69 vector 179 ISR_VECTOR_IRQ_70, // !< RISCV External Interrupt request 70 vector 180 ISR_VECTOR_IRQ_71, // !< RISCV External Interrupt request 71 vector 181 ISR_VECTOR_IRQ_72, // !< RISCV External Interrupt request 72 vector 182 ISR_VECTOR_IRQ_73, // !< RISCV External Interrupt request 73 vector 183 ISR_VECTOR_IRQ_74, // !< RISCV External Interrupt request 74 vector 184 ISR_VECTOR_IRQ_75, // !< RISCV External Interrupt request 75 vector 185 ISR_VECTOR_IRQ_76, // !< RISCV External Interrupt request 76 vector 186 ISR_VECTOR_IRQ_77, // !< RISCV External Interrupt request 77 vector 187 ISR_VECTOR_IRQ_78, // !< RISCV External Interrupt request 78 vector 188 ISR_VECTOR_IRQ_79, // !< RISCV External Interrupt request 79 vector 189 ISR_VECTOR_IRQ_80, // !< RISCV External Interrupt request 80 vector 190 ISR_VECTOR_IRQ_81, // !< RISCV External Interrupt request 81 vector 191 } isr_vector_t; 192 193 /** 194 * @brief Get the ram exception table address. 195 * @return The ram exception table address. 196 */ 197 const isr_function* isr_get_ramexceptiontable_addr(void); 198 199 typedef struct { 200 uint32_t mstatus; 201 uint32_t mepc; 202 uint32_t tp; /* X4 */ 203 uint32_t sp; /* X2 */ 204 205 uint32_t s11; /* X27 */ 206 uint32_t s10; /* X26 */ 207 uint32_t s9; /* X25 */ 208 uint32_t s8; /* X24 */ 209 uint32_t s7; /* X23 */ 210 uint32_t s6; /* X22 */ 211 uint32_t s5; /* X21 */ 212 uint32_t s4; /* X20 */ 213 uint32_t s3; /* X19 */ 214 uint32_t s2; /* X18 */ 215 216 uint32_t s1; /* X9 */ 217 uint32_t s0; /* X8 */ 218 219 uint32_t t6; /* X31 */ 220 uint32_t t5; /* X30 */ 221 uint32_t t4; /* X29 */ 222 uint32_t t3; /* X28 */ 223 224 uint32_t a7; /* X17 */ 225 uint32_t a6; /* X16 */ 226 uint32_t a5; /* X15 */ 227 uint32_t a4; /* X14 */ 228 uint32_t a3; /* X13 */ 229 uint32_t a2; /* X12 */ 230 uint32_t a1; /* X11 */ 231 uint32_t a0; /* X10 */ 232 233 uint32_t t2; /* X7 */ 234 uint32_t t1; /* X6 */ 235 uint32_t t0; /* X5 */ 236 237 uint32_t ra; /* X1 */ 238 } task_context_t; 239 240 typedef struct { 241 uint32_t ccause; 242 uint32_t mcause; 243 uint32_t mtval; 244 uint32_t gp; 245 task_context_t task_context; 246 } exc_context_t; 247 248 typedef struct exc_info { 249 uint16_t phase; 250 uint16_t type; 251 uint32_t fault_addr; 252 uint32_t thrd_pid; 253 uint16_t nest_cnt; 254 uint16_t reserved; 255 exc_context_t *context; 256 } exc_info_t; 257 258 /** 259 * @brief Reserve handler process. 260 */ 261 void reserve_handler(void); 262 263 /** 264 * @brief Default handler process. 265 */ 266 void default_handler(void); 267 268 /** 269 * @brief Print exception info. 270 * @param exc Exception info. 271 */ 272 void exc_info_display(const exc_info_t *exc); 273 /** 274 * @} 275 */ 276 #endif 277