1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides flash GIGADEVICE Configuration information. \n 16 * 17 * History: \n 18 * 2022-11-15， Create file. \n 19 */ 20 #ifndef FLASH_GIGADEVICE_CONFIG_H 21 #define FLASH_GIGADEVICE_CONFIG_H 22 23 /** 24 * @defgroup drivers_driver_flash_gigadevice_config Flash Gigadevice Config 25 * @ingroup drivers_driver_flash 26 * @{ 27 */ 28 29 #include "flash_common_config.h" 30 31 /* Gigadevice enter qspi mode cmd config. */ 32 /* GD25WQ64/GD25LE64EX gigadevice flash config. */ 33 static flash_cmd_exe_t g_gigadevice_gd25wq64_enter_qspi_mode_cmd[] = { 34 /* Write enable for volatile status register. */ 35 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 36 /* Write volatile configuration register, config XIP disable. */ 37 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { 0x01, 0x00, 0x02 } }, 38 /* Wait until the configuration is complete. qspi mode, max 104MHZ. */ 39 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 40 /* The END command, will not be executed and need return. */ 41 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 42 }; 43 44 /* GD25LX128 gigadevice flash config. */ 45 static flash_cmd_exe_t g_gigadevice_gd25lq128_enter_qspi_mode_cmd[] = { 46 /* Write enable for volatile status register. */ 47 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 48 /* Write volatile configuration register, config XIP disable. */ 49 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { 0x01, 0x00, 0x02 } }, 50 /* Enable QPI mode. */ 51 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 52 /* Set the dummy cycle to 6, with the maximum read frequency being 108MHZ. */ 53 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0xC0, 0x10} }, 54 /* The END command, will not be executed and need return. */ 55 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 56 }; 57 58 /* GD25LQ256 gigadevice flash config. */ 59 static flash_cmd_exe_t g_gigadevice_gd25lq256_enter_qspi_mode_cmd[] = { 60 /* Write enable for volatile status register. */ 61 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 62 /* Write volatile configuration register, config XIP disable. */ 63 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { 0x01, 0x00, 0x02 } }, 64 /* Write enable. */ 65 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WREN_CMD } }, 66 /* ENTER 4-BYTE ADDRESS MODE. */ 67 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0xB7 } }, 68 /* Wait until the configuration is complete. */ 69 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 70 /* Enable QPI mode. */ 71 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 72 /* Set the dummy cycle to 6, with the maximum read frequency being 108MHZ. */ 73 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0xC0, 0x10} }, 74 /* The END command, will not be executed and need return. */ 75 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 76 }; 77 78 /* GD25LQ32D gigadevice flash config. */ 79 static flash_cmd_exe_t g_gigadevice_gd25lq32d_enter_qspi_mode_cmd[] = { 80 /* Write enable for volatile status register. */ 81 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 82 /* Write volatile configuration register, config XIP disable. */ 83 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { 0x01, 0x00, 0x02 } }, 84 /* Enable QPI mode. */ 85 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 86 /* Set the dummy cycle to 6, with the maximum read frequency being 108MHZ. */ 87 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0xC0, 0x20} }, 88 /* The END command, will not be executed and need return. */ 89 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 90 }; 91 92 93 /* Gigadevice enter xip mode config. */ 94 /* GD25WQ64 gigadevice flash config. */ 95 static flash_qspi_xip_config_t g_gigadevice_gd25wq64_config = { 96 /* The config that before enter XIP mode. */ 97 WAIT_CYCLES_6, 98 HAL_SPI_INST_LEN_8, 99 HAL_SPI_ADDR_LEN_24, 100 HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 101 /* The config that after enter XIP mode. */ 102 WAIT_CYCLES_6, 103 HAL_SPI_INST_LEN_8, 104 HAL_SPI_ADDR_LEN_24, 105 HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 106 /* XIP 32bit addr & wrap config. */ 107 false, 108 false, 109 }; 110 111 /* GD25LE64EX gigadevice flash config. */ 112 static flash_qspi_xip_config_t g_gigadevice_gd25le64_config = { 113 /* The config that before enter XIP mode. */ 114 WAIT_CYCLES_6, 115 HAL_SPI_INST_LEN_8, 116 HAL_SPI_ADDR_LEN_24, 117 HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 118 /* The config that after enter XIP mode. */ 119 WAIT_CYCLES_6, 120 HAL_SPI_INST_LEN_8, 121 HAL_SPI_ADDR_LEN_24, 122 HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 123 /* XIP 32bit addr & wrap config. */ 124 false, 125 false, 126 }; 127 128 /* GD25LX128/GD25LQ32D gigadevice flash config. */ 129 static flash_qspi_xip_config_t g_gigadevice_gd25lx_config = { 130 /* The config that before enter XIP mode. */ 131 WAIT_CYCLES_6, 132 HAL_SPI_INST_LEN_8, 133 HAL_SPI_ADDR_LEN_24, 134 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 135 /* The config that after enter XIP mode. */ 136 WAIT_CYCLES_6, 137 HAL_SPI_INST_LEN_8, 138 HAL_SPI_ADDR_LEN_24, 139 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 140 /* XIP 32bit addr & wrap config. */ 141 false, 142 false, 143 }; 144 145 /* GD25LQ256 gigadevice flash config. */ 146 static flash_qspi_xip_config_t g_gigadevice_gd25lq256_config = { 147 /* The config that before enter XIP mode. */ 148 WAIT_CYCLES_4, 149 HAL_SPI_INST_LEN_0, 150 HAL_SPI_ADDR_LEN_32, 151 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 152 /* The config that after enter XIP mode. */ 153 WAIT_CYCLES_4, 154 HAL_SPI_INST_LEN_8, 155 HAL_SPI_ADDR_LEN_32, 156 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 157 /* XIP 32bit addr & wrap config. */ 158 true, 159 false, 160 }; 161 162 /** 163 * @} 164 */ 165 #endif