1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides flash MXIC Configuration information. \n 16 * 17 * History: \n 18 * 2022-11-15， Create file. \n 19 */ 20 #ifndef FLASH_MXIC_CONFIG_H 21 #define FLASH_MXIC_CONFIG_H 22 23 /** 24 * @defgroup drivers_driver_flash_mxic_config Flash Mxic Config 25 * @ingroup drivers_driver_flash 26 * @{ 27 */ 28 29 #include "flash_common_config.h" 30 31 /* Mxic enter qspi mode cmd config. */ 32 /* MX25R64/MX25R32 mxic flash config. */ 33 static flash_cmd_exe_t g_mxic_mx25rxx_enter_qspi_mode_cmd[] = { 34 /* Write enable. */ 35 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WREN_CMD } }, 36 /* Write configuration register, enable QPI & enable High performance mode. */ 37 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 4, { 0x01, 0x40, 0x00, 0x02 } }, 38 /* Wait until the configuration is complete. qspi mode 6 dummy cycle, max 80MHZ. */ 39 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 40 /* The END command, will not be executed and need return. */ 41 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 42 }; 43 44 /* MX25U64/MX25U128/MX25U12843 mxic falsh config. */ 45 static flash_cmd_exe_t g_mxic_mx25uxx_enter_qspi_mode_cmd[] = { 46 /* Enable QPI mode, MX25U64 dummy cycle 6, max 84MHZ; MX25U128/MX25U12843, dummy cycle 6, max 104MHZ. */ 47 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x35 } }, 48 /* The END command, will not be executed and need return. */ 49 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 50 }; 51 52 /* MX25U32 mxic falsh config. */ 53 static flash_cmd_exe_t g_mxic_mx25u32_enter_qspi_mode_cmd[] = { 54 /* Write enable. */ 55 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WREN_CMD } }, 56 /* Write configuration register, Enable QPI & enable High performance mode. */ 57 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 2, { 0x01, 0x40 } }, 58 /* Wait until the configuration is complete. The dummy cycle default va 4, max 84MHZ. */ 59 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 60 /* The END command, will not be executed and need return. */ 61 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 62 }; 63 64 65 /* Mxic enter xip mode config. */ 66 /* MX25R64/MX25R32 mxic flash config. */ 67 static flash_qspi_xip_config_t g_mxic_mx25rxx_config = { 68 /* Enter XIP mode before config. */ 69 WAIT_CYCLES_4, HAL_SPI_INST_LEN_8, HAL_SPI_ADDR_LEN_32, HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 70 /* Enter XIP mode after config. */ 71 WAIT_CYCLES_4, HAL_SPI_INST_LEN_0, HAL_SPI_ADDR_LEN_32, HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 72 /* XIP 32bit addr & wrap config. */ 73 false, 74 false, 75 }; 76 77 /* MX25U64/MX25U128/MX25U12843 mxic falsh config. */ 78 static flash_qspi_xip_config_t g_mxic_mx25uxx_config = { 79 /* Enter XIP mode before config. */ 80 WAIT_CYCLES_4, 81 HAL_SPI_INST_LEN_8, 82 HAL_SPI_ADDR_LEN_32, 83 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 84 /* Enter XIP mode after config. */ 85 WAIT_CYCLES_4, 86 HAL_SPI_INST_LEN_0, 87 HAL_SPI_ADDR_LEN_32, 88 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 89 /* XIP 32bit addr & wrap config. */ 90 false, 91 false, 92 }; 93 94 /* MX25U32 mxic falsh config. */ 95 static flash_qspi_xip_config_t g_mxic_mx25u32_config = { 96 /* Enter XIP mode before config. */ 97 WAIT_CYCLES_6, 98 HAL_SPI_INST_LEN_8, 99 HAL_SPI_ADDR_LEN_24, 100 HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 101 /* Enter XIP mode after config. */ 102 WAIT_CYCLES_6, 103 HAL_SPI_INST_LEN_8, 104 HAL_SPI_ADDR_LEN_24, 105 HAL_SPI_TRANS_TYPE_INST_S_ADDR_Q, 106 /* XIP 32bit addr & wrap config. */ 107 false, 108 false, 109 }; 110 111 /** 112 * @} 113 */ 114 #endif