1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides flash OTHERS Configuration information. \n 16 * 17 * History: \n 18 * 2022-11-15， Create file. \n 19 */ 20 #ifndef FLASH_OTHERS_CONFIG_H 21 #define FLASH_OTHERS_CONFIG_H 22 23 /** 24 * @defgroup drivers_driver_flash_other_config Flash Other Config 25 * @ingroup drivers_driver_flash 26 * @{ 27 */ 28 29 #include "flash_common_config.h" 30 31 /* OTHERS enter qspi mode cmd config. */ 32 /* Micro config. */ 33 /* MT25QU128 Micro flash config. */ 34 static flash_cmd_exe_t g_micro_mt25qu128_enter_qspi_mode_cmd[] = { 35 /* Write enable. */ 36 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WREN_CMD } }, 37 /* Write volatile configuration register, config dummy cycle 4, XIP disable. */ 38 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 2, { 0x81, 0x4B } }, 39 /* Wait until the configuration is complete. */ 40 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 41 /* Write disable. */ 42 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WRDI_CMD } }, 43 /* Wait until the write enable flag is cleared. */ 44 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 1, 0 } }, 45 /* Enable QPI mode. */ 46 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x35 } }, 47 /* The END command, will not be executed and need return. */ 48 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 49 }; 50 static flash_cmd_exe_t g_micro_mt25qu128_enter_xip_mode_cmd[] = { 51 /* Write enable. */ 52 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 1, { FLASH_WREN_CMD } }, 53 /* Write volatile configuration register, config dummy cycle 4, wrap 32byte,XIP enable. */ 54 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0x81, 0x41 } }, 55 /* Wait until the configuration is complete. */ 56 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_QUAD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 57 /* The END command, will not be executed and need return. */ 58 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 59 }; 60 61 /* MT25QU256 Micro flash config. */ 62 static flash_cmd_exe_t g_micro_mt25qu256_enter_qspi_mode_cmd[] = { 63 /* Write enable. */ 64 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WREN_CMD } }, 65 /* Write volatile configuration register, config dummy cycle 4, XIP disable. */ 66 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 2, { 0x81, 0x4B } }, 67 /* Write enable. */ 68 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WREN_CMD } }, 69 /* ENTER 4-BYTE ADDRESS MODE. */ 70 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0xB7 } }, 71 /* Wait until the configuration is complete. */ 72 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 73 /* Write disable. */ 74 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { FLASH_WRDI_CMD } }, 75 /* Wait until the write enable flag is cleared. */ 76 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 1, 0 } }, 77 /* Enable QPI mode. */ 78 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x35 } }, 79 /* The END command, will not be executed and need return. */ 80 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 81 }; 82 static flash_cmd_exe_t g_micro_mt25qu256_enter_xip_mode_cmd[] = { 83 /* Write enable. */ 84 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 1, { FLASH_WREN_CMD } }, 85 /* Write volatile configuration register, config dummy cycle 4, wrap 32byte,XIP enable. */ 86 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0x81, 0x41 } }, 87 /* Wait until the configuration is complete. */ 88 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_QUAD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 89 /* Write disable. */ 90 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 1, { FLASH_WRDI_CMD } }, 91 /* The END command, will not be executed and need return. */ 92 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 93 }; 94 95 /* PUYA config. */ 96 /* P25Q32LX PUYA flash config. */ 97 static flash_cmd_exe_t g_puya_p25q32lc_enter_qspi_mode_cmd[] = { 98 /* Write enable for volatile status register. */ 99 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 100 /* Write status register-2 to 0x2, enable QPI write bit. */ 101 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 2, { 0x31, 0x02 } }, 102 /* Wait until the configuration is complete. */ 103 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 104 /* Enable QPI mode. */ 105 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 106 /* Set the dummy cycle to 6, with the maximum read frequency being 104MHZ 70MHZ. */ 107 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0xC0, 0x20} }, 108 /* The END command, will not be executed and need return. */ 109 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 110 }; 111 112 /* ADESTO config. */ 113 /* AT25SL128A PUYA flash config. */ 114 static flash_cmd_exe_t g_adesto_at25sl128a_enter_qspi_mode_cmd[] = { 115 /* Write enable for volatile status register. */ 116 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 117 /* Write volatile configuration register, config XIP disable. */ 118 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { 0x01, 0x00, 0x02 } }, 119 /* Wait until the configuration is complete. */ 120 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 121 /* Enable QPI mode. The dummy cycle default value is 4, with the maximum read frequency being 90MHZ. */ 122 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 123 /* The END command, will not be executed and need return. */ 124 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 125 }; 126 127 /* ELITE config. */ 128 /* EN25SX128A PUYA flash config. */ 129 static flash_cmd_exe_t g_mxic_en25sxxa_enter_qspi_mode_cmd[] = { 130 /* Write enable for volatile status register. */ 131 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 132 /* Write volatile configuration register, config XIP disable. */ 133 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { 0x01, 0x00, 0x02 } }, 134 /* Enable QPI mode. */ 135 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 136 /* The END command, will not be executed and need return. */ 137 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 138 }; 139 140 /* XTX config. */ 141 /* XT25Q128D flash config. */ 142 static flash_cmd_exe_t g_xtx_xt25qxxd_enter_qspi_mode_cmd[] = { 143 /* Write enable for volatile status register. */ 144 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 145 /* Write status register-2 to 0x2, enable QPI write bit. */ 146 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 2, { 0x31, 0x02 } }, 147 /* Wait until the configuration is complete. */ 148 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 149 /* Enable QPI mode. */ 150 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 151 /* The END command, will not be executed and need return. */ 152 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 153 }; 154 155 /* OTHERS enter xip mode config. */ 156 /* Micro config. */ 157 /* MT25QU128 Micro flash config. */ 158 static flash_qspi_xip_config_t g_micro_mt25qu128_config = { 159 /* Enter XIP mode before config. */ 160 WAIT_CYCLES_2, 161 HAL_SPI_INST_LEN_8, 162 HAL_SPI_ADDR_LEN_32, 163 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 164 /* Enter XIP mode after config. */ 165 WAIT_CYCLES_2, 166 HAL_SPI_INST_LEN_0, 167 HAL_SPI_ADDR_LEN_32, 168 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 169 /* XIP 32bit addr & wrap config. */ 170 false, 171 true, 172 }; 173 174 /* MT25QU256 Micro flash config. */ 175 static flash_qspi_xip_config_t g_micro_mt25qu256_config = { 176 /* Enter XIP mode before config. */ 177 WAIT_CYCLES_2, 178 HAL_SPI_INST_LEN_0, 179 HAL_SPI_ADDR_LEN_32, 180 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 181 /* Enter XIP mode after config. */ 182 WAIT_CYCLES_2, 183 HAL_SPI_INST_LEN_8, 184 HAL_SPI_ADDR_LEN_32, 185 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 186 /* XIP 32bit addr & wrap config. */ 187 true, 188 true, 189 }; 190 191 /* PUYA config. */ 192 /* P25Q32LX PUYA flash config. */ 193 static flash_qspi_xip_config_t g_puya_p25q32lc_config = { 194 /* The config that before enter XIP mode. */ 195 WAIT_CYCLES_6, 196 HAL_SPI_INST_LEN_8, 197 HAL_SPI_ADDR_LEN_24, 198 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 199 /* The config that after enter XIP mode. */ 200 WAIT_CYCLES_6, 201 HAL_SPI_INST_LEN_8, 202 HAL_SPI_ADDR_LEN_24, 203 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 204 /* XIP 32bit addr & wrap config. */ 205 false, 206 false, 207 }; 208 209 /* ADESTO config. */ 210 /* AT25SL128A PUYA flash config. */ 211 static flash_qspi_xip_config_t g_adesto_at25sl128a_config = { 212 /* The config that before enter XIP mode. */ 213 WAIT_CYCLES_4, 214 HAL_SPI_INST_LEN_8, 215 HAL_SPI_ADDR_LEN_24, 216 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 217 /* The config that after enter XIP mode. */ 218 WAIT_CYCLES_4, 219 HAL_SPI_INST_LEN_8, 220 HAL_SPI_ADDR_LEN_24, 221 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 222 /* XIP 32bit addr & wrap config. */ 223 false, 224 false, 225 }; 226 227 /* ELITE config. */ 228 /* EN25SX128A PUYA flash config. */ 229 static flash_qspi_xip_config_t g_mxic_en25sxxa_config = { 230 /* The config that before enter XIP mode. */ 231 WAIT_CYCLES_6, 232 HAL_SPI_INST_LEN_8, 233 HAL_SPI_ADDR_LEN_24, 234 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 235 /* The config that after enter XIP mode. */ 236 WAIT_CYCLES_6, 237 HAL_SPI_INST_LEN_8, 238 HAL_SPI_ADDR_LEN_24, 239 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 240 /* XIP 32bit addr & wrap config. */ 241 false, 242 false, 243 }; 244 245 /* XTX config. */ 246 /* XT25QXXD flash config. */ 247 static flash_qspi_xip_config_t g_xtx_xt25qxxd_config = { 248 /* The config that before enter XIP mode. */ 249 WAIT_CYCLES_6, 250 HAL_SPI_INST_LEN_8, 251 HAL_SPI_ADDR_LEN_32, 252 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 253 /* The config that after enter XIP mode. */ 254 WAIT_CYCLES_6, 255 HAL_SPI_INST_LEN_0, 256 HAL_SPI_ADDR_LEN_32, 257 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 258 /* XIP 32bit addr & wrap config. */ 259 false, 260 false, 261 }; 262 /** 263 * @} 264 */ 265 #endif