1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides flash WINBOND Configuration information. \n 16 * 17 * History: \n 18 * 2022-11-15， Create file. \n 19 */ 20 #ifndef FLASH_WINBOND_CONFIG_H 21 #define FLASH_WINBOND_CONFIG_H 22 23 /** 24 * @defgroup drivers_driver_flash_winbond_config Flash Winbond Config 25 * @ingroup drivers_driver_flash 26 * @{ 27 */ 28 29 #include "flash_common_config.h" 30 31 /* Winbond enter qspi mode cmd config. */ 32 /* W25Q32/W25Q64/W25Q128/W25Q128JW winbond flash config. */ 33 static flash_cmd_exe_t g_winbond_w25qxx_enter_qspi_mode_cmd[] = { 34 /* Write enable for volatile status register. */ 35 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 36 /* Write status register-2 to 0x2, enable QPI write bit. */ 37 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 2, { 0x31, 0x02 } }, 38 /* Wait until the configuration is complete. */ 39 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 40 /* Enable QPI mode. */ 41 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 42 /* Set the dummy cycle to 6, with the maximum read frequency being 104MHZ. */ 43 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0xC0, 0x20} }, 44 /* The END command, will not execute and need return. */ 45 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 46 }; 47 48 /* W25Q256 winbond flash config. */ 49 static flash_cmd_exe_t g_winbond_w25q256_enter_qspi_mode_cmd[] = { 50 /* Write enable for volatile status register. */ 51 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 52 /* Write status register-2 to 0x2, enable QPI write bit. */ 53 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 2, { 0x31, 0x02 } }, 54 /* Wait until the configuration is complete. */ 55 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 56 /* Write enable for volatile status register. */ 57 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x50 } }, 58 /* ENTER 4-BYTE ADDRESS MODE. */ 59 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0xB7 } }, 60 /* Wait until the configuration is complete. */ 61 { FLASH_CMD_TYPE_PROCESSING, HAL_SPI_FRAME_FORMAT_STANDARD, 3, { FLASH_RDSR1_CMD, 0, 0 } }, 62 /* Enable QPI mode. */ 63 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_STANDARD, 1, { 0x38 } }, 64 /* Set the dummy cycle to 4, with the maximum read frequency being 80MHZ. */ 65 { FLASH_CMD_TYPE_CMD, HAL_SPI_FRAME_FORMAT_QUAD, 2, { 0xC0, 0x10} }, 66 /* The END command, will not execute and need return. */ 67 { FLASH_CMD_TYPE_END, HAL_SPI_FRAME_FORMAT_MAX_NUM, 0, { 0 } } 68 }; 69 70 71 /* Winbond enter xip mode config. */ 72 /* W25Q32/W25Q64/W25Q128 winbond flash config. */ 73 static flash_qspi_xip_config_t g_winbond_w25qxx_config = { 74 /* Enter XIP mode before config. */ 75 WAIT_CYCLES_4, 76 HAL_SPI_INST_LEN_8, 77 HAL_SPI_ADDR_LEN_32, 78 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 79 /* Enter XIP mode after config. */ 80 WAIT_CYCLES_4, 81 HAL_SPI_INST_LEN_0, 82 HAL_SPI_ADDR_LEN_32, 83 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 84 /* XIP 32bit addr & wrap config. */ 85 false, 86 false, 87 }; 88 89 /* W25Q256 winbond flash config. */ 90 static flash_qspi_xip_config_t g_winbond_w25q256_config = { 91 /* Enter XIP mode before config. */ 92 WAIT_CYCLES_2, 93 HAL_SPI_INST_LEN_0, 94 HAL_SPI_ADDR_LEN_32, 95 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 96 /* Enter XIP mode after config. */ 97 WAIT_CYCLES_2, 98 HAL_SPI_INST_LEN_8, 99 HAL_SPI_ADDR_LEN_32, 100 HAL_SPI_TRANS_TYPE_INST_Q_ADDR_Q, 101 /* XIP 32bit addr & wrap config. */ 102 true, 103 false, 104 }; 105 106 /** 107 * @} 108 */ 109 #endif