1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: OS Abstract Layer. 15 */ 16 17 /** 18 * @defgroup osal_barrier osal_barrier 19 */ 20 #ifndef __OSAL_BARRIER_H__ 21 #define __OSAL_BARRIER_H__ 22 23 #ifdef __cplusplus 24 #if __cplusplus 25 extern "C" { 26 #endif 27 #endif 28 29 /** 30 * @ingroup osal_barrier 31 * @brief General basic CPU memory barriers 32 * 33 * @par Description: 34 * The memory barrier mb() function ensures that any memory access that appears before the barrier is completed 35 * before the execution of any memory access that appears after the barrier. 36 * 37 * @par Support System: 38 * linux. 39 */ 40 void osal_mb(void); 41 42 /** 43 * @ingroup osal_barrier 44 * @brief Read basic CPU memory barriers 45 * 46 * @par Description: 47 * The read memory barrier rmb() function ensures that any read that appears before the barrier is completed 48 * before the execution of any read that appears after the barrier. 49 * 50 * @par Support System: 51 * linux. 52 */ 53 void osal_rmb(void); 54 55 /** 56 * @ingroup osal_barrier 57 * @brief Write basic CPU memory barriers 58 * 59 * @par Description: 60 * The write memory barrier wmb() function ensures that any write that appears before the barrier is completed 61 * before the execution of any write that appears after the barrier. 62 * 63 * @par Support System: 64 * linux. 65 */ 66 void osal_wmb(void); 67 68 /** 69 * @ingroup osal_barrier 70 * @brief General basic CPU memory barriers, SMP conditional. 71 * 72 * @par Description: 73 * Corresponding SMP versions of osal_mb. 74 * 75 * @par Support System: 76 * linux. 77 */ 78 void osal_smp_mb(void); 79 80 /** 81 * @ingroup osal_barrier 82 * @brief Read basic CPU memory barriers, SMP conditional. 83 * 84 * @par Description: 85 * Corresponding SMP versions of osal_rmb. 86 * 87 * @par Support System: 88 * linux. 89 */ 90 void osal_smp_rmb(void); 91 92 /** 93 * @ingroup osal_barrier 94 * @brief Write basic CPU memory barriers, SMP conditional. 95 * 96 * @par Description: 97 * Corresponding SMP versions of osal_wmb. 98 * 99 * @par Support System: 100 * linux. 101 */ 102 void osal_smp_wmb(void); 103 104 /** 105 * @ingroup osal_barrier 106 * @brief Instruction Synchronization Barrier. 107 * 108 * @par Description: 109 * Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following 110 * the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects 111 * of context altering operations, such as changing the ASID, or completed TLB maintenance operations, 112 * or branch predictor maintenance operations, as well as all changes to the CP15 registers, 113 * executed before the ISB instruction are visible to the instructions fetched after the ISB. 114 * In addition, the ISB instruction ensures that any branches that appear in program order after it 115 * are always written into the branch prediction logic with the context that is visible after the ISB instruction. 116 * This is required to ensure correct execution of the instruction stream. 117 * 118 * @par Support System: 119 * linux liteos. 120 */ 121 void osal_isb(void); 122 123 /** 124 * @ingroup osal_barrier 125 * @brief Data Synchronization Barrier. 126 * 127 * @par Description: 128 * Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after 129 * this instruction executes until this instruction completes. This instruction completes when: 130 * · All explicit memory accesses before this instruction complete. 131 * · All Cache, Branch predictor and TLB maintenance operations before this instruction complete. 132 * 133 * @par Support System: 134 * linux liteos. 135 */ 136 void osal_dsb(void); 137 138 /** 139 * @ingroup osal_barrier 140 * @brief Data Memory Barrier. 141 * 142 * @par Description: 143 * Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in program 144 * order before the DMB instruction are observed before any explicit memory accesses that appear in program order 145 * after the DMB instruction. It does not affect the ordering of any other instructions executing on the processor. 146 * 147 * @par Support System: 148 * linux liteos. 149 */ 150 void osal_dmb(void); 151 152 #ifdef __cplusplus 153 #if __cplusplus 154 } 155 #endif 156 #endif 157 #endif /* __OSAL_BARRIER_H__ */