1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 * Description: cache
15 *
16 * Create: 2021-12-16
17 */
18
19 #include <arch/cache.h>
20 #include "soc_osal.h"
21 #include "los_typedef.h"
22
23 /**
24 * @brief flush DCache.
25 * <li>The base address will be aligned to CACHE_LINE_SIZE(32Bytes) if it's not aligned to CACHE_LINE_SIZE.</li>
26 * @param phys_addr [IN] The start address need flush.
27 * @param size [IN] The size of flush memory.
28 */
osal_dcache_region_wb(void * kvirt,unsigned long phys_addr,unsigned long size)29 void osal_dcache_region_wb(void *kvirt, unsigned long phys_addr, unsigned long size)
30 {
31 // Make sure that phys_addr is valid when mmu does not exist, and user set its addr in kvirt.
32 phys_addr = (phys_addr == 0) ? (uintptr_t)kvirt : phys_addr;
33 ArchDCacheFlushByVa((uintptr_t)phys_addr, (uint32_t)size);
34 }
35
36 /**
37 * @brief invalid DCache.
38 * <li>The base address will be aligned to CACHE_LINE_SIZE(32Bytes) if it's not aligned to CACHE_LINE_SIZE.</li>
39 * @param addr [IN] The start address need invalid.
40 * @param size [IN] The size of invalid memory.
41 */
osal_dcache_region_inv(void * addr,unsigned long size)42 void osal_dcache_region_inv(void *addr, unsigned long size)
43 {
44 ArchDCacheInvByVa((uintptr_t)addr, (uint32_t)size);
45 }
46
47 /**
48 * @brief clean DCache.
49 * @par Description: This API is used to clean DCache.
50 * @attention The API will clean DCache according to based address and input size.</li>
51 */
osal_dcache_region_clean(void * addr,unsigned int size)52 void osal_dcache_region_clean(void *addr, unsigned int size)
53 {
54 ArchDCacheCleanByVa((uintptr_t)addr, (uint32_t)size);
55 }
56