1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 * reserved. Description: hmac tid head
15 * Create: 2020-7-5
16 */
17
18 #ifndef __HMAC_TID_H__
19 #define __HMAC_TID_H__
20
21 /*****************************************************************************
22 1 其他头文件包含
23 *****************************************************************************/
24 #include "dmac_ext_if_hcm.h"
25
26 #ifdef __cplusplus
27 #if __cplusplus
28 extern "C" {
29 #endif
30 #endif
31
32 /*****************************************************************************
33 2 宏定义
34 *****************************************************************************/
35 /*****************************************************************************
36 4 全局变量声明
37 *****************************************************************************/
38 typedef struct {
39 osal_u16 user_idx;
40 osal_u8 tid;
41 osal_u8 from_resume;
42 } hmac_tid_resume_stru;
43
44 /*****************************************************************************
45 10 函数声明
46 *****************************************************************************/
47 osal_void hmac_tid_pause(hmac_tid_stru *tid, osal_u8 type);
48 osal_u32 hmac_tid_resume(hmac_tid_stru *tid, osal_u8 type);
49 osal_void hmac_tid_tx_queue_init(hmac_tid_stru *tx_tid_queue, hmac_user_stru *hmac_user);
50 osal_void hmac_tid_tx_enqueue_update(hmac_device_stru *hmac_device, hmac_tid_stru *tid_queue, osal_u8 mpdu_num);
51 osal_void hmac_tid_tx_dequeue_update(hmac_device_stru *hmac_device, hmac_tid_stru *tid_queue, osal_u8 mpdu_num);
52 osal_u32 hmac_tid_clear(hmac_user_stru *hmac_user, hmac_device_stru *hmac_device);
53 osal_void hmac_tid_buffer_status_calc(hmac_user_stru *hmac_user, wlan_tidno_enum_uint8 tid);
54 #ifdef _PRE_WLAN_FEATURE_BSRP
55 osal_void hmac_tid_buffer_status_init(osal_void);
56 #endif
57 osal_s32 hmac_config_tid_resume_process(hmac_vap_stru *hmac_vap, frw_msg *msg);
58 osal_u32 hmac_tid_get_mpdu_by_index(hmac_tid_stru *tid_queue, osal_u16 mpdu_num, oal_netbuf_stru **netbuf_stru);
59 osal_u32 hmac_tid_delete_mpdu_head(hmac_tid_stru *tid_queue, osal_u16 mpdu_num);
60
hmac_tx_tid_buffer_len_decrease(hmac_tid_stru * tid_queue,oal_netbuf_stru * buf)61 static inline osal_void hmac_tx_tid_buffer_len_decrease(hmac_tid_stru *tid_queue, oal_netbuf_stru *buf)
62 {
63 oal_netbuf_stru *tid_netbuf_next = OSAL_NULL;
64 mac_tx_ctl_stru *tid_buffer_cb = OSAL_NULL;
65 oal_netbuf_stru *netbuf = buf;
66
67 while (netbuf != OSAL_NULL) {
68 tid_netbuf_next = oal_get_netbuf_next(netbuf);
69 tid_buffer_cb = (mac_tx_ctl_stru *)oal_netbuf_cb(netbuf);
70 tid_queue->tid_buffer_frame_len = (tid_queue->tid_buffer_frame_len < tid_buffer_cb->mpdu_payload_len) ? 0 :
71 (tid_queue->tid_buffer_frame_len - tid_buffer_cb->mpdu_payload_len);
72 netbuf = tid_netbuf_next;
73 }
74 }
75
hmac_tx_tid_buffer_len_increase(hmac_tid_stru * tid_queue,oal_netbuf_stru * buf)76 static inline osal_void hmac_tx_tid_buffer_len_increase(hmac_tid_stru *tid_queue, oal_netbuf_stru *buf)
77 {
78 oal_netbuf_stru *tid_netbuf_next = OSAL_NULL;
79 mac_tx_ctl_stru *tid_buffer_cb = OSAL_NULL;
80 oal_netbuf_stru *netbuf = buf;
81
82 while (netbuf != OSAL_NULL) {
83 tid_netbuf_next = oal_get_netbuf_next(netbuf);
84 tid_buffer_cb = (mac_tx_ctl_stru *)oal_netbuf_cb(netbuf);
85 tid_queue->tid_buffer_frame_len += tid_buffer_cb->mpdu_payload_len;
86 netbuf = tid_netbuf_next;
87 }
88 }
89
90 #ifdef __cplusplus
91 #if __cplusplus
92 }
93 #endif
94 #endif
95
96 #endif /* end of hmac_tid_rom.h */
97