1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare Multimedia Card Interface driver 4 * (Based on NXP driver for lpc 31xx) 5 * 6 * Copyright (C) 2009 NXP Semiconductors 7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8 */ 9 10 #ifndef _DW_MMC_H_ 11 #define _DW_MMC_H_ 12 13 #include <linux/scatterlist.h> 14 #include <linux/mmc/core.h> 15 #include <linux/dmaengine.h> 16 #include <linux/reset.h> 17 #include <linux/interrupt.h> 18 19 enum dw_mci_state { 20 STATE_IDLE = 0, 21 STATE_SENDING_CMD, 22 STATE_SENDING_DATA, 23 STATE_DATA_BUSY, 24 STATE_SENDING_STOP, 25 STATE_DATA_ERROR, 26 STATE_SENDING_CMD11, 27 STATE_WAITING_CMD11_DONE, 28 }; 29 30 enum { 31 EVENT_CMD_COMPLETE = 0, 32 EVENT_XFER_COMPLETE, 33 EVENT_DATA_COMPLETE, 34 EVENT_DATA_ERROR, 35 }; 36 37 enum dw_mci_cookie { 38 COOKIE_UNMAPPED, 39 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ 40 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ 41 }; 42 43 struct mmc_data; 44 45 enum { TRANS_MODE_PIO = 0, TRANS_MODE_IDMAC, TRANS_MODE_EDMAC }; 46 47 struct dw_mci_dma_slave { 48 struct dma_chan *ch; 49 enum dma_transfer_direction direction; 50 }; 51 52 /** 53 * struct dw_mci - MMC controller state shared between all slots 54 * @lock: Spinlock protecting the queue and associated data. 55 * @irq_lock: Spinlock protecting the INTMASK setting. 56 * @regs: Pointer to MMIO registers. 57 * @fifo_reg: Pointer to MMIO registers for data FIFO 58 * @sg: Scatterlist entry currently being processed by PIO code, if any. 59 * @sg_miter: PIO mapping scatterlist iterator. 60 * @mrq: The request currently being processed on @slot, 61 * or NULL if the controller is idle. 62 * @cmd: The command currently being sent to the card, or NULL. 63 * @data: The data currently being transferred, or NULL if no data 64 * transfer is in progress. 65 * @stop_abort: The command currently prepared for stoping transfer. 66 * @prev_blksz: The former transfer blksz record. 67 * @timing: Record of current ios timing. 68 * @use_dma: Which DMA channel is in use for the current transfer, zero 69 * denotes PIO mode. 70 * @using_dma: Whether DMA is in use for the current transfer. 71 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 72 * @sg_dma: Bus address of DMA buffer. 73 * @sg_cpu: Virtual address of DMA buffer. 74 * @dma_ops: Pointer to platform-specific DMA callbacks. 75 * @cmd_status: Snapshot of SR taken upon completion of the current 76 * @ring_size: Buffer size for idma descriptors. 77 * command. Only valid when EVENT_CMD_COMPLETE is pending. 78 * @dms: structure of slave-dma private data. 79 * @phy_regs: physical address of controller's register map 80 * @data_status: Snapshot of SR taken upon completion of the current 81 * data transfer. Only valid when EVENT_DATA_COMPLETE or 82 * EVENT_DATA_ERROR is pending. 83 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 84 * to be sent. 85 * @dir_status: Direction of current transfer. 86 * @tasklet: Tasklet running the request state machine. 87 * @pending_events: Bitmask of events flagged by the interrupt handler 88 * to be processed by the tasklet. 89 * @completed_events: Bitmask of events which the state machine has 90 * processed. 91 * @state: Tasklet state. 92 * @queue: List of slots waiting for access to the controller. 93 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 94 * rate and timeout calculations. 95 * @current_speed: Configured rate of the controller. 96 * @fifoth_val: The value of FIFOTH register. 97 * @verid: Denote Version ID. 98 * @dev: Device associated with the MMC controller. 99 * @pdata: Platform data associated with the MMC controller. 100 * @drv_data: Driver specific data for identified variant of the controller 101 * @priv: Implementation defined private data. 102 * @biu_clk: Pointer to bus interface unit clock instance. 103 * @ciu_clk: Pointer to card interface unit clock instance. 104 * @slot: Slots sharing this MMC controller. 105 * @fifo_depth: depth of FIFO. 106 * @data_addr_override: override fifo reg offset with this value. 107 * @wm_aligned: force fifo watermark equal with data length in PIO mode. 108 * Set as true if alignment is needed. 109 * @data_shift: log2 of FIFO item size. 110 * @part_buf_start: Start index in part_buf. 111 * @part_buf_count: Bytes of partial data in part_buf. 112 * @part_buf: Simple buffer for partial fifo reads/writes. 113 * @push_data: Pointer to FIFO push function. 114 * @pull_data: Pointer to FIFO pull function. 115 * @vqmmc_enabled: Status of vqmmc, should be true or false. 116 * @irq_flags: The flags to be passed to request_irq. 117 * @irq: The irq value to be passed to request_irq. 118 * @sdio_id0: Number of slot0 in the SDIO interrupt registers. 119 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. 120 * @cto_timer: Timer for broken command transfer over scheme. 121 * @dto_timer: Timer for broken data transfer over scheme. 122 * 123 * Locking 124 * ======= 125 * 126 * @lock is a softirq-safe spinlock protecting @queue as well as 127 * @slot, @mrq and @state. These must always be updated 128 * at the same time while holding @lock. 129 * The @mrq field of struct dw_mci_slot is also protected by @lock, 130 * and must always be written at the same time as the slot is added to 131 * @queue. 132 * 133 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 134 * to allow the interrupt handler to modify it directly. Held for only long 135 * enough to read-modify-write INTMASK and no other locks are grabbed when 136 * holding this one. 137 * 138 * @pending_events and @completed_events are accessed using atomic bit 139 * operations, so they don't need any locking. 140 * 141 * None of the fields touched by the interrupt handler need any 142 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 143 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 144 * interrupts must be disabled and @data_status updated with a 145 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 146 * CMDRDY interrupt must be disabled and @cmd_status updated with a 147 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 148 * bytes_xfered field of @data must be written. This is ensured by 149 * using barriers. 150 */ 151 struct dw_mci { 152 spinlock_t lock; 153 spinlock_t irq_lock; 154 void __iomem *regs; 155 void __iomem *fifo_reg; 156 u32 data_addr_override; 157 bool wm_aligned; 158 159 struct scatterlist *sg; 160 struct sg_mapping_iter sg_miter; 161 162 struct mmc_request *mrq; 163 struct mmc_command *cmd; 164 struct mmc_data *data; 165 struct mmc_command stop_abort; 166 unsigned int prev_blksz; 167 unsigned char timing; 168 169 /* DMA interface members */ 170 int use_dma; 171 int using_dma; 172 int dma_64bit_address; 173 174 dma_addr_t sg_dma; 175 void *sg_cpu; 176 const struct dw_mci_dma_ops *dma_ops; 177 /* For idmac */ 178 unsigned int ring_size; 179 180 /* For edmac */ 181 struct dw_mci_dma_slave *dms; 182 /* Registers's physical base address */ 183 resource_size_t phy_regs; 184 185 u32 cmd_status; 186 u32 data_status; 187 u32 stop_cmdr; 188 u32 dir_status; 189 struct tasklet_struct tasklet; 190 unsigned long pending_events; 191 unsigned long completed_events; 192 enum dw_mci_state state; 193 struct list_head queue; 194 195 u32 bus_hz; 196 u32 current_speed; 197 u32 fifoth_val; 198 u16 verid; 199 struct device *dev; 200 struct dw_mci_board *pdata; 201 const struct dw_mci_drv_data *drv_data; 202 void *priv; 203 struct clk *biu_clk; 204 struct clk *ciu_clk; 205 struct dw_mci_slot *slot; 206 207 /* FIFO push and pull */ 208 int fifo_depth; 209 int data_shift; 210 u8 part_buf_start; 211 u8 part_buf_count; 212 union { 213 u16 part_buf16; 214 u32 part_buf32; 215 u64 part_buf; 216 }; 217 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 218 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 219 220 bool vqmmc_enabled; 221 unsigned long irq_flags; /* IRQ flags */ 222 int irq; 223 224 int sdio_id0; 225 226 struct timer_list cmd11_timer; 227 struct timer_list cto_timer; 228 struct timer_list dto_timer; 229 bool need_xfer_timer; 230 struct timer_list xfer_timer; 231 }; 232 233 /* DMA ops for Internal/External DMAC interface */ 234 struct dw_mci_dma_ops { 235 /* DMA Ops */ 236 int (*init)(struct dw_mci *host); 237 int (*start)(struct dw_mci *host, unsigned int sg_len); 238 void (*complete)(void *host); 239 void (*stop)(struct dw_mci *host); 240 void (*cleanup)(struct dw_mci *host); 241 void (*exit)(struct dw_mci *host); 242 }; 243 244 struct dma_pdata; 245 246 /* Board platform data */ 247 struct dw_mci_board { 248 unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 249 250 u32 caps; /* Capabilities */ 251 u32 caps2; /* More capabilities */ 252 u32 pm_caps; /* PM capabilities */ 253 /* 254 * Override fifo depth. If 0, autodetect it from the FIFOTH register, 255 * but note that this may not be reliable after a bootloader has used 256 * it. 257 */ 258 unsigned int fifo_depth; 259 260 /* delay in mS before detecting cards after interrupt */ 261 u32 detect_delay_ms; 262 263 struct reset_control *rstc; 264 struct dw_mci_dma_ops *dma_ops; 265 struct dma_pdata *data; 266 }; 267 268 #define DW_MMC_240A 0x240a 269 #define DW_MMC_280A 0x280a 270 271 #define SDMMC_CTRL 0x000 272 #define SDMMC_PWREN 0x004 273 #define SDMMC_CLKDIV 0x008 274 #define SDMMC_CLKSRC 0x00c 275 #define SDMMC_CLKENA 0x010 276 #define SDMMC_TMOUT 0x014 277 #define SDMMC_CTYPE 0x018 278 #define SDMMC_BLKSIZ 0x01c 279 #define SDMMC_BYTCNT 0x020 280 #define SDMMC_INTMASK 0x024 281 #define SDMMC_CMDARG 0x028 282 #define SDMMC_CMD 0x02c 283 #define SDMMC_RESP0 0x030 284 #define SDMMC_RESP1 0x034 285 #define SDMMC_RESP2 0x038 286 #define SDMMC_RESP3 0x03c 287 #define SDMMC_MINTSTS 0x040 288 #define SDMMC_RINTSTS 0x044 289 #define SDMMC_STATUS 0x048 290 #define SDMMC_FIFOTH 0x04c 291 #define SDMMC_CDETECT 0x050 292 #define SDMMC_WRTPRT 0x054 293 #define SDMMC_GPIO 0x058 294 #define SDMMC_TCBCNT 0x05c 295 #define SDMMC_TBBCNT 0x060 296 #define SDMMC_DEBNCE 0x064 297 #define SDMMC_USRID 0x068 298 #define SDMMC_VERID 0x06c 299 #define SDMMC_HCON 0x070 300 #define SDMMC_UHS_REG 0x074 301 #define SDMMC_RST_N 0x078 302 #define SDMMC_BMOD 0x080 303 #define SDMMC_PLDMND 0x084 304 #define SDMMC_DBADDR 0x088 305 #define SDMMC_IDSTS 0x08c 306 #define SDMMC_IDINTEN 0x090 307 #define SDMMC_DSCADDR 0x094 308 #define SDMMC_BUFADDR 0x098 309 #define SDMMC_CDTHRCTL 0x100 310 #define SDMMC_UHS_REG_EXT 0x108 311 #define SDMMC_DDR_REG 0x10c 312 #define SDMMC_ENABLE_SHIFT 0x110 313 #define SDMMC_DATA(x) (x) 314 /* 315 * Registers to support idmac 64-bit address mode 316 */ 317 #define SDMMC_DBADDRL 0x088 318 #define SDMMC_DBADDRU 0x08c 319 #define SDMMC_IDSTS64 0x090 320 #define SDMMC_IDINTEN64 0x094 321 #define SDMMC_DSCADDRL 0x098 322 #define SDMMC_DSCADDRU 0x09c 323 #define SDMMC_BUFADDRL 0x0A0 324 #define SDMMC_BUFADDRU 0x0A4 325 326 /* 327 * Data offset is difference according to Version 328 * Lower than 2.40a : data register offest is 0x100 329 */ 330 #define DATA_OFFSET 0x100 331 #define DATA_240A_OFFSET 0x200 332 333 /* shift bit field */ 334 #define DW_MMC_SBF(f, v) ((v) << (f)) 335 336 /* Control register defines */ 337 #define SDMMC_CTRL_USE_IDMAC BIT(25) 338 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 339 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 340 #define SDMMC_CTRL_SEND_CCSD BIT(9) 341 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 342 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 343 #define SDMMC_CTRL_READ_WAIT BIT(6) 344 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 345 #define SDMMC_CTRL_INT_ENABLE BIT(4) 346 #define SDMMC_CTRL_DMA_RESET BIT(2) 347 #define SDMMC_CTRL_FIFO_RESET BIT(1) 348 #define SDMMC_CTRL_RESET BIT(0) 349 /* Clock Enable register defines */ 350 #define SDMMC_CLKEN_LOW_PWR BIT(16) 351 #define SDMMC_CLKEN_ENABLE BIT(0) 352 /* time-out register defines */ 353 #define SDMMC_TMOUT_DATA(n) DW_MMC_SBF(8, (n)) 354 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 355 #define SDMMC_TMOUT_RESP(n) ((n)&0xFF) 356 #define SDMMC_TMOUT_RESP_MSK 0xFF 357 /* card-type register defines */ 358 #define SDMMC_CTYPE_8BIT BIT(16) 359 #define SDMMC_CTYPE_4BIT BIT(0) 360 #define SDMMC_CTYPE_1BIT 0 361 /* Interrupt status & mask register defines */ 362 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 363 #define SDMMC_INT_EBE BIT(15) 364 #define SDMMC_INT_ACD BIT(14) 365 #define SDMMC_INT_SBE BIT(13) 366 #define SDMMC_INT_HLE BIT(12) 367 #define SDMMC_INT_FRUN BIT(11) 368 #define SDMMC_INT_HTO BIT(10) 369 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 370 #define SDMMC_INT_DRTO BIT(9) 371 #define SDMMC_INT_RTO BIT(8) 372 #define SDMMC_INT_DCRC BIT(7) 373 #define SDMMC_INT_RCRC BIT(6) 374 #define SDMMC_INT_RXDR BIT(5) 375 #define SDMMC_INT_TXDR BIT(4) 376 #define SDMMC_INT_DATA_OVER BIT(3) 377 #define SDMMC_INT_CMD_DONE BIT(2) 378 #define SDMMC_INT_RESP_ERR BIT(1) 379 #define SDMMC_INT_CD BIT(0) 380 #define SDMMC_INT_ERROR 0xbfc2 381 /* Command register defines */ 382 #define SDMMC_CMD_START BIT(31) 383 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 384 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 385 #define SDMMC_CMD_CCS_EXP BIT(23) 386 #define SDMMC_CMD_CEATA_RD BIT(22) 387 #define SDMMC_CMD_UPD_CLK BIT(21) 388 #define SDMMC_CMD_INIT BIT(15) 389 #define SDMMC_CMD_STOP BIT(14) 390 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 391 #define SDMMC_CMD_SEND_STOP BIT(12) 392 #define SDMMC_CMD_STRM_MODE BIT(11) 393 #define SDMMC_CMD_DAT_WR BIT(10) 394 #define SDMMC_CMD_DAT_EXP BIT(9) 395 #define SDMMC_CMD_RESP_CRC BIT(8) 396 #define SDMMC_CMD_RESP_LONG BIT(7) 397 #define SDMMC_CMD_RESP_EXP BIT(6) 398 #define SDMMC_CMD_INDX(n) ((n)&0x1F) 399 /* Status register defines */ 400 #define SDMMC_GET_FCNT(x) (((x) >> 17) & 0x1FFF) 401 #define SDMMC_STATUS_DMA_REQ BIT(31) 402 #define SDMMC_STATUS_BUSY BIT(9) 403 /* FIFOTH register defines */ 404 #define SDMMC_SET_FIFOTH(m, r, t) (((m)&0x7) << 28 | ((r)&0xFFF) << 16 | ((t)&0xFFF)) 405 /* HCON register defines */ 406 #define DMA_INTERFACE_IDMA (0x0) 407 #define DMA_INTERFACE_DWDMA (0x1) 408 #define DMA_INTERFACE_GDMA (0x2) 409 #define DMA_INTERFACE_NODMA (0x3) 410 #define SDMMC_GET_TRANS_MODE(x) (((x) >> 16) & 0x3) 411 #define SDMMC_GET_SLOT_NUM(x) ((((x) >> 1) & 0x1F) + 1) 412 #define SDMMC_GET_HDATA_WIDTH(x) (((x) >> 7) & 0x7) 413 #define SDMMC_GET_ADDR_CONFIG(x) (((x) >> 27) & 0x1) 414 /* Internal DMAC interrupt defines */ 415 #define SDMMC_IDMAC_INT_AI BIT(9) 416 #define SDMMC_IDMAC_INT_NI BIT(8) 417 #define SDMMC_IDMAC_INT_CES BIT(5) 418 #define SDMMC_IDMAC_INT_DU BIT(4) 419 #define SDMMC_IDMAC_INT_FBE BIT(2) 420 #define SDMMC_IDMAC_INT_RI BIT(1) 421 #define SDMMC_IDMAC_INT_TI BIT(0) 422 /* Internal DMAC bus mode bits */ 423 #define SDMMC_IDMAC_ENABLE BIT(7) 424 #define SDMMC_IDMAC_FB BIT(1) 425 #define SDMMC_IDMAC_SWRESET BIT(0) 426 /* H/W reset */ 427 #define SDMMC_RST_HWACTIVE 0x1 428 /* Version ID register define */ 429 #define SDMMC_GET_VERID(x) ((x)&0xFFFF) 430 /* Card read threshold */ 431 #define SDMMC_SET_THLD(v, x) (((v)&0xFFF) << 16 | (x)) 432 #define SDMMC_CARD_WR_THR_EN BIT(2) 433 #define SDMMC_CARD_RD_THR_EN BIT(0) 434 /* UHS-1 register defines */ 435 #define SDMMC_UHS_DDR BIT(16) 436 #define SDMMC_UHS_18V BIT(0) 437 /* DDR register defines */ 438 #define SDMMC_DDR_HS400 BIT(31) 439 /* Enable shift register defines */ 440 #define SDMMC_ENABLE_PHASE BIT(0) 441 /* All ctrl reset bits */ 442 #define SDMMC_CTRL_ALL_RESET_FLAGS (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 443 444 /* FIFO register access macros. These should not change the data endian-ness 445 * as they are written to memory to be dealt with by the upper layers 446 */ 447 #define mci_fifo_readw(__reg) __raw_readw(__reg) 448 #define mci_fifo_readl(__reg) __raw_readl(__reg) 449 #define mci_fifo_readq(__reg) __raw_readq(__reg) 450 451 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 452 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 453 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 454 455 /* Register access macros */ 456 #define mci_readl(dev, reg) readl_relaxed((dev)->regs + SDMMC_##reg) 457 #define mci_writel(dev, reg, value) writel_relaxed((value), (dev)->regs + SDMMC_##reg) 458 459 /* 16-bit FIFO access macros */ 460 #define mci_readw(dev, reg) readw_relaxed((dev)->regs + SDMMC_##reg) 461 #define mci_writew(dev, reg, value) writew_relaxed((value), (dev)->regs + SDMMC_##reg) 462 463 /* 64-bit FIFO access macros */ 464 #ifdef readq 465 #define mci_readq(dev, reg) readq_relaxed((dev)->regs + SDMMC_##reg) 466 #define mci_writeq(dev, reg, value) writeq_relaxed((value), (dev)->regs + SDMMC_##reg) 467 #else 468 /* 469 * Dummy readq implementation for architectures that don't define it. 470 * 471 * We would assume that none of these architectures would configure 472 * the IP block with a 64bit FIFO width, so this code will never be 473 * executed on those machines. Defining these macros here keeps the 474 * rest of the code free from ifdefs. 475 */ 476 #define mci_readq(dev, reg) (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) 477 #define mci_writeq(dev, reg, value) (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 478 479 #define __raw_writeq(__value, __reg) (*(volatile u64 __force *)(__reg) = (__value)) 480 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 481 #endif 482 483 extern int dw_mci_probe(struct dw_mci *host); 484 extern void dw_mci_remove(struct dw_mci *host); 485 #ifdef CONFIG_PM 486 extern int dw_mci_runtime_suspend(struct device *device); 487 extern int dw_mci_runtime_resume(struct device *device); 488 #endif 489 490 /** 491 * struct dw_mci_slot - MMC slot state 492 * @mmc: The mmc_host representing this slot. 493 * @host: The MMC controller this slot is using. 494 * @ctype: Card type for this slot. 495 * @mrq: mmc_request currently being processed or waiting to be 496 * processed, or NULL when the slot is idle. 497 * @queue_node: List node for placing this node in the @queue list of 498 * &struct dw_mci. 499 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 500 * @__clk_old: The last clock value that was requested from core. 501 * Keeping track of this helps us to avoid spamming the console. 502 * @flags: Random state bits associated with the slot. 503 * @id: Number of this slot. 504 * @sdio_id: Number of this slot in the SDIO interrupt registers. 505 */ 506 struct dw_mci_slot { 507 struct mmc_host *mmc; 508 struct dw_mci *host; 509 510 u32 ctype; 511 512 struct mmc_request *mrq; 513 struct list_head queue_node; 514 515 unsigned int clock; 516 unsigned int __clk_old; 517 518 unsigned long flags; 519 #define DW_MMC_CARD_PRESENT 0 520 #define DW_MMC_CARD_NEED_INIT 1 521 #define DW_MMC_CARD_NO_LOW_PWR 2 522 #define DW_MMC_CARD_NO_USE_HOLD 3 523 #define DW_MMC_CARD_NEEDS_POLL 4 524 int id; 525 int sdio_id; 526 }; 527 528 /** 529 * dw_mci driver data - dw-mshc implementation specific driver data. 530 * @caps: mmc subsystem specified capabilities of the controller(s). 531 * @num_caps: number of capabilities specified by @caps. 532 * @init: early implementation specific initialization. 533 * @set_ios: handle bus specific extensions. 534 * @parse_dt: parse implementation specific device tree properties. 535 * @execute_tuning: implementation specific tuning procedure. 536 * 537 * Provide controller implementation specific extensions. The usage of this 538 * data structure is fully optional and usage of each member in this structure 539 * is optional as well. 540 */ 541 struct dw_mci_drv_data { 542 unsigned long *caps; 543 u32 num_caps; 544 int (*init)(struct dw_mci *host); 545 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 546 int (*parse_dt)(struct dw_mci *host); 547 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); 548 int (*prepare_hs400_tuning)(struct dw_mci *host, struct mmc_ios *ios); 549 int (*switch_voltage)(struct mmc_host *mmc, struct mmc_ios *ios); 550 }; 551 #endif /* _DW_MMC_H_ */ 552