1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef H_DW_HDMI_H 7 #define H_DW_HDMI_H 8 9 #include <drm/drm_property.h> 10 #include <sound/hdmi-codec.h> 11 #include <media/cec.h> 12 13 struct drm_display_info; 14 struct drm_display_mode; 15 struct drm_encoder; 16 struct dw_hdmi; 17 struct dw_hdmi_qp; 18 struct platform_device; 19 20 /** 21 * DOC: Supported input formats and encodings 22 * 23 * Depending on the Hardware configuration of the Controller IP, it supports 24 * a subset of the following input formats and encodings on its internal 25 * 48bit bus. 26 * 27 * +----------------------+----------------------------------+------------------------------+ 28 * | Format Name | Format Code | Encodings | 29 * +----------------------+----------------------------------+------------------------------+ 30 * | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 31 * +----------------------+----------------------------------+------------------------------+ 32 * | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 33 * +----------------------+----------------------------------+------------------------------+ 34 * | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 35 * +----------------------+----------------------------------+------------------------------+ 36 * | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` | 37 * +----------------------+----------------------------------+------------------------------+ 38 * | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` | 39 * | | | or ``V4L2_YCBCR_ENC_709`` | 40 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 41 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 42 * +----------------------+----------------------------------+------------------------------+ 43 * | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` | 44 * | | | or ``V4L2_YCBCR_ENC_709`` | 45 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 46 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 47 * +----------------------+----------------------------------+------------------------------+ 48 * | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` | 49 * | | | or ``V4L2_YCBCR_ENC_709`` | 50 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 51 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 52 * +----------------------+----------------------------------+------------------------------+ 53 * | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` | 54 * | | | or ``V4L2_YCBCR_ENC_709`` | 55 * | | | or ``V4L2_YCBCR_ENC_XV601`` | 56 * | | | or ``V4L2_YCBCR_ENC_XV709`` | 57 * +----------------------+----------------------------------+------------------------------+ 58 * | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` | 59 * | | | or ``V4L2_YCBCR_ENC_709`` | 60 * +----------------------+----------------------------------+------------------------------+ 61 * | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` | 62 * | | | or ``V4L2_YCBCR_ENC_709`` | 63 * +----------------------+----------------------------------+------------------------------+ 64 * | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` | 65 * | | | or ``V4L2_YCBCR_ENC_709`` | 66 * +----------------------+----------------------------------+------------------------------+ 67 * | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` | 68 * | | | or ``V4L2_YCBCR_ENC_709`` | 69 * +----------------------+----------------------------------+------------------------------+ 70 * | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` | 71 * | | | or ``V4L2_YCBCR_ENC_709`` | 72 * +----------------------+----------------------------------+------------------------------+ 73 * | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` | 74 * | | | or ``V4L2_YCBCR_ENC_709`` | 75 * +----------------------+----------------------------------+------------------------------+ 76 * | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` | 77 * | | | or ``V4L2_YCBCR_ENC_709`` | 78 * +----------------------+----------------------------------+------------------------------+ 79 */ 80 81 enum { 82 DW_HDMI_RES_8, 83 DW_HDMI_RES_10, 84 DW_HDMI_RES_12, 85 DW_HDMI_RES_MAX, 86 }; 87 88 enum dw_hdmi_phy_type { 89 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, 90 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, 91 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, 92 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, 93 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, 94 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, 95 DW_HDMI_PHY_VENDOR_PHY = 0xfe, 96 }; 97 98 struct dw_hdmi_audio_tmds_n { 99 unsigned long tmds; 100 unsigned int n_32k; 101 unsigned int n_44k1; 102 unsigned int n_48k; 103 }; 104 105 struct dw_hdmi_mpll_config { 106 unsigned long mpixelclock; 107 struct { 108 u16 cpce; 109 u16 gmp; 110 } res[DW_HDMI_RES_MAX]; 111 }; 112 113 struct dw_hdmi_curr_ctrl { 114 unsigned long mpixelclock; 115 u16 curr[DW_HDMI_RES_MAX]; 116 }; 117 118 struct dw_hdmi_phy_config { 119 unsigned long mpixelclock; 120 u16 sym_ctr; /* clock symbol and transmitter control */ 121 u16 term; /* transmission termination value */ 122 u16 vlev_ctr; /* voltage level control */ 123 }; 124 125 struct dw_hdmi_link_config { 126 bool dsc_mode; 127 bool frl_mode; 128 int frl_lanes; 129 int rate_per_lane; 130 int hcactive; 131 u8 pps_payload[128]; 132 }; 133 134 struct dw_hdmi_phy_ops { 135 int (*init)(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *display, 136 const struct drm_display_mode *mode); 137 void (*disable)(struct dw_hdmi *hdmi, void *data); 138 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); 139 void (*update_hpd)(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense); 140 void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); 141 }; 142 143 struct dw_hdmi_qp_phy_ops { 144 int (*init)(struct dw_hdmi_qp *hdmi, void *data, struct drm_display_mode *mode); 145 void (*disable)(struct dw_hdmi_qp *hdmi, void *data); 146 enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, void *data); 147 void (*update_hpd)(struct dw_hdmi_qp *hdmi, void *data, bool force, bool disabled, bool rxsense); 148 void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data); 149 void (*set_mode)(struct dw_hdmi_qp *dw_hdmi, void *data, u32 mode_mask, bool enable); 150 }; 151 152 struct dw_hdmi_property_ops { 153 void (*attach_properties)(struct drm_connector *connector, unsigned int color, int version, void *data); 154 void (*destroy_properties)(struct drm_connector *connector, void *data); 155 int (*set_property)(struct drm_connector *connector, struct drm_connector_state *state, 156 struct drm_property *property, u64 val, void *data); 157 int (*get_property)(struct drm_connector *connector, const struct drm_connector_state *state, 158 struct drm_property *property, u64 *val, void *data); 159 }; 160 161 struct dw_hdmi_plat_data { 162 struct regmap *regm; 163 164 unsigned long input_bus_format; 165 unsigned long input_bus_encoding; 166 unsigned int max_tmdsclk; 167 bool use_drm_infoframe; 168 bool ycbcr_420_allowed; 169 bool unsupported_yuv_input; 170 bool unsupported_deep_color; 171 bool is_hdmi_qp; 172 173 /* 174 * Private data passed to all the .mode_valid() and .configure_phy() 175 * callback functions. 176 */ 177 void *priv_data; 178 179 /* Platform-specific mode validation (optional). */ 180 enum drm_mode_status (*mode_valid)(struct drm_connector *connector, void *data, const struct drm_display_info *info, 181 const struct drm_display_mode *mode); 182 183 /* Vendor PHY support */ 184 const struct dw_hdmi_phy_ops *phy_ops; 185 const struct dw_hdmi_qp_phy_ops *qp_phy_ops; 186 const char *phy_name; 187 void *phy_data; 188 unsigned int phy_force_vendor; 189 const struct dw_hdmi_audio_tmds_n *tmds_n_table; 190 191 /* Synopsys PHY support */ 192 const struct dw_hdmi_mpll_config *mpll_cfg; 193 const struct dw_hdmi_mpll_config *mpll_cfg_420; 194 const struct dw_hdmi_curr_ctrl *cur_ctr; 195 const struct dw_hdmi_phy_config *phy_config; 196 int (*configure_phy)(struct dw_hdmi *hdmi, void *data, unsigned long mpixelclock); 197 198 unsigned long (*get_input_bus_format)(void *data); 199 unsigned long (*get_output_bus_format)(void *data); 200 unsigned long (*get_enc_in_encoding)(void *data); 201 unsigned long (*get_enc_out_encoding)(void *data); 202 unsigned long (*get_quant_range)(void *data); 203 struct drm_property *(*get_hdr_property)(void *data); 204 struct drm_property_blob *(*get_hdr_blob)(void *data); 205 bool (*get_color_changed)(void *data); 206 int (*get_yuv422_format)(struct drm_connector *connector, struct edid *edid); 207 int (*get_edid_dsc_info)(void *data, struct edid *edid); 208 int (*get_next_hdr_data)(void *data, struct edid *edid, struct drm_connector *connector); 209 struct dw_hdmi_link_config *(*get_link_cfg)(void *data); 210 211 /* Vendor Property support */ 212 const struct dw_hdmi_property_ops *property_ops; 213 struct drm_connector *connector; 214 }; 215 216 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, const struct dw_hdmi_plat_data *plat_data); 217 void dw_hdmi_remove(struct dw_hdmi *hdmi); 218 void dw_hdmi_unbind(struct dw_hdmi *hdmi); 219 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, 220 struct dw_hdmi_plat_data *plat_data); 221 222 void dw_hdmi_suspend(struct dw_hdmi *hdmi); 223 void dw_hdmi_resume(struct dw_hdmi *hdmi); 224 225 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); 226 227 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, struct device *codec_dev); 228 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); 229 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); 230 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status); 231 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); 232 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); 233 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); 234 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, const struct drm_display_info *display); 235 236 /* PHY configuration */ 237 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); 238 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, unsigned char addr); 239 240 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); 241 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); 242 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); 243 244 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data); 245 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense); 246 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); 247 void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi); 248 void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val); 249 bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi); 250 int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi); 251 void dw_hdmi_set_cec_adap(struct dw_hdmi *hdmi, struct cec_adapter *adap); 252 253 void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi); 254 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, struct drm_encoder *encoder, 255 struct dw_hdmi_plat_data *plat_data); 256 void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi); 257 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi); 258 void dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp *hdmi, bool plug_in, bool change); 259 void dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp *hdmi, struct cec_adapter *adap); 260 int dw_hdmi_qp_set_earc(struct dw_hdmi_qp *hdmi); 261 void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned int rate); 262 void dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp *hdmi, unsigned int cnt); 263 void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi, u8 *channel_status); 264 void dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp *hdmi, unsigned int ca); 265 void dw_hdmi_qp_audio_enable(struct dw_hdmi_qp *hdmi); 266 void dw_hdmi_qp_audio_disable(struct dw_hdmi_qp *hdmi); 267 int dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp *hdmi, hdmi_codec_plugged_cb fn, struct device *codec_dev); 268 269 #endif /* __IMX_HDMI_H__ */ 270