1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author:
5 * Algea Cao <algea.cao@rock-chips.com>
6 */
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/extcon.h>
13 #include <linux/hdmi.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/regmap.h>
20 #include <linux/spinlock.h>
21
22 #include <drm/drm_atomic.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_dsc.h>
26 #include <drm/drm_edid.h>
27 #include <drm/drm_encoder_slave.h>
28 #include <drm/drm_of.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_scdc_helper.h>
32 #include <drm/bridge/dw_hdmi.h>
33
34 #include <uapi/linux/media-bus-format.h>
35 #include <uapi/linux/videodev2.h>
36
37 #include "dw-hdmi-qp-audio.h"
38 #include "dw-hdmi-qp.h"
39
40 #include <media/cec-notifier.h>
41
42 #define DDC_CI_ADDR 0x37
43 #define DDC_SEGMENT_ADDR 0x30
44
45 #define HDMI_EDID_LEN 512
46
47 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
48 #define SCDC_MIN_SOURCE_VERSION 0x1
49
50 #define HDMI14_MAX_TMDSCLK 340000000
51
52 static const unsigned int dw_hdmi_cable[] = {
53 EXTCON_DISP_HDMI,
54 EXTCON_NONE,
55 };
56
57 /*
58 * Unless otherwise noted, entries in this table are 100% optimization.
59 * Values can be obtained from hdmi_compute_n() but that function is
60 * slow so we pre-compute values we expect to see.
61 *
62 * All 32k and 48k values are expected to be the same (due to the way
63 * the math works) for any rate that's an exact kHz.
64 */
65 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
66 {
67 .tmds = 25175000,
68 .n_32k = 4096,
69 .n_44k1 = 12854,
70 .n_48k = 6144,
71 },
72 {
73 .tmds = 25200000,
74 .n_32k = 4096,
75 .n_44k1 = 5656,
76 .n_48k = 6144,
77 },
78 {
79 .tmds = 27000000,
80 .n_32k = 4096,
81 .n_44k1 = 5488,
82 .n_48k = 6144,
83 },
84 {
85 .tmds = 28320000,
86 .n_32k = 4096,
87 .n_44k1 = 5586,
88 .n_48k = 6144,
89 },
90 {
91 .tmds = 30240000,
92 .n_32k = 4096,
93 .n_44k1 = 5642,
94 .n_48k = 6144,
95 },
96 {
97 .tmds = 31500000,
98 .n_32k = 4096,
99 .n_44k1 = 5600,
100 .n_48k = 6144,
101 },
102 {
103 .tmds = 32000000,
104 .n_32k = 4096,
105 .n_44k1 = 5733,
106 .n_48k = 6144,
107 },
108 {
109 .tmds = 33750000,
110 .n_32k = 4096,
111 .n_44k1 = 6272,
112 .n_48k = 6144,
113 },
114 {
115 .tmds = 36000000,
116 .n_32k = 4096,
117 .n_44k1 = 5684,
118 .n_48k = 6144,
119 },
120 {
121 .tmds = 40000000,
122 .n_32k = 4096,
123 .n_44k1 = 5733,
124 .n_48k = 6144,
125 },
126 {
127 .tmds = 49500000,
128 .n_32k = 4096,
129 .n_44k1 = 5488,
130 .n_48k = 6144,
131 },
132 {
133 .tmds = 50000000,
134 .n_32k = 4096,
135 .n_44k1 = 5292,
136 .n_48k = 6144,
137 },
138 {
139 .tmds = 54000000,
140 .n_32k = 4096,
141 .n_44k1 = 5684,
142 .n_48k = 6144,
143 },
144 {
145 .tmds = 65000000,
146 .n_32k = 4096,
147 .n_44k1 = 7056,
148 .n_48k = 6144,
149 },
150 {
151 .tmds = 68250000,
152 .n_32k = 4096,
153 .n_44k1 = 5376,
154 .n_48k = 6144,
155 },
156 {
157 .tmds = 71000000,
158 .n_32k = 4096,
159 .n_44k1 = 7056,
160 .n_48k = 6144,
161 },
162 {
163 .tmds = 72000000,
164 .n_32k = 4096,
165 .n_44k1 = 5635,
166 .n_48k = 6144,
167 },
168 {
169 .tmds = 73250000,
170 .n_32k = 4096,
171 .n_44k1 = 14112,
172 .n_48k = 6144,
173 },
174 {
175 .tmds = 74250000,
176 .n_32k = 4096,
177 .n_44k1 = 6272,
178 .n_48k = 6144,
179 },
180 {
181 .tmds = 75000000,
182 .n_32k = 4096,
183 .n_44k1 = 5880,
184 .n_48k = 6144,
185 },
186 {
187 .tmds = 78750000,
188 .n_32k = 4096,
189 .n_44k1 = 5600,
190 .n_48k = 6144,
191 },
192 {
193 .tmds = 78800000,
194 .n_32k = 4096,
195 .n_44k1 = 5292,
196 .n_48k = 6144,
197 },
198 {
199 .tmds = 79500000,
200 .n_32k = 4096,
201 .n_44k1 = 4704,
202 .n_48k = 6144,
203 },
204 {
205 .tmds = 83500000,
206 .n_32k = 4096,
207 .n_44k1 = 7056,
208 .n_48k = 6144,
209 },
210 {
211 .tmds = 85500000,
212 .n_32k = 4096,
213 .n_44k1 = 5488,
214 .n_48k = 6144,
215 },
216 {
217 .tmds = 88750000,
218 .n_32k = 4096,
219 .n_44k1 = 14112,
220 .n_48k = 6144,
221 },
222 {
223 .tmds = 97750000,
224 .n_32k = 4096,
225 .n_44k1 = 14112,
226 .n_48k = 6144,
227 },
228 {
229 .tmds = 101000000,
230 .n_32k = 4096,
231 .n_44k1 = 7056,
232 .n_48k = 6144,
233 },
234 {
235 .tmds = 106500000,
236 .n_32k = 4096,
237 .n_44k1 = 4704,
238 .n_48k = 6144,
239 },
240 {
241 .tmds = 108000000,
242 .n_32k = 4096,
243 .n_44k1 = 5684,
244 .n_48k = 6144,
245 },
246 {
247 .tmds = 115500000,
248 .n_32k = 4096,
249 .n_44k1 = 5712,
250 .n_48k = 6144,
251 },
252 {
253 .tmds = 119000000,
254 .n_32k = 4096,
255 .n_44k1 = 5544,
256 .n_48k = 6144,
257 },
258 {
259 .tmds = 135000000,
260 .n_32k = 4096,
261 .n_44k1 = 5488,
262 .n_48k = 6144,
263 },
264 {
265 .tmds = 146250000,
266 .n_32k = 4096,
267 .n_44k1 = 6272,
268 .n_48k = 6144,
269 },
270 {
271 .tmds = 148500000,
272 .n_32k = 4096,
273 .n_44k1 = 5488,
274 .n_48k = 6144,
275 },
276 {
277 .tmds = 154000000,
278 .n_32k = 4096,
279 .n_44k1 = 5544,
280 .n_48k = 6144,
281 },
282 {
283 .tmds = 162000000,
284 .n_32k = 4096,
285 .n_44k1 = 5684,
286 .n_48k = 6144,
287 },
288
289 /* For 297 MHz+ HDMI spec have some other rule for setting N */
290 {
291 .tmds = 297000000,
292 .n_32k = 3073,
293 .n_44k1 = 4704,
294 .n_48k = 5120,
295 },
296 {
297 .tmds = 594000000,
298 .n_32k = 3073,
299 .n_44k1 = 9408,
300 .n_48k = 10240,
301 },
302
303 /* End of table */
304 {
305 .tmds = 0,
306 .n_32k = 0,
307 .n_44k1 = 0,
308 .n_48k = 0,
309 },
310 };
311
312 static const struct drm_display_mode dw_hdmi_default_modes[] = {
313 /* 16 - 1920x1080@60Hz 16:9 */
314 {
315 DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
318 },
319 /* 2 - 720x480@60Hz 4:3 */
320 {
321 DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
322 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
324 },
325 /* 4 - 1280x720@60Hz 16:9 */
326 {
327 DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
330 },
331 /* 31 - 1920x1080@50Hz 16:9 */
332 {
333 DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
336 },
337 /* 19 - 1280x720@50Hz 16:9 */
338 {
339 DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,
342 },
343 /* 17 - 720x576@50Hz 4:3 */
344 {
345 DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
348 },
349 /* 2 - 720x480@60Hz 4:3 */
350 {
351 DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
354 },
355 };
356
357 enum frl_mask {
358 FRL_3GBPS_3LANE = 1,
359 FRL_6GBPS_3LANE,
360 FRL_6GBPS_4LANE,
361 FRL_8GBPS_4LANE,
362 FRL_10GBPS_4LANE,
363 FRL_12GBPS_4LANE,
364 };
365
366 struct hdmi_vmode_qp {
367 bool mdataenablepolarity;
368
369 unsigned int previous_pixelclock;
370 unsigned long mpixelclock;
371 unsigned int mpixelrepetitioninput;
372 unsigned int mpixelrepetitionoutput;
373 unsigned long previous_tmdsclock;
374 unsigned int mtmdsclock;
375 };
376
377 struct hdmi_qp_data_info {
378 unsigned int enc_in_bus_format;
379 unsigned int enc_out_bus_format;
380 unsigned int enc_in_encoding;
381 unsigned int enc_out_encoding;
382 unsigned int quant_range;
383 unsigned int pix_repet_factor;
384 struct hdmi_vmode_qp video_mode;
385 bool update;
386 };
387
388 struct dw_hdmi_qp_i2c {
389 struct i2c_adapter adap;
390
391 struct mutex lock; /* used to serialize data transfers */
392 struct completion cmp;
393 u32 stat;
394
395 u8 slave_reg;
396 bool is_regaddr;
397 bool is_segment;
398
399 unsigned int scl_high_ns;
400 unsigned int scl_low_ns;
401 };
402
403 struct dw_hdmi_phy_data {
404 enum dw_hdmi_phy_type type;
405 const char *name;
406 unsigned int gen;
407 bool has_svsret;
408 int (*configure)(struct dw_hdmi_qp *hdmi, const struct dw_hdmi_plat_data *pdata, unsigned long mpixelclock);
409 };
410
411 struct dw_hdmi_qp {
412 struct drm_connector connector;
413 struct drm_bridge bridge;
414 struct platform_device *hdcp_dev;
415 struct platform_device *audio;
416
417 struct device *dev;
418 struct dw_hdmi_qp_i2c *i2c;
419
420 struct hdmi_qp_data_info hdmi_data;
421 const struct dw_hdmi_plat_data *plat_data;
422
423 int vic;
424 int main_irq;
425 int avp_irq;
426 int earc_irq;
427
428 u8 edid[HDMI_EDID_LEN];
429
430 struct {
431 const struct dw_hdmi_qp_phy_ops *ops;
432 const char *name;
433 void *data;
434 bool enabled;
435 } phy;
436
437 struct drm_display_mode previous_mode;
438
439 struct i2c_adapter *ddc;
440 void __iomem *regs;
441 bool sink_is_hdmi;
442 bool sink_has_audio;
443 bool hpd_state;
444
445 struct mutex mutex; /* for state below and previous_mode */
446 struct drm_connector *curr_conn; /* current connector (only valid when !disabled) */
447 enum drm_connector_force force; /* mutex-protected force state */
448 bool disabled; /* DRM has disabled our bridge */
449 bool bridge_is_on; /* indicates the bridge is on */
450 bool rxsense; /* rxsense state */
451 u8 phy_mask; /* desired phy int mask settings */
452 u8 mc_clkdis; /* clock disable register */
453
454 u32 scdc_intr;
455 u32 flt_intr;
456 u32 earc_intr;
457
458 spinlock_t audio_lock;
459 struct mutex audio_mutex;
460 unsigned int sample_rate;
461 unsigned int audio_cts;
462 unsigned int audio_n;
463 bool audio_enable;
464 void (*enable_audio)(struct dw_hdmi_qp *hdmi);
465 void (*disable_audio)(struct dw_hdmi_qp *hdmi);
466
467 struct dentry *debugfs_dir;
468 bool scramble_low_rates;
469
470 struct extcon_dev *extcon;
471
472 struct regmap *regm;
473
474 bool initialized; /* hdmi is enabled before bind */
475 struct completion flt_cmp;
476 struct completion earc_cmp;
477
478 struct cec_notifier *cec_notifier;
479 struct cec_adapter *cec_adap;
480 struct mutex cec_notifier_mutex;
481
482 hdmi_codec_plugged_cb plugged_cb;
483 struct device *codec_dev;
484 enum drm_connector_status last_connector_result;
485 };
486
hdmi_writel(struct dw_hdmi_qp * hdmi,u32 val,int offset)487 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset)
488 {
489 regmap_write(hdmi->regm, offset, val);
490 }
491
hdmi_readl(struct dw_hdmi_qp * hdmi,int offset)492 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset)
493 {
494 unsigned int val = 0;
495
496 regmap_read(hdmi->regm, offset, &val);
497
498 return val;
499 }
500
handle_plugged_change(struct dw_hdmi_qp * hdmi,bool plugged)501 static void handle_plugged_change(struct dw_hdmi_qp *hdmi, bool plugged)
502 {
503 if (hdmi->plugged_cb && hdmi->codec_dev) {
504 hdmi->plugged_cb(hdmi->codec_dev, plugged);
505 }
506 }
507
dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp * hdmi,hdmi_codec_plugged_cb fn,struct device * codec_dev)508 int dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp *hdmi, hdmi_codec_plugged_cb fn, struct device *codec_dev)
509 {
510 bool plugged;
511
512 mutex_lock(&hdmi->mutex);
513 hdmi->plugged_cb = fn;
514 hdmi->codec_dev = codec_dev;
515 plugged = hdmi->last_connector_result == connector_status_connected;
516 handle_plugged_change(hdmi, plugged);
517 mutex_unlock(&hdmi->mutex);
518
519 return 0;
520 }
521 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_plugged_cb);
522
hdmi_modb(struct dw_hdmi_qp * hdmi,u32 data,u32 mask,u32 reg)523 static void hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, u32 reg)
524 {
525 regmap_update_bits(hdmi->regm, reg, mask, data);
526 }
527
hdmi_set_cts_n(struct dw_hdmi_qp * hdmi,unsigned int cts,unsigned int n)528 static void hdmi_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts, unsigned int n)
529 {
530 /* Set N */
531 hdmi_modb(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0);
532
533 /* Set CTS */
534 if (cts) {
535 hdmi_modb(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK, AUDPKT_ACR_CONTROL1);
536 } else {
537 hdmi_modb(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK, AUDPKT_ACR_CONTROL1);
538 }
539
540 hdmi_modb(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK, AUDPKT_ACR_CONTROL1);
541 }
542
hdmi_match_tmds_n_table(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)543 static int hdmi_match_tmds_n_table(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, unsigned long freq)
544 {
545 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
546 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
547 int i;
548
549 if (plat_data->tmds_n_table) {
550 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
551 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
552 tmds_n = &plat_data->tmds_n_table[i];
553 break;
554 }
555 }
556 }
557
558 if (tmds_n == NULL) {
559 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
560 if (pixel_clk == common_tmds_n_table[i].tmds) {
561 tmds_n = &common_tmds_n_table[i];
562 break;
563 }
564 }
565 }
566
567 if (tmds_n == NULL) {
568 return -ENOENT;
569 }
570
571 switch (freq) {
572 case 0x7D00:
573 return tmds_n->n_32k;
574 case 0xAC44:
575 case 0x15888:
576 case 0x2B110:
577 return (freq / 0xAC44) * tmds_n->n_44k1;
578 case 0xBB80:
579 case 0x17700:
580 case 0x2EE00:
581 return (freq / 0xBB80) * tmds_n->n_48k;
582 default:
583 return -ENOENT;
584 }
585 }
586
hdmi_audio_math_diff(unsigned int freq,unsigned int n,unsigned int pixel_clk)587 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n, unsigned int pixel_clk)
588 {
589 u64 final, diff;
590 u64 cts;
591
592 final = (u64)pixel_clk * n;
593
594 cts = final;
595 do_div(cts, 0x80 * freq);
596
597 diff = final - (u64)cts * (0x80 * freq);
598
599 return diff;
600 }
601
hdmi_compute_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)602 static unsigned int hdmi_compute_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, unsigned long freq)
603 {
604 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
605 unsigned int max_n = (128 * freq) / 300;
606 unsigned int ideal_n = (128 * freq) / 1000;
607 unsigned int best_n_distance = ideal_n;
608 unsigned int best_n = 0;
609 u64 best_diff = U64_MAX;
610 int n;
611
612 /* If the ideal N could satisfy the audio math, then just take it */
613 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0) {
614 return ideal_n;
615 }
616
617 for (n = min_n; n <= max_n; n++) {
618 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
619 if (diff < best_diff || (diff == best_diff && abs(n - ideal_n) < best_n_distance)) {
620 best_n = n;
621 best_diff = diff;
622 best_n_distance = abs(best_n - ideal_n);
623 }
624
625 /*
626 * The best N already satisfy the audio math, and also be
627 * the closest value to ideal N, so just cut the loop.
628 */
629 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance)) {
630 break;
631 }
632 }
633
634 return best_n;
635 }
636
hdmi_find_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long sample_rate)637 static unsigned int hdmi_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, unsigned long sample_rate)
638 {
639 int n;
640
641 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
642 if (n > 0) {
643 return n;
644 }
645
646 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", pixel_clk);
647
648 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
649 }
650
651 /*
652 * When transmitting IEC60958 linear PCM audio, these registers allow to
653 * configure the channel status information of all the channel status
654 * bits in the IEC60958 frame. For the moment this configuration is only
655 * used when the I2S audio interface, General Purpose Audio (GPA),
656 * or AHB audio DMA (AHBAUDDMA) interface is active
657 * (for S/PDIF interface this information comes from the stream).
658 */
dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp * hdmi,u8 * channel_status)659 void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi, u8 *channel_status)
660 {
661 /* Set channel status */
662 hdmi_writel(hdmi, channel_status[0x3] | (channel_status[0x4] << 0x8), AUDPKT_CHSTATUS_OVR1);
663 hdmi_modb(hdmi, AUDPKT_CHSTATUS_OVR_EN, AUDPKT_CHSTATUS_OVR_EN_MASK, AUDPKT_CONTROL0);
664 }
665 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_status);
666
hdmi_set_clk_regenerator(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned int sample_rate)667 static void hdmi_set_clk_regenerator(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, unsigned int sample_rate)
668 {
669 unsigned int n = 0, cts = 0;
670
671 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
672
673 spin_lock_irq(&hdmi->audio_lock);
674 hdmi->audio_n = n;
675 hdmi->audio_cts = cts;
676 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
677 spin_unlock_irq(&hdmi->audio_lock);
678 }
679
hdmi_init_clk_regenerator(struct dw_hdmi_qp * hdmi)680 static void hdmi_init_clk_regenerator(struct dw_hdmi_qp *hdmi)
681 {
682 mutex_lock(&hdmi->audio_mutex);
683 hdmi_set_clk_regenerator(hdmi, 0x46CF710, hdmi->sample_rate);
684 mutex_unlock(&hdmi->audio_mutex);
685 }
686
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi_qp * hdmi)687 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi_qp *hdmi)
688 {
689 mutex_lock(&hdmi->audio_mutex);
690 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, hdmi->sample_rate);
691 mutex_unlock(&hdmi->audio_mutex);
692 }
693
dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp * hdmi,unsigned int rate)694 void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned int rate)
695 {
696 mutex_lock(&hdmi->audio_mutex);
697 hdmi->sample_rate = rate;
698 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, hdmi->sample_rate);
699 mutex_unlock(&hdmi->audio_mutex);
700 }
701 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_sample_rate);
702
dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp * hdmi,unsigned int cnt)703 void dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp *hdmi, unsigned int cnt)
704 {
705 }
706 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_count);
707
dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp * hdmi,unsigned int ca)708 void dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp *hdmi, unsigned int ca)
709 {
710 }
711 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_allocation);
712
hdmi_enable_audio_clk(struct dw_hdmi_qp * hdmi,bool enable)713 static void hdmi_enable_audio_clk(struct dw_hdmi_qp *hdmi, bool enable)
714 {
715 if (enable) {
716 hdmi_modb(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
717 } else {
718 hdmi_modb(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
719 }
720 }
721
dw_hdmi_i2s_audio_enable(struct dw_hdmi_qp * hdmi)722 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi_qp *hdmi)
723 {
724 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
725 hdmi_enable_audio_clk(hdmi, true);
726 }
727
dw_hdmi_i2s_audio_disable(struct dw_hdmi_qp * hdmi)728 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi_qp *hdmi)
729 {
730 hdmi_enable_audio_clk(hdmi, false);
731 }
732
dw_hdmi_qp_audio_enable(struct dw_hdmi_qp * hdmi)733 void dw_hdmi_qp_audio_enable(struct dw_hdmi_qp *hdmi)
734 {
735 unsigned long flags;
736
737 spin_lock_irqsave(&hdmi->audio_lock, flags);
738 hdmi->audio_enable = true;
739 if (hdmi->enable_audio) {
740 hdmi->enable_audio(hdmi);
741 }
742 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
743 }
744 EXPORT_SYMBOL_GPL(dw_hdmi_qp_audio_enable);
745
dw_hdmi_qp_audio_disable(struct dw_hdmi_qp * hdmi)746 void dw_hdmi_qp_audio_disable(struct dw_hdmi_qp *hdmi)
747 {
748 unsigned long flags;
749
750 spin_lock_irqsave(&hdmi->audio_lock, flags);
751 hdmi->audio_enable = false;
752 if (hdmi->disable_audio) {
753 hdmi->disable_audio(hdmi);
754 }
755 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
756 }
757 EXPORT_SYMBOL_GPL(dw_hdmi_qp_audio_disable);
758
hdmi_bus_fmt_is_rgb(unsigned int bus_format)759 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
760 {
761 switch (bus_format) {
762 case MEDIA_BUS_FMT_RGB888_1X24:
763 case MEDIA_BUS_FMT_RGB101010_1X30:
764 case MEDIA_BUS_FMT_RGB121212_1X36:
765 case MEDIA_BUS_FMT_RGB161616_1X48:
766 return true;
767
768 default:
769 return false;
770 }
771 }
772
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)773 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
774 {
775 switch (bus_format) {
776 case MEDIA_BUS_FMT_YUV8_1X24:
777 case MEDIA_BUS_FMT_YUV10_1X30:
778 case MEDIA_BUS_FMT_YUV12_1X36:
779 case MEDIA_BUS_FMT_YUV16_1X48:
780 return true;
781
782 default:
783 return false;
784 }
785 }
786
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)787 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
788 {
789 switch (bus_format) {
790 case MEDIA_BUS_FMT_UYVY8_1X16:
791 case MEDIA_BUS_FMT_UYVY10_1X20:
792 case MEDIA_BUS_FMT_UYVY12_1X24:
793 return true;
794
795 default:
796 return false;
797 }
798 }
799
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)800 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
801 {
802 switch (bus_format) {
803 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
804 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
805 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
806 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
807 return true;
808
809 default:
810 return false;
811 }
812 }
813
hdmi_bus_fmt_color_depth(unsigned int bus_format)814 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
815 {
816 switch (bus_format) {
817 case MEDIA_BUS_FMT_RGB888_1X24:
818 case MEDIA_BUS_FMT_YUV8_1X24:
819 case MEDIA_BUS_FMT_UYVY8_1X16:
820 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
821 return 0x8;
822
823 case MEDIA_BUS_FMT_RGB101010_1X30:
824 case MEDIA_BUS_FMT_YUV10_1X30:
825 case MEDIA_BUS_FMT_UYVY10_1X20:
826 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
827 return 0xA;
828
829 case MEDIA_BUS_FMT_RGB121212_1X36:
830 case MEDIA_BUS_FMT_YUV12_1X36:
831 case MEDIA_BUS_FMT_UYVY12_1X24:
832 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
833 return 0xC;
834
835 case MEDIA_BUS_FMT_RGB161616_1X48:
836 case MEDIA_BUS_FMT_YUV16_1X48:
837 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
838 return 0x10;
839
840 default:
841 return 0;
842 }
843 }
844
dw_hdmi_i2c_init(struct dw_hdmi_qp * hdmi)845 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi)
846 {
847 /* Software reset */
848 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
849 hdmi_writel(hdmi, 0x00, I2CM_CONTROL0);
850
851 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
852
853 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
854
855 /* Clear DONE and ERROR interrupts */
856 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, MAINUNIT_1_INT_CLEAR);
857 }
858
dw_hdmi_i2c_read(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)859 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, unsigned char *buf, unsigned int length)
860 {
861 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
862 int stat;
863
864 if (!i2c->is_regaddr) {
865 dev_dbg(hdmi->dev, "set read register address to 0\n");
866 i2c->slave_reg = 0x00;
867 i2c->is_regaddr = true;
868 }
869
870 while (length--) {
871 reinit_completion(&i2c->cmp);
872
873 hdmi_modb(hdmi, i2c->slave_reg++ << 0xC, I2CM_ADDR, I2CM_INTERFACE_CONTROL0);
874
875 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
876
877 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 0xA);
878 if (!stat) {
879 dev_err(hdmi->dev, "i2c read time out!\n");
880 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
881 return -EAGAIN;
882 }
883
884 /* Check for error condition on the bus */
885 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
886 dev_err(hdmi->dev, "i2c read err!\n");
887 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
888 return -EIO;
889 }
890
891 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff;
892 dev_dbg(hdmi->dev, "i2c read done! i2c->stat:%02x 0x%02x\n", i2c->stat,
893 hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3));
894 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
895 }
896 i2c->is_segment = false;
897
898 return 0;
899 }
900
dw_hdmi_i2c_write(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)901 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, unsigned char *buf, unsigned int length)
902 {
903 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
904 int stat;
905
906 if (!i2c->is_regaddr) {
907 /* Use the first write byte as register address */
908 i2c->slave_reg = buf[0];
909 length--;
910 buf++;
911 i2c->is_regaddr = true;
912 }
913
914 while (length--) {
915 reinit_completion(&i2c->cmp);
916
917 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
918 hdmi_modb(hdmi, i2c->slave_reg++ << 0xC, I2CM_ADDR, I2CM_INTERFACE_CONTROL0);
919 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
920
921 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 0xA);
922 if (!stat) {
923 dev_err(hdmi->dev, "i2c write time out!\n");
924 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
925 return -EAGAIN;
926 }
927
928 /* Check for error condition on the bus */
929 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
930 dev_err(hdmi->dev, "i2c write nack!\n");
931 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
932 return -EIO;
933 }
934 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
935 }
936 dev_dbg(hdmi->dev, "i2c write done!\n");
937 return 0;
938 }
939
dw_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)940 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
941 {
942 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap);
943 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
944 u8 addr = msgs[0].addr;
945 int i, ret = 0;
946
947 if (addr == DDC_CI_ADDR) {
948 /*
949 * The internal I2C controller does not support the multi-byte
950 * read and write operations needed for DDC/CI.
951 * TOFIX: Blacklist the DDC/CI address until we filter out
952 * unsupported I2C operations.
953 */
954 return -EOPNOTSUPP;
955 }
956
957 dev_dbg(hdmi->dev, "i2c xfer: num: %d, addr: %#x\n", num, addr);
958
959 for (i = 0; i < num; i++) {
960 if (msgs[i].len == 0) {
961 dev_err(hdmi->dev, "unsupported transfer %d/%d, no data\n", i + 1, num);
962 return -EOPNOTSUPP;
963 }
964 }
965
966 mutex_lock(&i2c->lock);
967
968 /* Unmute DONE and ERROR interrupts */
969 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
970 MAINUNIT_1_INT_MASK_N);
971
972 /* Set slave device address taken from the first I2C message */
973 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) {
974 addr = DDC_ADDR;
975 }
976
977 hdmi_modb(hdmi, addr << 0x5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
978
979 /* Set slave device register address on transfer */
980 i2c->is_regaddr = false;
981
982 /* Set segment pointer for I2C extended read mode operation */
983 i2c->is_segment = false;
984
985 for (i = 0; i < num; i++) {
986 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", i + 1, num, msgs[i].len, msgs[i].flags);
987
988 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
989 i2c->is_segment = true;
990 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, I2CM_INTERFACE_CONTROL1);
991 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, I2CM_INTERFACE_CONTROL1);
992 } else {
993 if (msgs[i].flags & I2C_M_RD) {
994 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
995 } else {
996 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
997 }
998 }
999 if (ret < 0) {
1000 break;
1001 }
1002 }
1003
1004 if (!ret) {
1005 ret = num;
1006 }
1007
1008 /* Mute DONE and ERROR interrupts */
1009 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, MAINUNIT_1_INT_MASK_N);
1010
1011 mutex_unlock(&i2c->lock);
1012
1013 return ret;
1014 }
1015
dw_hdmi_i2c_func(struct i2c_adapter * adapter)1016 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
1017 {
1018 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1019 }
1020
1021 static const struct i2c_algorithm dw_hdmi_algorithm = {
1022 .master_xfer = dw_hdmi_i2c_xfer,
1023 .functionality = dw_hdmi_i2c_func,
1024 };
1025
dw_hdmi_i2c_adapter(struct dw_hdmi_qp * hdmi)1026 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi_qp *hdmi)
1027 {
1028 struct i2c_adapter *adap;
1029 struct dw_hdmi_qp_i2c *i2c;
1030 int ret;
1031
1032 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
1033 if (!i2c) {
1034 return ERR_PTR(-ENOMEM);
1035 }
1036
1037 mutex_init(&i2c->lock);
1038 init_completion(&i2c->cmp);
1039
1040 adap = &i2c->adap;
1041 adap->class = I2C_CLASS_DDC;
1042 adap->owner = THIS_MODULE;
1043 adap->dev.parent = hdmi->dev;
1044 adap->algo = &dw_hdmi_algorithm;
1045 strscpy(adap->name, "ddc", sizeof(adap->name));
1046 i2c_set_adapdata(adap, hdmi);
1047
1048 ret = i2c_add_adapter(adap);
1049 if (ret) {
1050 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
1051 devm_kfree(hdmi->dev, i2c);
1052 return ERR_PTR(ret);
1053 }
1054
1055 hdmi->i2c = i2c;
1056
1057 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
1058
1059 return adap;
1060 }
1061
1062 #define HDMI_PHY_EARC_MASK BIT(29)
1063
dw_hdmi_qp_set_earc(struct dw_hdmi_qp * hdmi)1064 int dw_hdmi_qp_set_earc(struct dw_hdmi_qp *hdmi)
1065 {
1066 u32 stat, ret;
1067
1068 /* set hdmi phy earc mode */
1069 hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_PHY_EARC_MASK, true);
1070
1071 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1072 if (ret) {
1073 return ret;
1074 }
1075
1076 reinit_completion(&hdmi->earc_cmp);
1077
1078 hdmi_modb(hdmi, EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ | EARCRX_CMDC_DISCOVERY_DONE_IRQ,
1079 EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ | EARCRX_CMDC_DISCOVERY_DONE_IRQ, EARCRX_0_INT_MASK_N);
1080
1081 /* start discovery */
1082 hdmi_modb(hdmi, EARCRX_CMDC_DISCOVERY_EN, EARCRX_CMDC_DISCOVERY_EN, EARCRX_CMDC_CONTROL);
1083
1084 /*
1085 * The eARC TX device drives a logic-high-voltage-level
1086 * pulse on the physical HPD connector pin, after
1087 * at least 100 ms of low voltage level to start the
1088 * eARC Discovery process.
1089 */
1090 hdmi_modb(hdmi, EARCRX_CONNECTOR_HPD, EARCRX_CONNECTOR_HPD, EARCRX_CMDC_CONTROL);
1091
1092 stat = wait_for_completion_timeout(&hdmi->earc_cmp, HZ / 0xA);
1093 if (!stat) {
1094 return -EAGAIN;
1095 }
1096
1097 if (hdmi->earc_intr & EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ) {
1098 dev_err(hdmi->dev, "discovery timeout\n");
1099 return -ETIMEDOUT;
1100 } else if (hdmi->earc_intr & EARCRX_CMDC_DISCOVERY_DONE_IRQ) {
1101 dev_info(hdmi->dev, "discovery done\n");
1102 } else {
1103 dev_err(hdmi->dev, "discovery failed\n");
1104 return -EINVAL;
1105 }
1106
1107 hdmi_writel(hdmi, 1, EARCRX_DMAC_PHY_CONTROL);
1108 hdmi_modb(hdmi, EARCRX_CMDC_SWINIT_P, EARCRX_CMDC_SWINIT_P, EARCRX_CMDC_CONFIG0);
1109
1110 hdmi_writel(hdmi, 0xf3, EARCRX_DMAC_CONFIG);
1111 hdmi_writel(hdmi, 0x63, EARCRX_DMAC_CONTROL0);
1112 hdmi_writel(hdmi, 0xff, EARCRX_DMAC_CONTROL1);
1113
1114 hdmi_modb(hdmi,
1115 EARCRX_XACTREAD_STOP_CFG | EARCRX_XACTREAD_RETRY_CFG | EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 |
1116 EARCRX_CMDC_XACT_RESTART_EN,
1117 EARCRX_XACTREAD_STOP_CFG | EARCRX_XACTREAD_RETRY_CFG | EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 |
1118 EARCRX_CMDC_XACT_RESTART_EN,
1119 EARCRX_CMDC_CONFIG0);
1120
1121 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER0);
1122 hdmi_writel(hdmi, 0x1b0e, EARCRX_DMAC_CHSTATUS_STREAMER1);
1123 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER2);
1124 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER3);
1125 hdmi_writel(hdmi, 0xf2000000, EARCRX_DMAC_CHSTATUS_STREAMER4);
1126 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER5);
1127 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER6);
1128 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER7);
1129 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER8);
1130
1131 return 0;
1132 }
1133 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_earc);
1134
1135 /* -----------------------------------------------------------------------------
1136 * HDMI TX Setup
1137 */
1138
hdmi_config_AVI(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1139 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, const struct drm_connector *connector,
1140 const struct drm_display_mode *mode)
1141 {
1142 struct hdmi_avi_infoframe frame;
1143 u32 val, i, j;
1144 u8 buff[17];
1145 enum hdmi_quantization_range rgb_quant_range = hdmi->hdmi_data.quant_range;
1146
1147 /* Initialise info frame from DRM mode */
1148 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1149
1150 /*
1151 * Ignore monitor selectable quantization, use quantization set
1152 * by the user
1153 */
1154 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, rgb_quant_range);
1155 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) {
1156 frame.colorspace = HDMI_COLORSPACE_YUV444;
1157 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1158 frame.colorspace = HDMI_COLORSPACE_YUV422;
1159 } else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1160 frame.colorspace = HDMI_COLORSPACE_YUV420;
1161 } else {
1162 frame.colorspace = HDMI_COLORSPACE_RGB;
1163 }
1164
1165 /* Set up colorimetry */
1166 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1167 switch (hdmi->hdmi_data.enc_out_encoding) {
1168 case V4L2_YCBCR_ENC_601:
1169 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) {
1170 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1171 } else {
1172 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1173 }
1174 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1175 break;
1176 case V4L2_YCBCR_ENC_709:
1177 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) {
1178 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1179 } else {
1180 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1181 }
1182 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1183 break;
1184 case V4L2_YCBCR_ENC_BT2020:
1185 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) {
1186 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1187 } else {
1188 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1189 }
1190 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_BT2020;
1191 break;
1192 default: /* Carries no data */
1193 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1194 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1195 break;
1196 }
1197 } else {
1198 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1199 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1200 }
1201
1202 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1203
1204 hdmi_avi_infoframe_pack_only(&frame, buff, 17);
1205
1206 /*
1207 * The Designware IP uses a different byte format from standard
1208 * AVI info frames, though generally the bits are in the correct
1209 * bytes.
1210 */
1211
1212 val = (frame.version << 8) | (frame.length << 16);
1213 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0);
1214
1215 for (i = 0; i < 4; i++) {
1216 for (j = 0; j < 4; j++) {
1217 if (i * 4 + j >= 14) {
1218 break;
1219 }
1220 if (!j) {
1221 val = buff[i * 4 + j + 3];
1222 }
1223 val |= buff[i * 4 + j + 3] << (8 * j);
1224 }
1225
1226 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
1227 }
1228
1229 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN);
1230 }
1231
hdmi_config_CVTEM(struct dw_hdmi_qp * hdmi)1232 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi)
1233 {
1234 u8 ds_type = 0;
1235 u8 sync = 1;
1236 u8 vfr = 1;
1237 u8 afr = 0;
1238 u8 new = 1;
1239 u8 end = 0;
1240 u8 data_set_length = 136;
1241 u8 hb1[6] = {0x80, 0, 0, 0, 0, 0x40};
1242 u8 *pps_body;
1243 u32 val, i, reg;
1244 struct drm_display_mode *mode = &hdmi->previous_mode;
1245 int hsync, hfront, hback;
1246 struct dw_hdmi_link_config *link_cfg;
1247 void *data = hdmi->plat_data->phy_data;
1248
1249 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN);
1250
1251 if (hdmi->plat_data->get_link_cfg) {
1252 link_cfg = hdmi->plat_data->get_link_cfg(data);
1253 } else {
1254 dev_err(hdmi->dev, "can't get frl link cfg\n");
1255 return;
1256 }
1257
1258 if (!link_cfg->dsc_mode) {
1259 dev_info(hdmi->dev, "don't use dsc mode\n");
1260 return;
1261 }
1262
1263 pps_body = link_cfg->pps_payload;
1264
1265 hsync = mode->hsync_end - mode->hsync_start;
1266 hback = mode->htotal - mode->hsync_end;
1267 hfront = mode->hsync_start - mode->hdisplay;
1268
1269 for (i = 0; i < 6; i++) {
1270 val = (i << 16) | (hb1[i] << 8);
1271 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20);
1272 }
1273
1274 val = (new << 7) | (end << 6) | (ds_type << 4) | (afr << 3) | (vfr << 2) | (sync << 1);
1275 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1);
1276
1277 val = (data_set_length << 16) | (pps_body[0] << 24);
1278 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2);
1279
1280 reg = PKT0_EMP_CVTEM_CONTENTS3;
1281 for (i = 1; i < 125; i++) {
1282 if (reg == PKT1_EMP_CVTEM_CONTENTS0 || reg == PKT2_EMP_CVTEM_CONTENTS0 || reg == PKT3_EMP_CVTEM_CONTENTS0 ||
1283 reg == PKT4_EMP_CVTEM_CONTENTS0 || reg == PKT5_EMP_CVTEM_CONTENTS0) {
1284 reg += 4;
1285 i--;
1286 continue;
1287 }
1288 if (i % 4 == 1) {
1289 val = pps_body[i];
1290 }
1291 if (i % 4 == 2) {
1292 val |= pps_body[i] << 8;
1293 }
1294 if (i % 4 == 3) {
1295 val |= pps_body[i] << 16;
1296 }
1297 if (!(i % 4)) {
1298 val |= pps_body[i] << 24;
1299 hdmi_writel(hdmi, val, reg);
1300 reg += 4;
1301 }
1302 }
1303
1304 val = ((hfront & 0xff) << 24) | (pps_body[127] << 16) | (pps_body[126] << 8) | pps_body[125];
1305 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6);
1306
1307 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff);
1308 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7);
1309
1310 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff);
1311 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1);
1312
1313 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) {
1314 hdmi_writel(hdmi, 0, i);
1315 }
1316
1317 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN);
1318 }
1319
hdmi_config_drm_infoframe(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector)1320 static void hdmi_config_drm_infoframe(struct dw_hdmi_qp *hdmi, const struct drm_connector *connector)
1321 {
1322 const struct drm_connector_state *conn_state = connector->state;
1323 struct hdr_output_metadata *hdr_metadata;
1324 struct hdmi_drm_infoframe frame;
1325 u8 buffer[30];
1326 ssize_t err;
1327 int i;
1328 u32 val;
1329
1330 if (!hdmi->plat_data->use_drm_infoframe) {
1331 return;
1332 }
1333
1334 hdmi_modb(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
1335
1336 if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
1337 DRM_DEBUG("No need to set HDR metadata in infoframe\n");
1338 return;
1339 }
1340
1341 if (!conn_state->hdr_output_metadata) {
1342 DRM_DEBUG("source metadata not set yet\n");
1343 return;
1344 }
1345
1346 hdr_metadata = (struct hdr_output_metadata *)conn_state->hdr_output_metadata->data;
1347
1348 if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf & BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
1349 DRM_ERROR("Not support EOTF %d\n", hdr_metadata->hdmi_metadata_type1.eotf);
1350 return;
1351 }
1352
1353 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1354 if (err < 0) {
1355 return;
1356 }
1357
1358 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1359 if (err < 0) {
1360 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1361 return;
1362 }
1363
1364 val = (frame.version << 8) | (frame.length << 16);
1365 hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS0);
1366
1367 for (i = 0; i <= frame.length; i++) {
1368 if (i % 4 == 0) {
1369 val = buffer[3 + i];
1370 }
1371 val |= buffer[3 + i] << ((i % 4) * 8);
1372
1373 if (i % 4 == 3 || (i == (frame.length))) {
1374 hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS1 + ((i / 4) * 4));
1375 }
1376 }
1377
1378 hdmi_modb(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
1379
1380 DRM_DEBUG("%s eotf %d end\n", __func__, hdr_metadata->hdmi_metadata_type1.eotf);
1381 }
1382
1383 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
dw_hdmi_support_scdc(struct dw_hdmi_qp * hdmi,const struct drm_display_info * display)1384 static bool dw_hdmi_support_scdc(struct dw_hdmi_qp *hdmi, const struct drm_display_info *display)
1385 {
1386 /* Disable if no DDC bus */
1387 if (!hdmi->ddc) {
1388 return false;
1389 }
1390
1391 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1392 if (!display->hdmi.scdc.supported || !display->hdmi.scdc.scrambling.supported) {
1393 return false;
1394 }
1395
1396 /*
1397 * Disable if display only support low TMDS rates and scrambling
1398 * for low rates is not supported either
1399 */
1400 if (!display->hdmi.scdc.scrambling.low_rates && display->max_tmds_clock <= 340000) {
1401 return false;
1402 }
1403
1404 return true;
1405 }
1406
hdmi_set_frl_mask(int frl_rate)1407 static int hdmi_set_frl_mask(int frl_rate)
1408 {
1409 switch (frl_rate) {
1410 case 48:
1411 return FRL_12GBPS_4LANE;
1412 case 40:
1413 return FRL_10GBPS_4LANE;
1414 case 32:
1415 return FRL_8GBPS_4LANE;
1416 case 24:
1417 return FRL_6GBPS_4LANE;
1418 case 18:
1419 return FRL_6GBPS_3LANE;
1420 case 9:
1421 return FRL_3GBPS_3LANE;
1422 default:
1423 break;
1424 }
1425
1426 return 0;
1427 }
1428
hdmi_start_flt(struct dw_hdmi_qp * hdmi,u8 rate)1429 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate)
1430 {
1431 u8 val;
1432 u8 ffe_lv = 0;
1433 int i = 0, stat;
1434
1435 /* FLT_READY & FFE_LEVELS read */
1436 for (i = 0; i < 20; i++) {
1437 drm_scdc_readb(hdmi->ddc, SCDC_STATUS_FLAGS_0, &val);
1438 if (val & BIT(6)) {
1439 break;
1440 }
1441 msleep(20);
1442 }
1443
1444 if (i == 20) {
1445 dev_err(hdmi->dev, "sink flt isn't ready\n");
1446 return -EINVAL;
1447 }
1448
1449 hdmi_modb(hdmi, SCDC_UPD_FLAGS_RD_IRQ, SCDC_UPD_FLAGS_RD_IRQ, MAINUNIT_1_INT_MASK_N);
1450 hdmi_modb(hdmi, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR,
1451 SCDC_CONFIG0);
1452
1453 /* max ffe level 3 */
1454 val = 3 << 4 | hdmi_set_frl_mask(rate);
1455 drm_scdc_writeb(hdmi->ddc, 0x31, val);
1456
1457 /* select FRL_RATE & FFE_LEVELS */
1458 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0);
1459
1460 /* Start LTS_3 state in source DUT */
1461 reinit_completion(&hdmi->flt_cmp);
1462 hdmi_modb(hdmi, FLT_EXIT_TO_LTSP_IRQ, FLT_EXIT_TO_LTSP_IRQ, MAINUNIT_1_INT_MASK_N);
1463 hdmi_writel(hdmi, 1, FLT_CONTROL0);
1464
1465 /* wait for completed link training at source side */
1466 stat = wait_for_completion_timeout(&hdmi->flt_cmp, HZ * 2);
1467 if (!stat) {
1468 dev_err(hdmi->dev, "wait lts3 finish time out\n");
1469 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
1470 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, MAINUNIT_1_INT_MASK_N);
1471 return -EAGAIN;
1472 }
1473
1474 if (!(hdmi->flt_intr & FLT_EXIT_TO_LTSP_IRQ)) {
1475 dev_err(hdmi->dev, "not to ltsp\n");
1476 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
1477 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, MAINUNIT_1_INT_MASK_N);
1478 return -EINVAL;
1479 }
1480
1481 return 0;
1482 }
1483
1484 #define HDMI_MODE_FRL_MASK BIT(30)
1485
hdmi_set_op_mode(struct dw_hdmi_qp * hdmi,struct dw_hdmi_link_config * link_cfg,const struct drm_connector * connector)1486 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, struct dw_hdmi_link_config *link_cfg,
1487 const struct drm_connector *connector)
1488 {
1489 int frl_rate;
1490
1491 hdmi_writel(hdmi, 0, FLT_CONFIG0);
1492 if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) {
1493 drm_scdc_writeb(hdmi->ddc, 0x31, 0);
1494 }
1495 msleep(20);
1496 if (!link_cfg->frl_mode) {
1497 dev_info(hdmi->dev, "dw hdmi qp use tmds mode\n");
1498 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0);
1499 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1500 return;
1501 }
1502
1503 if (link_cfg->frl_lanes == 4) {
1504 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, LINK_CONFIG0);
1505 } else {
1506 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1507 }
1508
1509 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0);
1510
1511 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane;
1512 hdmi_start_flt(hdmi, frl_rate);
1513 }
1514
hdmi_get_tmdsclock(struct dw_hdmi_qp * hdmi,unsigned long mpixelclock)1515 static unsigned long hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock)
1516 {
1517 unsigned long tmdsclock = mpixelclock;
1518 unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
1519
1520 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1521 switch (depth) {
1522 case 16:
1523 tmdsclock = mpixelclock * 2;
1524 break;
1525 case 12:
1526 tmdsclock = mpixelclock * 3 / 2;
1527 break;
1528 case 10:
1529 tmdsclock = mpixelclock * 5 / 4;
1530 break;
1531 default:
1532 break;
1533 }
1534 }
1535
1536 return tmdsclock;
1537 }
1538
dw_hdmi_qp_setup(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1539 static int dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi, const struct drm_connector *connector,
1540 const struct drm_display_mode *mode)
1541 {
1542 int ret;
1543 void *data = hdmi->plat_data->phy_data;
1544 struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode;
1545 struct dw_hdmi_link_config *link_cfg;
1546 u8 bytes = 0;
1547
1548 hdmi->vic = drm_match_cea_mode(mode);
1549
1550 if (!hdmi->vic) {
1551 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1552 } else {
1553 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1554 }
1555
1556 if (hdmi->plat_data->get_enc_out_encoding) {
1557 hdmi->hdmi_data.enc_out_encoding = hdmi->plat_data->get_enc_out_encoding(data);
1558 } else if ((hdmi->vic == 6) || (hdmi->vic == 7) || (hdmi->vic == 21) || (hdmi->vic == 22) || (hdmi->vic == 2) ||
1559 (hdmi->vic == 3) || (hdmi->vic == 17) || (hdmi->vic == 18)) {
1560 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1561 } else {
1562 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1563 }
1564
1565 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1566 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1567 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1568 } else {
1569 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1570 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1571 }
1572 /* Get input format from plat data or fallback to RGB888 */
1573 if (hdmi->plat_data->get_input_bus_format) {
1574 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->get_input_bus_format(data);
1575 } else if (hdmi->plat_data->input_bus_format) {
1576 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->input_bus_format;
1577 } else {
1578 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1579 }
1580
1581 /* Default to RGB888 output format */
1582 if (hdmi->plat_data->get_output_bus_format) {
1583 hdmi->hdmi_data.enc_out_bus_format = hdmi->plat_data->get_output_bus_format(data);
1584 } else {
1585 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1586 }
1587
1588 /* Get input encoding from plat data or fallback to none */
1589 if (hdmi->plat_data->get_enc_in_encoding) {
1590 hdmi->hdmi_data.enc_in_encoding = hdmi->plat_data->get_enc_in_encoding(data);
1591 } else if (hdmi->plat_data->input_bus_encoding) {
1592 hdmi->hdmi_data.enc_in_encoding = hdmi->plat_data->input_bus_encoding;
1593 } else {
1594 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1595 }
1596
1597 if (hdmi->plat_data->get_quant_range) {
1598 hdmi->hdmi_data.quant_range = hdmi->plat_data->get_quant_range(data);
1599 } else {
1600 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1601 }
1602
1603 if (hdmi->plat_data->get_link_cfg) {
1604 link_cfg = hdmi->plat_data->get_link_cfg(data);
1605 } else {
1606 return -EINVAL;
1607 }
1608
1609 hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_MODE_FRL_MASK, link_cfg->frl_mode);
1610
1611 /*
1612 * According to the dw-hdmi specification 6.4.2
1613 * vp_pr_cd[3:0]:
1614 * 0000b: No pixel repetition (pixel sent only once)
1615 * 0001b: Pixel sent two times (pixel repeated once)
1616 */
1617 hdmi->hdmi_data.pix_repet_factor = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1618 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1619
1620 vmode->previous_pixelclock = vmode->mpixelclock;
1621 vmode->mpixelclock = mode->crtc_clock * 1000;
1622 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) {
1623 vmode->mpixelclock *= 2;
1624 }
1625 dev_dbg(hdmi->dev, "final pixclk = %ld\n", vmode->mpixelclock);
1626 vmode->previous_tmdsclock = vmode->mtmdsclock;
1627 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
1628 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1629 vmode->mtmdsclock /= 2;
1630 }
1631 dev_info(hdmi->dev, "final tmdsclk = %d\n", vmode->mtmdsclock);
1632
1633 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1634 if (ret) {
1635 return ret;
1636 }
1637
1638 if (hdmi->sink_has_audio) {
1639 dev_dbg(hdmi->dev, "sink has audio support\n");
1640
1641 /* HDMI Initialization Step E - Configure audio */
1642 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1643 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
1644 }
1645
1646 /* not for DVI mode */
1647 if (hdmi->sink_is_hdmi) {
1648 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1649 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0);
1650 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
1651 if (!link_cfg->frl_mode) {
1652 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) {
1653 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes);
1654 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1655 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1656 drm_scdc_set_scrambling(hdmi->ddc, 1);
1657 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0);
1658 } else {
1659 if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) {
1660 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1661 drm_scdc_set_scrambling(hdmi->ddc, 0);
1662 }
1663 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0);
1664 }
1665 }
1666 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1667 hdmi_config_AVI(hdmi, connector, mode);
1668 hdmi_config_CVTEM(hdmi);
1669 hdmi_config_drm_infoframe(hdmi, connector);
1670 hdmi_set_op_mode(hdmi, link_cfg, connector);
1671 } else {
1672 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0);
1673 dev_info(hdmi->dev, "%s DVI mode\n", __func__);
1674 }
1675
1676 return 0;
1677 }
1678
dw_hdmi_connector_detect(struct drm_connector * connector,bool force)1679 static enum drm_connector_status dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1680 {
1681 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1682
1683 mutex_lock(&hdmi->mutex);
1684 hdmi->force = DRM_FORCE_UNSPECIFIED;
1685 mutex_unlock(&hdmi->mutex);
1686
1687 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1688 }
1689
dw_hdmi_update_hdr_property(struct drm_connector * connector)1690 static int dw_hdmi_update_hdr_property(struct drm_connector *connector)
1691 {
1692 struct drm_device *dev = connector->dev;
1693 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1694 void *data = hdmi->plat_data->phy_data;
1695 const struct hdr_static_metadata *metadata = &connector->hdr_sink_metadata.hdmi_type1;
1696 size_t size = sizeof(*metadata);
1697 struct drm_property *property;
1698 struct drm_property_blob *blob;
1699 int ret;
1700
1701 if (hdmi->plat_data->get_hdr_property) {
1702 property = hdmi->plat_data->get_hdr_property(data);
1703 } else {
1704 return -EINVAL;
1705 }
1706
1707 if (hdmi->plat_data->get_hdr_blob) {
1708 blob = hdmi->plat_data->get_hdr_blob(data);
1709 } else {
1710 return -EINVAL;
1711 }
1712
1713 ret = drm_property_replace_global_blob(dev, &blob, size, metadata, &connector->base, property);
1714 return ret;
1715 }
1716
dw_hdmi_connector_get_modes(struct drm_connector * connector)1717 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1718 {
1719 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1720 struct hdr_static_metadata *metedata = &connector->hdr_sink_metadata.hdmi_type1;
1721 struct edid *edid;
1722 struct drm_display_mode *mode;
1723 struct drm_display_info *info = &connector->display_info;
1724 void *data = hdmi->plat_data->phy_data;
1725 int i, ret = 0;
1726
1727 if (!hdmi->ddc) {
1728 return 0;
1729 }
1730
1731 memset(metedata, 0, sizeof(*metedata));
1732 edid = drm_get_edid(connector, hdmi->ddc);
1733 if (edid) {
1734 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", edid->width_cm, edid->height_cm);
1735
1736 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1737 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1738 drm_connector_update_edid_property(connector, edid);
1739 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
1740 if (hdmi->plat_data->get_edid_dsc_info) {
1741 hdmi->plat_data->get_edid_dsc_info(data, edid);
1742 }
1743 ret = drm_add_edid_modes(connector, edid);
1744 dw_hdmi_update_hdr_property(connector);
1745 kfree(edid);
1746 } else {
1747 hdmi->sink_is_hdmi = true;
1748 hdmi->sink_has_audio = true;
1749
1750 for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
1751 const struct drm_display_mode *ptr = &dw_hdmi_default_modes[i];
1752
1753 mode = drm_mode_duplicate(connector->dev, ptr);
1754 if (mode) {
1755 if (!i) {
1756 mode->type = DRM_MODE_TYPE_PREFERRED;
1757 mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1758 }
1759 drm_mode_probed_add(connector, mode);
1760 ret++;
1761 }
1762 }
1763 info->edid_hdmi_dc_modes = 0;
1764 info->hdmi.y420_dc_modes = 0;
1765 info->color_formats = 0;
1766
1767 dev_info(hdmi->dev, "failed to get edid\n");
1768 }
1769
1770 return ret;
1771 }
1772
dw_hdmi_atomic_connector_set_property(struct drm_connector * connector,struct drm_connector_state * state,struct drm_property * property,uint64_t val)1773 static int dw_hdmi_atomic_connector_set_property(struct drm_connector *connector, struct drm_connector_state *state,
1774 struct drm_property *property, uint64_t val)
1775 {
1776 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1777 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1778
1779 if (ops && ops->set_property) {
1780 return ops->set_property(connector, state, property, val, hdmi->plat_data->phy_data);
1781 } else {
1782 return -EINVAL;
1783 }
1784 }
1785
dw_hdmi_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)1786 static int dw_hdmi_atomic_connector_get_property(struct drm_connector *connector,
1787 const struct drm_connector_state *state, struct drm_property *property,
1788 uint64_t *val)
1789 {
1790 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1791 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1792
1793 if (ops && ops->get_property) {
1794 return ops->get_property(connector, state, property, val, hdmi->plat_data->phy_data);
1795 } else {
1796 return -EINVAL;
1797 }
1798 }
1799
dw_hdmi_connector_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)1800 static int dw_hdmi_connector_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val)
1801 {
1802 return dw_hdmi_atomic_connector_set_property(connector, NULL, property, val);
1803 }
1804
dw_hdmi_attach_properties(struct dw_hdmi_qp * hdmi)1805 static void dw_hdmi_attach_properties(struct dw_hdmi_qp *hdmi)
1806 {
1807 unsigned int color = MEDIA_BUS_FMT_RGB888_1X24;
1808 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1809
1810 if (ops && ops->attach_properties) {
1811 return ops->attach_properties(&hdmi->connector, color, 0, hdmi->plat_data->phy_data);
1812 }
1813 }
1814
dw_hdmi_destroy_properties(struct dw_hdmi_qp * hdmi)1815 static void dw_hdmi_destroy_properties(struct dw_hdmi_qp *hdmi)
1816 {
1817 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1818
1819 if (ops && ops->destroy_properties) {
1820 return ops->destroy_properties(&hdmi->connector, hdmi->plat_data->phy_data);
1821 }
1822 }
1823
dw_hdmi_connector_best_encoder(struct drm_connector * connector)1824 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector *connector)
1825 {
1826 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1827
1828 return hdmi->bridge.encoder;
1829 }
1830
dw_hdmi_color_changed(struct drm_connector * connector)1831 static bool dw_hdmi_color_changed(struct drm_connector *connector)
1832 {
1833 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1834 void *data = hdmi->plat_data->phy_data;
1835 bool ret = false;
1836
1837 if (hdmi->plat_data->get_color_changed) {
1838 ret = hdmi->plat_data->get_color_changed(data);
1839 }
1840
1841 return ret;
1842 }
1843
hdr_metadata_equal(const struct drm_connector_state * old_state,const struct drm_connector_state * new_state)1844 static bool hdr_metadata_equal(const struct drm_connector_state *old_state, const struct drm_connector_state *new_state)
1845 {
1846 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
1847 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
1848
1849 if (!old_blob || !new_blob) {
1850 return old_blob == new_blob;
1851 }
1852
1853 if (old_blob->length != new_blob->length) {
1854 return false;
1855 }
1856
1857 return !memcmp(old_blob->data, new_blob->data, old_blob->length);
1858 }
1859
dw_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1860 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state)
1861 {
1862 struct drm_connector_state *old_state = drm_atomic_get_old_connector_state(state, connector);
1863 struct drm_connector_state *new_state = drm_atomic_get_new_connector_state(state, connector);
1864 struct drm_crtc *crtc = new_state->crtc;
1865 struct drm_crtc_state *crtc_state;
1866 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1867 struct drm_display_mode *mode = NULL;
1868 void *data = hdmi->plat_data->phy_data;
1869 struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode;
1870 unsigned int in_bus_format = hdmi->hdmi_data.enc_in_bus_format;
1871 unsigned int out_bus_format = hdmi->hdmi_data.enc_out_bus_format;
1872 bool color_changed = false;
1873
1874 if (!crtc) {
1875 return 0;
1876 }
1877
1878 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1879 if (IS_ERR(crtc_state)) {
1880 return PTR_ERR(crtc_state);
1881 }
1882
1883 /*
1884 * If HDMI is enabled in uboot, it's need to record
1885 * drm_display_mode and set phy status to enabled.
1886 */
1887 if (!vmode->mpixelclock) {
1888 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1889 if (hdmi->plat_data->get_enc_in_encoding) {
1890 hdmi->hdmi_data.enc_in_encoding = hdmi->plat_data->get_enc_in_encoding(data);
1891 }
1892 if (hdmi->plat_data->get_enc_out_encoding) {
1893 hdmi->hdmi_data.enc_out_encoding = hdmi->plat_data->get_enc_out_encoding(data);
1894 }
1895 if (hdmi->plat_data->get_input_bus_format) {
1896 hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->get_input_bus_format(data);
1897 }
1898 if (hdmi->plat_data->get_output_bus_format) {
1899 hdmi->hdmi_data.enc_out_bus_format = hdmi->plat_data->get_output_bus_format(data);
1900 }
1901
1902 mode = &crtc_state->mode;
1903 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1904 vmode->mpixelclock = mode->crtc_clock * 1000;
1905 vmode->previous_pixelclock = mode->clock;
1906 vmode->previous_tmdsclock = mode->clock;
1907 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
1908 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1909 vmode->mtmdsclock /= 2;
1910 }
1911
1912 if (in_bus_format != hdmi->hdmi_data.enc_in_bus_format ||
1913 out_bus_format != hdmi->hdmi_data.enc_out_bus_format) {
1914 color_changed = true;
1915 }
1916 }
1917
1918 if (!hdr_metadata_equal(old_state, new_state) || dw_hdmi_color_changed(connector) || color_changed) {
1919 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1920 if (IS_ERR(crtc_state)) {
1921 return PTR_ERR(crtc_state);
1922 }
1923
1924 crtc_state->mode_changed = true;
1925 }
1926
1927 return 0;
1928 }
1929
dw_hdmi_connector_force(struct drm_connector * connector)1930 static void dw_hdmi_connector_force(struct drm_connector *connector)
1931 {
1932 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, connector);
1933
1934 mutex_lock(&hdmi->mutex);
1935
1936 if (hdmi->force != connector->force) {
1937 if (!hdmi->disabled && connector->force == DRM_FORCE_OFF) {
1938 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
1939 } else if (hdmi->disabled && connector->force == DRM_FORCE_ON) {
1940 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
1941 }
1942 }
1943
1944 hdmi->force = connector->force;
1945 mutex_unlock(&hdmi->mutex);
1946 }
1947
dw_hdmi_qp_fill_modes(struct drm_connector * connector,u32 max_x,u32 max_y)1948 static int dw_hdmi_qp_fill_modes(struct drm_connector *connector, u32 max_x, u32 max_y)
1949 {
1950 return drm_helper_probe_single_connector_modes(connector, 9000, 9000);
1951 }
1952
1953 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1954 .fill_modes = dw_hdmi_qp_fill_modes,
1955 .detect = dw_hdmi_connector_detect,
1956 .destroy = drm_connector_cleanup,
1957 .force = dw_hdmi_connector_force,
1958 .reset = drm_atomic_helper_connector_reset,
1959 .set_property = dw_hdmi_connector_set_property,
1960 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1961 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1962 .atomic_set_property = dw_hdmi_atomic_connector_set_property,
1963 .atomic_get_property = dw_hdmi_atomic_connector_get_property,
1964 };
1965
1966 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1967 .get_modes = dw_hdmi_connector_get_modes,
1968 .best_encoder = dw_hdmi_connector_best_encoder,
1969 .atomic_check = dw_hdmi_connector_atomic_check,
1970 };
1971
dw_hdmi_qp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1972 static int dw_hdmi_qp_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
1973 {
1974 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1975 struct drm_encoder *encoder = bridge->encoder;
1976 struct drm_connector *connector = &hdmi->connector;
1977 struct cec_connector_info conn_info;
1978 struct cec_notifier *notifier;
1979
1980 connector->interlace_allowed = 1;
1981 connector->polled = DRM_CONNECTOR_POLL_HPD;
1982
1983 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1984
1985 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1986
1987 drm_connector_attach_encoder(connector, encoder);
1988 dw_hdmi_attach_properties(hdmi);
1989
1990 cec_fill_conn_info_from_drm(&conn_info, connector);
1991 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
1992 if (!notifier) {
1993 return -ENOMEM;
1994 }
1995
1996 mutex_lock(&hdmi->cec_notifier_mutex);
1997 hdmi->cec_notifier = notifier;
1998 mutex_unlock(&hdmi->cec_notifier_mutex);
1999
2000 return 0;
2001 }
2002
dw_hdmi_qp_bridge_detach(struct drm_bridge * bridge)2003 static void dw_hdmi_qp_bridge_detach(struct drm_bridge *bridge)
2004 {
2005 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2006
2007 mutex_lock(&hdmi->cec_notifier_mutex);
2008 cec_notifier_conn_unregister(hdmi->cec_notifier);
2009 hdmi->cec_notifier = NULL;
2010 mutex_unlock(&hdmi->cec_notifier_mutex);
2011 }
2012
dw_hdmi_qp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)2013 static enum drm_mode_status dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info,
2014 const struct drm_display_mode *mode)
2015 {
2016 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2017 struct drm_connector *connector = &hdmi->connector;
2018 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2019 enum drm_mode_status mode_status = MODE_OK;
2020
2021 if (pdata->mode_valid) {
2022 mode_status = pdata->mode_valid(connector, pdata->priv_data, info, mode);
2023 }
2024
2025 return mode_status;
2026 }
2027
dw_hdmi_qp_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * orig_mode,const struct drm_display_mode * mode)2028 static void dw_hdmi_qp_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *orig_mode,
2029 const struct drm_display_mode *mode)
2030 {
2031 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2032
2033 mutex_lock(&hdmi->mutex);
2034
2035 /* Store the display mode for plugin/DKMS poweron events */
2036 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2037
2038 mutex_unlock(&hdmi->mutex);
2039 }
2040
dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2041 static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_state)
2042 {
2043 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2044
2045 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
2046 handle_plugged_change(hdmi, false);
2047 mutex_lock(&hdmi->mutex);
2048 hdmi->disabled = true;
2049 hdmi->curr_conn = NULL;
2050 hdmi_writel(hdmi, 0, PKTSCHED_PKT_EN);
2051 if (hdmi->phy.ops->disable) {
2052 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2053 }
2054 mutex_unlock(&hdmi->mutex);
2055 }
2056
dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2057 static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_state)
2058 {
2059 struct dw_hdmi_qp *hdmi = bridge->driver_private;
2060 struct drm_atomic_state *state = old_state->base.state;
2061 struct drm_connector *connector;
2062
2063 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
2064
2065 mutex_lock(&hdmi->mutex);
2066 hdmi->disabled = false;
2067 hdmi->curr_conn = connector;
2068 dw_hdmi_qp_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2069 mutex_unlock(&hdmi->mutex);
2070 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
2071 handle_plugged_change(hdmi, true);
2072 }
2073
2074 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2075 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2076 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2077 .atomic_reset = drm_atomic_helper_bridge_reset,
2078 .attach = dw_hdmi_qp_bridge_attach,
2079 .detach = dw_hdmi_qp_bridge_detach,
2080 .mode_set = dw_hdmi_qp_bridge_mode_set,
2081 .mode_valid = dw_hdmi_qp_bridge_mode_valid,
2082 .atomic_enable = dw_hdmi_qp_bridge_atomic_enable,
2083 .atomic_disable = dw_hdmi_qp_bridge_atomic_disable,
2084 };
2085
dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp * hdmi,struct cec_adapter * adap)2086 void dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp *hdmi, struct cec_adapter *adap)
2087 {
2088 hdmi->cec_adap = adap;
2089 }
2090 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_cec_adap);
2091
dw_hdmi_qp_main_hardirq(int irq,void * dev_id)2092 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id)
2093 {
2094 struct dw_hdmi_qp *hdmi = dev_id;
2095 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
2096 u32 stat;
2097
2098 stat = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS);
2099
2100 i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | I2CM_NACK_RCVD_IRQ);
2101 hdmi->scdc_intr = stat & (SCDC_UPD_FLAGS_RD_IRQ | SCDC_UPD_FLAGS_CHG_IRQ | SCDC_UPD_FLAGS_CLR_IRQ |
2102 SCDC_RR_REPLY_STOP_IRQ | SCDC_NACK_RCVD_IRQ);
2103 hdmi->flt_intr = stat & (FLT_EXIT_TO_LTSP_IRQ | FLT_EXIT_TO_LTS4_IRQ | FLT_EXIT_TO_LTSL_IRQ);
2104
2105 dev_dbg(hdmi->dev, "i2c main unit irq:%#x\n", stat);
2106 if (i2c->stat) {
2107 hdmi_writel(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR);
2108 complete(&i2c->cmp);
2109 }
2110
2111 if (hdmi->flt_intr) {
2112 dev_dbg(hdmi->dev, "i2c flt irq:%#x\n", hdmi->flt_intr);
2113 hdmi_writel(hdmi, hdmi->flt_intr, MAINUNIT_1_INT_CLEAR);
2114 complete(&hdmi->flt_cmp);
2115 }
2116
2117 if (hdmi->scdc_intr) {
2118 u8 val;
2119
2120 dev_dbg(hdmi->dev, "i2c scdc irq:%#x\n", hdmi->scdc_intr);
2121 hdmi_writel(hdmi, hdmi->scdc_intr, MAINUNIT_1_INT_CLEAR);
2122 val = hdmi_readl(hdmi, SCDC_STATUS0);
2123 /* frl start */
2124 if (val & BIT(0x4)) {
2125 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
2126 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, MAINUNIT_1_INT_MASK_N);
2127 dev_info(hdmi->dev, "frl start\n");
2128 }
2129 }
2130
2131 if (stat) {
2132 return IRQ_HANDLED;
2133 }
2134
2135 return IRQ_NONE;
2136 }
2137
dw_hdmi_qp_avp_hardirq(int irq,void * dev_id)2138 static irqreturn_t dw_hdmi_qp_avp_hardirq(int irq, void *dev_id)
2139 {
2140 struct dw_hdmi_qp *hdmi = dev_id;
2141 u32 stat;
2142
2143 stat = hdmi_readl(hdmi, AVP_1_INT_STATUS);
2144 if (stat) {
2145 dev_dbg(hdmi->dev, "HDCP irq %#x\n", stat);
2146 stat &= ~stat;
2147 hdmi_writel(hdmi, stat, AVP_1_INT_MASK_N);
2148 return IRQ_WAKE_THREAD;
2149 }
2150
2151 return IRQ_NONE;
2152 }
2153
dw_hdmi_qp_earc_hardirq(int irq,void * dev_id)2154 static irqreturn_t dw_hdmi_qp_earc_hardirq(int irq, void *dev_id)
2155 {
2156 struct dw_hdmi_qp *hdmi = dev_id;
2157 u32 stat;
2158
2159 stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS);
2160 if (stat) {
2161 dev_dbg(hdmi->dev, "earc irq %#x\n", stat);
2162 stat &= ~stat;
2163 hdmi_writel(hdmi, stat, EARCRX_0_INT_MASK_N);
2164 return IRQ_WAKE_THREAD;
2165 }
2166
2167 return IRQ_NONE;
2168 }
2169
dw_hdmi_qp_avp_irq(int irq,void * dev_id)2170 static irqreturn_t dw_hdmi_qp_avp_irq(int irq, void *dev_id)
2171 {
2172 struct dw_hdmi_qp *hdmi = dev_id;
2173 u32 stat;
2174
2175 stat = hdmi_readl(hdmi, AVP_1_INT_STATUS);
2176 if (!stat) {
2177 return IRQ_NONE;
2178 }
2179
2180 hdmi_writel(hdmi, stat, AVP_1_INT_CLEAR);
2181
2182 return IRQ_HANDLED;
2183 }
2184
dw_hdmi_qp_earc_irq(int irq,void * dev_id)2185 static irqreturn_t dw_hdmi_qp_earc_irq(int irq, void *dev_id)
2186 {
2187 struct dw_hdmi_qp *hdmi = dev_id;
2188 u32 stat;
2189
2190 stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS);
2191 if (!stat) {
2192 return IRQ_NONE;
2193 }
2194
2195 hdmi_writel(hdmi, stat, EARCRX_0_INT_CLEAR);
2196
2197 hdmi->earc_intr = stat;
2198 complete(&hdmi->earc_cmp);
2199
2200 return IRQ_HANDLED;
2201 }
2202
dw_hdmi_detect_phy(struct dw_hdmi_qp * hdmi)2203 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi)
2204 {
2205 u8 phy_type;
2206
2207 phy_type = hdmi->plat_data->phy_force_vendor ? DW_HDMI_PHY_VENDOR_PHY : 0;
2208
2209 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2210 /* Vendor PHYs require support from the glue layer. */
2211 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) {
2212 dev_err(hdmi->dev, "Vendor HDMI PHY not supported by glue layer\n");
2213 return -ENODEV;
2214 }
2215
2216 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops;
2217 hdmi->phy.data = hdmi->plat_data->phy_data;
2218 hdmi->phy.name = hdmi->plat_data->phy_name;
2219 }
2220
2221 return 0;
2222 }
2223
dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp * hdmi,bool plug_in,bool change)2224 void dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp *hdmi, bool plug_in, bool change)
2225 {
2226 enum drm_connector_status status = plug_in ? connector_status_connected : connector_status_disconnected;
2227
2228 if (!plug_in) {
2229 cec_notifier_set_phys_addr(hdmi->cec_notifier, CEC_PHYS_ADDR_INVALID);
2230 }
2231
2232 if (hdmi->bridge.dev) {
2233 if (change && hdmi->cec_adap && hdmi->cec_adap->devnode.registered) {
2234 cec_queue_pin_hpd_event(hdmi->cec_adap, hdmi->hpd_state, ktime_get());
2235 }
2236 drm_bridge_hpd_notify(&hdmi->bridge, status);
2237 }
2238 }
2239 EXPORT_SYMBOL_GPL(dw_hdmi_qp_cec_set_hpd);
2240
2241 static const struct regmap_config hdmi_regmap_config = {
2242 .reg_bits = 32,
2243 .val_bits = 32,
2244 .reg_stride = 4,
2245 .max_register = EARCRX_1_INT_FORCE,
2246 };
2247
_dw_hdmi_probe(struct platform_device * pdev,const struct dw_hdmi_plat_data * plat_data)2248 static struct dw_hdmi_qp *_dw_hdmi_probe(struct platform_device *pdev, const struct dw_hdmi_plat_data *plat_data)
2249 {
2250 struct device *dev = &pdev->dev;
2251 struct device_node *np = dev->of_node;
2252 struct device_node *ddc_node;
2253 struct dw_hdmi_qp *hdmi;
2254 struct dw_hdmi_qp_i2s_audio_data audio;
2255 struct platform_device_info pdevinfo;
2256 struct resource *iores = NULL;
2257 int irq;
2258 int ret;
2259
2260 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2261 if (!hdmi) {
2262 return ERR_PTR(-ENOMEM);
2263 }
2264
2265 hdmi->connector.stereo_allowed = 1;
2266 hdmi->plat_data = plat_data;
2267 hdmi->dev = dev;
2268 hdmi->sample_rate = 0xBB80;
2269 hdmi->disabled = true;
2270
2271 mutex_init(&hdmi->mutex);
2272 mutex_init(&hdmi->audio_mutex);
2273 mutex_init(&hdmi->cec_notifier_mutex);
2274 spin_lock_init(&hdmi->audio_lock);
2275
2276 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2277 if (ddc_node) {
2278 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2279 of_node_put(ddc_node);
2280 if (!hdmi->ddc) {
2281 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2282 return ERR_PTR(-EPROBE_DEFER);
2283 }
2284 } else {
2285 dev_dbg(hdmi->dev, "no ddc property found\n");
2286 }
2287 if (!plat_data->regm) {
2288 const struct regmap_config *reg_config;
2289
2290 reg_config = &hdmi_regmap_config;
2291
2292 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2293 hdmi->regs = devm_ioremap_resource(dev, iores);
2294 if (IS_ERR(hdmi->regs)) {
2295 ret = PTR_ERR(hdmi->regs);
2296 goto err_res;
2297 }
2298
2299 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2300 if (IS_ERR(hdmi->regm)) {
2301 dev_err(dev, "Failed to configure regmap\n");
2302 ret = PTR_ERR(hdmi->regm);
2303 goto err_res;
2304 }
2305 } else {
2306 hdmi->regm = plat_data->regm;
2307 }
2308
2309 ret = dw_hdmi_detect_phy(hdmi);
2310 if (ret < 0) {
2311 goto err_res;
2312 }
2313
2314 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
2315 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
2316 hdmi_writel(hdmi, 0x198B7B25, TIMER_BASE_CONFIG0);
2317
2318 irq = platform_get_irq(pdev, 0);
2319 if (irq < 0) {
2320 ret = irq;
2321 goto err_res;
2322 }
2323
2324 hdmi->avp_irq = irq;
2325 ret = devm_request_threaded_irq(dev, hdmi->avp_irq, dw_hdmi_qp_avp_hardirq, dw_hdmi_qp_avp_irq, IRQF_SHARED,
2326 dev_name(dev), hdmi);
2327 if (ret) {
2328 goto err_res;
2329 }
2330
2331 irq = platform_get_irq(pdev, 0x2);
2332 if (irq < 0) {
2333 ret = irq;
2334 goto err_res;
2335 }
2336
2337 hdmi->earc_irq = irq;
2338 ret = devm_request_threaded_irq(dev, hdmi->earc_irq, dw_hdmi_qp_earc_hardirq, dw_hdmi_qp_earc_irq, IRQF_SHARED,
2339 dev_name(dev), hdmi);
2340 if (ret) {
2341 goto err_res;
2342 }
2343
2344 irq = platform_get_irq(pdev, 0x3);
2345 if (irq < 0) {
2346 ret = irq;
2347 goto err_res;
2348 }
2349
2350 hdmi->main_irq = irq;
2351 ret =
2352 devm_request_threaded_irq(dev, hdmi->main_irq, dw_hdmi_qp_main_hardirq, NULL, IRQF_SHARED, dev_name(dev), hdmi);
2353 if (ret) {
2354 goto err_res;
2355 }
2356
2357 hdmi_init_clk_regenerator(hdmi);
2358
2359 /* If DDC bus is not specified, try to register HDMI I2C bus */
2360 if (!hdmi->ddc) {
2361 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2362 if (IS_ERR(hdmi->ddc)) {
2363 hdmi->ddc = NULL;
2364 }
2365 /*
2366 * Read high and low time from device tree. If not available use
2367 * the default timing scl clock rate is about 99.6KHz.
2368 */
2369 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns", &hdmi->i2c->scl_high_ns)) {
2370 hdmi->i2c->scl_high_ns = 0x1264;
2371 }
2372 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns", &hdmi->i2c->scl_low_ns)) {
2373 hdmi->i2c->scl_low_ns = 0x1334;
2374 }
2375 }
2376
2377 hdmi->bridge.driver_private = hdmi;
2378 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2379 #ifdef CONFIG_OF
2380 hdmi->bridge.of_node = pdev->dev.of_node;
2381 #endif
2382
2383 if (hdmi->phy.ops->setup_hpd) {
2384 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2385 }
2386
2387 hdmi->connector.ycbcr_420_allowed = hdmi->plat_data->ycbcr_420_allowed;
2388
2389 audio.hdmi = hdmi;
2390 audio.eld = hdmi->connector.eld;
2391 audio.write = hdmi_writel;
2392 audio.read = hdmi_readl;
2393 audio.mod = hdmi_modb;
2394 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2395 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2396
2397 memset(&pdevinfo, 0, sizeof(pdevinfo));
2398 pdevinfo.parent = dev;
2399 pdevinfo.id = PLATFORM_DEVID_AUTO;
2400 pdevinfo.name = "dw-hdmi-qp-i2s-audio";
2401 pdevinfo.data = &audio;
2402 pdevinfo.size_data = sizeof(audio);
2403 pdevinfo.dma_mask = DMA_BIT_MASK(0x20);
2404 hdmi->audio = platform_device_register_full(&pdevinfo);
2405
2406 hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable);
2407 if (IS_ERR(hdmi->extcon)) {
2408 dev_err(hdmi->dev, "allocate extcon failed\n");
2409 ret = PTR_ERR(hdmi->extcon);
2410 goto err_res;
2411 }
2412
2413 ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon);
2414 if (ret) {
2415 dev_err(hdmi->dev, "failed to register extcon: %d\n", ret);
2416 goto err_res;
2417 }
2418
2419 ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI, EXTCON_PROP_DISP_HPD);
2420 if (ret) {
2421 dev_err(hdmi->dev, "failed to set USB property capability: %d\n", ret);
2422 goto err_res;
2423 }
2424
2425 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2426 if (hdmi->i2c) {
2427 dw_hdmi_i2c_init(hdmi);
2428 }
2429
2430 init_completion(&hdmi->flt_cmp);
2431 init_completion(&hdmi->earc_cmp);
2432
2433 if (of_property_read_bool(np, "scramble-low-rates")) {
2434 hdmi->scramble_low_rates = true;
2435 }
2436
2437 return hdmi;
2438
2439 err_res:
2440 if (hdmi->i2c) {
2441 i2c_del_adapter(&hdmi->i2c->adap);
2442 } else {
2443 i2c_put_adapter(hdmi->ddc);
2444 }
2445
2446 return ERR_PTR(ret);
2447 }
2448
_dw_hdmi_remove(struct dw_hdmi_qp * hdmi)2449 static void _dw_hdmi_remove(struct dw_hdmi_qp *hdmi)
2450 {
2451 if (hdmi->avp_irq) {
2452 disable_irq(hdmi->avp_irq);
2453 }
2454
2455 if (hdmi->main_irq) {
2456 disable_irq(hdmi->main_irq);
2457 }
2458
2459 if (hdmi->earc_irq) {
2460 disable_irq(hdmi->earc_irq);
2461 }
2462
2463 dw_hdmi_destroy_properties(hdmi);
2464 hdmi->connector.funcs->destroy(&hdmi->connector);
2465
2466 if (hdmi->audio && !IS_ERR(hdmi->audio)) {
2467 platform_device_unregister(hdmi->audio);
2468 }
2469
2470 if (hdmi->bridge.encoder) {
2471 hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder);
2472 }
2473
2474 if (hdmi->i2c) {
2475 i2c_del_adapter(&hdmi->i2c->adap);
2476 } else {
2477 i2c_put_adapter(hdmi->ddc);
2478 }
2479 }
2480
2481 /* -----------------------------------------------------------------------------
2482 * Bind/unbind API, used from platforms based on the component framework.
2483 */
dw_hdmi_qp_bind(struct platform_device * pdev,struct drm_encoder * encoder,struct dw_hdmi_plat_data * plat_data)2484 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2485 struct dw_hdmi_plat_data *plat_data)
2486 {
2487 struct dw_hdmi_qp *hdmi;
2488 int ret;
2489
2490 hdmi = _dw_hdmi_probe(pdev, plat_data);
2491 if (IS_ERR(hdmi)) {
2492 return hdmi;
2493 }
2494
2495 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
2496 if (ret) {
2497 _dw_hdmi_remove(hdmi);
2498 dev_err(hdmi->dev, "Failed to initialize bridge with drm\n");
2499 return ERR_PTR(ret);
2500 }
2501
2502 plat_data->connector = &hdmi->connector;
2503
2504 return hdmi;
2505 }
2506 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind);
2507
dw_hdmi_qp_unbind(struct dw_hdmi_qp * hdmi)2508 void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi)
2509 {
2510 _dw_hdmi_remove(hdmi);
2511 }
2512 EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind);
2513
dw_hdmi_qp_suspend(struct device * dev,struct dw_hdmi_qp * hdmi)2514 void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi)
2515 {
2516 if (!hdmi) {
2517 dev_warn(dev, "Hdmi has not been initialized\n");
2518 return;
2519 }
2520
2521 mutex_lock(&hdmi->mutex);
2522
2523 /*
2524 * When system shutdown, hdmi should be disabled.
2525 * When system suspend, dw_hdmi_qp_bridge_disable will disable hdmi first.
2526 * To prevent duplicate operation, we should determine whether hdmi
2527 * has been disabled.
2528 */
2529 if (!hdmi->disabled) {
2530 hdmi->disabled = true;
2531 }
2532 mutex_unlock(&hdmi->mutex);
2533
2534 if (hdmi->avp_irq) {
2535 disable_irq(hdmi->avp_irq);
2536 }
2537
2538 if (hdmi->main_irq) {
2539 disable_irq(hdmi->main_irq);
2540 }
2541
2542 if (hdmi->earc_irq) {
2543 disable_irq(hdmi->earc_irq);
2544 }
2545
2546 pinctrl_pm_select_sleep_state(dev);
2547 }
2548 EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend);
2549
dw_hdmi_qp_resume(struct device * dev,struct dw_hdmi_qp * hdmi)2550 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
2551 {
2552 if (!hdmi) {
2553 dev_warn(dev, "Hdmi has not been initialized\n");
2554 return;
2555 }
2556
2557 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
2558 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
2559 hdmi_writel(hdmi, 0x198B7B25, TIMER_BASE_CONFIG0);
2560
2561 pinctrl_pm_select_default_state(dev);
2562 mutex_lock(&hdmi->mutex);
2563 if (hdmi->i2c) {
2564 dw_hdmi_i2c_init(hdmi);
2565 }
2566 if (hdmi->avp_irq) {
2567 enable_irq(hdmi->avp_irq);
2568 }
2569
2570 if (hdmi->main_irq) {
2571 enable_irq(hdmi->main_irq);
2572 }
2573
2574 if (hdmi->earc_irq) {
2575 enable_irq(hdmi->earc_irq);
2576 }
2577
2578 mutex_unlock(&hdmi->mutex);
2579 }
2580 EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume);
2581
2582 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
2583 MODULE_DESCRIPTION("DW HDMI QP transmitter driver");
2584 MODULE_LICENSE("GPL");
2585 MODULE_ALIAS("platform:dw-hdmi-qp");
2586