1 /*
2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/of.h>
26 #include <linux/phy/phy.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/rockchip/cpu.h>
30 #include <linux/slab.h>
31
32 #define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000
33
34 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
35
36 /* REG: 0x00 */
37 #define PRE_PLL_REFCLK_SEL_MASK BIT(0)
38 #define PRE_PLL_REFCLK_SEL_PCLK BIT(0)
39 #define PRE_PLL_REFCLK_SEL_OSCCLK 0
40 /* REG: 0x01 */
41 #define BYPASS_RXSENSE_EN_MASK BIT(2)
42 #define BYPASS_RXSENSE_EN BIT(2)
43 #define BYPASS_PWRON_EN_MASK BIT(1)
44 #define BYPASS_PWRON_EN BIT(1)
45 #define BYPASS_PLLPD_EN_MASK BIT(0)
46 #define BYPASS_PLLPD_EN BIT(0)
47 /* REG: 0x02 */
48 #define BYPASS_PDATA_EN_MASK BIT(4)
49 #define BYPASS_PDATA_EN BIT(4)
50 #define PDATAEN_MASK BIT(0)
51 #define PDATAEN_DISABLE BIT(0)
52 #define PDATAEN_ENABLE 0
53 /* REG: 0x03 */
54 #define BYPASS_AUTO_TERM_RES_CAL BIT(7)
55 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
56 /* REG: 0x04 */
57 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
58 /* REG: 0xaa */
59 #define POST_PLL_CTRL_MASK BIT(0)
60 #define POST_PLL_CTRL_MANUAL BIT(0)
61 /* REG: 0xe0 */
62 #define POST_PLL_POWER_MASK BIT(5)
63 #define POST_PLL_POWER_DOWN BIT(5)
64 #define POST_PLL_POWER_UP 0
65 #define PRE_PLL_POWER_MASK BIT(4)
66 #define PRE_PLL_POWER_DOWN BIT(4)
67 #define PRE_PLL_POWER_UP 0
68 #define RXSENSE_CLK_CH_MASK BIT(3)
69 #define RXSENSE_CLK_CH_ENABLE BIT(3)
70 #define RXSENSE_DATA_CH2_MASK BIT(2)
71 #define RXSENSE_DATA_CH2_ENABLE BIT(2)
72 #define RXSENSE_DATA_CH1_MASK BIT(1)
73 #define RXSENSE_DATA_CH1_ENABLE BIT(1)
74 #define RXSENSE_DATA_CH0_MASK BIT(0)
75 #define RXSENSE_DATA_CH0_ENABLE BIT(0)
76 /* REG: 0xe1 */
77 #define BANDGAP_MASK BIT(4)
78 #define BANDGAP_ENABLE BIT(4)
79 #define BANDGAP_DISABLE 0
80 #define TMDS_DRIVER_MASK GENMASK(3, 0)
81 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0)
82 #define TMDS_DRIVER_DISABLE 0
83 /* REG: 0xe2 */
84 #define PRE_PLL_FB_DIV_8_MASK BIT(7)
85 #define PRE_PLL_FB_DIV_8_SHIFT 7
86 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
87 #define PCLK_VCO_DIV_5_MASK BIT(5)
88 #define PCLK_VCO_DIV_5_SHIFT 5
89 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
90 #define PRE_PLL_PRE_DIV_MASK GENMASK(4, 0)
91 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
92 /* REG: 0xe3 */
93 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
94 /* REG: 0xe4 */
95 #define PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
96 #define PRE_PLL_PCLK_DIV_B_SHIFT 5
97 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
98 #define PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
99 #define PRE_PLL_PCLK_DIV_A_SHIFT 0
100 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
101 /* REG: 0xe5 */
102 #define PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
103 #define PRE_PLL_PCLK_DIV_C_SHIFT 5
104 #define PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
105 #define PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
106 #define PRE_PLL_PCLK_DIV_D_SHIFT 0
107 #define PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
108 /* REG: 0xe6 */
109 #define PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4)
110 #define PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)
111 #define PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)
112 #define PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
113 #define PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0)
114 #define PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)
115 /* REG: 0xe8 */
116 #define PRE_PLL_LOCK_STATUS BIT(0)
117 /* REG: 0xe9 */
118 #define POST_PLL_POST_DIV_EN_MASK GENMASK(7, 6)
119 #define POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)
120 #define POST_PLL_POST_DIV_DISABLE 0
121 #define POST_PLL_PRE_DIV_MASK GENMASK(4, 0)
122 #define POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
123 /* REG: 0xea */
124 #define POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
125 /* REG: 0xeb */
126 #define POST_PLL_FB_DIV_8_MASK BIT(7)
127 #define POST_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
128 #define POST_PLL_POST_DIV_MASK GENMASK(5, 4)
129 #define POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)
130 #define POST_PLL_LOCK_STATUS BIT(0)
131 /* REG: 0xee */
132 #define TMDS_CH_TA_MASK GENMASK(7, 4)
133 #define TMDS_CH_TA_ENABLE UPDATE(0xf, 7, 4)
134 #define TMDS_CH_TA_DISABLE 0
135 /* REG: 0xef */
136 #define TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)
137 #define TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)
138 #define TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
139 #define TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)
140 /* REG: 0xf0 */
141 #define TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4)
142 #define TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)
143 #define TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2)
144 #define TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
145 #define TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0)
146 #define TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)
147 /* REG: 0xf1 */
148 #define TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)
149 #define TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)
150 /* REG: 0xf2 */
151 #define TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)
152 #define TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)
153
154 enum inno_hdmi_phy_type { INNO_HDMI_PHY_RK3228, INNO_HDMI_PHY_RK3328 };
155
156 struct phy_config {
157 unsigned long tmdsclock;
158 u8 regs[14];
159 };
160
161 struct inno_hdmi_phy_drv_data;
162
163 struct inno_hdmi_phy {
164 struct device *dev;
165 struct regmap *regmap;
166
167 int irq;
168
169 struct phy *phy;
170 struct clk *sysclk;
171 struct phy_config *phy_cfg;
172
173 /* platform data */
174 struct inno_hdmi_phy_drv_data *plat_data;
175
176 /* efuse flag */
177 bool efuse_flag;
178
179 /* clk provider */
180 struct clk_hw hw;
181 struct clk *pclk;
182 unsigned long pixclock;
183 unsigned long tmdsclock;
184 };
185
186 struct pre_pll_config {
187 unsigned long pixclock;
188 unsigned long tmdsclock;
189 u8 prediv;
190 u16 fbdiv;
191 u8 tmds_div_a;
192 u8 tmds_div_b;
193 u8 tmds_div_c;
194 u8 pclk_div_a;
195 u8 pclk_div_b;
196 u8 pclk_div_c;
197 u8 pclk_div_d;
198 u8 vco_div_5_en;
199 u32 fracdiv;
200 };
201
202 struct post_pll_config {
203 unsigned long tmdsclock;
204 u8 prediv;
205 u16 fbdiv;
206 u8 postdiv;
207 u8 version;
208 };
209
210 struct inno_hdmi_phy_ops {
211 void (*init)(struct inno_hdmi_phy *inno);
212 int (*power_on)(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg);
213 void (*power_off)(struct inno_hdmi_phy *inno);
214 int (*pre_pll_update)(struct inno_hdmi_phy *inno, const struct pre_pll_config *cfg);
215 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno, unsigned long parent_rate);
216 };
217
218 struct inno_hdmi_phy_drv_data {
219 enum inno_hdmi_phy_type dev_type;
220 const struct inno_hdmi_phy_ops *ops;
221 const struct phy_config *phy_cfg_table;
222 };
223
224 /*
225 * If only using integer freq div can't get frequency we want, frac
226 * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
227 * 110.9375 Mhz must use frac div 0xF00000. The actual frequency is different
228 * from the target frequency. Such as the tmds clock 110.9375 Mhz,
229 * the actual tmds clock we get is 110.93719 Mhz. It is important
230 * to note that RK322X platforms do not support frac div.
231 */
232 static const struct pre_pll_config pre_pll_cfg_table[] = {
233 {27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
234 {27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
235 {40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
236 {40000000, 50000000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
237 {59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
238 {59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
239 {59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
240 {59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
241 {65000000, 65000000, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
242 {65000000, 81250000, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
243 {71000000, 71000000, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
244 {71000000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0},
245 {74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
246 {74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
247 {74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
248 {74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
249 {83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0},
250 {83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000},
251 {85750000, 85750000, 3, 343, 0, 3, 3, 1, 0, 0, 8, 0, 0},
252 {88750000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 8, 0, 0},
253 {88750000, 110937500, 1, 110, 2, 1, 1, 1, 1, 0, 5, 0, 0xF00000},
254 {108000000, 108000000, 1, 90, 3, 0, 0, 1, 0, 0, 5, 0, 0},
255 {108000000, 135000000, 1, 90, 0, 2, 2, 1, 0, 0, 5, 0, 0},
256 {119000000, 119000000, 1, 119, 2, 1, 1, 1, 0, 0, 6, 0, 0},
257 {119000000, 148750000, 1, 99, 0, 2, 2, 1, 0, 0, 5, 0, 0x2AAAAA},
258 {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
259 {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
260 {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
261 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
262 {162000000, 162000000, 1, 108, 0, 2, 2, 1, 0, 0, 4, 0, 0},
263 {162000000, 202500000, 1, 135, 0, 2, 2, 1, 0, 0, 5, 0, 0},
264 {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
265 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
266 {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
267 {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
268 {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
269 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
270 {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
271 {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
272 {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
273 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
274 {~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}};
275
276 static const struct post_pll_config post_pll_cfg_table[] = {
277 {33750000, 1, 40, 8, 1}, {33750000, 1, 80, 8, 2}, {33750000, 1, 10, 2, 4},
278 {74250000, 1, 40, 8, 1}, {74250000, 18, 80, 8, 2}, {148500000, 2, 40, 4, 3},
279 {297000000, 4, 40, 2, 3}, {594000000, 8, 40, 1, 3}, {~0UL, 0, 0, 0, 0}};
280
281 static const struct phy_config rk3228_phy_cfg[] = {{
282 165000000,
283 {
284 0xaa,
285 0x00,
286 0x44,
287 0x44,
288 0x00,
289 0x00,
290 0x00,
291 0x00,
292 0x00,
293 0x00,
294 0x00,
295 0x00,
296 0x00,
297 0x00,
298 },
299 }, {
300 340000000,
301 {
302 0xaa,
303 0x15,
304 0x6a,
305 0xaa,
306 0x00,
307 0x00,
308 0x00,
309 0x00,
310 0x00,
311 0x00,
312 0x00,
313 0x00,
314 0x00,
315 0x00,
316 },
317 }, {
318 594000000,
319 {
320 0xaa,
321 0x15,
322 0x7a,
323 0xaa,
324 0x00,
325 0x00,
326 0x00,
327 0x00,
328 0x00,
329 0x00,
330 0x00,
331 0x00,
332 0x00,
333 0x00,
334 },
335 }, {
336 ~0UL,
337 {
338 0x00,
339 0x00,
340 0x00,
341 0x00,
342 0x00,
343 0x00,
344 0x00,
345 0x00,
346 0x00,
347 0x00,
348 0x00,
349 0x00,
350 0x00,
351 0x00,
352 },
353 }};
354
355 static const struct phy_config rk3328_phy_cfg[] = {{
356 165000000,
357 {
358 0x07,
359 0x0a,
360 0x0a,
361 0x0a,
362 0x00,
363 0x00,
364 0x08,
365 0x08,
366 0x08,
367 0x00,
368 0xac,
369 0xcc,
370 0xcc,
371 0xcc,
372 },
373 }, {
374 340000000,
375 {
376 0x0b,
377 0x0d,
378 0x0d,
379 0x0d,
380 0x07,
381 0x15,
382 0x08,
383 0x08,
384 0x08,
385 0x3f,
386 0xac,
387 0xcc,
388 0xcd,
389 0xdd,
390 },
391 }, {
392 594000000,
393 {
394 0x10,
395 0x1a,
396 0x1a,
397 0x1a,
398 0x07,
399 0x15,
400 0x08,
401 0x08,
402 0x08,
403 0x00,
404 0xac,
405 0xcc,
406 0xcc,
407 0xcc,
408 },
409 }, {
410 ~0UL,
411 {
412 0x00,
413 0x00,
414 0x00,
415 0x00,
416 0x00,
417 0x00,
418 0x00,
419 0x00,
420 0x00,
421 0x00,
422 0x00,
423 0x00,
424 0x00,
425 0x00,
426 },
427 }};
428
to_inno_hdmi_phy(struct clk_hw * hw)429 static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw)
430 {
431 return container_of(hw, struct inno_hdmi_phy, hw);
432 }
433
inno_write(struct inno_hdmi_phy * inno,u32 reg,u8 val)434 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
435 {
436 regmap_write(inno->regmap, reg * 0x04, val);
437 }
438
inno_read(struct inno_hdmi_phy * inno,u32 reg)439 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
440 {
441 u32 val;
442
443 regmap_read(inno->regmap, reg * 0x04, &val);
444
445 return val;
446 }
447
inno_update_bits(struct inno_hdmi_phy * inno,u8 reg,u8 mask,u8 val)448 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, u8 mask, u8 val)
449 {
450 regmap_update_bits(inno->regmap, reg * 0x04, mask, val);
451 }
452
inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy * inno,int rate)453 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, int rate)
454 {
455 int bus_width = phy_get_bus_width(inno->phy);
456 u32 tmdsclk;
457
458 switch (bus_width) {
459 case 0x04:
460 tmdsclk = (u32)rate / 0x02;
461 break;
462 case 0x05:
463 tmdsclk = (u32)rate * 0x05 / 0x08;
464 break;
465 case 0x06:
466 tmdsclk = (u32)rate * 0x03 / 0x04;
467 break;
468 case 0x0A:
469 tmdsclk = (u32)rate * 0x05 / 0x04;
470 break;
471 case 0x0C:
472 tmdsclk = (u32)rate * 0x03 / 0x02;
473 break;
474 case 0x10:
475 tmdsclk = (u32)rate * 0x02;
476 break;
477 default:
478 tmdsclk = rate;
479 }
480
481 return tmdsclk;
482 }
483
inno_hdmi_phy_hardirq(int irq,void * dev_id)484 static irqreturn_t inno_hdmi_phy_hardirq(int irq, void *dev_id)
485 {
486 struct inno_hdmi_phy *inno = dev_id;
487 int intr_stat1, intr_stat2, intr_stat3;
488
489 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
490 return IRQ_NONE;
491 }
492
493 intr_stat1 = inno_read(inno, 0x04);
494 intr_stat2 = inno_read(inno, 0x06);
495 intr_stat3 = inno_read(inno, 0x08);
496
497 if (intr_stat1) {
498 inno_write(inno, 0x04, intr_stat1);
499 }
500 if (intr_stat2) {
501 inno_write(inno, 0x06, intr_stat2);
502 }
503 if (intr_stat3) {
504 inno_write(inno, 0x08, intr_stat3);
505 }
506
507 if (intr_stat1 || intr_stat2 || intr_stat3) {
508 return IRQ_WAKE_THREAD;
509 }
510
511 return IRQ_HANDLED;
512 }
513
inno_hdmi_phy_irq(int irq,void * dev_id)514 static irqreturn_t inno_hdmi_phy_irq(int irq, void *dev_id)
515 {
516 struct inno_hdmi_phy *inno = dev_id;
517
518 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
519 return IRQ_NONE;
520 }
521 /* set pdata_en to 0 */
522 inno_update_bits(inno, 0x02, 1, 0);
523
524 udelay(0x0A);
525
526 /* set pdata_en to 1 */
527 inno_update_bits(inno, 0x02, 1, 1);
528
529 return IRQ_HANDLED;
530 }
531
532 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate);
533
inno_hdmi_phy_power_on(struct phy * phy)534 static int inno_hdmi_phy_power_on(struct phy *phy)
535 {
536 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
537 const struct post_pll_config *cfg = post_pll_cfg_table;
538 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
539 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
540 u32 chipversion = 1;
541
542 if (inno->phy_cfg) {
543 phy_cfg = inno->phy_cfg;
544 }
545
546 if (!tmdsclock) {
547 dev_err(inno->dev, "TMDS clock is zero!\n");
548 return -EINVAL;
549 }
550
551 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && rockchip_get_cpu_version()) {
552 chipversion = 0x02;
553 } else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && tmdsclock <= 0x202FBF0 && inno->efuse_flag) {
554 chipversion = 0x04;
555 }
556
557 for (; cfg->tmdsclock != ~0UL; cfg++) {
558 if (tmdsclock <= cfg->tmdsclock && cfg->version & chipversion) {
559 break;
560 }
561 }
562
563 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) {
564 if (tmdsclock <= phy_cfg->tmdsclock) {
565 break;
566 }
567 }
568
569 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) {
570 return -EINVAL;
571 }
572
573 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
574 inno_hdmi_phy_clk_set_rate(&inno->hw, inno->pixclock, 0);
575
576 if (inno->plat_data->ops->power_on) {
577 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
578 } else {
579 return -EINVAL;
580 }
581 }
582
inno_hdmi_phy_power_off(struct phy * phy)583 static int inno_hdmi_phy_power_off(struct phy *phy)
584 {
585 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
586
587 if (inno->plat_data->ops->power_off) {
588 inno->plat_data->ops->power_off(inno);
589 }
590
591 inno->tmdsclock = 0;
592 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
593
594 return 0;
595 }
596
597 static const struct phy_ops inno_hdmi_phy_ops = {
598 .owner = THIS_MODULE,
599 .power_on = inno_hdmi_phy_power_on,
600 .power_off = inno_hdmi_phy_power_off,
601 };
602
inno_hdmi_phy_clk_is_prepared(struct clk_hw * hw)603 static int inno_hdmi_phy_clk_is_prepared(struct clk_hw *hw)
604 {
605 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
606 u8 status;
607
608 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
609 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK;
610 } else {
611 status = inno_read(inno, 0xa0) & 1;
612 }
613
614 return status ? 0 : 1;
615 }
616
inno_hdmi_phy_clk_prepare(struct clk_hw * hw)617 static int inno_hdmi_phy_clk_prepare(struct clk_hw *hw)
618 {
619 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
620
621 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
622 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
623 } else {
624 inno_update_bits(inno, 0xa0, 1, 0);
625 }
626
627 return 0;
628 }
629
inno_hdmi_phy_clk_unprepare(struct clk_hw * hw)630 static void inno_hdmi_phy_clk_unprepare(struct clk_hw *hw)
631 {
632 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
633
634 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) {
635 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
636 } else {
637 inno_update_bits(inno, 0xa0, 1, 1);
638 }
639 }
640
inno_hdmi_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)641 static unsigned long inno_hdmi_phy_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
642 {
643 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
644
645 if (inno->plat_data->ops->recalc_rate) {
646 return inno->plat_data->ops->recalc_rate(inno, parent_rate);
647 } else {
648 return inno->pixclock;
649 }
650 }
651
inno_hdmi_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)652 static long inno_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate)
653 {
654 int i;
655 const struct pre_pll_config *cfg = pre_pll_cfg_table;
656 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
657 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
658
659 for (; cfg->pixclock != ~0UL; cfg++) {
660 if (cfg->pixclock == rate) {
661 break;
662 }
663 }
664
665 /* XXX: Limit pixel clock under 600MHz */
666 if (cfg->pixclock > 0x23C34600) {
667 return -EINVAL;
668 }
669
670 /*
671 * If there is no dts phy cfg table, use default phy cfg table.
672 * The tmds clock maximum is 594MHz. So there is no need to check
673 * whether tmds clock is out of range.
674 */
675 if (!inno->phy_cfg) {
676 return cfg->pixclock;
677 }
678
679 /* Check if tmds clock is out of dts phy config's range. */
680 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {
681 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) {
682 break;
683 }
684 }
685
686 if (inno->phy_cfg[i].tmdsclock == ~0UL) {
687 return -EINVAL;
688 }
689
690 return cfg->pixclock;
691 }
692
inno_hdmi_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)693 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
694 {
695 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
696 const struct pre_pll_config *cfg = pre_pll_cfg_table;
697 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
698
699 dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n", __func__, rate, tmdsclock);
700
701 if (inno->tmdsclock == tmdsclock) {
702 return 0;
703 }
704
705 for (; cfg->pixclock != ~0UL; cfg++) {
706 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) {
707 break;
708 }
709 }
710
711 if (cfg->pixclock == ~0UL) {
712 dev_err(inno->dev, "unsupported rate %lu\n", rate);
713 return -EINVAL;
714 }
715
716 if (inno->plat_data->ops->pre_pll_update) {
717 inno->plat_data->ops->pre_pll_update(inno, cfg);
718 }
719
720 inno->pixclock = rate;
721 inno->tmdsclock = tmdsclock;
722
723 return 0;
724 }
725
726 static const struct clk_ops inno_hdmi_phy_clk_ops = {
727 .prepare = inno_hdmi_phy_clk_prepare,
728 .unprepare = inno_hdmi_phy_clk_unprepare,
729 .is_prepared = inno_hdmi_phy_clk_is_prepared,
730 .recalc_rate = inno_hdmi_phy_clk_recalc_rate,
731 .round_rate = inno_hdmi_phy_clk_round_rate,
732 .set_rate = inno_hdmi_phy_clk_set_rate,
733 };
734
inno_hdmi_phy_clk_register(struct inno_hdmi_phy * inno)735 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
736 {
737 struct device *dev = inno->dev;
738 struct device_node *np = dev->of_node;
739 struct clk_init_data init = {};
740 struct clk *refclk;
741 const char *parent_name;
742 int ret;
743
744 refclk = devm_clk_get(dev, "refclk");
745 if (IS_ERR(refclk)) {
746 dev_err(dev, "failed to get ref clock\n");
747 return PTR_ERR(refclk);
748 }
749
750 parent_name = __clk_get_name(refclk);
751
752 init.parent_names = &parent_name;
753 init.num_parents = 1;
754 init.flags = 0;
755 init.name = "pin_hd20_pclk";
756 init.ops = &inno_hdmi_phy_clk_ops;
757
758 /* optional override of the clock name */
759 of_property_read_string(np, "clock-output-names", &init.name);
760
761 inno->hw.init = &init;
762
763 inno->pclk = devm_clk_register(dev, &inno->hw);
764 if (IS_ERR(inno->pclk)) {
765 ret = PTR_ERR(inno->pclk);
766 dev_err(dev, "failed to register clock: %d\n", ret);
767 return ret;
768 }
769
770 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->pclk);
771 if (ret) {
772 dev_err(dev, "failed to register OF clock provider: %d\n", ret);
773 return ret;
774 }
775
776 return 0;
777 }
778
inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)779 static int inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg,
780 const struct phy_config *phy_cfg)
781 {
782 int pll_tries;
783 u32 m, v;
784
785 /* pdata_en disable */
786 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE);
787
788 /* Power down Post-PLL */
789 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
790 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
791
792 /* Post-PLL update */
793 m = POST_PLL_PRE_DIV_MASK;
794 v = POST_PLL_PRE_DIV(cfg->prediv);
795 inno_update_bits(inno, 0xe9, m, v);
796
797 m = POST_PLL_FB_DIV_8_MASK;
798 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8);
799 inno_update_bits(inno, 0xeb, m, v);
800 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));
801
802 if (cfg->postdiv == 1) {
803 /* Disable Post-PLL post divider */
804 m = POST_PLL_POST_DIV_EN_MASK;
805 v = POST_PLL_POST_DIV_DISABLE;
806 inno_update_bits(inno, 0xe9, m, v);
807 } else {
808 /* Enable Post-PLL post divider */
809 m = POST_PLL_POST_DIV_EN_MASK;
810 v = POST_PLL_POST_DIV_ENABLE;
811 inno_update_bits(inno, 0xe9, m, v);
812
813 m = POST_PLL_POST_DIV_MASK;
814 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1);
815 inno_update_bits(inno, 0xeb, m, v);
816 }
817
818 for (v = 0; v < 0x04; v++) {
819 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
820 }
821
822 /* Power up Post-PLL */
823 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP);
824 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
825
826 /* BandGap enable */
827 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE);
828
829 /* TMDS driver enable */
830 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE);
831
832 /* Wait for post PLL lock */
833 pll_tries = 0;
834 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) {
835 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) {
836 dev_err(inno->dev, "Post-PLL unlock\n");
837 return -ETIMEDOUT;
838 }
839
840 pll_tries++;
841 usleep_range(0x64, 0x6E);
842 }
843
844 if (cfg->tmdsclock > 0x1443FD00) {
845 msleep(0x64);
846 }
847
848 /* pdata_en enable */
849 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE);
850 return 0;
851 }
852
inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy * inno)853 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
854 {
855 /* TMDS driver Disable */
856 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE);
857
858 /* BandGap Disable */
859 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE);
860
861 /* Post-PLL power down */
862 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
863 }
864
inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy * inno)865 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
866 {
867 u32 m, v;
868 struct nvmem_cell *cell;
869 unsigned char *efuse_buf;
870 size_t len;
871
872 /*
873 * Use phy internal register control
874 * rxsense/poweron/pllpd/pdataen signal.
875 */
876 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK | BYPASS_PLLPD_EN_MASK;
877 v = BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN;
878 inno_update_bits(inno, 0x01, m, v);
879 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN);
880
881 /*
882 * reg0xe9 default value is 0xe4, reg0xea is 0x50.
883 * if phy had been set in uboot, one of them will be different.
884 */
885 if ((inno_read(inno, 0xe9) != 0xe4 || inno_read(inno, 0xea) != 0x50)) {
886 dev_info(inno->dev, "phy had been powered up\n");
887 inno->phy->power_count = 1;
888 } else {
889 inno_hdmi_phy_rk3228_power_off(inno);
890 /* manual power down post-PLL */
891 inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL);
892 }
893
894 cell = nvmem_cell_get(inno->dev, "hdmi_phy_flag");
895 if (IS_ERR(cell)) {
896 dev_err(inno->dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
897 return;
898 }
899 efuse_buf = nvmem_cell_read(cell, &len);
900 nvmem_cell_put(cell);
901 if (len == 1) {
902 inno->efuse_flag = efuse_buf[0] ? true : false;
903 }
904 kfree(efuse_buf);
905 }
906
inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy * inno,const struct pre_pll_config * cfg)907 static int inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno, const struct pre_pll_config *cfg)
908 {
909 int pll_tries;
910 u32 m, v;
911
912 /* Power down PRE-PLL */
913 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
914
915 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK;
916 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv);
917 inno_update_bits(inno, 0xe2, m, v);
918
919 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
920
921 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK;
922 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a);
923 inno_update_bits(inno, 0xe4, m, v);
924
925 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK;
926 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d);
927 inno_update_bits(inno, 0xe5, m, v);
928
929 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK | PRE_PLL_TMDSCLK_DIV_B_MASK;
930 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
931 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b);
932 inno_update_bits(inno, 0xe6, m, v);
933
934 /* Power up PRE-PLL */
935 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
936
937 /* Wait for Pre-PLL lock */
938 pll_tries = 0;
939 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) {
940 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) {
941 dev_err(inno->dev, "Pre-PLL unlock\n");
942 return -ETIMEDOUT;
943 }
944
945 pll_tries++;
946 usleep_range(0x64, 0x6E);
947 }
948
949 return 0;
950 }
951
inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)952 static int inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg,
953 const struct phy_config *phy_cfg)
954 {
955 u32 val;
956 u64 temp;
957
958 /* set pdata_en to 0 */
959 inno_update_bits(inno, 0x02, 1, 0);
960 /* Power off post PLL */
961 inno_update_bits(inno, 0xaa, 1, 1);
962
963 val = cfg->fbdiv & 0xff;
964 inno_write(inno, 0xac, val);
965 if (cfg->postdiv == 1) {
966 inno_write(inno, 0xaa, 0x02);
967 val = (cfg->fbdiv >> 0x08) | cfg->prediv;
968 inno_write(inno, 0xab, val);
969 } else {
970 val = (cfg->postdiv / 0x02) - 1;
971 inno_write(inno, 0xad, val);
972 val = (cfg->fbdiv >> 0x08) | cfg->prediv;
973 inno_write(inno, 0xab, val);
974 inno_write(inno, 0xaa, 0x0e);
975 }
976
977 for (val = 0; val < 0x0E; val++) {
978 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);
979 }
980
981 /* bit[7:6] of reg c8/c9/ca/c8 is ESD detect threshold:
982 * 00 - 340mV
983 * 01 - 280mV
984 * 10 - 260mV
985 * 11 - 240mV
986 * default is 240mV, now we set it to 340mV
987 */
988 inno_write(inno, 0xc8, 0);
989 inno_write(inno, 0xc9, 0);
990 inno_write(inno, 0xca, 0);
991 inno_write(inno, 0xcb, 0);
992
993 if (phy_cfg->tmdsclock > 0x1443FD00) {
994 /* Set termination resistor to 100ohm */
995 val = clk_get_rate(inno->sysclk) / 0x186A0;
996 inno_write(inno, 0xc5, ((val >> 0x08) & 0xff) | 0x80);
997 inno_write(inno, 0xc6, val & 0xff);
998 inno_write(inno, 0xc7, 0x03 << 1);
999 inno_write(inno, 0xc5, ((val >> 0x08) & 0xff));
1000 } else {
1001 inno_write(inno, 0xc5, 0x81);
1002 /* clk termination resistor is 50ohm */
1003 if (phy_cfg->tmdsclock > 0x9D5B340) {
1004 inno_write(inno, 0xc8, 0x30);
1005 }
1006 /* data termination resistor is 150ohm */
1007 inno_write(inno, 0xc9, 0x10);
1008 inno_write(inno, 0xca, 0x10);
1009 inno_write(inno, 0xcb, 0x10);
1010 }
1011
1012 /* set TMDS sync detection counter length */
1013 temp = 0xB1069A800;
1014 do_div(temp, inno->tmdsclock);
1015 inno_write(inno, 0xd8, (temp >> 0x08) & 0xff);
1016 inno_write(inno, 0xd9, temp & 0xff);
1017
1018 /* Power up post PLL */
1019 inno_update_bits(inno, 0xaa, 1, 0);
1020 /* Power up tmds driver */
1021 inno_update_bits(inno, 0xb0, 0x04, 0x04);
1022 inno_write(inno, 0xb2, 0x0f);
1023
1024 /* Wait for post PLL lock */
1025 for (val = 0; val < 0x05; val++) {
1026 if (inno_read(inno, 0xaf) & 1) {
1027 break;
1028 }
1029 usleep_range(0x3E8, 0x7D0);
1030 }
1031 if (!(inno_read(inno, 0xaf) & 1)) {
1032 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");
1033 return -ETIMEDOUT;
1034 }
1035 if (phy_cfg->tmdsclock > 0x1443FD00) {
1036 msleep(0x64);
1037 }
1038 /* set pdata_en to 1 */
1039 inno_update_bits(inno, 0x02, 1, 1);
1040
1041 /* Enable PHY IRQ */
1042 inno_write(inno, 0x05, 0x22);
1043 inno_write(inno, 0x07, 0x22);
1044 return 0;
1045 }
1046
inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy * inno)1047 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1048 {
1049 /* Power off driver */
1050 inno_write(inno, 0xb2, 0);
1051 /* Power off band gap */
1052 inno_update_bits(inno, 0xb0, 0x04, 0);
1053 /* Power off post pll */
1054 inno_update_bits(inno, 0xaa, 1, 1);
1055
1056 /* Disable PHY IRQ */
1057 inno_write(inno, 0x05, 0);
1058 inno_write(inno, 0x07, 0);
1059 }
1060
inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy * inno)1061 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
1062 {
1063 /*
1064 * Use phy internal register control
1065 * rxsense/poweron/pllpd/pdataen signal.
1066 */
1067 inno_write(inno, 0x01, 0x07);
1068 inno_write(inno, 0x02, 0x91);
1069
1070 /*
1071 * reg0xc8 default value is 0xc0, if phy had been set in uboot,
1072 * the value of bit[7:6] will be zero.
1073 */
1074 if ((inno_read(inno, 0xc8) & 0xc0) == 0) {
1075 dev_info(inno->dev, "phy had been powered up\n");
1076 inno->phy->power_count = 1;
1077 } else {
1078 /* manual power down post-PLL */
1079 inno_hdmi_phy_rk3328_power_off(inno);
1080 }
1081 }
1082
inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy * inno,const struct pre_pll_config * cfg)1083 static int inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno, const struct pre_pll_config *cfg)
1084 {
1085 u32 val;
1086
1087 /* Power off PLL */
1088 inno_update_bits(inno, 0xa0, 1, 1);
1089 /* Configure pre-pll */
1090 inno_update_bits(inno, 0xa0, 0x02, (cfg->vco_div_5_en & 1) << 1);
1091 inno_write(inno, 0xa1, cfg->prediv);
1092 if (cfg->fracdiv) {
1093 val = ((cfg->fbdiv >> 0x08) & 0x0f) | 0xc0;
1094 } else {
1095 val = ((cfg->fbdiv >> 0x08) & 0x0f) | 0xf0;
1096 }
1097 inno_write(inno, 0xa2, val);
1098 inno_write(inno, 0xa3, cfg->fbdiv & 0xff);
1099 val = (cfg->pclk_div_a & 0x1f) | ((cfg->pclk_div_b & 0x03) << 0x05);
1100 inno_write(inno, 0xa5, val);
1101 val = (cfg->pclk_div_d & 0x1f) | ((cfg->pclk_div_c & 0x03) << 0x05);
1102 inno_write(inno, 0xa6, val);
1103 val = ((cfg->tmds_div_a & 0x03) << 0x04) | ((cfg->tmds_div_b & 0x03) << 0x02) | (cfg->tmds_div_c & 0x03);
1104 inno_write(inno, 0xa4, val);
1105
1106 if (cfg->fracdiv) {
1107 val = cfg->fracdiv & 0xff;
1108 inno_write(inno, 0xd3, val);
1109 val = (cfg->fracdiv >> 0x08) & 0xff;
1110 inno_write(inno, 0xd2, val);
1111 val = (cfg->fracdiv >> 0x10) & 0xff;
1112 inno_write(inno, 0xd1, val);
1113 } else {
1114 inno_write(inno, 0xd3, 0);
1115 inno_write(inno, 0xd2, 0);
1116 inno_write(inno, 0xd1, 0);
1117 }
1118
1119 /* Power up PLL */
1120 inno_update_bits(inno, 0xa0, 1, 0);
1121
1122 /* Wait for PLL lock */
1123 for (val = 0; val < 0x05; val++) {
1124 if (inno_read(inno, 0xa9) & 1) {
1125 break;
1126 }
1127 usleep_range(0x3E8, 0x7D0);
1128 }
1129 if (val == 0x05) {
1130 dev_err(inno->dev, "Pre-PLL unlock\n");
1131 return -ETIMEDOUT;
1132 }
1133
1134 return 0;
1135 }
1136
inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy * inno,unsigned long parent_rate)1137 static unsigned long inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, unsigned long parent_rate)
1138 {
1139 unsigned long frac;
1140 u8 nd, no_a, no_b, no_d;
1141 u16 nf;
1142 u64 vco = parent_rate;
1143
1144 nd = inno_read(inno, 0xa1) & 0x3f;
1145 nf = ((inno_read(inno, 0xa2) & 0x0f) << 0x08) | inno_read(inno, 0xa3);
1146 vco *= nf;
1147 if ((inno_read(inno, 0xa2) & 0x30) == 0) {
1148 frac = inno_read(inno, 0xd3) | (inno_read(inno, 0xd2) << 0x08) | (inno_read(inno, 0xd1) << 0x10);
1149 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 0x18));
1150 }
1151 if (inno_read(inno, 0xa0) & 0x02) {
1152 do_div(vco, nd * 0x05);
1153 } else {
1154 no_a = inno_read(inno, 0xa5) & 0x1f;
1155 no_b = ((inno_read(inno, 0xa5) >> 0x05) & 0x07) + 0x02;
1156 no_d = inno_read(inno, 0xa6) & 0x1f;
1157 if (no_a == 1) {
1158 do_div(vco, nd * no_b * no_d * 0x02);
1159 } else {
1160 do_div(vco, nd * no_a * no_d * 0x02);
1161 }
1162 }
1163
1164 frac = vco;
1165 inno->pixclock = DIV_ROUND_CLOSEST(frac, 0x3E8) * 0x3E8;
1166
1167 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1168
1169 return frac;
1170 }
1171
inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy * inno,unsigned long parent_rate)1172 static unsigned long inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy *inno, unsigned long parent_rate)
1173 {
1174 u8 nd, no_a, no_b, no_d;
1175 u16 nf;
1176 u64 vco = parent_rate;
1177
1178 nd = inno_read(inno, 0xe2) & 0x1f;
1179 nf = ((inno_read(inno, 0xe2) & 0x80) << 1) | inno_read(inno, 0xe3);
1180 vco *= nf;
1181
1182 if ((inno_read(inno, 0xe2) >> 0x05) & 0x1) {
1183 do_div(vco, nd * 0x05);
1184 } else {
1185 no_a = inno_read(inno, 0xe4) & 0x1f;
1186 if (!no_a) {
1187 no_a = 1;
1188 }
1189 no_b = ((inno_read(inno, 0xe4) >> 0x05) & 0x3) + 0x02;
1190 no_d = inno_read(inno, 0xe5) & 0x1f;
1191
1192 if (no_a == 1) {
1193 do_div(vco, nd * no_b * no_d * 0x02);
1194 } else {
1195 do_div(vco, nd * no_a * no_d * 0x02);
1196 }
1197 }
1198
1199 inno->pixclock = vco;
1200
1201 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1202
1203 return inno->pixclock;
1204 }
1205
1206 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
1207 .init = inno_hdmi_phy_rk3228_init,
1208 .power_on = inno_hdmi_phy_rk3228_power_on,
1209 .power_off = inno_hdmi_phy_rk3228_power_off,
1210 .pre_pll_update = inno_hdmi_phy_rk3228_pre_pll_update,
1211 .recalc_rate = inno_hdmi_rk3228_phy_pll_recalc_rate,
1212 };
1213
1214 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = {
1215 .init = inno_hdmi_phy_rk3328_init,
1216 .power_on = inno_hdmi_phy_rk3328_power_on,
1217 .power_off = inno_hdmi_phy_rk3328_power_off,
1218 .pre_pll_update = inno_hdmi_phy_rk3328_pre_pll_update,
1219 .recalc_rate = inno_hdmi_rk3328_phy_pll_recalc_rate,
1220 };
1221
1222 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
1223 .dev_type = INNO_HDMI_PHY_RK3228,
1224 .ops = &rk3228_hdmi_phy_ops,
1225 .phy_cfg_table = rk3228_phy_cfg,
1226 };
1227
1228 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = {
1229 .dev_type = INNO_HDMI_PHY_RK3328,
1230 .ops = &rk3328_hdmi_phy_ops,
1231 .phy_cfg_table = rk3328_phy_cfg,
1232 };
1233
1234 static const struct of_device_id inno_hdmi_phy_of_match[] = {
1235 {.compatible = "rockchip,rk3228-hdmi-phy", .data = &rk3228_hdmi_phy_drv_data},
1236 {.compatible = "rockchip,rk3328-hdmi-phy", .data = &rk3328_hdmi_phy_drv_data},
1237 {}};
1238 MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match);
1239
1240 static const struct regmap_config inno_hdmi_phy_regmap_config = {
1241 .reg_bits = 32,
1242 .val_bits = 32,
1243 .reg_stride = 4,
1244 .max_register = 0x400,
1245 };
1246
inno_hdmi_update_phy_table(struct inno_hdmi_phy * inno,u32 * config,struct phy_config * phy_cfg,int phy_table_size)1247 static int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, struct phy_config *phy_cfg,
1248 int phy_table_size)
1249 {
1250 int i, j;
1251
1252 for (i = 0; i < phy_table_size; i++) {
1253 phy_cfg[i].tmdsclock = (unsigned long)config[i * 0x0F];
1254
1255 for (j = 0; j < 0x0E; j++) {
1256 phy_cfg[i].regs[j] = (u8)config[i * 0x0F + 1 + j];
1257 }
1258 }
1259
1260 /*
1261 * The last set of phy cfg is used to indicate whether
1262 * there is no more phy cfg data.
1263 */
1264 phy_cfg[i].tmdsclock = ~0UL;
1265 for (j = 0; j < 0x0E; j++) {
1266 phy_cfg[i].regs[j] = 0;
1267 }
1268
1269 return 0;
1270 }
1271
1272 #define PHY_TAB_LEN 60
1273
inno_hdmi_phy_probe(struct platform_device * pdev)1274 static int inno_hdmi_phy_probe(struct platform_device *pdev)
1275 {
1276 struct device *dev = &pdev->dev;
1277 struct device_node *np = dev->of_node;
1278 struct inno_hdmi_phy *inno;
1279 const struct of_device_id *match;
1280 struct phy_provider *phy_provider;
1281 struct resource *res;
1282 void __iomem *regs;
1283 u32 *phy_config;
1284 int ret, val, phy_table_size;
1285
1286 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
1287 if (!inno) {
1288 return -ENOMEM;
1289 }
1290
1291 inno->dev = dev;
1292
1293 match = of_match_node(inno_hdmi_phy_of_match, pdev->dev.of_node);
1294 inno->plat_data = (struct inno_hdmi_phy_drv_data *)match->data;
1295 if (!inno->plat_data || !inno->plat_data->ops) {
1296 return -EINVAL;
1297 }
1298
1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 regs = devm_ioremap_resource(dev, res);
1301 if (IS_ERR(regs)) {
1302 return PTR_ERR(regs);
1303 }
1304
1305 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1306 if (IS_ERR(inno->sysclk)) {
1307 ret = PTR_ERR(inno->sysclk);
1308 dev_err(inno->dev, "Unable to get inno phy sysclk: %d\n", ret);
1309 return ret;
1310 }
1311 ret = clk_prepare_enable(inno->sysclk);
1312 if (ret) {
1313 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1314 return ret;
1315 }
1316
1317 inno->regmap = devm_regmap_init_mmio(dev, regs, &inno_hdmi_phy_regmap_config);
1318 if (IS_ERR(inno->regmap)) {
1319 ret = PTR_ERR(inno->regmap);
1320 dev_err(dev, "failed to init regmap: %d\n", ret);
1321 goto err_regsmap;
1322 }
1323
1324 inno->phy = devm_phy_create(dev, NULL, &inno_hdmi_phy_ops);
1325 if (IS_ERR(inno->phy)) {
1326 dev_err(dev, "failed to create HDMI PHY\n");
1327 ret = PTR_ERR(inno->phy);
1328 goto err_regsmap;
1329 }
1330
1331 if (of_get_property(np, "rockchip,phy-table", &val)) {
1332 if (val % PHY_TAB_LEN || !val) {
1333 dev_err(dev, "Invalid phy cfg table format!\n");
1334 return -EINVAL;
1335 }
1336
1337 phy_config = kmalloc(val, GFP_KERNEL);
1338 if (!phy_config) {
1339 dev_err(dev, "kmalloc phy table failed\n");
1340 return -ENOMEM;
1341 }
1342
1343 phy_table_size = val / PHY_TAB_LEN;
1344 /* Effective phy cfg data and the end of phy cfg table */
1345 inno->phy_cfg = devm_kzalloc(dev, val + PHY_TAB_LEN, GFP_KERNEL);
1346 if (!inno->phy_cfg) {
1347 kfree(phy_config);
1348 return -ENOMEM;
1349 }
1350 of_property_read_u32_array(np, "rockchip,phy-table", phy_config, val / sizeof(u32));
1351 ret = inno_hdmi_update_phy_table(inno, phy_config, inno->phy_cfg, phy_table_size);
1352 if (ret) {
1353 kfree(phy_config);
1354 return ret;
1355 }
1356 kfree(phy_config);
1357 } else {
1358 dev_dbg(dev, "use default hdmi phy table\n");
1359 }
1360
1361 phy_set_drvdata(inno->phy, inno);
1362 phy_set_bus_width(inno->phy, 0x08);
1363
1364 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1365 if (IS_ERR(phy_provider)) {
1366 dev_err(dev, "failed to register PHY provider\n");
1367 ret = PTR_ERR(phy_provider);
1368 goto err_regsmap;
1369 }
1370
1371 if (inno->plat_data->ops->init) {
1372 inno->plat_data->ops->init(inno);
1373 }
1374
1375 ret = inno_hdmi_phy_clk_register(inno);
1376 if (ret) {
1377 goto err_regsmap;
1378 }
1379
1380 inno->irq = platform_get_irq(pdev, 0);
1381 if (inno->irq > 0) {
1382 ret = devm_request_threaded_irq(inno->dev, inno->irq, inno_hdmi_phy_hardirq, inno_hdmi_phy_irq, IRQF_SHARED,
1383 dev_name(inno->dev), inno);
1384 if (ret) {
1385 goto err_irq;
1386 }
1387 }
1388 platform_set_drvdata(pdev, inno);
1389 return 0;
1390
1391 err_irq:
1392 of_clk_del_provider(pdev->dev.of_node);
1393 err_regsmap:
1394 clk_disable_unprepare(inno->sysclk);
1395 return ret;
1396 }
1397
inno_hdmi_phy_remove(struct platform_device * pdev)1398 static int inno_hdmi_phy_remove(struct platform_device *pdev)
1399 {
1400 struct inno_hdmi_phy *inno = platform_get_drvdata(pdev);
1401
1402 of_clk_del_provider(pdev->dev.of_node);
1403 clk_disable_unprepare(inno->sysclk);
1404 return 0;
1405 }
1406
1407 static struct platform_driver inno_hdmi_phy_driver = {
1408 .probe = inno_hdmi_phy_probe,
1409 .remove = inno_hdmi_phy_remove,
1410 .driver =
1411 {
1412 .name = "inno-hdmi-phy",
1413 .of_match_table = of_match_ptr(inno_hdmi_phy_of_match),
1414 },
1415 };
1416
1417 module_platform_driver(inno_hdmi_phy_driver);
1418
1419 MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");
1420 MODULE_LICENSE("GPL v2");
1421