1 /* 2 * Copyright (c) 2022 FuZhou Lockzhiner Electronic Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __RK2206_H 17 #define __RK2206_H 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 /****************************************************************************************/ 22 /* */ 23 /* Module Structure Section */ 24 /* */ 25 /****************************************************************************************/ 26 #ifndef __ASSEMBLY__ 27 /* TIMER Register Structure Define */ 28 struct TIMER_REG { 29 __IO uint32_t LOAD_COUNT[2]; /* Address Offset: 0x0000 */ 30 __I uint32_t CURRENT_VALUE[2]; /* Address Offset: 0x0008 */ 31 __IO uint32_t CONTROLREG; /* Address Offset: 0x0010 */ 32 uint32_t RESERVED0014; /* Address Offset: 0x0014 */ 33 __O uint32_t INTSTATUS; /* Address Offset: 0x0018 */ 34 }; 35 /* WDT Register Structure Define */ 36 struct WDT_REG { 37 __IO uint32_t CR; /* Address Offset: 0x0000 */ 38 __IO uint32_t TORR; /* Address Offset: 0x0004 */ 39 __I uint32_t CCVR; /* Address Offset: 0x0008 */ 40 __O uint32_t CRR; /* Address Offset: 0x000C */ 41 __I uint32_t STAT; /* Address Offset: 0x0010 */ 42 __I uint32_t EOI; /* Address Offset: 0x0014 */ 43 }; 44 /* I2C Register Structure Define */ 45 struct I2C_REG { 46 __IO uint32_t CON; /* Address Offset: 0x0000 */ 47 __IO uint32_t CLKDIV; /* Address Offset: 0x0004 */ 48 __IO uint32_t MRXADDR; /* Address Offset: 0x0008 */ 49 __IO uint32_t MRXRADDR; /* Address Offset: 0x000C */ 50 __IO uint32_t MTXCNT; /* Address Offset: 0x0010 */ 51 __IO uint32_t MRXCNT; /* Address Offset: 0x0014 */ 52 __IO uint32_t IEN; /* Address Offset: 0x0018 */ 53 __IO uint32_t IPD; /* Address Offset: 0x001C */ 54 __I uint32_t FCNT; /* Address Offset: 0x0020 */ 55 __IO uint32_t SCL_OE_DB; /* Address Offset: 0x0024 */ 56 uint32_t RESERVED0028[54]; /* Address Offset: 0x0028 */ 57 __IO uint32_t TXDATA[8]; /* Address Offset: 0x0100 */ 58 uint32_t RESERVED0120[56]; /* Address Offset: 0x0120 */ 59 __I uint32_t RXDATA[8]; /* Address Offset: 0x0200 */ 60 __I uint32_t ST; /* Address Offset: 0x0220 */ 61 __IO uint32_t DBGCTRL; /* Address Offset: 0x0224 */ 62 }; 63 /* UART Register Structure Define */ 64 struct UART_REG { 65 union { 66 __I uint32_t RBR; /* Address Offset: 0x0000 */ 67 __O uint32_t THR; /* Address Offset: 0x0000 */ 68 __IO uint32_t DLL; /* Address Offset: 0x0000 */ 69 }; 70 union { 71 __IO uint32_t DLH; /* Address Offset: 0x0004 */ 72 __IO uint32_t IER; /* Address Offset: 0x0004 */ 73 }; 74 union { 75 __I uint32_t IIR; /* Address Offset: 0x0008 */ 76 __O uint32_t FCR; /* Address Offset: 0x0008 */ 77 }; 78 __IO uint32_t LCR; /* Address Offset: 0x000C */ 79 __IO uint32_t MCR; /* Address Offset: 0x0010 */ 80 __I uint32_t LSR; /* Address Offset: 0x0014 */ 81 __I uint32_t MSR; /* Address Offset: 0x0018 */ 82 __IO uint32_t SCR; /* Address Offset: 0x001C */ 83 uint32_t RESERVED0020[4]; /* Address Offset: 0x0020 */ 84 union { 85 __I uint32_t SRBR; /* Address Offset: 0x0030 */ 86 __I uint32_t STHR; /* Address Offset: 0x0030 */ 87 }; 88 uint32_t RESERVED0034[15]; /* Address Offset: 0x0034 */ 89 __IO uint32_t FAR; /* Address Offset: 0x0070 */ 90 __I uint32_t TFR; /* Address Offset: 0x0074 */ 91 __O uint32_t RFW; /* Address Offset: 0x0078 */ 92 __I uint32_t USR; /* Address Offset: 0x007C */ 93 __IO uint32_t TFL; /* Address Offset: 0x0080 */ 94 __I uint32_t RFL; /* Address Offset: 0x0084 */ 95 __O uint32_t SRR; /* Address Offset: 0x0088 */ 96 __IO uint32_t SRTS; /* Address Offset: 0x008C */ 97 __IO uint32_t SBCR; /* Address Offset: 0x0090 */ 98 __IO uint32_t SDMAM; /* Address Offset: 0x0094 */ 99 __IO uint32_t SFE; /* Address Offset: 0x0098 */ 100 __IO uint32_t SRT; /* Address Offset: 0x009C */ 101 __IO uint32_t STET; /* Address Offset: 0x00A0 */ 102 __IO uint32_t HTX; /* Address Offset: 0x00A4 */ 103 __O uint32_t DMASA; /* Address Offset: 0x00A8 */ 104 uint32_t RESERVED00AC[18]; /* Address Offset: 0x00AC */ 105 __I uint32_t CPR; /* Address Offset: 0x00F4 */ 106 __I uint32_t UCV; /* Address Offset: 0x00F8 */ 107 __I uint32_t CTR; /* Address Offset: 0x00FC */ 108 }; 109 /* PWM Register Structure Define */ 110 struct PWM_CHANNEL { 111 __I uint32_t CNT; 112 __IO uint32_t PERIOD_HPR; 113 __IO uint32_t DUTY_LPR; 114 __IO uint32_t CTRL; 115 }; 116 struct PWM_REG { 117 struct PWM_CHANNEL CHANNELS[4]; /* Address Offset: 0x0000 */ 118 __IO uint32_t INTSTS; /* Address Offset: 0x0040 */ 119 __IO uint32_t INT_EN; /* Address Offset: 0x0044 */ 120 uint32_t RESERVED0048[2]; /* Address Offset: 0x0048 */ 121 __IO uint32_t FIFO_CTRL; /* Address Offset: 0x0050 */ 122 __IO uint32_t FIFO_INTSTS; /* Address Offset: 0x0054 */ 123 __IO uint32_t FIFO_TOUTTHR; /* Address Offset: 0x0058 */ 124 __IO uint32_t VERSION_ID; /* Address Offset: 0x005C */ 125 __I uint32_t FIFO; /* Address Offset: 0x0060 */ 126 uint32_t RESERVED0064[7]; /* Address Offset: 0x0064 */ 127 __IO uint32_t PWRMATCH_CTRL; /* Address Offset: 0x0080 */ 128 __IO uint32_t PWRMATCH_LPRE; /* Address Offset: 0x0084 */ 129 __IO uint32_t PWRMATCH_HPRE; /* Address Offset: 0x0088 */ 130 __IO uint32_t PWRMATCH_LD; /* Address Offset: 0x008C */ 131 __IO uint32_t PWRMATCH_HD_ZERO; /* Address Offset: 0x0090 */ 132 __IO uint32_t PWRMATCH_HD_ONE; /* Address Offset: 0x0094 */ 133 __IO uint32_t PWRMATCH_VALUE[10]; /* Address Offset: 0x0098 */ 134 uint32_t RESERVED00C0[3]; /* Address Offset: 0x00C0 */ 135 __I uint32_t PWM3_PWRCAPTURE_VALUE; /* Address Offset: 0x00CC */ 136 __IO uint32_t FILTER_CTRL; /* Address Offset: 0x00D0 */ 137 }; 138 /* SPI Register Structure Define */ 139 struct SPI_REG { 140 __IO uint32_t CTRLR[2]; /* Address Offset: 0x0000 */ 141 __IO uint32_t ENR; /* Address Offset: 0x0008 */ 142 __IO uint32_t SER; /* Address Offset: 0x000C */ 143 __IO uint32_t BAUDR; /* Address Offset: 0x0010 */ 144 __IO uint32_t TXFTLR; /* Address Offset: 0x0014 */ 145 __IO uint32_t RXFTLR; /* Address Offset: 0x0018 */ 146 __I uint32_t TXFLR; /* Address Offset: 0x001C */ 147 __I uint32_t RXFLR; /* Address Offset: 0x0020 */ 148 __IO uint32_t SR; /* Address Offset: 0x0024 */ 149 __IO uint32_t IPR; /* Address Offset: 0x0028 */ 150 __IO uint32_t IMR; /* Address Offset: 0x002C */ 151 __IO uint32_t ISR; /* Address Offset: 0x0030 */ 152 __IO uint32_t RISR; /* Address Offset: 0x0034 */ 153 __O uint32_t ICR; /* Address Offset: 0x0038 */ 154 __IO uint32_t DMACR; /* Address Offset: 0x003C */ 155 __IO uint32_t DMATDLR; /* Address Offset: 0x0040 */ 156 __IO uint32_t DMARDLR; /* Address Offset: 0x0044 */ 157 uint32_t RESERVED0048; /* Address Offset: 0x0048 */ 158 __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ 159 __IO uint32_t BYPASS; /* Address Offset: 0x0050 */ 160 uint32_t RESERVED0054[235]; /* Address Offset: 0x0054 */ 161 __O uint32_t TXDR; /* Address Offset: 0x0400 */ 162 uint32_t RESERVED0404[255]; /* Address Offset: 0x0404 */ 163 __IO uint32_t RXDR; /* Address Offset: 0x0800 */ 164 }; 165 /* EFUSE_CTL Register Structure Define */ 166 struct EFUSE_CTL_REG { 167 __IO uint32_t MOD; /* Address Offset: 0x0000 */ 168 __IO uint32_t RD_MASK; /* Address Offset: 0x0004 */ 169 __IO uint32_t PG_MASK; /* Address Offset: 0x0008 */ 170 uint32_t RESERVED000C[2]; /* Address Offset: 0x000C */ 171 __IO uint32_t INT_CON; /* Address Offset: 0x0014 */ 172 __O uint32_t INT_STATUS; /* Address Offset: 0x0018 */ 173 __IO uint32_t USER_CTRL; /* Address Offset: 0x001C */ 174 __I uint32_t DOUT; /* Address Offset: 0x0020 */ 175 __IO uint32_t AUTO_CTRL; /* Address Offset: 0x0024 */ 176 __IO uint32_t T_CSB_P; /* Address Offset: 0x0028 */ 177 __IO uint32_t T_PGENB_P; /* Address Offset: 0x002C */ 178 __IO uint32_t T_LOAD_P; /* Address Offset: 0x0030 */ 179 __IO uint32_t T_ADDR_P; /* Address Offset: 0x0034 */ 180 __IO uint32_t T_STROBE_P; /* Address Offset: 0x0038 */ 181 __IO uint32_t T_CSB_R; /* Address Offset: 0x003C */ 182 __IO uint32_t T_PGENB_R; /* Address Offset: 0x0040 */ 183 __IO uint32_t T_LOAD_R; /* Address Offset: 0x0044 */ 184 __IO uint32_t T_ADDR_R; /* Address Offset: 0x0048 */ 185 __IO uint32_t T_STROBE_R; /* Address Offset: 0x004C */ 186 __IO uint32_t REVISION; /* Address Offset: 0x0050 */ 187 }; 188 /* MBOX Register Structure Define */ 189 struct MBOX_CMD_DAT { 190 __IO uint32_t CMD; 191 __IO uint32_t DATA; 192 }; 193 struct MBOX_REG { 194 __IO uint32_t A2B_INTEN; /* Address Offset: 0x0000 */ 195 __IO uint32_t A2B_STATUS; /* Address Offset: 0x0004 */ 196 struct MBOX_CMD_DAT A2B[4]; /* Address Offset: 0x0008 */ 197 __IO uint32_t B2A_INTEN; /* Address Offset: 0x0028 */ 198 __IO uint32_t B2A_STATUS; /* Address Offset: 0x002C */ 199 struct MBOX_CMD_DAT B2A[4]; /* Address Offset: 0x0030 */ 200 uint32_t RESERVED0050[44]; /* Address Offset: 0x0050 */ 201 __IO uint32_t ATOMIC_LOCK[32]; /* Address Offset: 0x0100 */ 202 }; 203 /* SARADC Register Structure Define */ 204 struct SARADC_REG { 205 __I uint32_t DATA; /* Address Offset: 0x0000 */ 206 __I uint32_t STAS; /* Address Offset: 0x0004 */ 207 __IO uint32_t CTRL; /* Address Offset: 0x0008 */ 208 __IO uint32_t DLY_PU_SOC; /* Address Offset: 0x000C */ 209 }; 210 /* INTC Register Structure Define */ 211 struct INTC_REG { 212 __IO uint32_t IRQ_INTEN_L; /* Address Offset: 0x0000 */ 213 __IO uint32_t IRQ_INTEN_H; /* Address Offset: 0x0004 */ 214 __IO uint32_t IRQ_INTMASK_L; /* Address Offset: 0x0008 */ 215 __IO uint32_t IRQ_INTMASK_H; /* Address Offset: 0x000C */ 216 __IO uint32_t IRQ_INTFORCE_L; /* Address Offset: 0x0010 */ 217 __IO uint32_t IRQ_INTFORCE_H; /* Address Offset: 0x0014 */ 218 __I uint32_t IRQ_RAWSTATUS_L; /* Address Offset: 0x0018 */ 219 __I uint32_t IRQ_RAWSTATUS_H; /* Address Offset: 0x001C */ 220 __I uint32_t IRQ_STATUS_L; /* Address Offset: 0x0020 */ 221 __I uint32_t IRQ_STATUS_H; /* Address Offset: 0x0024 */ 222 __I uint32_t IRQ_MASKSTATUS_L; /* Address Offset: 0x0028 */ 223 __I uint32_t IRQ_MASKSTATUS_H; /* Address Offset: 0x002C */ 224 __I uint32_t IRQ_FINALSTATUS_L; /* Address Offset: 0x0030 */ 225 __I uint32_t IRQ_FINALSTATUS_H; /* Address Offset: 0x0034 */ 226 uint32_t RESERVED0038[34]; /* Address Offset: 0x0038 */ 227 __IO uint32_t FIQ_INTEN; /* Address Offset: 0x00C0 */ 228 __IO uint32_t FIQ_INTMASK; /* Address Offset: 0x00C4 */ 229 __IO uint32_t FIQ_INTFORCE; /* Address Offset: 0x00C8 */ 230 __I uint32_t FIQ_RAWSTATUS; /* Address Offset: 0x00CC */ 231 __I uint32_t FIQ_STATUS; /* Address Offset: 0x00D0 */ 232 __I uint32_t FIQ_FINALSTATUS; /* Address Offset: 0x00D4 */ 233 __IO uint32_t IRQ_PLEVEL; /* Address Offset: 0x00D8 */ 234 uint32_t RESERVED00DC[3]; /* Address Offset: 0x00DC */ 235 __IO uint32_t IRQ_PR_OFFSET; /* Address Offset: 0x00E8 */ 236 uint32_t RESERVED00EC[195]; /* Address Offset: 0x00EC */ 237 __I uint32_t AHB_ICTL_COMP_VERSION; /* Address Offset: 0x03F8 */ 238 __I uint32_t ICTL_COMP_TYPE; /* Address Offset: 0x03FC */ 239 }; 240 /* DMA Register Structure Define */ 241 struct DMA_CHAN_REGS { 242 __IO uint32_t SAR; 243 uint32_t RESERVED0004; 244 __IO uint32_t DAR; 245 uint32_t RESERVED000C; 246 __IO uint32_t LLP; 247 uint32_t RESERVED0014; 248 __IO uint32_t CTL_LO; 249 __IO uint32_t CTL_HI; 250 __IO uint32_t SSTAT; 251 uint32_t RESERVED0024; 252 __IO uint32_t DSTAT; 253 uint32_t RESERVED002C; 254 __IO uint32_t SSTATAR; 255 uint32_t RESERVED0034; 256 __IO uint32_t DSTATAR; 257 uint32_t RESERVED003C; 258 __IO uint32_t CFG_LO; 259 __IO uint32_t CFG_HI; 260 __IO uint32_t SGR; 261 uint32_t RESERVED004C; 262 __IO uint32_t DSR; 263 uint32_t RESERVED; 264 }; 265 struct DMA_IRQ_REGS { 266 __IO uint32_t TFR; 267 uint32_t RESERVED02C4; 268 __IO uint32_t BLOCK; 269 uint32_t RESERVED02CC; 270 __IO uint32_t SRCTRAN; 271 uint32_t RESERVED02D4; 272 __IO uint32_t DSTTRAN; 273 uint32_t RESERVED02DC; 274 __IO uint32_t ERR; 275 uint32_t RESERVED; 276 }; 277 struct DMA_REG { 278 struct DMA_CHAN_REGS CHAN[6]; /* Address Offset: 0x0000 */ 279 uint32_t RESERVED0210[44]; /* Address Offset: 0x0210 */ 280 struct DMA_IRQ_REGS RAW; /* Address Offset: 0x02C0 */ 281 struct DMA_IRQ_REGS STATUS; /* Address Offset: 0x02E8 */ 282 struct DMA_IRQ_REGS MASK; /* Address Offset: 0x0310 */ 283 struct DMA_IRQ_REGS CLEAR; /* Address Offset: 0x0338 */ 284 __I uint32_t STATUSINT; /* Address Offset: 0x0360 */ 285 uint32_t RESERVED0364[13]; /* Address Offset: 0x0364 */ 286 __IO uint32_t DMACFGREG; /* Address Offset: 0x0398 */ 287 uint32_t RESERVED039C; /* Address Offset: 0x039C */ 288 __IO uint32_t CHENREG; /* Address Offset: 0x03A0 */ 289 }; 290 /* FSPI Register Structure Define */ 291 struct FSPI_REG { 292 __IO uint32_t CTRL0; /* Address Offset: 0x0000 */ 293 __IO uint32_t IMR; /* Address Offset: 0x0004 */ 294 __O uint32_t ICLR; /* Address Offset: 0x0008 */ 295 __IO uint32_t FTLR; /* Address Offset: 0x000C */ 296 __IO uint32_t RCVR; /* Address Offset: 0x0010 */ 297 __IO uint32_t AX0; /* Address Offset: 0x0014 */ 298 __IO uint32_t ABIT0; /* Address Offset: 0x0018 */ 299 __IO uint32_t ISR; /* Address Offset: 0x001C */ 300 __IO uint32_t FSR; /* Address Offset: 0x0020 */ 301 __I uint32_t SR; /* Address Offset: 0x0024 */ 302 __I uint32_t RISR; /* Address Offset: 0x0028 */ 303 __I uint32_t VER; /* Address Offset: 0x002C */ 304 __IO uint32_t QOP; /* Address Offset: 0x0030 */ 305 __IO uint32_t EXT_CTRL; /* Address Offset: 0x0034 */ 306 __IO uint32_t POLL_CTRL; /* Address Offset: 0x0038 */ 307 __IO uint32_t DLL_CTRL0; /* Address Offset: 0x003C */ 308 __IO uint32_t HRDYMASK; /* Address Offset: 0x0040 */ 309 __IO uint32_t EXT_AX; /* Address Offset: 0x0044 */ 310 __IO uint32_t SCLK_INATM_CNT; /* Address Offset: 0x0048 */ 311 __IO uint32_t AUTO_RF_CNT; /* Address Offset: 0x004C */ 312 __O uint32_t XMMC_WCMD0; /* Address Offset: 0x0050 */ 313 __O uint32_t XMMC_RCMD0; /* Address Offset: 0x0054 */ 314 __IO uint32_t XMMC_CTRL; /* Address Offset: 0x0058 */ 315 __IO uint32_t MODE; /* Address Offset: 0x005C */ 316 __IO uint32_t DEVRGN; /* Address Offset: 0x0060 */ 317 __IO uint32_t DEVSIZE0; /* Address Offset: 0x0064 */ 318 __IO uint32_t TME0; /* Address Offset: 0x0068 */ 319 __IO uint32_t POLLDLY_CTRL; /* Address Offset: 0x006C */ 320 uint32_t RESERVED0070[4]; /* Address Offset: 0x0070 */ 321 __O uint32_t DMATR; /* Address Offset: 0x0080 */ 322 __IO uint32_t DMAADDR; /* Address Offset: 0x0084 */ 323 uint32_t RESERVED0088[2]; /* Address Offset: 0x0088 */ 324 __I uint32_t POLL_DATA; /* Address Offset: 0x0090 */ 325 __IO uint32_t XMMCSR; /* Address Offset: 0x0094 */ 326 uint32_t RESERVED0098[26]; /* Address Offset: 0x0098 */ 327 __O uint32_t CMD; /* Address Offset: 0x0100 */ 328 __O uint32_t ADDR; /* Address Offset: 0x0104 */ 329 __IO uint32_t DATA; /* Address Offset: 0x0108 */ 330 uint32_t RESERVED010C[61]; /* Address Offset: 0x010C */ 331 __IO uint32_t CTRL1; /* Address Offset: 0x0200 */ 332 uint32_t RESERVED0204[4]; /* Address Offset: 0x0204 */ 333 __IO uint32_t AX1; /* Address Offset: 0x0214 */ 334 __IO uint32_t ABIT1; /* Address Offset: 0x0218 */ 335 uint32_t RESERVED021C[8]; /* Address Offset: 0x021C */ 336 __IO uint32_t DLL_CTRL1; /* Address Offset: 0x023C */ 337 uint32_t RESERVED0240[4]; /* Address Offset: 0x0240 */ 338 __O uint32_t XMMC_WCMD1; /* Address Offset: 0x0250 */ 339 __O uint32_t XMMC_RCMD1; /* Address Offset: 0x0254 */ 340 uint32_t RESERVED0258[3]; /* Address Offset: 0x0258 */ 341 __IO uint32_t DEVSIZE1; /* Address Offset: 0x0264 */ 342 __IO uint32_t TME1; /* Address Offset: 0x0268 */ 343 }; 344 /* ICACHE Register Structure Define */ 345 struct ICACHE_REG { 346 __IO uint32_t CACHE_CTRL; /* Address Offset: 0x0000 */ 347 __IO uint32_t CACHE_MAINTAIN[2]; /* Address Offset: 0x0004 */ 348 __IO uint32_t STB_TIMEOUT_CTRL; /* Address Offset: 0x000C */ 349 uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ 350 __IO uint32_t CACHE_INT_EN; /* Address Offset: 0x0020 */ 351 __IO uint32_t CACHE_INT_ST; /* Address Offset: 0x0024 */ 352 __IO uint32_t CACHE_ERR_HADDR; /* Address Offset: 0x0028 */ 353 uint32_t RESERVED002C; /* Address Offset: 0x002C */ 354 __I uint32_t CACHE_STATUS; /* Address Offset: 0x0030 */ 355 uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ 356 __I uint32_t PMU_RD_NUM_CNT; /* Address Offset: 0x0040 */ 357 __I uint32_t PMU_WR_NUM_CNT; /* Address Offset: 0x0044 */ 358 __I uint32_t PMU_SRAM_RD_HIT_CNT; /* Address Offset: 0x0048 */ 359 __I uint32_t PMU_HB_RD_HIT_CNT; /* Address Offset: 0x004C */ 360 __IO uint32_t PMU_STB_RD_HIT_CNT; /* Address Offset: 0x0050 */ 361 __I uint32_t PMU_RD_HIT_CNT; /* Address Offset: 0x0054 */ 362 __I uint32_t PMU_WR_HIT_CNT; /* Address Offset: 0x0058 */ 363 __I uint32_t PMU_RD_MISS_PENALTY_CNT; /* Address Offset: 0x005C */ 364 __I uint32_t PMU_WR_MISS_PENALTY_CNT; /* Address Offset: 0x0060 */ 365 __I uint32_t PMU_RD_LAT_CNT; /* Address Offset: 0x0064 */ 366 __I uint32_t PMU_WR_LAT_CNT; /* Address Offset: 0x0068 */ 367 uint32_t RESERVED006C[33]; /* Address Offset: 0x006C */ 368 __I uint32_t REVISION; /* Address Offset: 0x00F0 */ 369 }; 370 /* DCACHE Register Structure Define */ 371 struct DCACHE_REG { 372 __IO uint32_t CACHE_CTRL; /* Address Offset: 0x0000 */ 373 __IO uint32_t CACHE_MAINTAIN[2]; /* Address Offset: 0x0004 */ 374 __IO uint32_t STB_TIMEOUT_CTRL; /* Address Offset: 0x000C */ 375 uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ 376 __IO uint32_t CACHE_INT_EN; /* Address Offset: 0x0020 */ 377 __IO uint32_t CACHE_INT_ST; /* Address Offset: 0x0024 */ 378 __IO uint32_t CACHE_ERR_HADDR; /* Address Offset: 0x0028 */ 379 uint32_t RESERVED002C; /* Address Offset: 0x002C */ 380 __I uint32_t CACHE_STATUS; /* Address Offset: 0x0030 */ 381 uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ 382 __I uint32_t PMU_RD_NUM_CNT; /* Address Offset: 0x0040 */ 383 __I uint32_t PMU_WR_NUM_CNT; /* Address Offset: 0x0044 */ 384 __I uint32_t PMU_SRAM_RD_HIT_CNT; /* Address Offset: 0x0048 */ 385 __I uint32_t PMU_HB_RD_HIT_CNT; /* Address Offset: 0x004C */ 386 __IO uint32_t PMU_STB_RD_HIT_CNT; /* Address Offset: 0x0050 */ 387 __I uint32_t PMU_RD_HIT_CNT; /* Address Offset: 0x0054 */ 388 __I uint32_t PMU_WR_HIT_CNT; /* Address Offset: 0x0058 */ 389 __I uint32_t PMU_RD_MISS_PENALTY_CNT; /* Address Offset: 0x005C */ 390 __I uint32_t PMU_WR_MISS_PENALTY_CNT; /* Address Offset: 0x0060 */ 391 __I uint32_t PMU_RD_LAT_CNT; /* Address Offset: 0x0064 */ 392 __I uint32_t PMU_WR_LAT_CNT; /* Address Offset: 0x0068 */ 393 uint32_t RESERVED006C[33]; /* Address Offset: 0x006C */ 394 __I uint32_t REVISION; /* Address Offset: 0x00F0 */ 395 }; 396 /* VOP Register Structure Define */ 397 struct VOP_REG { 398 __IO uint32_t CON; /* Address Offset: 0x0000 */ 399 __I uint32_t VERSION; /* Address Offset: 0x0004 */ 400 __IO uint32_t TIMING; /* Address Offset: 0x0008 */ 401 __IO uint32_t LCD_SIZE; /* Address Offset: 0x000C */ 402 __IO uint32_t FIFO_WATERMARK; /* Address Offset: 0x0010 */ 403 __O uint32_t SRT; /* Address Offset: 0x0014 */ 404 __IO uint32_t INT_EN; /* Address Offset: 0x0018 */ 405 __IO uint32_t INT_CLEAR; /* Address Offset: 0x001C */ 406 __IO uint32_t INT_STATUS; /* Address Offset: 0x0020 */ 407 __IO uint32_t STATUS; /* Address Offset: 0x0024 */ 408 __IO uint32_t CMD; /* Address Offset: 0x0028 */ 409 __IO uint32_t DATA; /* Address Offset: 0x002C */ 410 __IO uint32_t START; /* Address Offset: 0x0030 */ 411 }; 412 /* AUDIOPWM Register Structure Define */ 413 struct AUDIOPWM_REG { 414 __I uint32_t VERSION; /* Address Offset: 0x0000 */ 415 __IO uint32_t XFER; /* Address Offset: 0x0004 */ 416 __IO uint32_t SRC_CFG; /* Address Offset: 0x0008 */ 417 uint32_t RESERVED000C; /* Address Offset: 0x000C */ 418 __IO uint32_t PWM_CFG; /* Address Offset: 0x0010 */ 419 __I uint32_t PWM_ST; /* Address Offset: 0x0014 */ 420 __I uint32_t PWM_BUF_01; /* Address Offset: 0x0018 */ 421 __I uint32_t PWM_BUF_23; /* Address Offset: 0x001C */ 422 __IO uint32_t FIFO_CFG; /* Address Offset: 0x0020 */ 423 __I uint32_t FIFO_LVL; /* Address Offset: 0x0024 */ 424 __IO uint32_t FIFO_INT_EN; /* Address Offset: 0x0028 */ 425 __IO uint32_t FIFO_INT_ST; /* Address Offset: 0x002C */ 426 uint32_t RESERVED0030[20]; /* Address Offset: 0x0030 */ 427 __O uint32_t FIFO_ENTRY; /* Address Offset: 0x0080 */ 428 }; 429 /* HYPERBUS Register Structure Define */ 430 struct HYPERBUS_REG { 431 __I uint32_t CSR; /* Address Offset: 0x0000 */ 432 __IO uint32_t IEN; /* Address Offset: 0x0004 */ 433 __IO uint32_t ISR; /* Address Offset: 0x0008 */ 434 uint32_t RESERVED000C; /* Address Offset: 0x000C */ 435 __IO uint32_t MBR[2]; /* Address Offset: 0x0010 */ 436 uint32_t RESERVED0018[2]; /* Address Offset: 0x0018 */ 437 __IO uint32_t MCR[2]; /* Address Offset: 0x0020 */ 438 uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */ 439 __IO uint32_t MTR[2]; /* Address Offset: 0x0030 */ 440 uint32_t RESERVED0038[2]; /* Address Offset: 0x0038 */ 441 __IO uint32_t GPOR; /* Address Offset: 0x0040 */ 442 __IO uint32_t WPR; /* Address Offset: 0x0044 */ 443 __IO uint32_t LBR; /* Address Offset: 0x0048 */ 444 __IO uint32_t TAR; /* Address Offset: 0x004C */ 445 __IO uint32_t RWDSIC; /* Address Offset: 0x0050 */ 446 __IO uint32_t CA2RSVD; /* Address Offset: 0x0054 */ 447 __IO uint32_t SPCSR; /* Address Offset: 0x0058 */ 448 }; 449 /* PMU Register Structure Define */ 450 struct PMU_REG { 451 __IO uint32_t WAKEUP_CFG; /* Address Offset: 0x0000 */ 452 __IO uint32_t PWRDN_ST; /* Address Offset: 0x0004 */ 453 __IO uint32_t PWRMODE_CON; /* Address Offset: 0x0008 */ 454 __IO uint32_t SFT_CON; /* Address Offset: 0x000C */ 455 __IO uint32_t INT_CON; /* Address Offset: 0x0010 */ 456 __IO uint32_t INT_ST; /* Address Offset: 0x0014 */ 457 __IO uint32_t BUS_IDLE_ST; /* Address Offset: 0x0018 */ 458 __IO uint32_t POWER_ST; /* Address Offset: 0x001C */ 459 __IO uint32_t OSC_CNT; /* Address Offset: 0x0020 */ 460 __IO uint32_t PLLLOCK_CNT; /* Address Offset: 0x0024 */ 461 __IO uint32_t PLLRST_CNT; /* Address Offset: 0x0028 */ 462 __IO uint32_t RET_CON; /* Address Offset: 0x002C */ 463 __IO uint32_t INFO_TX_CON; /* Address Offset: 0x0030 */ 464 uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ 465 __IO uint32_t SYS_REG[4]; /* Address Offset: 0x0040 */ 466 uint32_t RESERVED0050[12]; /* Address Offset: 0x0050 */ 467 __IO uint32_t TIMEOUT_CNT; /* Address Offset: 0x0080 */ 468 }; 469 /* GPIO Register Structure Define */ 470 struct GPIO_REG { 471 __IO uint32_t SWPORT_DR_L; /* Address Offset: 0x0000 */ 472 __IO uint32_t SWPORT_DR_H; /* Address Offset: 0x0004 */ 473 __IO uint32_t SWPORT_DDR_L; /* Address Offset: 0x0008 */ 474 __IO uint32_t SWPORT_DDR_H; /* Address Offset: 0x000C */ 475 __IO uint32_t INT_EN_L; /* Address Offset: 0x0010 */ 476 __IO uint32_t INT_EN_H; /* Address Offset: 0x0014 */ 477 __IO uint32_t INT_MASK_L; /* Address Offset: 0x0018 */ 478 __IO uint32_t INT_MASK_H; /* Address Offset: 0x001C */ 479 __IO uint32_t INT_TYPE_L; /* Address Offset: 0x0020 */ 480 __IO uint32_t INT_TYPE_H; /* Address Offset: 0x0024 */ 481 __IO uint32_t INT_POLARITY_L; /* Address Offset: 0x0028 */ 482 __IO uint32_t INT_POLARITY_H; /* Address Offset: 0x002C */ 483 __IO uint32_t INT_BOTHEDGE_L; /* Address Offset: 0x0030 */ 484 __IO uint32_t INT_BOTHEDGE_H; /* Address Offset: 0x0034 */ 485 __IO uint32_t DEBOUNCE_L; /* Address Offset: 0x0038 */ 486 __IO uint32_t DEBOUNCE_H; /* Address Offset: 0x003C */ 487 __IO uint32_t DBCLK_DIV_EN_L; /* Address Offset: 0x0040 */ 488 __IO uint32_t DBCLK_DIV_EN_H; /* Address Offset: 0x0044 */ 489 __IO uint32_t DBCLK_DIV_CON; /* Address Offset: 0x0048 */ 490 uint32_t RESERVED004C; /* Address Offset: 0x004C */ 491 __I uint32_t INT_STATUS; /* Address Offset: 0x0050 */ 492 uint32_t RESERVED0054; /* Address Offset: 0x0054 */ 493 __I uint32_t INT_RAWSTATUS; /* Address Offset: 0x0058 */ 494 uint32_t RESERVED005C; /* Address Offset: 0x005C */ 495 __O uint32_t PORT_EOI_L; /* Address Offset: 0x0060 */ 496 __O uint32_t PORT_EOI_H; /* Address Offset: 0x0064 */ 497 uint32_t RESERVED0068[2]; /* Address Offset: 0x0068 */ 498 __I uint32_t EXT_PORT; /* Address Offset: 0x0070 */ 499 uint32_t RESERVED0074; /* Address Offset: 0x0074 */ 500 __I uint32_t VER_ID; /* Address Offset: 0x0078 */ 501 }; 502 /* ACDCDIG Register Structure Define */ 503 struct ACDCDIG_REG { 504 __IO uint32_t SYSCTRL0; /* Address Offset: 0x0000 */ 505 uint32_t RESERVED0004[15]; /* Address Offset: 0x0004 */ 506 __IO uint32_t ADCVUCTL; /* Address Offset: 0x0040 */ 507 __IO uint32_t ADCVUCTIME; /* Address Offset: 0x0044 */ 508 __IO uint32_t ADCDIGEN; /* Address Offset: 0x0048 */ 509 __IO uint32_t ADCCLKCTRL; /* Address Offset: 0x004C */ 510 uint32_t RESERVED0050; /* Address Offset: 0x0050 */ 511 __IO uint32_t ADCINT_DIV; /* Address Offset: 0x0054 */ 512 uint32_t RESERVED0058[5]; /* Address Offset: 0x0058 */ 513 __IO uint32_t ADCSCLKTXINT_DIV; /* Address Offset: 0x006C */ 514 uint32_t RESERVED0070[5]; /* Address Offset: 0x0070 */ 515 __IO uint32_t ADCCFG1; /* Address Offset: 0x0084 */ 516 __IO uint32_t ADCVOLL[2]; /* Address Offset: 0x0088 */ 517 uint32_t RESERVED0090[2]; /* Address Offset: 0x0090 */ 518 __IO uint32_t ADCVOLR0; /* Address Offset: 0x0098 */ 519 uint32_t RESERVED009C[3]; /* Address Offset: 0x009C */ 520 __IO uint32_t ADCVOGP; /* Address Offset: 0x00A8 */ 521 __I uint32_t ADCRVOLL[2]; /* Address Offset: 0x00AC */ 522 uint32_t RESERVED00B4[2]; /* Address Offset: 0x00B4 */ 523 __I uint32_t ADCRVOLR0; /* Address Offset: 0x00BC */ 524 uint32_t RESERVED00C0[3]; /* Address Offset: 0x00C0 */ 525 __IO uint32_t ADCALC[3]; /* Address Offset: 0x00CC */ 526 __IO uint32_t ADCNG; /* Address Offset: 0x00D8 */ 527 __I uint32_t ADCNGST; /* Address Offset: 0x00DC */ 528 __IO uint32_t ADCHPFEN; /* Address Offset: 0x00E0 */ 529 __IO uint32_t ADCHPFCF; /* Address Offset: 0x00E4 */ 530 uint32_t RESERVED00E8; /* Address Offset: 0x00E8 */ 531 __IO uint32_t ADCPGL[2]; /* Address Offset: 0x00EC */ 532 uint32_t RESERVED00F4[2]; /* Address Offset: 0x00F4 */ 533 __IO uint32_t ADCPGR0; /* Address Offset: 0x00FC */ 534 uint32_t RESERVED0100[3]; /* Address Offset: 0x0100 */ 535 __IO uint32_t ADCLILMT[2]; /* Address Offset: 0x010C */ 536 __IO uint32_t ADCDMICNG[2]; /* Address Offset: 0x0114 */ 537 uint32_t RESERVED011C[9]; /* Address Offset: 0x011C */ 538 __IO uint32_t DACVUCTL; /* Address Offset: 0x0140 */ 539 __IO uint32_t DACVUCTIME; /* Address Offset: 0x0144 */ 540 __IO uint32_t DACDIGEN; /* Address Offset: 0x0148 */ 541 __IO uint32_t DACCLKCTRL; /* Address Offset: 0x014C */ 542 uint32_t RESERVED0150; /* Address Offset: 0x0150 */ 543 __IO uint32_t DACINT_DIV; /* Address Offset: 0x0154 */ 544 uint32_t RESERVED0158[5]; /* Address Offset: 0x0158 */ 545 __IO uint32_t DACSCLKRXINT_DIV; /* Address Offset: 0x016C */ 546 uint32_t RESERVED0170[5]; /* Address Offset: 0x0170 */ 547 __IO uint32_t DACCFG1; /* Address Offset: 0x0184 */ 548 __IO uint32_t DACMUTE; /* Address Offset: 0x0188 */ 549 __I uint32_t DACMUTEST; /* Address Offset: 0x018C */ 550 __IO uint32_t DACVOLL0; /* Address Offset: 0x0190 */ 551 uint32_t RESERVED0194[7]; /* Address Offset: 0x0194 */ 552 __IO uint32_t DACVOGP; /* Address Offset: 0x01B0 */ 553 __I uint32_t DACRVOLL0; /* Address Offset: 0x01B4 */ 554 uint32_t RESERVED01B8[7]; /* Address Offset: 0x01B8 */ 555 __IO uint32_t DACLMT[3]; /* Address Offset: 0x01D4 */ 556 __IO uint32_t DACMIXCTRLL; /* Address Offset: 0x01E0 */ 557 uint32_t RESERVED01E4; /* Address Offset: 0x01E4 */ 558 __IO uint32_t DACHPF; /* Address Offset: 0x01E8 */ 559 uint32_t RESERVED01EC[37]; /* Address Offset: 0x01EC */ 560 __IO uint32_t I2C_FLT_CON[2]; /* Address Offset: 0x0280 */ 561 __IO uint32_t I2C_CON[2]; /* Address Offset: 0x0288 */ 562 __IO uint32_t I2C_CLKDIVL[2]; /* Address Offset: 0x0290 */ 563 __IO uint32_t I2C_CLKDIVH[2]; /* Address Offset: 0x0298 */ 564 __IO uint32_t I2C_MAXCNT; /* Address Offset: 0x02A0 */ 565 __IO uint32_t I2C_SCLOE_DB[4]; /* Address Offset: 0x02A4 */ 566 __IO uint32_t I2C_TMOUTL; /* Address Offset: 0x02B4 */ 567 __IO uint32_t I2C_TMOUTH; /* Address Offset: 0x02B8 */ 568 __IO uint32_t I2C_DEV_ADDR; /* Address Offset: 0x02BC */ 569 __IO uint32_t I2C_REG_ADDR; /* Address Offset: 0x02C0 */ 570 __IO uint32_t I2C_STATUS; /* Address Offset: 0x02C4 */ 571 uint32_t RESERVED02C8[14]; /* Address Offset: 0x02C8 */ 572 __IO uint32_t I2S_TXCR[3]; /* Address Offset: 0x0300 */ 573 __IO uint32_t I2S_RXCR[2]; /* Address Offset: 0x030C */ 574 __IO uint32_t I2S_CKR[2]; /* Address Offset: 0x0314 */ 575 __IO uint32_t I2S_XFER; /* Address Offset: 0x031C */ 576 __O uint32_t I2S_CLR; /* Address Offset: 0x0320 */ 577 uint32_t RESERVED0324[23]; /* Address Offset: 0x0324 */ 578 __I uint32_t VERSION; /* Address Offset: 0x0380 */ 579 }; 580 /* GRF Register Structure Define */ 581 struct GRF_REG { 582 __IO uint32_t GPIO0A_IOMUX_L; /* Address Offset: 0x0000 */ 583 __IO uint32_t GPIO0A_IOMUX_H; /* Address Offset: 0x0004 */ 584 __IO uint32_t GPIO0B_IOMUX_L; /* Address Offset: 0x0008 */ 585 __IO uint32_t GPIO0B_IOMUX_H; /* Address Offset: 0x000C */ 586 __IO uint32_t GPIO0C_IOMUX_L; /* Address Offset: 0x0010 */ 587 __IO uint32_t GPIO0C_IOMUX_H; /* Address Offset: 0x0014 */ 588 __IO uint32_t GPIO0D_IOMUX_L; /* Address Offset: 0x0018 */ 589 __IO uint32_t GPIO0D_IOMUX_H; /* Address Offset: 0x001C */ 590 __IO uint32_t GPIO1A_IOMUX_L; /* Address Offset: 0x0020 */ 591 __IO uint32_t GPIO1A_IOMUX_H; /* Address Offset: 0x0024 */ 592 __IO uint32_t GPIO1B_IOMUX_L; /* Address Offset: 0x0028 */ 593 __IO uint32_t GPIO1B_IOMUX_H; /* Address Offset: 0x002C */ 594 __IO uint32_t GPIO1C_IOMUX_L; /* Address Offset: 0x0030 */ 595 uint32_t RESERVED0034; /* Address Offset: 0x0034 */ 596 __IO uint32_t GPIO1D_IOMUX_L; /* Address Offset: 0x0038 */ 597 uint32_t RESERVED003C[49]; /* Address Offset: 0x003C */ 598 __IO uint32_t GPIO0A_P; /* Address Offset: 0x0100 */ 599 __IO uint32_t GPIO0B_P; /* Address Offset: 0x0104 */ 600 __IO uint32_t GPIO0C_P; /* Address Offset: 0x0108 */ 601 __IO uint32_t GPIO0D_P; /* Address Offset: 0x010C */ 602 __IO uint32_t GPIO1A_P; /* Address Offset: 0x0110 */ 603 __IO uint32_t GPIO1B_P; /* Address Offset: 0x0114 */ 604 __IO uint32_t GPIO1C_P; /* Address Offset: 0x0118 */ 605 __IO uint32_t GPIO1D_P; /* Address Offset: 0x011C */ 606 uint32_t RESERVED0120[56]; /* Address Offset: 0x0120 */ 607 __IO uint32_t SOC_CON0; /* Address Offset: 0x0200 */ 608 __IO uint32_t SOC_CON1; /* Address Offset: 0x0204 */ 609 __IO uint32_t SOC_CON2; /* Address Offset: 0x0208 */ 610 __IO uint32_t SOC_CON3; /* Address Offset: 0x020C */ 611 __IO uint32_t SOC_CON4; /* Address Offset: 0x0210 */ 612 __IO uint32_t SOC_CON5; /* Address Offset: 0x0214 */ 613 __IO uint32_t SOC_CON6; /* Address Offset: 0x0218 */ 614 __IO uint32_t SOC_CON7; /* Address Offset: 0x021C */ 615 __IO uint32_t SOC_CON8; /* Address Offset: 0x0220 */ 616 __IO uint32_t SOC_CON9; /* Address Offset: 0x0224 */ 617 __IO uint32_t SOC_CON10; /* Address Offset: 0x0228 */ 618 __IO uint32_t SOC_CON11; /* Address Offset: 0x022C */ 619 __IO uint32_t SOC_CON12; /* Address Offset: 0x0230 */ 620 __IO uint32_t SOC_CON13; /* Address Offset: 0x0234 */ 621 __IO uint32_t SOC_CON14; /* Address Offset: 0x0238 */ 622 __IO uint32_t SOC_CON15; /* Address Offset: 0x023C */ 623 __IO uint32_t SOC_CON16; /* Address Offset: 0x0240 */ 624 __IO uint32_t SOC_CON17; /* Address Offset: 0x0244 */ 625 __IO uint32_t SOC_CON18; /* Address Offset: 0x0248 */ 626 __IO uint32_t SOC_CON19; /* Address Offset: 0x024C */ 627 __IO uint32_t SOC_CON20; /* Address Offset: 0x0250 */ 628 __IO uint32_t SOC_CON21; /* Address Offset: 0x0254 */ 629 __IO uint32_t SOC_CON22; /* Address Offset: 0x0258 */ 630 __IO uint32_t SOC_CON23; /* Address Offset: 0x025C */ 631 __IO uint32_t SOC_CON24; /* Address Offset: 0x0260 */ 632 __IO uint32_t SOC_CON25; /* Address Offset: 0x0264 */ 633 __IO uint32_t SOC_CON26; /* Address Offset: 0x0268 */ 634 __IO uint32_t SOC_CON27; /* Address Offset: 0x026C */ 635 __IO uint32_t SOC_CON28; /* Address Offset: 0x0270 */ 636 __IO uint32_t SOC_CON29; /* Address Offset: 0x0274 */ 637 __IO uint32_t SOC_CON30; /* Address Offset: 0x0278 */ 638 __IO uint32_t SOC_CON31; /* Address Offset: 0x027C */ 639 __I uint32_t SOC_STATUS; /* Address Offset: 0x0280 */ 640 uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ 641 __IO uint32_t MCU0_CON0; /* Address Offset: 0x0300 */ 642 __IO uint32_t MCU0_CON1; /* Address Offset: 0x0304 */ 643 __IO uint32_t MCU1_CON0; /* Address Offset: 0x0308 */ 644 __IO uint32_t MCU1_CON1; /* Address Offset: 0x030C */ 645 uint32_t RESERVED0310[4]; /* Address Offset: 0x0310 */ 646 __IO uint32_t DSP_CON0; /* Address Offset: 0x0320 */ 647 __IO uint32_t DSP_CON1; /* Address Offset: 0x0324 */ 648 __IO uint32_t DSP_CON2; /* Address Offset: 0x0328 */ 649 uint32_t RESERVED032C[5]; /* Address Offset: 0x032C */ 650 __IO uint32_t SOC_UOC0; /* Address Offset: 0x0340 */ 651 __IO uint32_t SOC_UOC1; /* Address Offset: 0x0344 */ 652 __IO uint32_t SOC_UOC2; /* Address Offset: 0x0348 */ 653 uint32_t RESERVED034C[13]; /* Address Offset: 0x034C */ 654 __I uint32_t MCU0_STATUS; /* Address Offset: 0x0380 */ 655 __IO uint32_t MCU1_STATUS; /* Address Offset: 0x0384 */ 656 __I uint32_t DSP_STAT0; /* Address Offset: 0x0388 */ 657 __I uint32_t DSP_STAT1; /* Address Offset: 0x038C */ 658 uint32_t RESERVED0390[28]; /* Address Offset: 0x0390 */ 659 __IO uint32_t GRF_FAST_BOOT; /* Address Offset: 0x0400 */ 660 __IO uint32_t GRF_FAST_BOOT_ADDR; /* Address Offset: 0x0404 */ 661 uint32_t RESERVED0408[62]; /* Address Offset: 0x0408 */ 662 __IO uint32_t WLAN_CON; /* Address Offset: 0x0500 */ 663 __IO uint32_t WLANCLK_CON; /* Address Offset: 0x0504 */ 664 __IO uint32_t WLAN_GPIO_IN; /* Address Offset: 0x0508 */ 665 __IO uint32_t WLAN_GPIO_OUT; /* Address Offset: 0x050C */ 666 uint32_t RESERVED0510[28]; /* Address Offset: 0x0510 */ 667 __O uint32_t WLAN_STATUS; /* Address Offset: 0x0580 */ 668 uint32_t RESERVED0584[63]; /* Address Offset: 0x0584 */ 669 __IO uint32_t USB2_DISCONNECT_CON; /* Address Offset: 0x0680 */ 670 __IO uint32_t USB2_LINESTATE_CON; /* Address Offset: 0x0684 */ 671 __IO uint32_t USB2_BVALID_CON; /* Address Offset: 0x0688 */ 672 __IO uint32_t USB2_ID_CON; /* Address Offset: 0x068C */ 673 __IO uint32_t USB2_DETECT_IRQ_ENABLE; /* Address Offset: 0x0690 */ 674 __IO uint32_t USB2_DETECT_IRQ_STATUS; /* Address Offset: 0x0694 */ 675 __IO uint32_t USB2_DETECT_IRQ_STATUS_CLR; /* Address Offset: 0x0698 */ 676 uint32_t RESERVED069C[25]; /* Address Offset: 0x069C */ 677 __IO uint32_t HW_SPINLOCK[64]; /* Address Offset: 0x0700 */ 678 __IO uint32_t OS_REG0; /* Address Offset: 0x0800 */ 679 __IO uint32_t OS_REG1; /* Address Offset: 0x0804 */ 680 __IO uint32_t OS_REG2; /* Address Offset: 0x0808 */ 681 __IO uint32_t OS_REG3; /* Address Offset: 0x080C */ 682 __IO uint32_t OS_REG4; /* Address Offset: 0x0810 */ 683 __IO uint32_t OS_REG5; /* Address Offset: 0x0814 */ 684 __IO uint32_t OS_REG6; /* Address Offset: 0x0818 */ 685 __IO uint32_t OS_REG7; /* Address Offset: 0x081C */ 686 __I uint32_t GRF_SOC_VERSION; /* Address Offset: 0x0820 */ 687 }; 688 /* CRU Register Structure Define */ 689 struct CRU_REG { 690 __IO uint32_t GPLL_CON[5]; /* Address Offset: 0x0000 */ 691 uint32_t RESERVED0014[3]; /* Address Offset: 0x0014 */ 692 __IO uint32_t VPLL_CON[5]; /* Address Offset: 0x0020 */ 693 uint32_t RESERVED0034[27]; /* Address Offset: 0x0034 */ 694 __IO uint32_t MODE_CON00; /* Address Offset: 0x00A0 */ 695 uint32_t RESERVED00A4[3]; /* Address Offset: 0x00A4 */ 696 __IO uint32_t GLB_CNT_TH; /* Address Offset: 0x00B0 */ 697 __O uint32_t GLB_RST_ST; /* Address Offset: 0x00B4 */ 698 __IO uint32_t GLB_SRST_FST_VALUE; /* Address Offset: 0x00B8 */ 699 __IO uint32_t GLB_SRST_SND_VALUE; /* Address Offset: 0x00BC */ 700 __IO uint32_t GLB_RST_CON; /* Address Offset: 0x00C0 */ 701 uint32_t RESERVED00C4[15]; /* Address Offset: 0x00C4 */ 702 __IO uint32_t CRU_CLKSEL_CON[37]; /* Address Offset: 0x0100 */ 703 uint32_t RESERVED0194[91]; /* Address Offset: 0x0194 */ 704 __IO uint32_t CRU_CLKGATE_CON[13]; /* Address Offset: 0x0300 */ 705 uint32_t RESERVED0334[19]; /* Address Offset: 0x0334 */ 706 __O uint32_t SSCGTBL0_3; /* Address Offset: 0x0380 */ 707 __O uint32_t SSCGTBL4_7; /* Address Offset: 0x0384 */ 708 __O uint32_t SSCGTBL8_11; /* Address Offset: 0x0388 */ 709 __O uint32_t SSCGTBL12_15; /* Address Offset: 0x038C */ 710 __O uint32_t SSCGTBL16_19; /* Address Offset: 0x0390 */ 711 __O uint32_t SSCGTBL20_23; /* Address Offset: 0x0394 */ 712 __O uint32_t SSCGTBL24_27; /* Address Offset: 0x0398 */ 713 __O uint32_t SSCGTBL28_31; /* Address Offset: 0x039C */ 714 __O uint32_t SSCGTBL32_35; /* Address Offset: 0x03A0 */ 715 __O uint32_t SSCGTBL36_39; /* Address Offset: 0x03A4 */ 716 __O uint32_t SSCGTBL40_43; /* Address Offset: 0x03A8 */ 717 __O uint32_t SSCGTBL44_47; /* Address Offset: 0x03AC */ 718 __O uint32_t SSCGTBL48_51; /* Address Offset: 0x03B0 */ 719 __O uint32_t SSCGTBL52_55; /* Address Offset: 0x03B4 */ 720 __O uint32_t SSCGTBL56_59; /* Address Offset: 0x03B8 */ 721 __O uint32_t SSCGTBL60_63; /* Address Offset: 0x03BC */ 722 __O uint32_t SSCGTBL64_67; /* Address Offset: 0x03C0 */ 723 __O uint32_t SSCGTBL68_71; /* Address Offset: 0x03C4 */ 724 __O uint32_t SSCGTBL72_75; /* Address Offset: 0x03C8 */ 725 __O uint32_t SSCGTBL76_79; /* Address Offset: 0x03CC */ 726 __O uint32_t SSCGTBL80_83; /* Address Offset: 0x03D0 */ 727 __O uint32_t SSCGTBL84_87; /* Address Offset: 0x03D4 */ 728 __O uint32_t SSCGTBL88_91; /* Address Offset: 0x03D8 */ 729 __O uint32_t SSCGTBL92_95; /* Address Offset: 0x03DC */ 730 __O uint32_t SSCGTBL96_99; /* Address Offset: 0x03E0 */ 731 __O uint32_t SSCGTBL100_103; /* Address Offset: 0x03E4 */ 732 __O uint32_t SSCGTBL104_107; /* Address Offset: 0x03E8 */ 733 __O uint32_t SSCGTBL108_111; /* Address Offset: 0x03EC */ 734 __O uint32_t SSCGTBL112_115; /* Address Offset: 0x03F0 */ 735 __O uint32_t SSCGTBL116_119; /* Address Offset: 0x03F4 */ 736 __O uint32_t SSCGTBL120_123; /* Address Offset: 0x03F8 */ 737 __O uint32_t SSCGTBL124_127; /* Address Offset: 0x03FC */ 738 __IO uint32_t CRU_SOFTRST_CON[13]; /* Address Offset: 0x0400 */ 739 uint32_t RESERVED0434[19]; /* Address Offset: 0x0434 */ 740 __IO uint32_t SDMMC_CON[2]; /* Address Offset: 0x0480 */ 741 }; 742 /* PVTM Register Structure Define */ 743 struct PVTM_REG { 744 __IO uint32_t VERSION; /* Address Offset: 0x0000 */ 745 __IO uint32_t CON[2]; /* Address Offset: 0x0004 */ 746 uint32_t RESERVED000C[29]; /* Address Offset: 0x000C */ 747 __IO uint32_t STATUS[2]; /* Address Offset: 0x0080 */ 748 }; 749 /* TOUCH_SENSOR Register Structure Define */ 750 struct TOUCH_SENSOR_REG { 751 __IO uint32_t CH_START; /* Address Offset: 0x0000 */ 752 __IO uint32_t CH_ENABLE[2]; /* Address Offset: 0x0004 */ 753 __IO uint32_t CH_DIV; /* Address Offset: 0x000C */ 754 __IO uint32_t CH_IRQ_EN[4]; /* Address Offset: 0x0010 */ 755 __IO uint32_t CH_IRQ_ST_POS; /* Address Offset: 0x0020 */ 756 __IO uint32_t CH_IRQ_ST_NEG; /* Address Offset: 0x0024 */ 757 __IO uint32_t CH_IRQ_RAW; /* Address Offset: 0x0028 */ 758 __IO uint32_t CH_IRQ_CLEAR[2]; /* Address Offset: 0x002C */ 759 __IO uint32_t CH_CHARGE_THRESHOLD; /* Address Offset: 0x0034 */ 760 __IO uint32_t CH_FILTER_STABLE_TIME; /* Address Offset: 0x0038 */ 761 __IO uint32_t CH_IRQ_SEL; /* Address Offset: 0x003C */ 762 __IO uint32_t CH_LOCK; /* Address Offset: 0x0040 */ 763 __IO uint32_t CH_RC_TYPE_SEL; /* Address Offset: 0x0044 */ 764 __IO uint32_t CH_RC_SPEED_STEP_CNT; /* Address Offset: 0x0048 */ 765 uint32_t RESERVED004C[45]; /* Address Offset: 0x004C */ 766 __IO uint32_t CH0_CNT; /* Address Offset: 0x0100 */ 767 __IO uint32_t CH0_CNT_DC; /* Address Offset: 0x0104 */ 768 __IO uint32_t CH0_CNT_DO; /* Address Offset: 0x0108 */ 769 __IO uint32_t CH0_CNT_FILTER; /* Address Offset: 0x010C */ 770 uint32_t RESERVED0110[60]; /* Address Offset: 0x0110 */ 771 __IO uint32_t CH1_CNT; /* Address Offset: 0x0200 */ 772 __IO uint32_t CH1_CNT_DC; /* Address Offset: 0x0204 */ 773 __IO uint32_t CH1_CNT_DO; /* Address Offset: 0x0208 */ 774 __IO uint32_t CH1_CNT_FILTER; /* Address Offset: 0x020C */ 775 uint32_t RESERVED0210[60]; /* Address Offset: 0x0210 */ 776 __IO uint32_t CH2_CNT; /* Address Offset: 0x0300 */ 777 __IO uint32_t CH2_CNT_DC; /* Address Offset: 0x0304 */ 778 __IO uint32_t CH2_CNT_DO; /* Address Offset: 0x0308 */ 779 __IO uint32_t CH2_CNT_FILTER; /* Address Offset: 0x030C */ 780 uint32_t RESERVED0310[60]; /* Address Offset: 0x0310 */ 781 __IO uint32_t CH3_CNT; /* Address Offset: 0x0400 */ 782 __IO uint32_t CH3_CNT_DC; /* Address Offset: 0x0404 */ 783 __IO uint32_t CH3_CNT_DO; /* Address Offset: 0x0408 */ 784 __IO uint32_t CH3_CNT_FILTER; /* Address Offset: 0x040C */ 785 uint32_t RESERVED0410[60]; /* Address Offset: 0x0410 */ 786 __IO uint32_t CH4_CNT; /* Address Offset: 0x0500 */ 787 __IO uint32_t CH4_CNT_DC; /* Address Offset: 0x0504 */ 788 __IO uint32_t CH4_CNT_DO; /* Address Offset: 0x0508 */ 789 __IO uint32_t CH4_CNT_FILTER; /* Address Offset: 0x050C */ 790 uint32_t RESERVED0510[60]; /* Address Offset: 0x0510 */ 791 __IO uint32_t CH5_CNT; /* Address Offset: 0x0600 */ 792 __IO uint32_t CH5_CNT_DC; /* Address Offset: 0x0604 */ 793 __IO uint32_t CH5_CNT_DO; /* Address Offset: 0x0608 */ 794 __IO uint32_t CH5_CNT_FILTER; /* Address Offset: 0x060C */ 795 uint32_t RESERVED0610[60]; /* Address Offset: 0x0610 */ 796 __IO uint32_t CH6_CNT; /* Address Offset: 0x0700 */ 797 __IO uint32_t CH6_CNT_DC; /* Address Offset: 0x0704 */ 798 __IO uint32_t CH6_CNT_DO; /* Address Offset: 0x0708 */ 799 __IO uint32_t CH6_CNT_FILTER; /* Address Offset: 0x070C */ 800 uint32_t RESERVED0710[60]; /* Address Offset: 0x0710 */ 801 __IO uint32_t CH7_CNT; /* Address Offset: 0x0800 */ 802 __IO uint32_t CH7_CNT_DC; /* Address Offset: 0x0804 */ 803 __IO uint32_t CH7_CNT_DO; /* Address Offset: 0x0808 */ 804 __IO uint32_t CH7_CNT_FILTER; /* Address Offset: 0x080C */ 805 uint32_t RESERVED0810[60]; /* Address Offset: 0x0810 */ 806 __IO uint32_t CH8_CNT; /* Address Offset: 0x0900 */ 807 __IO uint32_t CH8_CNT_DC; /* Address Offset: 0x0904 */ 808 __IO uint32_t CH8_CNT_DO; /* Address Offset: 0x0908 */ 809 __IO uint32_t CH8_CNT_FILTER; /* Address Offset: 0x090C */ 810 uint32_t RESERVED0910[444]; /* Address Offset: 0x0910 */ 811 __IO uint32_t CH9_CNT; /* Address Offset: 0x1000 */ 812 __IO uint32_t CH9_CNT_DC; /* Address Offset: 0x1004 */ 813 __IO uint32_t CH9_CNT_DO; /* Address Offset: 0x1008 */ 814 __IO uint32_t CH9_CNT_FILTER; /* Address Offset: 0x100C */ 815 uint32_t RESERVED1010[60]; /* Address Offset: 0x1010 */ 816 __IO uint32_t CH10_CNT; /* Address Offset: 0x1100 */ 817 __IO uint32_t CH10_CNT_DC; /* Address Offset: 0x1104 */ 818 __IO uint32_t CH10_CNT_DO; /* Address Offset: 0x1108 */ 819 __IO uint32_t CH10_CNT_FILTER; /* Address Offset: 0x110C */ 820 uint32_t RESERVED1110[60]; /* Address Offset: 0x1110 */ 821 __IO uint32_t CH11_CNT; /* Address Offset: 0x1200 */ 822 __IO uint32_t CH11_CNT_DC; /* Address Offset: 0x1204 */ 823 __IO uint32_t CH11_CNT_DO; /* Address Offset: 0x1208 */ 824 __IO uint32_t CH11_CNT_FILTER; /* Address Offset: 0x120C */ 825 uint32_t RESERVED1210[60]; /* Address Offset: 0x1210 */ 826 __IO uint32_t CH12_CNT; /* Address Offset: 0x1300 */ 827 __IO uint32_t CH12_CNT_DC; /* Address Offset: 0x1304 */ 828 __IO uint32_t CH12_CNT_DO; /* Address Offset: 0x1308 */ 829 __IO uint32_t CH12_CNT_FILTER; /* Address Offset: 0x130C */ 830 uint32_t RESERVED1310[60]; /* Address Offset: 0x1310 */ 831 __IO uint32_t CH13_CNT; /* Address Offset: 0x1400 */ 832 __IO uint32_t CH13_CNT_DC; /* Address Offset: 0x1404 */ 833 __IO uint32_t CH13_CNT_DO; /* Address Offset: 0x1408 */ 834 __IO uint32_t CH13_CNT_FILTER; /* Address Offset: 0x140C */ 835 uint32_t RESERVED1410[60]; /* Address Offset: 0x1410 */ 836 __IO uint32_t CH14_CNT; /* Address Offset: 0x1500 */ 837 __IO uint32_t CH14_CNT_DC; /* Address Offset: 0x1504 */ 838 __IO uint32_t CH14_CNT_DO; /* Address Offset: 0x1508 */ 839 __IO uint32_t CH14_CNT_FILTER; /* Address Offset: 0x150C */ 840 uint32_t RESERVED1510[60]; /* Address Offset: 0x1510 */ 841 __IO uint32_t CH15_CNT; /* Address Offset: 0x1600 */ 842 __IO uint32_t CH15_CNT_DC; /* Address Offset: 0x1604 */ 843 __IO uint32_t CH15_CNT_DO; /* Address Offset: 0x1608 */ 844 __IO uint32_t CH15_CNT_FILTER; /* Address Offset: 0x160C */ 845 uint32_t RESERVED1610[60]; /* Address Offset: 0x1610 */ 846 __IO uint32_t CH16_CNT; /* Address Offset: 0x1700 */ 847 __IO uint32_t CH16_CNT_DC; /* Address Offset: 0x1704 */ 848 __IO uint32_t CH16_CNT_DO; /* Address Offset: 0x1708 */ 849 __IO uint32_t CH16_CNT_FILTER; /* Address Offset: 0x170C */ 850 uint32_t RESERVED1710[60]; /* Address Offset: 0x1710 */ 851 __IO uint32_t CH17_CNT; /* Address Offset: 0x1800 */ 852 __IO uint32_t CH17_CNT_DC; /* Address Offset: 0x1804 */ 853 __IO uint32_t CH17_CNT_DO; /* Address Offset: 0x1808 */ 854 __IO uint32_t CH17_CNT_FILTER; /* Address Offset: 0x180C */ 855 uint32_t RESERVED1810[60]; /* Address Offset: 0x1810 */ 856 __IO uint32_t CH18_CNT; /* Address Offset: 0x1900 */ 857 __IO uint32_t CH18_CNT_DC; /* Address Offset: 0x1904 */ 858 __IO uint32_t CH18_CNT_DO; /* Address Offset: 0x1908 */ 859 __IO uint32_t CH18_CNT_FILTER; /* Address Offset: 0x190C */ 860 uint32_t RESERVED1910[444]; /* Address Offset: 0x1910 */ 861 __IO uint32_t CH19_CNT; /* Address Offset: 0x2000 */ 862 __IO uint32_t CH19_CNT_DC; /* Address Offset: 0x2004 */ 863 __IO uint32_t CH19_CNT_DO; /* Address Offset: 0x2008 */ 864 __IO uint32_t CH19_CNT_FILTER; /* Address Offset: 0x200C */ 865 }; 866 /* TSADC Register Structure Define */ 867 struct TSADC_REG { 868 __IO uint32_t USER_CON; /* Address Offset: 0x0000 */ 869 __IO uint32_t AUTO_CON; /* Address Offset: 0x0004 */ 870 __IO uint32_t INT_EN; /* Address Offset: 0x0008 */ 871 __IO uint32_t INT_PD; /* Address Offset: 0x000C */ 872 uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ 873 __I uint32_t DATA[2]; /* Address Offset: 0x0020 */ 874 uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */ 875 __IO uint32_t COMP_INT[2]; /* Address Offset: 0x0030 */ 876 uint32_t RESERVED0038[2]; /* Address Offset: 0x0038 */ 877 __IO uint32_t COMP_SHUT[2]; /* Address Offset: 0x0040 */ 878 uint32_t RESERVED0048[6]; /* Address Offset: 0x0048 */ 879 __IO uint32_t HIGHT_INT_DEBOUNCE; /* Address Offset: 0x0060 */ 880 __IO uint32_t HIGHT_TSHUT_DEBOUNCE; /* Address Offset: 0x0064 */ 881 __IO uint32_t AUTO_PERIOD; /* Address Offset: 0x0068 */ 882 __IO uint32_t AUTO_PERIOD_HT; /* Address Offset: 0x006C */ 883 uint32_t RESERVED0070[4]; /* Address Offset: 0x0070 */ 884 __IO uint32_t COMP_LOW_INT[2]; /* Address Offset: 0x0080 */ 885 }; 886 /* I2STDM Register Structure Define */ 887 struct I2STDM_REG { 888 __IO uint32_t TXCR; /* Address Offset: 0x0000 */ 889 __IO uint32_t RXCR; /* Address Offset: 0x0004 */ 890 __IO uint32_t CKR; /* Address Offset: 0x0008 */ 891 __IO uint32_t TXFIFOLR; /* Address Offset: 0x000C */ 892 __IO uint32_t DMACR; /* Address Offset: 0x0010 */ 893 __IO uint32_t INTCR; /* Address Offset: 0x0014 */ 894 __IO uint32_t INTSR; /* Address Offset: 0x0018 */ 895 __IO uint32_t XFER; /* Address Offset: 0x001C */ 896 __IO uint32_t CLR; /* Address Offset: 0x0020 */ 897 __IO uint32_t TXDR; /* Address Offset: 0x0024 */ 898 __IO uint32_t RXDR; /* Address Offset: 0x0028 */ 899 __IO uint32_t RXFIFOLR; /* Address Offset: 0x002C */ 900 __IO uint32_t TDM_TXCTRL; /* Address Offset: 0x0030 */ 901 __IO uint32_t TDM_RXCTRL; /* Address Offset: 0x0034 */ 902 __IO uint32_t CLKDIV; /* Address Offset: 0x0038 */ 903 __IO uint32_t VERSION; /* Address Offset: 0x003C */ 904 }; 905 /* PDM Register Structure Define */ 906 struct PDM_REG { 907 __IO uint32_t SYSCONFIG; /* Address Offset: 0x0000 */ 908 __IO uint32_t CTRL[2]; /* Address Offset: 0x0004 */ 909 __IO uint32_t CLK_CTRL; /* Address Offset: 0x000C */ 910 __IO uint32_t HPF_CTRL; /* Address Offset: 0x0010 */ 911 __IO uint32_t FIFO_CTRL; /* Address Offset: 0x0014 */ 912 __IO uint32_t DMA_CTRL; /* Address Offset: 0x0018 */ 913 __IO uint32_t INT_EN; /* Address Offset: 0x001C */ 914 __O uint32_t INT_CLR; /* Address Offset: 0x0020 */ 915 __I uint32_t INT_ST; /* Address Offset: 0x0024 */ 916 uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */ 917 __I uint32_t RXFIFO_DATA_REG; /* Address Offset: 0x0030 */ 918 __I uint32_t DATA0R_REG; /* Address Offset: 0x0034 */ 919 __I uint32_t DATA0L_REG; /* Address Offset: 0x0038 */ 920 uint32_t RESERVED003C[6]; /* Address Offset: 0x003C */ 921 __I uint32_t DATA_VALID; /* Address Offset: 0x0054 */ 922 __IO uint32_t VERSION; /* Address Offset: 0x0058 */ 923 uint32_t RESERVED005C[233]; /* Address Offset: 0x005C */ 924 __IO uint32_t INCR_RXDR; /* Address Offset: 0x0400 */ 925 }; 926 /* VAD Register Structure Define */ 927 struct VAD_REG { 928 __IO uint32_t CONTROL; /* Address Offset: 0x0000 */ 929 __IO uint32_t VS_ADDR; /* Address Offset: 0x0004 */ 930 uint32_t RESERVED0008[17]; /* Address Offset: 0x0008 */ 931 __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ 932 __IO uint32_t RAM_START_ADDR; /* Address Offset: 0x0050 */ 933 __IO uint32_t RAM_END_ADDR; /* Address Offset: 0x0054 */ 934 __IO uint32_t RAM_CUR_ADDR; /* Address Offset: 0x0058 */ 935 __IO uint32_t DET_CON[6]; /* Address Offset: 0x005C */ 936 __IO uint32_t INT; /* Address Offset: 0x0074 */ 937 __IO uint32_t AUX_CON0; /* Address Offset: 0x0078 */ 938 __I uint32_t SAMPLE_CNT; /* Address Offset: 0x007C */ 939 __IO uint32_t RAM_START_ADDR_BUS; /* Address Offset: 0x0080 */ 940 __IO uint32_t RAM_END_ADDR_BUS; /* Address Offset: 0x0084 */ 941 __IO uint32_t RAM_CUR_ADDR_BUS; /* Address Offset: 0x0088 */ 942 __IO uint32_t AUX_CON1; /* Address Offset: 0x008C */ 943 uint32_t RESERVED0090[28]; /* Address Offset: 0x0090 */ 944 __IO uint32_t NOISE_FIRST_DATA; /* Address Offset: 0x0100 */ 945 uint32_t RESERVED0104[126]; /* Address Offset: 0x0104 */ 946 __IO uint32_t NOISE_LAST_DATA; /* Address Offset: 0x02FC */ 947 }; 948 /* LPW_SYSBUS Register Structure Define */ 949 struct LPW_SYSBUS_REG { 950 __IO uint32_t MIPS_MCU_CONTROL; /* Address Offset: 0x0000 */ 951 uint32_t RESERVED0004[11]; /* Address Offset: 0x0004 */ 952 __IO uint32_t MIPS_MCU_SYS_CORE_MEM_CTRL; /* Address Offset: 0x0030 */ 953 __IO uint32_t MIPS_MCU_SYS_CORE_MEM_WDATA; /* Address Offset: 0x0034 */ 954 __IO uint32_t MIPS_MCU_SYS_CORE_MEM_RDATA; /* Address Offset: 0x0038 */ 955 uint32_t RESERVED003C[5]; /* Address Offset: 0x003C */ 956 __IO uint32_t MIPS_MCU_BOOT_EXCP_INSTR_0; /* Address Offset: 0x0050 */ 957 __IO uint32_t MIPS_MCU_BOOT_EXCP_INSTR_1; /* Address Offset: 0x0054 */ 958 __IO uint32_t MIPS_MCU_BOOT_EXCP_INSTR_2; /* Address Offset: 0x0058 */ 959 __IO uint32_t MIPS_MCU_BOOT_EXCP_INSTR_3; /* Address Offset: 0x005C */ 960 uint32_t RESERVED0060[244]; /* Address Offset: 0x0060 */ 961 __IO uint32_t UCCP_CORE_HOST_TO_MTX_CMD; /* Address Offset: 0x0430 */ 962 __IO uint32_t UCCP_CORE_MTX_TO_HOST_CMD; /* Address Offset: 0x0434 */ 963 __IO uint32_t UCCP_CORE_HOST_TO_MTX_ACK; /* Address Offset: 0x0438 */ 964 __IO uint32_t UCCP_CORE_MTX_TO_HOST_ACK; /* Address Offset: 0x043C */ 965 __IO uint32_t UCCP_CORE_HOST_INT_ENABLE; /* Address Offset: 0x0440 */ 966 __IO uint32_t UCCP_CORE_MTX_INT_ENABLE; /* Address Offset: 0x0444 */ 967 uint32_t RESERVED0448[209]; /* Address Offset: 0x0448 */ 968 __IO uint32_t UCCP_SOC_FAB_STATUS; /* Address Offset: 0x078C */ 969 uint32_t RESERVED0790[2343]; /* Address Offset: 0x0790 */ 970 __IO uint32_t UCC_SLEEP_CTRL_DATA_0; /* Address Offset: 0x2C2C */ 971 uint32_t RESERVED2C30[105]; /* Address Offset: 0x2C30 */ 972 __IO uint32_t UCC_SLEEP_CTRL_MCU_BOOT_ADDR_MS; /* Address Offset: 0x2DD4 */ 973 __IO uint32_t UCC_SLEEP_CTRL_MCU_BOOT_ADDR_LS; /* Address Offset: 0x2DD8 */ 974 }; 975 /* LPW_PBUS Register Structure Define */ 976 struct LPW_PBUS_REG { 977 uint32_t RESERVED0000[3840]; /* Address Offset: 0x0000 */ 978 __IO uint32_t EDC_GPIO0_OUT; /* Address Offset: 0x3C00 */ 979 __IO uint32_t EDC_GPIO1_OUT; /* Address Offset: 0x3C04 */ 980 __IO uint32_t EDC_GPIO0_IN; /* Address Offset: 0x3C08 */ 981 __IO uint32_t EDC_GPIO1_IN; /* Address Offset: 0x3C0C */ 982 uint32_t RESERVED3C10[5124]; /* Address Offset: 0x3C10 */ 983 __IO uint32_t RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1; /* Address Offset: 0x8C20 */ 984 }; 985 /* VICAP Register Structure Define */ 986 struct VICAP_REG { 987 __IO uint32_t DVP_CTRL; /* Address Offset: 0x0000 */ 988 __IO uint32_t DVP_INTEN; /* Address Offset: 0x0004 */ 989 __IO uint32_t DVP_INTSTAT; /* Address Offset: 0x0008 */ 990 __IO uint32_t DVP_FOR; /* Address Offset: 0x000C */ 991 __IO uint32_t DVP_DMA_IDLE_REQ; /* Address Offset: 0x0010 */ 992 __IO uint32_t DVP_FRM0_ADDR_Y; /* Address Offset: 0x0014 */ 993 __IO uint32_t DVP_FRM0_ADDR_UV; /* Address Offset: 0x0018 */ 994 __IO uint32_t DVP_FRM1_ADDR_Y; /* Address Offset: 0x001C */ 995 __IO uint32_t DVP_FRM1_ADDR_UV; /* Address Offset: 0x0020 */ 996 __IO uint32_t DVP_VIR_LINE_WIDTH; /* Address Offset: 0x0024 */ 997 __IO uint32_t DVP_SET_SIZE; /* Address Offset: 0x0028 */ 998 __IO uint32_t DVP_BLOCK_LINE_NUM; /* Address Offset: 0x002C */ 999 __IO uint32_t DVP_BLOCK0_ADDR_Y; /* Address Offset: 0x0030 */ 1000 __IO uint32_t DVP_BLOCK0_ADDR_UV; /* Address Offset: 0x0034 */ 1001 __IO uint32_t DVP_BLOCK1_ADDR_Y; /* Address Offset: 0x0038 */ 1002 __IO uint32_t DVP_BLOCK1_ADDR_UV; /* Address Offset: 0x003C */ 1003 __IO uint32_t DVP_BLOCK_STATUS; /* Address Offset: 0x0040 */ 1004 __IO uint32_t DVP_CROP; /* Address Offset: 0x0044 */ 1005 __IO uint32_t DVP_PATH_SEL; /* Address Offset: 0x0048 */ 1006 __IO uint32_t DVP_LINE_INT_NUM; /* Address Offset: 0x004C */ 1007 __IO uint32_t DVP_WATER_LINE; /* Address Offset: 0x0050 */ 1008 __IO uint32_t DVP_FIFO_ENTRY; /* Address Offset: 0x0054 */ 1009 uint32_t RESERVED0058[2]; /* Address Offset: 0x0058 */ 1010 __I uint32_t DVP_FRAME_STATUS; /* Address Offset: 0x0060 */ 1011 __I uint32_t DVP_CUR_DST; /* Address Offset: 0x0064 */ 1012 __IO uint32_t DVP_LAST_LINE; /* Address Offset: 0x0068 */ 1013 __IO uint32_t DVP_LAST_PIX; /* Address Offset: 0x006C */ 1014 }; 1015 /* MMC Register Structure Define */ 1016 struct MMC_REG { 1017 __IO uint32_t CTRL; /* Address Offset: 0x0000 */ 1018 __IO uint32_t PWREN; /* Address Offset: 0x0004 */ 1019 __IO uint32_t CLKDIV; /* Address Offset: 0x0008 */ 1020 __IO uint32_t CLKSRC; /* Address Offset: 0x000C */ 1021 __IO uint32_t CLKENA; /* Address Offset: 0x0010 */ 1022 __IO uint32_t TMOUT; /* Address Offset: 0x0014 */ 1023 __IO uint32_t CTYPE; /* Address Offset: 0x0018 */ 1024 __IO uint32_t BLKSIZ; /* Address Offset: 0x001C */ 1025 __IO uint32_t BYTCNT; /* Address Offset: 0x0020 */ 1026 __IO uint32_t INTMASK; /* Address Offset: 0x0024 */ 1027 __IO uint32_t CMDARG; /* Address Offset: 0x0028 */ 1028 __IO uint32_t CMD; /* Address Offset: 0x002C */ 1029 __I uint32_t RESP[4]; /* Address Offset: 0x0030 */ 1030 __IO uint32_t MINTSTS; /* Address Offset: 0x0040 */ 1031 __IO uint32_t RINTSTS; /* Address Offset: 0x0044 */ 1032 __I uint32_t STATUS; /* Address Offset: 0x0048 */ 1033 __IO uint32_t FIFOTH; /* Address Offset: 0x004C */ 1034 __I uint32_t CDETECT; /* Address Offset: 0x0050 */ 1035 __IO uint32_t WRTPRT; /* Address Offset: 0x0054 */ 1036 uint32_t RESERVED0058; /* Address Offset: 0x0058 */ 1037 __I uint32_t TCBCNT; /* Address Offset: 0x005C */ 1038 __I uint32_t TBBCNT; /* Address Offset: 0x0060 */ 1039 __IO uint32_t DEBNCE; /* Address Offset: 0x0064 */ 1040 __IO uint32_t USRID; /* Address Offset: 0x0068 */ 1041 __I uint32_t VERID; /* Address Offset: 0x006C */ 1042 __I uint32_t HCON; /* Address Offset: 0x0070 */ 1043 __IO uint32_t UHSREG; /* Address Offset: 0x0074 */ 1044 __IO uint32_t RSTN; /* Address Offset: 0x0078 */ 1045 uint32_t RESERVED007C; /* Address Offset: 0x007C */ 1046 __IO uint32_t BMOD; /* Address Offset: 0x0080 */ 1047 __O uint32_t PLDMND; /* Address Offset: 0x0084 */ 1048 __IO uint32_t DBADDR; /* Address Offset: 0x0088 */ 1049 __IO uint32_t IDSTS; /* Address Offset: 0x008C */ 1050 __IO uint32_t IDINTEN; /* Address Offset: 0x0090 */ 1051 __IO uint32_t DSCADDR; /* Address Offset: 0x0094 */ 1052 __IO uint32_t BUFADDR; /* Address Offset: 0x0098 */ 1053 uint32_t RESERVED009C[25]; /* Address Offset: 0x009C */ 1054 __IO uint32_t CARDTHRCTL; /* Address Offset: 0x0100 */ 1055 __IO uint32_t BACKEND_POWER; /* Address Offset: 0x0104 */ 1056 uint32_t RESERVED0108; /* Address Offset: 0x0108 */ 1057 __IO uint32_t EMMCDDR_REG; /* Address Offset: 0x010C */ 1058 uint32_t RESERVED0110[4]; /* Address Offset: 0x0110 */ 1059 __IO uint32_t RDYINT_GEN; /* Address Offset: 0x0120 */ 1060 uint32_t RESERVED0124[55]; /* Address Offset: 0x0124 */ 1061 __IO uint32_t FIFO_BASE; /* Address Offset: 0x0200 */ 1062 }; 1063 /* CRYPTO Register Structure Define */ 1064 struct CRYPTO_REG { 1065 __IO uint32_t CLK_CTL; /* Address Offset: 0x0000 */ 1066 __IO uint32_t RST_CTL; /* Address Offset: 0x0004 */ 1067 __IO uint32_t DMA_INT_EN; /* Address Offset: 0x0008 */ 1068 __O uint32_t DMA_INT_ST; /* Address Offset: 0x000C */ 1069 __IO uint32_t DMA_CTL; /* Address Offset: 0x0010 */ 1070 __IO uint32_t DMA_LLI_ADDR; /* Address Offset: 0x0014 */ 1071 __I uint32_t DMA_ST; /* Address Offset: 0x0018 */ 1072 __I uint32_t DMA_STATE; /* Address Offset: 0x001C */ 1073 __I uint32_t DMA_LLI_RADDR; /* Address Offset: 0x0020 */ 1074 __I uint32_t DMA_SRC_RADDR; /* Address Offset: 0x0024 */ 1075 __I uint32_t DMA_DST_WADDR; /* Address Offset: 0x0028 */ 1076 __I uint32_t DMA_ITEM_ID; /* Address Offset: 0x002C */ 1077 uint32_t RESERVED0030[4]; /* Address Offset: 0x0030 */ 1078 __IO uint32_t FIFO_CTL; /* Address Offset: 0x0040 */ 1079 __IO uint32_t BC_CTL; /* Address Offset: 0x0044 */ 1080 __IO uint32_t HASH_CTL; /* Address Offset: 0x0048 */ 1081 __I uint32_t CIPHER_ST; /* Address Offset: 0x004C */ 1082 __I uint32_t CIPHER_STATE; /* Address Offset: 0x0050 */ 1083 uint32_t RESERVED0054[43]; /* Address Offset: 0x0054 */ 1084 __IO uint32_t CHN_IV[8][4]; /* Address Offset: 0x0100 */ 1085 __IO uint32_t CHN_KEY[8][4]; /* Address Offset: 0x0180 */ 1086 __IO uint32_t CHN_PKEY[8][4]; /* Address Offset: 0x0200 */ 1087 __IO uint32_t CHN_PC_LEN[8][2]; /* Address Offset: 0x0280 */ 1088 __IO uint32_t CHN_AAD_LEN[8][2]; /* Address Offset: 0x02C0 */ 1089 __IO uint32_t CHN_IV_LEN[8][1]; /* Address Offset: 0x0300 */ 1090 __I uint32_t CHN_TAG[8][4]; /* Address Offset: 0x0320 */ 1091 __I uint32_t HASH_DOUT[16]; /* Address Offset: 0x03A0 */ 1092 __O uint32_t TAG_VALID; /* Address Offset: 0x03E0 */ 1093 __O uint32_t HASH_VALID; /* Address Offset: 0x03E4 */ 1094 uint32_t RESERVED03E8[2]; /* Address Offset: 0x03E8 */ 1095 __IO uint32_t VERSION; /* Address Offset: 0x03F0 */ 1096 uint32_t RESERVED03F4[3]; /* Address Offset: 0x03F4 */ 1097 __IO uint32_t RNG_CTL; /* Address Offset: 0x0400 */ 1098 __IO uint32_t RNG_SAMPLE_CNT; /* Address Offset: 0x0404 */ 1099 uint32_t RESERVED0408[2]; /* Address Offset: 0x0408 */ 1100 __IO uint32_t RNG_DOUT[8]; /* Address Offset: 0x0410 */ 1101 uint32_t RESERVED0430[20]; /* Address Offset: 0x0430 */ 1102 __IO uint32_t RAM_CTL; /* Address Offset: 0x0480 */ 1103 __I uint32_t RAM_ST; /* Address Offset: 0x0484 */ 1104 uint32_t RESERVED0488[6]; /* Address Offset: 0x0488 */ 1105 __IO uint32_t DEBUG_CTL; /* Address Offset: 0x04A0 */ 1106 __I uint32_t DEBUG_ST; /* Address Offset: 0x04A4 */ 1107 __IO uint32_t DEBUG_MONITOR; /* Address Offset: 0x04A8 */ 1108 uint32_t RESERVED04AC[213]; /* Address Offset: 0x04AC */ 1109 __IO uint32_t PKA_MEM_MAP[32]; /* Address Offset: 0x0800 */ 1110 __O uint32_t PKA_OPCODE; /* Address Offset: 0x0880 */ 1111 __IO uint32_t N_NP_T0_T1_ADDR; /* Address Offset: 0x0884 */ 1112 __I uint32_t PKA_STATUS; /* Address Offset: 0x0888 */ 1113 __O uint32_t PKA_SW_RESET; /* Address Offset: 0x088C */ 1114 __IO uint32_t PKA_L[8]; /* Address Offset: 0x0890 */ 1115 __I uint32_t PKA_PIPE_RDY; /* Address Offset: 0x08B0 */ 1116 __I uint32_t PKA_DONE; /* Address Offset: 0x08B4 */ 1117 __IO uint32_t PKA_MON_SELECT; /* Address Offset: 0x08B8 */ 1118 __IO uint32_t PKA_DEBUG_REG_EN; /* Address Offset: 0x08BC */ 1119 __IO uint32_t DEBUG_CNT_ADDR; /* Address Offset: 0x08C0 */ 1120 __O uint32_t DEBUG_EXT_ADDR; /* Address Offset: 0x08C4 */ 1121 __I uint32_t PKA_DEBUG_HALT; /* Address Offset: 0x08C8 */ 1122 uint32_t RESERVED08CC; /* Address Offset: 0x08CC */ 1123 __I uint32_t PKA_MON_READ; /* Address Offset: 0x08D0 */ 1124 __IO uint32_t PKA_INT_ENA; /* Address Offset: 0x08D4 */ 1125 __O uint32_t PKA_INT_ST; /* Address Offset: 0x08D8 */ 1126 uint32_t RESERVED08DC[457]; /* Address Offset: 0x08DC */ 1127 __IO uint32_t SRAM_ADDR; /* Address Offset: 0x1000 */ 1128 }; 1129 /* SPI2APB Register Structure Define */ 1130 struct SPI2APB_REG { 1131 __IO uint32_t CTRL0; /* Address Offset: 0x0000 */ 1132 uint32_t RESERVED0004[8]; /* Address Offset: 0x0004 */ 1133 __I uint32_t SR; /* Address Offset: 0x0024 */ 1134 uint32_t RESERVED0028; /* Address Offset: 0x0028 */ 1135 __IO uint32_t IMR; /* Address Offset: 0x002C */ 1136 uint32_t RESERVED0030; /* Address Offset: 0x0030 */ 1137 __IO uint32_t RISR; /* Address Offset: 0x0034 */ 1138 __O uint32_t ICR; /* Address Offset: 0x0038 */ 1139 uint32_t RESERVED003C[3]; /* Address Offset: 0x003C */ 1140 __IO uint32_t VERSION; /* Address Offset: 0x0048 */ 1141 uint32_t RESERVED004C; /* Address Offset: 0x004C */ 1142 __IO uint32_t QUICK_REG[3]; /* Address Offset: 0x0050 */ 1143 }; 1144 #endif /* __ASSEMBLY__ */ 1145 /****************************************************************************************/ 1146 /* */ 1147 /* Module Address Section */ 1148 /* */ 1149 /****************************************************************************************/ 1150 /* Memory Base */ 1151 #define TIMER0_BASE 0x40000000U /* TIMER0 base address */ 1152 #define TIMER1_BASE 0x40000020U /* TIMER1 base address */ 1153 #define TIMER2_BASE 0x40000040U /* TIMER2 base address */ 1154 #define TIMER3_BASE 0x40000060U /* TIMER3 base address */ 1155 #define TIMER4_BASE 0x40000080U /* TIMER4 base address */ 1156 #define TIMER5_BASE 0x400000A0U /* TIMER5 base address */ 1157 #define WDT0_BASE 0x40010000U /* WDT0 base address */ 1158 #define WDT1_BASE 0x40020000U /* WDT1 base address */ 1159 #define WDT2_BASE 0x40030000U /* WDT2 base address */ 1160 #define I2C0_BASE 0x40040000U /* I2C0 base address */ 1161 #define I2C1_BASE 0x40050000U /* I2C1 base address */ 1162 #define I2C2_BASE 0x40060000U /* I2C2 base address */ 1163 #define UART0_BASE 0x40070000U /* UART0 base address */ 1164 #define UART1_BASE 0x40080000U /* UART1 base address */ 1165 #define UART2_BASE 0x40090000U /* UART2 base address */ 1166 #define PWM0_BASE 0x400A0000U /* PWM0 base address */ 1167 #define PWM1_BASE 0x400B0000U /* PWM1 base address */ 1168 #define PWM2_BASE 0x400C0000U /* PWM2 base address */ 1169 #define SPI0_BASE 0x400D0000U /* SPI0 base address */ 1170 #define SPI1_BASE 0x400E0000U /* SPI1 base address */ 1171 #define EFUSE_CTL0_BASE 0x400F0000U /* EFUSE_CTL0 base address */ 1172 #define MBOX0_BASE 0x40100000U /* MBOX0 base address */ 1173 #define MBOX1_BASE 0x40110000U /* MBOX1 base address */ 1174 #define SARADC_BASE 0x40120000U /* SARADC base address */ 1175 #define INTC_BASE 0x40130000U /* INTC base address */ 1176 #define DMA_BASE 0x40200000U /* DMA base address */ 1177 #define FSPI0_BASE 0x40210000U /* FSPI0 base address */ 1178 #define FSPI1_BASE 0x40220000U /* FSPI1 base address */ 1179 #define ICACHE_BASE 0x40230000U /* ICACHE base address */ 1180 #define DCACHE_BASE 0x40234000U /* DCACHE base address */ 1181 #define VOP_BASE 0x40250000U /* VOP base address */ 1182 #define AUDIOPWM_BASE 0x40260000U /* AUDIOPWM base address */ 1183 #define HYPERBUS_BASE 0x40300000U /* HYPERBUS base address */ 1184 #define PMU_BASE 0x41000000U /* PMU base address */ 1185 #define GPIO0_BASE 0x41010000U /* GPIO0 base address */ 1186 #define GPIO1_BASE 0x41020000U /* GPIO1 base address */ 1187 #define TIMER6_BASE 0x41030000U /* TIMER6 base address */ 1188 #define ACDCDIG_BASE 0x41040000U /* ACDCDIG base address */ 1189 #define GRF_BASE 0x41050000U /* GRF base address */ 1190 #define CRU_BASE 0x41060000U /* CRU base address */ 1191 #define PVTM_BASE 0x41080000U /* PVTM base address */ 1192 #define TOUCH_SENSOR_BASE 0x41090000U /* TOUCH_SENSOR base address */ 1193 #define TSADC_BASE 0x410A0000U /* TSADC base address */ 1194 #define I2STDM0_BASE 0x41100000U /* I2STDM0 base address */ 1195 #define I2STDM1_BASE 0x41110000U /* I2STDM1 base address */ 1196 #define PDM0_BASE 0x41120000U /* PDM0 base address */ 1197 #define VAD_BASE 0x41130000U /* VAD base address */ 1198 #define LPW_SYSBUS_BASE 0x42000000U /* LPW_SYSBUS base address */ 1199 #define LPW_PBUS_BASE 0x42040000U /* LPW_PBUS base address */ 1200 #define VICAP_BASE 0x43000000U /* VICAP base address */ 1201 #define MMC_BASE 0x43010000U /* MMC base address */ 1202 #define CRYPTO_BASE 0x43020000U /* CRYPTO base address */ 1203 #define SPI2APB_BASE 0x43080000U /* SPI2APB base address */ 1204 /****************************************************************************************/ 1205 /* */ 1206 /* Module Variable Section */ 1207 /* */ 1208 /****************************************************************************************/ 1209 /* Module Variable Define */ 1210 1211 #define TIMER0 ((struct TIMER_REG *) TIMER0_BASE) 1212 #define TIMER1 ((struct TIMER_REG *) TIMER1_BASE) 1213 #define TIMER2 ((struct TIMER_REG *) TIMER2_BASE) 1214 #define TIMER3 ((struct TIMER_REG *) TIMER3_BASE) 1215 #define TIMER4 ((struct TIMER_REG *) TIMER4_BASE) 1216 #define TIMER5 ((struct TIMER_REG *) TIMER5_BASE) 1217 #define WDT0 ((struct WDT_REG *) WDT0_BASE) 1218 #define WDT1 ((struct WDT_REG *) WDT1_BASE) 1219 #define WDT2 ((struct WDT_REG *) WDT2_BASE) 1220 #define I2C0 ((struct I2C_REG *) I2C0_BASE) 1221 #define I2C1 ((struct I2C_REG *) I2C1_BASE) 1222 #define I2C2 ((struct I2C_REG *) I2C2_BASE) 1223 #define UART0 ((struct UART_REG *) UART0_BASE) 1224 #define UART1 ((struct UART_REG *) UART1_BASE) 1225 #define UART2 ((struct UART_REG *) UART2_BASE) 1226 #define PWM0 ((struct PWM_REG *) PWM0_BASE) 1227 #define PWM1 ((struct PWM_REG *) PWM1_BASE) 1228 #define PWM2 ((struct PWM_REG *) PWM2_BASE) 1229 #define SPI0 ((struct SPI_REG *) SPI0_BASE) 1230 #define SPI1 ((struct SPI_REG *) SPI1_BASE) 1231 #define EFUSE_CTL0 ((struct EFUSE_CTL_REG *) EFUSE_CTL0_BASE) 1232 #define MBOX0 ((struct MBOX_REG *) MBOX0_BASE) 1233 #define MBOX1 ((struct MBOX_REG *) MBOX1_BASE) 1234 #define SARADC ((struct SARADC_REG *) SARADC_BASE) 1235 #define INTC ((struct INTC_REG *) INTC_BASE) 1236 #define DMA ((struct DMA_REG *) DMA_BASE) 1237 #define FSPI0 ((struct FSPI_REG *) FSPI0_BASE) 1238 #define FSPI1 ((struct FSPI_REG *) FSPI1_BASE) 1239 #define ICACHE ((struct ICACHE_REG *) ICACHE_BASE) 1240 #define DCACHE ((struct DCACHE_REG *) DCACHE_BASE) 1241 #define VOP ((struct VOP_REG *) VOP_BASE) 1242 #define AUDIOPWM ((struct AUDIOPWM_REG *) AUDIOPWM_BASE) 1243 #define HYPERBUS ((struct HYPERBUS_REG *) HYPERBUS_BASE) 1244 #define PMU ((struct PMU_REG *) PMU_BASE) 1245 #define GPIO0 ((struct GPIO_REG *) GPIO0_BASE) 1246 #define GPIO1 ((struct GPIO_REG *) GPIO1_BASE) 1247 #define TIMER6 ((struct TIMER_REG *) TIMER6_BASE) 1248 #define ACDCDIG ((struct ACDCDIG_REG *) ACDCDIG_BASE) 1249 #define GRF ((struct GRF_REG *) GRF_BASE) 1250 #define CRU ((struct CRU_REG *) CRU_BASE) 1251 #define PVTM ((struct PVTM_REG *) PVTM_BASE) 1252 #define TOUCH_SENSOR ((struct TOUCH_SENSOR_REG *) TOUCH_SENSOR_BASE) 1253 #define TSADC ((struct TSADC_REG *) TSADC_BASE) 1254 #define I2STDM0 ((struct I2STDM_REG *) I2STDM0_BASE) 1255 #define I2STDM1 ((struct I2STDM_REG *) I2STDM1_BASE) 1256 #define PDM0 ((struct PDM_REG *) PDM0_BASE) 1257 #define VAD ((struct VAD_REG *) VAD_BASE) 1258 #define LPW_SYSBUS ((struct LPW_SYSBUS_REG *) LPW_SYSBUS_BASE) 1259 #define LPW_PBUS ((struct LPW_PBUS_REG *) LPW_PBUS_BASE) 1260 #define VICAP ((struct VICAP_REG *) VICAP_BASE) 1261 #define MMC ((struct MMC_REG *) MMC_BASE) 1262 #define CRYPTO ((struct CRYPTO_REG *) CRYPTO_BASE) 1263 #define SPI2APB ((struct SPI2APB_REG *) SPI2APB_BASE) 1264 1265 #define IS_SARADC_INSTANCE(instance) ((instance) == SARADC) 1266 #define IS_INTC_INSTANCE(instance) ((instance) == INTC) 1267 #define IS_DMA_INSTANCE(instance) ((instance) == DMA) 1268 #define IS_ICACHE_INSTANCE(instance) ((instance) == ICACHE) 1269 #define IS_DCACHE_INSTANCE(instance) ((instance) == DCACHE) 1270 #define IS_VOP_INSTANCE(instance) ((instance) == VOP) 1271 #define IS_AUDIOPWM_INSTANCE(instance) ((instance) == AUDIOPWM) 1272 #define IS_HYPERBUS_INSTANCE(instance) ((instance) == HYPERBUS) 1273 #define IS_PMU_INSTANCE(instance) ((instance) == PMU) 1274 #define IS_ACDCDIG_INSTANCE(instance) ((instance) == ACDCDIG) 1275 #define IS_GRF_INSTANCE(instance) ((instance) == GRF) 1276 #define IS_CRU_INSTANCE(instance) ((instance) == CRU) 1277 #define IS_PVTM_INSTANCE(instance) ((instance) == PVTM) 1278 #define IS_TOUCH_SENSOR_INSTANCE(instance) ((instance) == TOUCH_SENSOR) 1279 #define IS_TSADC_INSTANCE(instance) ((instance) == TSADC) 1280 #define IS_VAD_INSTANCE(instance) ((instance) == VAD) 1281 #define IS_LPW_SYSBUS_INSTANCE(instance) ((instance) == LPW_SYSBUS) 1282 #define IS_LPW_PBUS_INSTANCE(instance) ((instance) == LPW_PBUS) 1283 #define IS_VICAP_INSTANCE(instance) ((instance) == VICAP) 1284 #define IS_MMC_INSTANCE(instance) ((instance) == MMC) 1285 #define IS_CRYPTO_INSTANCE(instance) ((instance) == CRYPTO) 1286 #define IS_SPI2APB_INSTANCE(instance) ((instance) == SPI2APB) 1287 #define IS_TIMER_INSTANCE(instance) (((instance) == TIMER0) || ((instance) == TIMER1) \ 1288 || ((instance) == TIMER2) || ((instance) == TIMER3) || ((instance) == TIMER4) \ 1289 || ((instance) == TIMER5) || ((instance) == TIMER6)) 1290 #define IS_WDT_INSTANCE(instance) (((instance) == WDT0) || ((instance) == WDT1) || ((instance) == WDT2)) 1291 #define IS_I2C_INSTANCE(instance) (((instance) == I2C0) || ((instance) == I2C1) || ((instance) == I2C2)) 1292 #define IS_UART_INSTANCE(instance) (((instance) == UART0) || ((instance) == UART1) || ((instance) == UART2)) 1293 #define IS_PWM_INSTANCE(instance) (((instance) == PWM0) || ((instance) == PWM1) || ((instance) == PWM2)) 1294 #define IS_SPI_INSTANCE(instance) (((instance) == SPI0) || ((instance) == SPI1)) 1295 #define IS_EFUSE_CTL_INSTANCE(instance) ((instance) == EFUSE_CTL0) 1296 #define IS_MBOX_INSTANCE(instance) (((instance) == MBOX0) || ((instance) == MBOX1)) 1297 #define IS_FSPI_INSTANCE(instance) (((instance) == FSPI0) || ((instance) == FSPI1)) 1298 #define IS_GPIO_INSTANCE(instance) (((instance) == GPIO0) || ((instance) == GPIO1)) 1299 #define IS_I2STDM_INSTANCE(instance) (((instance) == I2STDM0) || ((instance) == I2STDM1)) 1300 #define IS_PDM_INSTANCE(instance) ((instance) == PDM0) 1301 /****************************************************************************************/ 1302 /* */ 1303 /* Register Bitmap Section */ 1304 /* */ 1305 /****************************************************************************************/ 1306 /*****************************************TIMER******************************************/ 1307 /* LOAD_COUNT0 */ 1308 #define TIMER_LOAD_COUNT0_OFFSET (0x0U) 1309 #define TIMER_LOAD_COUNT0_COUNT0_SHIFT (0U) 1310 #define TIMER_LOAD_COUNT0_COUNT0_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT0_COUNT0_SHIFT) 1311 /* LOAD_COUNT1 */ 1312 #define TIMER_LOAD_COUNT1_OFFSET (0x4U) 1313 #define TIMER_LOAD_COUNT1_COUNT1_SHIFT (0U) 1314 #define TIMER_LOAD_COUNT1_COUNT1_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT1_COUNT1_SHIFT) 1315 /* CURRENT_VALUE0 */ 1316 #define TIMER_CURRENT_VALUE0_OFFSET (0x8U) 1317 #define TIMER_CURRENT_VALUE0 (0x0U) 1318 #define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT (0U) 1319 #define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT) 1320 /* CURRENT_VALUE1 */ 1321 #define TIMER_CURRENT_VALUE1_OFFSET (0xCU) 1322 #define TIMER_CURRENT_VALUE1 (0x0U) 1323 #define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT (0U) 1324 #define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT) 1325 /* CONTROLREG */ 1326 #define TIMER_CONTROLREG_OFFSET (0x10U) 1327 #define TIMER_CONTROLREG_TIMER_ENABLE_SHIFT (0U) 1328 #define TIMER_CONTROLREG_TIMER_ENABLE_MASK (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) 1329 #define TIMER_CONTROLREG_TIMER_MODE_SHIFT (1U) 1330 #define TIMER_CONTROLREG_TIMER_MODE_MASK (0x1U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) 1331 #define TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT (2U) 1332 #define TIMER_CONTROLREG_TIMER_INT_MASK_MASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) 1333 /* INTSTATUS */ 1334 #define TIMER_INTSTATUS_OFFSET (0x18U) 1335 #define TIMER_INTSTATUS_INT_PD_SHIFT (0U) 1336 #define TIMER_INTSTATUS_INT_PD_MASK (0x1U << TIMER_INTSTATUS_INT_PD_SHIFT) 1337 /******************************************WDT*******************************************/ 1338 /* CR */ 1339 #define WDT_CR_OFFSET (0x0U) 1340 #define WDT_CR_WDT_EN_SHIFT (0U) 1341 #define WDT_CR_WDT_EN_MASK (0x1U << WDT_CR_WDT_EN_SHIFT) 1342 #define WDT_CR_RESP_MODE_SHIFT (1U) 1343 #define WDT_CR_RESP_MODE_MASK (0x1U << WDT_CR_RESP_MODE_SHIFT) 1344 #define WDT_CR_RST_PULSE_LENGTH_SHIFT (2U) 1345 #define WDT_CR_RST_PULSE_LENGTH_MASK (0x7U << WDT_CR_RST_PULSE_LENGTH_SHIFT) 1346 /* TORR */ 1347 #define WDT_TORR_OFFSET (0x4U) 1348 #define WDT_TORR_TIMEOUT_PERIOD_SHIFT (0U) 1349 #define WDT_TORR_TIMEOUT_PERIOD_MASK (0xFU << WDT_TORR_TIMEOUT_PERIOD_SHIFT) 1350 /* CCVR */ 1351 #define WDT_CCVR_OFFSET (0x8U) 1352 #define WDT_CCVR (0xFFFFU) 1353 #define WDT_CCVR_CUR_CNT_SHIFT (0U) 1354 #define WDT_CCVR_CUR_CNT_MASK (0xFFFFFFFFU << WDT_CCVR_CUR_CNT_SHIFT) 1355 /* CRR */ 1356 #define WDT_CRR_OFFSET (0xCU) 1357 #define WDT_CRR_CNT_RESTART_SHIFT (0U) 1358 #define WDT_CRR_CNT_RESTART_MASK (0xFFU << WDT_CRR_CNT_RESTART_SHIFT) 1359 /* STAT */ 1360 #define WDT_STAT_OFFSET (0x10U) 1361 #define WDT_STAT (0x0U) 1362 #define WDT_STAT_INT_STATUS_SHIFT (0U) 1363 #define WDT_STAT_INT_STATUS_MASK (0x1U << WDT_STAT_INT_STATUS_SHIFT) 1364 /* EOI */ 1365 #define WDT_EOI_OFFSET (0x14U) 1366 #define WDT_EOI (0x0U) 1367 #define WDT_EOI_INT_CLR_SHIFT (0U) 1368 #define WDT_EOI_INT_CLR_MASK (0x1U << WDT_EOI_INT_CLR_SHIFT) 1369 /******************************************I2C*******************************************/ 1370 /* CON */ 1371 #define I2C_CON_OFFSET (0x0U) 1372 #define I2C_CON_I2C_EN_SHIFT (0U) 1373 #define I2C_CON_I2C_EN_MASK (0x1U << I2C_CON_I2C_EN_SHIFT) 1374 #define I2C_CON_I2C_MODE_SHIFT (1U) 1375 #define I2C_CON_I2C_MODE_MASK (0x3U << I2C_CON_I2C_MODE_SHIFT) 1376 #define I2C_CON_START_SHIFT (3U) 1377 #define I2C_CON_START_MASK (0x1U << I2C_CON_START_SHIFT) 1378 #define I2C_CON_STOP_SHIFT (4U) 1379 #define I2C_CON_STOP_MASK (0x1U << I2C_CON_STOP_SHIFT) 1380 #define I2C_CON_ACK_SHIFT (5U) 1381 #define I2C_CON_ACK_MASK (0x1U << I2C_CON_ACK_SHIFT) 1382 #define I2C_CON_ACT2NAK_SHIFT (6U) 1383 #define I2C_CON_ACT2NAK_MASK (0x1U << I2C_CON_ACT2NAK_SHIFT) 1384 #define I2C_CON_DATA_UPD_ST_SHIFT (8U) 1385 #define I2C_CON_DATA_UPD_ST_MASK (0x7U << I2C_CON_DATA_UPD_ST_SHIFT) 1386 #define I2C_CON_START_SETUP_SHIFT (12U) 1387 #define I2C_CON_START_SETUP_MASK (0x3U << I2C_CON_START_SETUP_SHIFT) 1388 #define I2C_CON_STOP_SETUP_SHIFT (14U) 1389 #define I2C_CON_STOP_SETUP_MASK (0x3U << I2C_CON_STOP_SETUP_SHIFT) 1390 #define I2C_CON_VERSION_SHIFT (16U) 1391 #define I2C_CON_VERSION_MASK (0xFFFFU << I2C_CON_VERSION_SHIFT) 1392 /* CLKDIV */ 1393 #define I2C_CLKDIV_OFFSET (0x4U) 1394 #define I2C_CLKDIV_CLKDIVL_SHIFT (0U) 1395 #define I2C_CLKDIV_CLKDIVL_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVL_SHIFT) 1396 #define I2C_CLKDIV_CLKDIVH_SHIFT (16U) 1397 #define I2C_CLKDIV_CLKDIVH_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVH_SHIFT) 1398 /* MRXADDR */ 1399 #define I2C_MRXADDR_OFFSET (0x8U) 1400 #define I2C_MRXADDR_SADDR_SHIFT (0U) 1401 #define I2C_MRXADDR_SADDR_MASK (0xFFFFFFU << I2C_MRXADDR_SADDR_SHIFT) 1402 #define I2C_MRXADDR_ADDLVLD_SHIFT (24U) 1403 #define I2C_MRXADDR_ADDLVLD_MASK (0x1U << I2C_MRXADDR_ADDLVLD_SHIFT) 1404 #define I2C_MRXADDR_ADDMVLD_SHIFT (25U) 1405 #define I2C_MRXADDR_ADDMVLD_MASK (0x1U << I2C_MRXADDR_ADDMVLD_SHIFT) 1406 #define I2C_MRXADDR_ADDHVLD_SHIFT (26U) 1407 #define I2C_MRXADDR_ADDHVLD_MASK (0x1U << I2C_MRXADDR_ADDHVLD_SHIFT) 1408 /* MRXRADDR */ 1409 #define I2C_MRXRADDR_OFFSET (0xCU) 1410 #define I2C_MRXRADDR_SRADDR_SHIFT (0U) 1411 #define I2C_MRXRADDR_SRADDR_MASK (0xFFFFFFU << I2C_MRXRADDR_SRADDR_SHIFT) 1412 #define I2C_MRXRADDR_SRADDLVLD_SHIFT (24U) 1413 #define I2C_MRXRADDR_SRADDLVLD_MASK (0x1U << I2C_MRXRADDR_SRADDLVLD_SHIFT) 1414 #define I2C_MRXRADDR_SRADDMVLD_SHIFT (25U) 1415 #define I2C_MRXRADDR_SRADDMVLD_MASK (0x1U << I2C_MRXRADDR_SRADDMVLD_SHIFT) 1416 #define I2C_MRXRADDR_SRADDHVLD_SHIFT (26U) 1417 #define I2C_MRXRADDR_SRADDHVLD_MASK (0x1U << I2C_MRXRADDR_SRADDHVLD_SHIFT) 1418 /* MTXCNT */ 1419 #define I2C_MTXCNT_OFFSET (0x10U) 1420 #define I2C_MTXCNT_MTXCNT_SHIFT (0U) 1421 #define I2C_MTXCNT_MTXCNT_MASK (0x3FU << I2C_MTXCNT_MTXCNT_SHIFT) 1422 /* MRXCNT */ 1423 #define I2C_MRXCNT_OFFSET (0x14U) 1424 #define I2C_MRXCNT_MRXCNT_SHIFT (0U) 1425 #define I2C_MRXCNT_MRXCNT_MASK (0x3FU << I2C_MRXCNT_MRXCNT_SHIFT) 1426 /* IEN */ 1427 #define I2C_IEN_OFFSET (0x18U) 1428 #define I2C_IEN_BTFIEN_SHIFT (0U) 1429 #define I2C_IEN_BTFIEN_MASK (0x1U << I2C_IEN_BTFIEN_SHIFT) 1430 #define I2C_IEN_BRFIEN_SHIFT (1U) 1431 #define I2C_IEN_BRFIEN_MASK (0x1U << I2C_IEN_BRFIEN_SHIFT) 1432 #define I2C_IEN_MBTFIEN_SHIFT (2U) 1433 #define I2C_IEN_MBTFIEN_MASK (0x1U << I2C_IEN_MBTFIEN_SHIFT) 1434 #define I2C_IEN_MBRFIEN_SHIFT (3U) 1435 #define I2C_IEN_MBRFIEN_MASK (0x1U << I2C_IEN_MBRFIEN_SHIFT) 1436 #define I2C_IEN_STARTIEN_SHIFT (4U) 1437 #define I2C_IEN_STARTIEN_MASK (0x1U << I2C_IEN_STARTIEN_SHIFT) 1438 #define I2C_IEN_STOPIEN_SHIFT (5U) 1439 #define I2C_IEN_STOPIEN_MASK (0x1U << I2C_IEN_STOPIEN_SHIFT) 1440 #define I2C_IEN_NAKRCVIEN_SHIFT (6U) 1441 #define I2C_IEN_NAKRCVIEN_MASK (0x1U << I2C_IEN_NAKRCVIEN_SHIFT) 1442 #define I2C_IEN_SLAVEHDSCLEN_SHIFT (7U) 1443 #define I2C_IEN_SLAVEHDSCLEN_MASK (0x1U << I2C_IEN_SLAVEHDSCLEN_SHIFT) 1444 /* IPD */ 1445 #define I2C_IPD_OFFSET (0x1CU) 1446 #define I2C_IPD_BTFIPD_SHIFT (0U) 1447 #define I2C_IPD_BTFIPD_MASK (0x1U << I2C_IPD_BTFIPD_SHIFT) 1448 #define I2C_IPD_BRFIPD_SHIFT (1U) 1449 #define I2C_IPD_BRFIPD_MASK (0x1U << I2C_IPD_BRFIPD_SHIFT) 1450 #define I2C_IPD_MBTFIPD_SHIFT (2U) 1451 #define I2C_IPD_MBTFIPD_MASK (0x1U << I2C_IPD_MBTFIPD_SHIFT) 1452 #define I2C_IPD_MBRFIPD_SHIFT (3U) 1453 #define I2C_IPD_MBRFIPD_MASK (0x1U << I2C_IPD_MBRFIPD_SHIFT) 1454 #define I2C_IPD_STARTIPD_SHIFT (4U) 1455 #define I2C_IPD_STARTIPD_MASK (0x1U << I2C_IPD_STARTIPD_SHIFT) 1456 #define I2C_IPD_STOPIPD_SHIFT (5U) 1457 #define I2C_IPD_STOPIPD_MASK (0x1U << I2C_IPD_STOPIPD_SHIFT) 1458 #define I2C_IPD_NAKRCVIPD_SHIFT (6U) 1459 #define I2C_IPD_NAKRCVIPD_MASK (0x1U << I2C_IPD_NAKRCVIPD_SHIFT) 1460 #define I2C_IPD_SLAVEHDSCLIPD_SHIFT (7U) 1461 #define I2C_IPD_SLAVEHDSCLIPD_MASK (0x1U << I2C_IPD_SLAVEHDSCLIPD_SHIFT) 1462 /* FCNT */ 1463 #define I2C_FCNT_OFFSET (0x20U) 1464 #define I2C_FCNT (0x0U) 1465 #define I2C_FCNT_FCNT_SHIFT (0U) 1466 #define I2C_FCNT_FCNT_MASK (0x3FU << I2C_FCNT_FCNT_SHIFT) 1467 /* SCL_OE_DB */ 1468 #define I2C_SCL_OE_DB_OFFSET (0x24U) 1469 #define I2C_SCL_OE_DB_SCL_OE_DB_SHIFT (0U) 1470 #define I2C_SCL_OE_DB_SCL_OE_DB_MASK (0xFFU << I2C_SCL_OE_DB_SCL_OE_DB_SHIFT) 1471 /* TXDATA0 */ 1472 #define I2C_TXDATA0_OFFSET (0x100U) 1473 #define I2C_TXDATA0_TXDATA0_SHIFT (0U) 1474 #define I2C_TXDATA0_TXDATA0_MASK (0xFFFFFFFFU << I2C_TXDATA0_TXDATA0_SHIFT) 1475 /* TXDATA1 */ 1476 #define I2C_TXDATA1_OFFSET (0x104U) 1477 #define I2C_TXDATA1_TXDATA1_SHIFT (0U) 1478 #define I2C_TXDATA1_TXDATA1_MASK (0xFFFFFFFFU << I2C_TXDATA1_TXDATA1_SHIFT) 1479 /* TXDATA2 */ 1480 #define I2C_TXDATA2_OFFSET (0x108U) 1481 #define I2C_TXDATA2_TXDATA2_SHIFT (0U) 1482 #define I2C_TXDATA2_TXDATA2_MASK (0xFFFFFFFFU << I2C_TXDATA2_TXDATA2_SHIFT) 1483 /* TXDATA3 */ 1484 #define I2C_TXDATA3_OFFSET (0x10CU) 1485 #define I2C_TXDATA3_TXDATA3_SHIFT (0U) 1486 #define I2C_TXDATA3_TXDATA3_MASK (0xFFFFFFFFU << I2C_TXDATA3_TXDATA3_SHIFT) 1487 /* TXDATA4 */ 1488 #define I2C_TXDATA4_OFFSET (0x110U) 1489 #define I2C_TXDATA4_TXDATA4_SHIFT (0U) 1490 #define I2C_TXDATA4_TXDATA4_MASK (0xFFFFFFFFU << I2C_TXDATA4_TXDATA4_SHIFT) 1491 /* TXDATA5 */ 1492 #define I2C_TXDATA5_OFFSET (0x114U) 1493 #define I2C_TXDATA5_TXDATA5_SHIFT (0U) 1494 #define I2C_TXDATA5_TXDATA5_MASK (0xFFFFFFFFU << I2C_TXDATA5_TXDATA5_SHIFT) 1495 /* TXDATA6 */ 1496 #define I2C_TXDATA6_OFFSET (0x118U) 1497 #define I2C_TXDATA6_TXDATA6_SHIFT (0U) 1498 #define I2C_TXDATA6_TXDATA6_MASK (0xFFFFFFFFU << I2C_TXDATA6_TXDATA6_SHIFT) 1499 /* TXDATA7 */ 1500 #define I2C_TXDATA7_OFFSET (0x11CU) 1501 #define I2C_TXDATA7_TXDATA7_SHIFT (0U) 1502 #define I2C_TXDATA7_TXDATA7_MASK (0xFFFFFFFFU << I2C_TXDATA7_TXDATA7_SHIFT) 1503 /* RXDATA0 */ 1504 #define I2C_RXDATA0_OFFSET (0x200U) 1505 #define I2C_RXDATA0 (0x0U) 1506 #define I2C_RXDATA0_RXDATA0_SHIFT (0U) 1507 #define I2C_RXDATA0_RXDATA0_MASK (0xFFFFFFFFU << I2C_RXDATA0_RXDATA0_SHIFT) 1508 /* RXDATA1 */ 1509 #define I2C_RXDATA1_OFFSET (0x204U) 1510 #define I2C_RXDATA1 (0x0U) 1511 #define I2C_RXDATA1_RXDATA1_SHIFT (0U) 1512 #define I2C_RXDATA1_RXDATA1_MASK (0xFFFFFFFFU << I2C_RXDATA1_RXDATA1_SHIFT) 1513 /* RXDATA2 */ 1514 #define I2C_RXDATA2_OFFSET (0x208U) 1515 #define I2C_RXDATA2 (0x0U) 1516 #define I2C_RXDATA2_RXDATA2_SHIFT (0U) 1517 #define I2C_RXDATA2_RXDATA2_MASK (0xFFFFFFFFU << I2C_RXDATA2_RXDATA2_SHIFT) 1518 /* RXDATA3 */ 1519 #define I2C_RXDATA3_OFFSET (0x20CU) 1520 #define I2C_RXDATA3 (0x0U) 1521 #define I2C_RXDATA3_RXDATA3_SHIFT (0U) 1522 #define I2C_RXDATA3_RXDATA3_MASK (0xFFFFFFFFU << I2C_RXDATA3_RXDATA3_SHIFT) 1523 /* RXDATA4 */ 1524 #define I2C_RXDATA4_OFFSET (0x210U) 1525 #define I2C_RXDATA4 (0x0U) 1526 #define I2C_RXDATA4_RXDATA4_SHIFT (0U) 1527 #define I2C_RXDATA4_RXDATA4_MASK (0xFFFFFFFFU << I2C_RXDATA4_RXDATA4_SHIFT) 1528 /* RXDATA5 */ 1529 #define I2C_RXDATA5_OFFSET (0x214U) 1530 #define I2C_RXDATA5 (0x0U) 1531 #define I2C_RXDATA5_RXDATA5_SHIFT (0U) 1532 #define I2C_RXDATA5_RXDATA5_MASK (0xFFFFFFFFU << I2C_RXDATA5_RXDATA5_SHIFT) 1533 /* RXDATA6 */ 1534 #define I2C_RXDATA6_OFFSET (0x218U) 1535 #define I2C_RXDATA6 (0x0U) 1536 #define I2C_RXDATA6_RXDATA6_SHIFT (0U) 1537 #define I2C_RXDATA6_RXDATA6_MASK (0xFFFFFFFFU << I2C_RXDATA6_RXDATA6_SHIFT) 1538 /* RXDATA7 */ 1539 #define I2C_RXDATA7_OFFSET (0x21CU) 1540 #define I2C_RXDATA7 (0x0U) 1541 #define I2C_RXDATA7_RXDATA7_SHIFT (0U) 1542 #define I2C_RXDATA7_RXDATA7_MASK (0xFFFFFFFFU << I2C_RXDATA7_RXDATA7_SHIFT) 1543 /* ST */ 1544 #define I2C_ST_OFFSET (0x220U) 1545 #define I2C_ST (0x0U) 1546 #define I2C_ST_SDA_ST_SHIFT (0U) 1547 #define I2C_ST_SDA_ST_MASK (0x1U << I2C_ST_SDA_ST_SHIFT) 1548 #define I2C_ST_SCL_ST_SHIFT (1U) 1549 #define I2C_ST_SCL_ST_MASK (0x1U << I2C_ST_SCL_ST_SHIFT) 1550 /* DBGCTRL */ 1551 #define I2C_DBGCTRL_OFFSET (0x224U) 1552 #define I2C_DBGCTRL_FLT_F_SHIFT (0U) 1553 #define I2C_DBGCTRL_FLT_F_MASK (0xFU << I2C_DBGCTRL_FLT_F_SHIFT) 1554 #define I2C_DBGCTRL_FLT_R_SHIFT (4U) 1555 #define I2C_DBGCTRL_FLT_R_MASK (0xFU << I2C_DBGCTRL_FLT_R_SHIFT) 1556 #define I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT (8U) 1557 #define I2C_DBGCTRL_SLV_HOLD_SCL_TH_MASK (0xFU << I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT) 1558 #define I2C_DBGCTRL_FLT_EN_SHIFT (12U) 1559 #define I2C_DBGCTRL_FLT_EN_MASK (0x1U << I2C_DBGCTRL_FLT_EN_SHIFT) 1560 #define I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT (13U) 1561 #define I2C_DBGCTRL_NAK_RELEASE_SCL_MASK (0x1U << I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT) 1562 #define I2C_DBGCTRL_H0_CHECK_SCL_SHIFT (14U) 1563 #define I2C_DBGCTRL_H0_CHECK_SCL_MASK (0x1U << I2C_DBGCTRL_H0_CHECK_SCL_SHIFT) 1564 /******************************************UART******************************************/ 1565 /* RBR */ 1566 #define UART_RBR_OFFSET (0x0U) 1567 #define UART_RBR (0x0U) 1568 #define UART_RBR_DATA_INPUT_SHIFT (0U) 1569 #define UART_RBR_DATA_INPUT_MASK (0xFFU << UART_RBR_DATA_INPUT_SHIFT) 1570 /* THR */ 1571 #define UART_THR_OFFSET (0x0U) 1572 #define UART_THR_DATA_OUTPUT_SHIFT (0U) 1573 #define UART_THR_DATA_OUTPUT_MASK (0xFFU << UART_THR_DATA_OUTPUT_SHIFT) 1574 /* DLL */ 1575 #define UART_DLL_OFFSET (0x0U) 1576 #define UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT (0U) 1577 #define UART_DLL_BAUD_RATE_DIVISOR_L_MASK (0xFFU << UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT) 1578 /* DLH */ 1579 #define UART_DLH_OFFSET (0x4U) 1580 #define UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT (0U) 1581 #define UART_DLH_BAUD_RATE_DIVISOR_H_MASK (0xFFU << UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT) 1582 /* IER */ 1583 #define UART_IER_OFFSET (0x4U) 1584 #define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT (0U) 1585 #define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_MASK (0x1U << UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT) 1586 #define UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT (1U) 1587 #define UART_IER_TRANS_HOLD_EMPTY_INT_EN_MASK (0x1U << UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT) 1588 #define UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT (2U) 1589 #define UART_IER_RECEIVE_LINE_STATUS_INT_EN_MASK (0x1U << UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT) 1590 #define UART_IER_MODEM_STATUS_INT_EN_SHIFT (3U) 1591 #define UART_IER_MODEM_STATUS_INT_EN_MASK (0x1U << UART_IER_MODEM_STATUS_INT_EN_SHIFT) 1592 #define UART_IER_PROG_THRE_INT_EN_SHIFT (7U) 1593 #define UART_IER_PROG_THRE_INT_EN_MASK (0x1U << UART_IER_PROG_THRE_INT_EN_SHIFT) 1594 /* IIR */ 1595 #define UART_IIR_OFFSET (0x8U) 1596 #define UART_IIR (0x0U) 1597 #define UART_IIR_INT_ID_SHIFT (0U) 1598 #define UART_IIR_INT_ID_MASK (0xFU << UART_IIR_INT_ID_SHIFT) 1599 #define UART_IIR_FIFOS_EN_SHIFT (6U) 1600 #define UART_IIR_FIFOS_EN_MASK (0x3U << UART_IIR_FIFOS_EN_SHIFT) 1601 /* FCR */ 1602 #define UART_FCR_OFFSET (0x8U) 1603 #define UART_FCR_FIFO_EN_SHIFT (0U) 1604 #define UART_FCR_FIFO_EN_MASK (0x1U << UART_FCR_FIFO_EN_SHIFT) 1605 #define UART_FCR_RCVR_FIFO_RESET_SHIFT (1U) 1606 #define UART_FCR_RCVR_FIFO_RESET_MASK (0x1U << UART_FCR_RCVR_FIFO_RESET_SHIFT) 1607 #define UART_FCR_XMIT_FIFO_RESET_SHIFT (2U) 1608 #define UART_FCR_XMIT_FIFO_RESET_MASK (0x1U << UART_FCR_XMIT_FIFO_RESET_SHIFT) 1609 #define UART_FCR_DMA_MODE_SHIFT (3U) 1610 #define UART_FCR_DMA_MODE_MASK (0x1U << UART_FCR_DMA_MODE_SHIFT) 1611 #define UART_FCR_TX_EMPTY_TRIGGER_SHIFT (4U) 1612 #define UART_FCR_TX_EMPTY_TRIGGER_MASK (0x3U << UART_FCR_TX_EMPTY_TRIGGER_SHIFT) 1613 #define UART_FCR_RCVR_TRIGGER_SHIFT (6U) 1614 #define UART_FCR_RCVR_TRIGGER_MASK (0x3U << UART_FCR_RCVR_TRIGGER_SHIFT) 1615 /* LCR */ 1616 #define UART_LCR_OFFSET (0xCU) 1617 #define UART_LCR_DATA_LENGTH_SEL_SHIFT (0U) 1618 #define UART_LCR_DATA_LENGTH_SEL_MASK (0x3U << UART_LCR_DATA_LENGTH_SEL_SHIFT) 1619 #define UART_LCR_STOP_BITS_NUM_SHIFT (2U) 1620 #define UART_LCR_STOP_BITS_NUM_MASK (0x1U << UART_LCR_STOP_BITS_NUM_SHIFT) 1621 #define UART_LCR_PARITY_EN_SHIFT (3U) 1622 #define UART_LCR_PARITY_EN_MASK (0x1U << UART_LCR_PARITY_EN_SHIFT) 1623 #define UART_LCR_EVEN_PARITY_SEL_SHIFT (4U) 1624 #define UART_LCR_EVEN_PARITY_SEL_MASK (0x1U << UART_LCR_EVEN_PARITY_SEL_SHIFT) 1625 #define UART_LCR_BREAK_CTRL_SHIFT (6U) 1626 #define UART_LCR_BREAK_CTRL_MASK (0x1U << UART_LCR_BREAK_CTRL_SHIFT) 1627 #define UART_LCR_DIV_LAT_ACCESS_SHIFT (7U) 1628 #define UART_LCR_DIV_LAT_ACCESS_MASK (0x1U << UART_LCR_DIV_LAT_ACCESS_SHIFT) 1629 /* MCR */ 1630 #define UART_MCR_OFFSET (0x10U) 1631 #define UART_MCR_DATA_TERMINAL_READY_SHIFT (0U) 1632 #define UART_MCR_DATA_TERMINAL_READY_MASK (0x1U << UART_MCR_DATA_TERMINAL_READY_SHIFT) 1633 #define UART_MCR_REQ_TO_SEND_SHIFT (1U) 1634 #define UART_MCR_REQ_TO_SEND_MASK (0x1U << UART_MCR_REQ_TO_SEND_SHIFT) 1635 #define UART_MCR_OUT1_SHIFT (2U) 1636 #define UART_MCR_OUT1_MASK (0x1U << UART_MCR_OUT1_SHIFT) 1637 #define UART_MCR_OUT2_SHIFT (3U) 1638 #define UART_MCR_OUT2_MASK (0x1U << UART_MCR_OUT2_SHIFT) 1639 #define UART_MCR_LOOPBACK_SHIFT (4U) 1640 #define UART_MCR_LOOPBACK_MASK (0x1U << UART_MCR_LOOPBACK_SHIFT) 1641 #define UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT (5U) 1642 #define UART_MCR_AUTO_FLOW_CTRL_EN_MASK (0x1U << UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT) 1643 #define UART_MCR_SIR_MODE_EN_SHIFT (6U) 1644 #define UART_MCR_SIR_MODE_EN_MASK (0x1U << UART_MCR_SIR_MODE_EN_SHIFT) 1645 /* LSR */ 1646 #define UART_LSR_OFFSET (0x14U) 1647 #define UART_LSR (0x0U) 1648 #define UART_LSR_DATA_READY_SHIFT (0U) 1649 #define UART_LSR_DATA_READY_MASK (0x1U << UART_LSR_DATA_READY_SHIFT) 1650 #define UART_LSR_OVERRUN_ERROR_SHIFT (1U) 1651 #define UART_LSR_OVERRUN_ERROR_MASK (0x1U << UART_LSR_OVERRUN_ERROR_SHIFT) 1652 #define UART_LSR_PARITY_EROR_SHIFT (2U) 1653 #define UART_LSR_PARITY_EROR_MASK (0x1U << UART_LSR_PARITY_EROR_SHIFT) 1654 #define UART_LSR_FRAMING_ERROR_SHIFT (3U) 1655 #define UART_LSR_FRAMING_ERROR_MASK (0x1U << UART_LSR_FRAMING_ERROR_SHIFT) 1656 #define UART_LSR_BREAK_INT_SHIFT (4U) 1657 #define UART_LSR_BREAK_INT_MASK (0x1U << UART_LSR_BREAK_INT_SHIFT) 1658 #define UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT (5U) 1659 #define UART_LSR_TRANS_HOLD_REG_EMPTY_MASK (0x1U << UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT) 1660 #define UART_LSR_TRANS_EMPTY_SHIFT (6U) 1661 #define UART_LSR_TRANS_EMPTY_MASK (0x1U << UART_LSR_TRANS_EMPTY_SHIFT) 1662 #define UART_LSR_RECEIVER_FIFO_ERROR_SHIFT (7U) 1663 #define UART_LSR_RECEIVER_FIFO_ERROR_MASK (0x1U << UART_LSR_RECEIVER_FIFO_ERROR_SHIFT) 1664 /* MSR */ 1665 #define UART_MSR_OFFSET (0x18U) 1666 #define UART_MSR (0x0U) 1667 #define UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT (0U) 1668 #define UART_MSR_DELTA_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT) 1669 #define UART_MSR_DELTA_DATA_SET_READY_SHIFT (1U) 1670 #define UART_MSR_DELTA_DATA_SET_READY_MASK (0x1U << UART_MSR_DELTA_DATA_SET_READY_SHIFT) 1671 #define UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT (2U) 1672 #define UART_MSR_TRAILING_EDGE_RING_INDICATOR_MASK (0x1U << UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT) 1673 #define UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT (3U) 1674 #define UART_MSR_DELTA_DATA_CARRIER_DETECT_MASK (0x1U << UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT) 1675 #define UART_MSR_CLEAR_TO_SEND_SHIFT (4U) 1676 #define UART_MSR_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_CLEAR_TO_SEND_SHIFT) 1677 #define UART_MSR_DATA_SET_READY_SHIFT (5U) 1678 #define UART_MSR_DATA_SET_READY_MASK (0x1U << UART_MSR_DATA_SET_READY_SHIFT) 1679 #define UART_MSR_RING_INDICATOR_SHIFT (6U) 1680 #define UART_MSR_RING_INDICATOR_MASK (0x1U << UART_MSR_RING_INDICATOR_SHIFT) 1681 #define UART_MSR_DATA_CARRIOR_DETECT_SHIFT (7U) 1682 #define UART_MSR_DATA_CARRIOR_DETECT_MASK (0x1U << UART_MSR_DATA_CARRIOR_DETECT_SHIFT) 1683 /* SCR */ 1684 #define UART_SCR_OFFSET (0x1CU) 1685 #define UART_SCR_TEMP_STORE_SPACE_SHIFT (0U) 1686 #define UART_SCR_TEMP_STORE_SPACE_MASK (0xFFU << UART_SCR_TEMP_STORE_SPACE_SHIFT) 1687 /* SRBR */ 1688 #define UART_SRBR_OFFSET (0x30U) 1689 #define UART_SRBR (0x0U) 1690 #define UART_SRBR_SHADOW_RBR_SHIFT (0U) 1691 #define UART_SRBR_SHADOW_RBR_MASK (0xFFU << UART_SRBR_SHADOW_RBR_SHIFT) 1692 /* STHR */ 1693 #define UART_STHR_OFFSET (0x30U) 1694 #define UART_STHR (0x0U) 1695 #define UART_STHR_SHADOW_THR_SHIFT (0U) 1696 #define UART_STHR_SHADOW_THR_MASK (0xFFU << UART_STHR_SHADOW_THR_SHIFT) 1697 /* FAR */ 1698 #define UART_FAR_OFFSET (0x70U) 1699 #define UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT (0U) 1700 #define UART_FAR_FIFO_ACCESS_TEST_EN_MASK (0x1U << UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT) 1701 /* TFR */ 1702 #define UART_TFR_OFFSET (0x74U) 1703 #define UART_TFR (0x0U) 1704 #define UART_TFR_TRANS_FIFO_READ_SHIFT (0U) 1705 #define UART_TFR_TRANS_FIFO_READ_MASK (0xFFU << UART_TFR_TRANS_FIFO_READ_SHIFT) 1706 /* RFW */ 1707 #define UART_RFW_OFFSET (0x78U) 1708 #define UART_RFW_RECEIVE_FIFO_WRITE_SHIFT (0U) 1709 #define UART_RFW_RECEIVE_FIFO_WRITE_MASK (0xFFU << UART_RFW_RECEIVE_FIFO_WRITE_SHIFT) 1710 #define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT (8U) 1711 #define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT) 1712 #define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT (9U) 1713 #define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT) 1714 /* USR */ 1715 #define UART_USR_OFFSET (0x7CU) 1716 #define UART_USR (0x0U) 1717 #define UART_USR_UART_BUSY_SHIFT (0U) 1718 #define UART_USR_UART_BUSY_MASK (0x1U << UART_USR_UART_BUSY_SHIFT) 1719 #define UART_USR_TRANS_FIFO_NOT_FULL_SHIFT (1U) 1720 #define UART_USR_TRANS_FIFO_NOT_FULL_MASK (0x1U << UART_USR_TRANS_FIFO_NOT_FULL_SHIFT) 1721 #define UART_USR_TRASN_FIFO_EMPTY_SHIFT (2U) 1722 #define UART_USR_TRASN_FIFO_EMPTY_MASK (0x1U << UART_USR_TRASN_FIFO_EMPTY_SHIFT) 1723 #define UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT (3U) 1724 #define UART_USR_RECEIVE_FIFO_NOT_EMPTY_MASK (0x1U << UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT) 1725 #define UART_USR_RECEIVE_FIFO_FULL_SHIFT (4U) 1726 #define UART_USR_RECEIVE_FIFO_FULL_MASK (0x1U << UART_USR_RECEIVE_FIFO_FULL_SHIFT) 1727 /* TFL */ 1728 #define UART_TFL_OFFSET (0x80U) 1729 #define UART_TFL_TRANS_FIFO_LEVEL_SHIFT (0U) 1730 #define UART_TFL_TRANS_FIFO_LEVEL_MASK (0x1FU << UART_TFL_TRANS_FIFO_LEVEL_SHIFT) 1731 /* RFL */ 1732 #define UART_RFL_OFFSET (0x84U) 1733 #define UART_RFL (0x0U) 1734 #define UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT (0U) 1735 #define UART_RFL_RECEIVE_FIFO_LEVEL_MASK (0x1FU << UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT) 1736 /* SRR */ 1737 #define UART_SRR_OFFSET (0x88U) 1738 #define UART_SRR_UART_RESET_SHIFT (0U) 1739 #define UART_SRR_UART_RESET_MASK (0x1U << UART_SRR_UART_RESET_SHIFT) 1740 #define UART_SRR_RCVR_FIFO_RESET_SHIFT (1U) 1741 #define UART_SRR_RCVR_FIFO_RESET_MASK (0x1U << UART_SRR_RCVR_FIFO_RESET_SHIFT) 1742 #define UART_SRR_XMIT_FIFO_RESET_SHIFT (2U) 1743 #define UART_SRR_XMIT_FIFO_RESET_MASK (0x1U << UART_SRR_XMIT_FIFO_RESET_SHIFT) 1744 /* SRTS */ 1745 #define UART_SRTS_OFFSET (0x8CU) 1746 #define UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT (0U) 1747 #define UART_SRTS_SHADOW_REQ_TO_SEND_MASK (0x1U << UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT) 1748 /* SBCR */ 1749 #define UART_SBCR_OFFSET (0x90U) 1750 #define UART_SBCR_SHADOW_BREAK_CTRL_SHIFT (0U) 1751 #define UART_SBCR_SHADOW_BREAK_CTRL_MASK (0x1U << UART_SBCR_SHADOW_BREAK_CTRL_SHIFT) 1752 /* SDMAM */ 1753 #define UART_SDMAM_OFFSET (0x94U) 1754 #define UART_SDMAM_SHADOW_DMA_MODE_SHIFT (0U) 1755 #define UART_SDMAM_SHADOW_DMA_MODE_MASK (0x1U << UART_SDMAM_SHADOW_DMA_MODE_SHIFT) 1756 /* SFE */ 1757 #define UART_SFE_OFFSET (0x98U) 1758 #define UART_SFE_SHADOW_FIFO_EN_SHIFT (0U) 1759 #define UART_SFE_SHADOW_FIFO_EN_MASK (0x1U << UART_SFE_SHADOW_FIFO_EN_SHIFT) 1760 /* SRT */ 1761 #define UART_SRT_OFFSET (0x9CU) 1762 #define UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT (0U) 1763 #define UART_SRT_SHADOW_RCVR_TRIGGER_MASK (0x1U << UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT) 1764 /* STET */ 1765 #define UART_STET_OFFSET (0xA0U) 1766 #define UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT (0U) 1767 #define UART_STET_SHADOW_TX_EMPTY_TRIGGER_MASK (0x1U << UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT) 1768 /* HTX */ 1769 #define UART_HTX_OFFSET (0xA4U) 1770 #define UART_HTX_HALT_TX_EN_SHIFT (0U) 1771 #define UART_HTX_HALT_TX_EN_MASK (0x1U << UART_HTX_HALT_TX_EN_SHIFT) 1772 /* DMASA */ 1773 #define UART_DMASA_OFFSET (0xA8U) 1774 #define UART_DMASA_DMA_SOFTWARE_ACK_SHIFT (0U) 1775 #define UART_DMASA_DMA_SOFTWARE_ACK_MASK (0x1U << UART_DMASA_DMA_SOFTWARE_ACK_SHIFT) 1776 /* CPR */ 1777 #define UART_CPR_OFFSET (0xF4U) 1778 #define UART_CPR (0x0U) 1779 #define UART_CPR_APB_DATA_WIDTH_SHIFT (0U) 1780 #define UART_CPR_APB_DATA_WIDTH_MASK (0x3U << UART_CPR_APB_DATA_WIDTH_SHIFT) 1781 #define UART_CPR_AFCE_MODE_SHIFT (4U) 1782 #define UART_CPR_AFCE_MODE_MASK (0x1U << UART_CPR_AFCE_MODE_SHIFT) 1783 #define UART_CPR_THRE_MODE_SHIFT (5U) 1784 #define UART_CPR_THRE_MODE_MASK (0x1U << UART_CPR_THRE_MODE_SHIFT) 1785 #define UART_CPR_SIR_MODE_SHIFT (6U) 1786 #define UART_CPR_SIR_MODE_MASK (0x1U << UART_CPR_SIR_MODE_SHIFT) 1787 #define UART_CPR_SIR_LP_MODE_SHIFT (7U) 1788 #define UART_CPR_SIR_LP_MODE_MASK (0x1U << UART_CPR_SIR_LP_MODE_SHIFT) 1789 #define UART_CPR_NEW_FEAT_SHIFT (8U) 1790 #define UART_CPR_NEW_FEAT_MASK (0x1U << UART_CPR_NEW_FEAT_SHIFT) 1791 #define UART_CPR_FIFO_ACCESS_SHIFT (9U) 1792 #define UART_CPR_FIFO_ACCESS_MASK (0x1U << UART_CPR_FIFO_ACCESS_SHIFT) 1793 #define UART_CPR_FIFO_STAT_SHIFT (10U) 1794 #define UART_CPR_FIFO_STAT_MASK (0x1U << UART_CPR_FIFO_STAT_SHIFT) 1795 #define UART_CPR_SHADOW_SHIFT (11U) 1796 #define UART_CPR_SHADOW_MASK (0x1U << UART_CPR_SHADOW_SHIFT) 1797 #define UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT (12U) 1798 #define UART_CPR_UART_ADD_ENCODED_PARAMS_MASK (0x1U << UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT) 1799 #define UART_CPR_DMA_EXTRA_SHIFT (13U) 1800 #define UART_CPR_DMA_EXTRA_MASK (0x1U << UART_CPR_DMA_EXTRA_SHIFT) 1801 #define UART_CPR_FIFO_MODE_SHIFT (16U) 1802 #define UART_CPR_FIFO_MODE_MASK (0xFFU << UART_CPR_FIFO_MODE_SHIFT) 1803 /* UCV */ 1804 #define UART_UCV_OFFSET (0xF8U) 1805 #define UART_UCV (0x330372AU) 1806 #define UART_UCV_VER_SHIFT (0U) 1807 #define UART_UCV_VER_MASK (0xFFFFFFFFU << UART_UCV_VER_SHIFT) 1808 /* CTR */ 1809 #define UART_CTR_OFFSET (0xFCU) 1810 #define UART_CTR (0x44570110U) 1811 #define UART_CTR_PERIPHERAL_ID_SHIFT (0U) 1812 #define UART_CTR_PERIPHERAL_ID_MASK (0xFFFFFFFFU << UART_CTR_PERIPHERAL_ID_SHIFT) 1813 /******************************************PWM*******************************************/ 1814 /* PWM0_CNT */ 1815 #define PWM_PWM0_CNT_OFFSET (0x0U) 1816 #define PWM_PWM0_CNT (0x0U) 1817 #define PWM_PWM0_CNT_CNT_SHIFT (0U) 1818 #define PWM_PWM0_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM0_CNT_CNT_SHIFT) 1819 /* PWM0_PERIOD_HPR */ 1820 #define PWM_PWM0_PERIOD_HPR_OFFSET (0x4U) 1821 #define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) 1822 #define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT) 1823 /* PWM0_DUTY_LPR */ 1824 #define PWM_PWM0_DUTY_LPR_OFFSET (0x8U) 1825 #define PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT (0U) 1826 #define PWM_PWM0_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT) 1827 /* PWM0_CTRL */ 1828 #define PWM_PWM0_CTRL_OFFSET (0xCU) 1829 #define PWM_PWM0_CTRL_PWM_EN_SHIFT (0U) 1830 #define PWM_PWM0_CTRL_PWM_EN_MASK (0x1U << PWM_PWM0_CTRL_PWM_EN_SHIFT) 1831 #define PWM_PWM0_CTRL_PWM_MODE_SHIFT (1U) 1832 #define PWM_PWM0_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM0_CTRL_PWM_MODE_SHIFT) 1833 #define PWM_PWM0_CTRL_DUTY_POL_SHIFT (3U) 1834 #define PWM_PWM0_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM0_CTRL_DUTY_POL_SHIFT) 1835 #define PWM_PWM0_CTRL_INACTIVE_POL_SHIFT (4U) 1836 #define PWM_PWM0_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) 1837 #define PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT (5U) 1838 #define PWM_PWM0_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) 1839 #define PWM_PWM0_CTRL_CONLOCK_SHIFT (6U) 1840 #define PWM_PWM0_CTRL_CONLOCK_MASK (0x1U << PWM_PWM0_CTRL_CONLOCK_SHIFT) 1841 #define PWM_PWM0_CTRL_CH_CNT_EN_SHIFT (7U) 1842 #define PWM_PWM0_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM0_CTRL_CH_CNT_EN_SHIFT) 1843 #define PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT (8U) 1844 #define PWM_PWM0_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) 1845 #define PWM_PWM0_CTRL_CLK_SEL_SHIFT (9U) 1846 #define PWM_PWM0_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SEL_SHIFT) 1847 #define PWM_PWM0_CTRL_PRESCALE_SHIFT (12U) 1848 #define PWM_PWM0_CTRL_PRESCALE_MASK (0x7U << PWM_PWM0_CTRL_PRESCALE_SHIFT) 1849 #define PWM_PWM0_CTRL_SCALE_SHIFT (16U) 1850 #define PWM_PWM0_CTRL_SCALE_MASK (0xFFU << PWM_PWM0_CTRL_SCALE_SHIFT) 1851 #define PWM_PWM0_CTRL_RPT_SHIFT (24U) 1852 #define PWM_PWM0_CTRL_RPT_MASK (0xFFU << PWM_PWM0_CTRL_RPT_SHIFT) 1853 /* PWM1_CNT */ 1854 #define PWM_PWM1_CNT_OFFSET (0x10U) 1855 #define PWM_PWM1_CNT (0x0U) 1856 #define PWM_PWM1_CNT_CNT_SHIFT (0U) 1857 #define PWM_PWM1_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM1_CNT_CNT_SHIFT) 1858 /* PWM1_PERIOD_HPR */ 1859 #define PWM_PWM1_PERIOD_HPR_OFFSET (0x14U) 1860 #define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) 1861 #define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT) 1862 /* PWM1_DUTY_LPR */ 1863 #define PWM_PWM1_DUTY_LPR_OFFSET (0x18U) 1864 #define PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT (0U) 1865 #define PWM_PWM1_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT) 1866 /* PWM1_CTRL */ 1867 #define PWM_PWM1_CTRL_OFFSET (0x1CU) 1868 #define PWM_PWM1_CTRL_PWM_EN_SHIFT (0U) 1869 #define PWM_PWM1_CTRL_PWM_EN_MASK (0x1U << PWM_PWM1_CTRL_PWM_EN_SHIFT) 1870 #define PWM_PWM1_CTRL_PWM_MODE_SHIFT (1U) 1871 #define PWM_PWM1_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM1_CTRL_PWM_MODE_SHIFT) 1872 #define PWM_PWM1_CTRL_DUTY_POL_SHIFT (3U) 1873 #define PWM_PWM1_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM1_CTRL_DUTY_POL_SHIFT) 1874 #define PWM_PWM1_CTRL_INACTIVE_POL_SHIFT (4U) 1875 #define PWM_PWM1_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM1_CTRL_INACTIVE_POL_SHIFT) 1876 #define PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT (5U) 1877 #define PWM_PWM1_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT) 1878 #define PWM_PWM1_CTRL_CONLOCK_SHIFT (6U) 1879 #define PWM_PWM1_CTRL_CONLOCK_MASK (0x1U << PWM_PWM1_CTRL_CONLOCK_SHIFT) 1880 #define PWM_PWM1_CTRL_CH_CNT_EN_SHIFT (7U) 1881 #define PWM_PWM1_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM1_CTRL_CH_CNT_EN_SHIFT) 1882 #define PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT (8U) 1883 #define PWM_PWM1_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT) 1884 #define PWM_PWM1_CTRL_CLK_SEL_SHIFT (9U) 1885 #define PWM_PWM1_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SEL_SHIFT) 1886 #define PWM_PWM1_CTRL_PRESCALE_SHIFT (12U) 1887 #define PWM_PWM1_CTRL_PRESCALE_MASK (0x7U << PWM_PWM1_CTRL_PRESCALE_SHIFT) 1888 #define PWM_PWM1_CTRL_SCALE_SHIFT (16U) 1889 #define PWM_PWM1_CTRL_SCALE_MASK (0xFFU << PWM_PWM1_CTRL_SCALE_SHIFT) 1890 #define PWM_PWM1_CTRL_RPT_SHIFT (24U) 1891 #define PWM_PWM1_CTRL_RPT_MASK (0xFFU << PWM_PWM1_CTRL_RPT_SHIFT) 1892 /* PWM2_CNT */ 1893 #define PWM_PWM2_CNT_OFFSET (0x20U) 1894 #define PWM_PWM2_CNT (0x0U) 1895 #define PWM_PWM2_CNT_CNT_SHIFT (0U) 1896 #define PWM_PWM2_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM2_CNT_CNT_SHIFT) 1897 /* PWM2_PERIOD_HPR */ 1898 #define PWM_PWM2_PERIOD_HPR_OFFSET (0x24U) 1899 #define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) 1900 #define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT) 1901 /* PWM2_DUTY_LPR */ 1902 #define PWM_PWM2_DUTY_LPR_OFFSET (0x28U) 1903 #define PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT (0U) 1904 #define PWM_PWM2_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT) 1905 /* PWM2_CTRL */ 1906 #define PWM_PWM2_CTRL_OFFSET (0x2CU) 1907 #define PWM_PWM2_CTRL_PWM_EN_SHIFT (0U) 1908 #define PWM_PWM2_CTRL_PWM_EN_MASK (0x1U << PWM_PWM2_CTRL_PWM_EN_SHIFT) 1909 #define PWM_PWM2_CTRL_PWM_MODE_SHIFT (1U) 1910 #define PWM_PWM2_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM2_CTRL_PWM_MODE_SHIFT) 1911 #define PWM_PWM2_CTRL_DUTY_POL_SHIFT (3U) 1912 #define PWM_PWM2_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM2_CTRL_DUTY_POL_SHIFT) 1913 #define PWM_PWM2_CTRL_INACTIVE_POL_SHIFT (4U) 1914 #define PWM_PWM2_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM2_CTRL_INACTIVE_POL_SHIFT) 1915 #define PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT (5U) 1916 #define PWM_PWM2_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT) 1917 #define PWM_PWM2_CTRL_CONLOCK_SHIFT (6U) 1918 #define PWM_PWM2_CTRL_CONLOCK_MASK (0x1U << PWM_PWM2_CTRL_CONLOCK_SHIFT) 1919 #define PWM_PWM2_CTRL_CH_CNT_EN_SHIFT (7U) 1920 #define PWM_PWM2_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM2_CTRL_CH_CNT_EN_SHIFT) 1921 #define PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT (8U) 1922 #define PWM_PWM2_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT) 1923 #define PWM_PWM2_CTRL_CLK_SEL_SHIFT (9U) 1924 #define PWM_PWM2_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SEL_SHIFT) 1925 #define PWM_PWM2_CTRL_PRESCALE_SHIFT (12U) 1926 #define PWM_PWM2_CTRL_PRESCALE_MASK (0x7U << PWM_PWM2_CTRL_PRESCALE_SHIFT) 1927 #define PWM_PWM2_CTRL_SCALE_SHIFT (16U) 1928 #define PWM_PWM2_CTRL_SCALE_MASK (0xFFU << PWM_PWM2_CTRL_SCALE_SHIFT) 1929 #define PWM_PWM2_CTRL_RPT_SHIFT (24U) 1930 #define PWM_PWM2_CTRL_RPT_MASK (0xFFU << PWM_PWM2_CTRL_RPT_SHIFT) 1931 /* PWM3_CNT */ 1932 #define PWM_PWM3_CNT_OFFSET (0x30U) 1933 #define PWM_PWM3_CNT (0x0U) 1934 #define PWM_PWM3_CNT_CNT_SHIFT (0U) 1935 #define PWM_PWM3_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM3_CNT_CNT_SHIFT) 1936 /* PWM3_PERIOD_HPR */ 1937 #define PWM_PWM3_PERIOD_HPR_OFFSET (0x34U) 1938 #define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) 1939 #define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT) 1940 /* PWM3_DUTY_LPR */ 1941 #define PWM_PWM3_DUTY_LPR_OFFSET (0x38U) 1942 #define PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT (0U) 1943 #define PWM_PWM3_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT) 1944 /* PWM3_CTRL */ 1945 #define PWM_PWM3_CTRL_OFFSET (0x3CU) 1946 #define PWM_PWM3_CTRL_PWM_EN_SHIFT (0U) 1947 #define PWM_PWM3_CTRL_PWM_EN_MASK (0x1U << PWM_PWM3_CTRL_PWM_EN_SHIFT) 1948 #define PWM_PWM3_CTRL_PWM_MODE_SHIFT (1U) 1949 #define PWM_PWM3_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM3_CTRL_PWM_MODE_SHIFT) 1950 #define PWM_PWM3_CTRL_DUTY_POL_SHIFT (3U) 1951 #define PWM_PWM3_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM3_CTRL_DUTY_POL_SHIFT) 1952 #define PWM_PWM3_CTRL_INACTIVE_POL_SHIFT (4U) 1953 #define PWM_PWM3_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM3_CTRL_INACTIVE_POL_SHIFT) 1954 #define PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT (5U) 1955 #define PWM_PWM3_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT) 1956 #define PWM_PWM3_CTRL_CONLOCK_SHIFT (6U) 1957 #define PWM_PWM3_CTRL_CONLOCK_MASK (0x1U << PWM_PWM3_CTRL_CONLOCK_SHIFT) 1958 #define PWM_PWM3_CTRL_CH_CNT_EN_SHIFT (7U) 1959 #define PWM_PWM3_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM3_CTRL_CH_CNT_EN_SHIFT) 1960 #define PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT (8U) 1961 #define PWM_PWM3_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT) 1962 #define PWM_PWM3_CTRL_CLK_SEL_SHIFT (9U) 1963 #define PWM_PWM3_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SEL_SHIFT) 1964 #define PWM_PWM3_CTRL_PRESCALE_SHIFT (12U) 1965 #define PWM_PWM3_CTRL_PRESCALE_MASK (0x7U << PWM_PWM3_CTRL_PRESCALE_SHIFT) 1966 #define PWM_PWM3_CTRL_SCALE_SHIFT (16U) 1967 #define PWM_PWM3_CTRL_SCALE_MASK (0xFFU << PWM_PWM3_CTRL_SCALE_SHIFT) 1968 #define PWM_PWM3_CTRL_RPT_SHIFT (24U) 1969 #define PWM_PWM3_CTRL_RPT_MASK (0xFFU << PWM_PWM3_CTRL_RPT_SHIFT) 1970 /* INTSTS */ 1971 #define PWM_INTSTS_OFFSET (0x40U) 1972 #define PWM_INTSTS_CH0_INTSTS_SHIFT (0U) 1973 #define PWM_INTSTS_CH0_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_INTSTS_SHIFT) 1974 #define PWM_INTSTS_CH1_INTSTS_SHIFT (1U) 1975 #define PWM_INTSTS_CH1_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_INTSTS_SHIFT) 1976 #define PWM_INTSTS_CH2_INTSTS_SHIFT (2U) 1977 #define PWM_INTSTS_CH2_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_INTSTS_SHIFT) 1978 #define PWM_INTSTS_CH3_INTSTS_SHIFT (3U) 1979 #define PWM_INTSTS_CH3_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_INTSTS_SHIFT) 1980 #define PWM_INTSTS_CH0_PWR_INTSTS_SHIFT (4U) 1981 #define PWM_INTSTS_CH0_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_PWR_INTSTS_SHIFT) 1982 #define PWM_INTSTS_CH1_PWR_INTSTS_SHIFT (5U) 1983 #define PWM_INTSTS_CH1_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_PWR_INTSTS_SHIFT) 1984 #define PWM_INTSTS_CH2_PWR_INTSTS_SHIFT (6U) 1985 #define PWM_INTSTS_CH2_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_PWR_INTSTS_SHIFT) 1986 #define PWM_INTSTS_CH3_PWR_INTSTS_SHIFT (7U) 1987 #define PWM_INTSTS_CH3_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_PWR_INTSTS_SHIFT) 1988 #define PWM_INTSTS_CH0_POL_SHIFT (8U) 1989 #define PWM_INTSTS_CH0_POL_MASK (0x1U << PWM_INTSTS_CH0_POL_SHIFT) 1990 #define PWM_INTSTS_CH1_POL_SHIFT (9U) 1991 #define PWM_INTSTS_CH1_POL_MASK (0x1U << PWM_INTSTS_CH1_POL_SHIFT) 1992 #define PWM_INTSTS_CH2_POL_SHIFT (10U) 1993 #define PWM_INTSTS_CH2_POL_MASK (0x1U << PWM_INTSTS_CH2_POL_SHIFT) 1994 #define PWM_INTSTS_CH3_POL_SHIFT (11U) 1995 #define PWM_INTSTS_CH3_POL_MASK (0x1U << PWM_INTSTS_CH3_POL_SHIFT) 1996 /* INT_EN */ 1997 #define PWM_INT_EN_OFFSET (0x44U) 1998 #define PWM_INT_EN_CH0_INT_EN_SHIFT (0U) 1999 #define PWM_INT_EN_CH0_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_INT_EN_SHIFT) 2000 #define PWM_INT_EN_CH1_INT_EN_SHIFT (1U) 2001 #define PWM_INT_EN_CH1_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_INT_EN_SHIFT) 2002 #define PWM_INT_EN_CH2_INT_EN_SHIFT (2U) 2003 #define PWM_INT_EN_CH2_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_INT_EN_SHIFT) 2004 #define PWM_INT_EN_CH3_INT_EN_SHIFT (3U) 2005 #define PWM_INT_EN_CH3_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_INT_EN_SHIFT) 2006 #define PWM_INT_EN_CH0_PWR_INT_EN_SHIFT (4U) 2007 #define PWM_INT_EN_CH0_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_PWR_INT_EN_SHIFT) 2008 #define PWM_INT_EN_CH1_PWR_INT_EN_SHIFT (5U) 2009 #define PWM_INT_EN_CH1_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_PWR_INT_EN_SHIFT) 2010 #define PWM_INT_EN_CH2_PWR_INT_EN_SHIFT (6U) 2011 #define PWM_INT_EN_CH2_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_PWR_INT_EN_SHIFT) 2012 #define PWM_INT_EN_CH3_PWR_INT_EN_SHIFT (7U) 2013 #define PWM_INT_EN_CH3_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_PWR_INT_EN_SHIFT) 2014 /* FIFO_CTRL */ 2015 #define PWM_FIFO_CTRL_OFFSET (0x50U) 2016 #define PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT (0U) 2017 #define PWM_FIFO_CTRL_FIFO_MODE_SEL_MASK (0x1U << PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT) 2018 #define PWM_FIFO_CTRL_FULL_INT_EN_SHIFT (1U) 2019 #define PWM_FIFO_CTRL_FULL_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_FULL_INT_EN_SHIFT) 2020 #define PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT (2U) 2021 #define PWM_FIFO_CTRL_OVERFLOW_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT) 2022 #define PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT (3U) 2023 #define PWM_FIFO_CTRL_WATERMARK_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT) 2024 #define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT (4U) 2025 #define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_MASK (0x7U << PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT) 2026 #define PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT (8U) 2027 #define PWM_FIFO_CTRL_DMA_MODE_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT) 2028 #define PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT (9U) 2029 #define PWM_FIFO_CTRL_TIMEOUT_EN_MASK (0x1U << PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT) 2030 #define PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT (10U) 2031 #define PWM_FIFO_CTRL_DMA_CH_SEL_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT) 2032 #define PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT (12U) 2033 #define PWM_FIFO_CTRL_DMA_CH_SEL_MASK (0x3U << PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT) 2034 /* FIFO_INTSTS */ 2035 #define PWM_FIFO_INTSTS_OFFSET (0x54U) 2036 #define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT (0U) 2037 #define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT) 2038 #define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT (1U) 2039 #define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT) 2040 #define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT (2U) 2041 #define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT) 2042 #define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT (3U) 2043 #define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT) 2044 #define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT (4U) 2045 #define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT) 2046 /* FIFO_TOUTTHR */ 2047 #define PWM_FIFO_TOUTTHR_OFFSET (0x58U) 2048 #define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT (0U) 2049 #define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_MASK (0xFFFFFU << PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT) 2050 /* VERSION_ID */ 2051 #define PWM_VERSION_ID_OFFSET (0x5CU) 2052 #define PWM_VERSION_ID_SVN_VERSION_SHIFT (0U) 2053 #define PWM_VERSION_ID_SVN_VERSION_MASK (0xFFFFU << PWM_VERSION_ID_SVN_VERSION_SHIFT) 2054 #define PWM_VERSION_ID_MINOR_VERSION_SHIFT (16U) 2055 #define PWM_VERSION_ID_MINOR_VERSION_MASK (0xFFU << PWM_VERSION_ID_MINOR_VERSION_SHIFT) 2056 #define PWM_VERSION_ID_MAIN_VERSION_SHIFT (24U) 2057 #define PWM_VERSION_ID_MAIN_VERSION_MASK (0xFFU << PWM_VERSION_ID_MAIN_VERSION_SHIFT) 2058 /* FIFO */ 2059 #define PWM_FIFO_OFFSET (0x60U) 2060 #define PWM_FIFO (0x0U) 2061 #define PWM_FIFO_CYCLE_CNT_SHIFT (0U) 2062 #define PWM_FIFO_CYCLE_CNT_MASK (0x7FFFFFFFU << PWM_FIFO_CYCLE_CNT_SHIFT) 2063 #define PWM_FIFO_POL_SHIFT (31U) 2064 #define PWM_FIFO_POL_MASK (0x1U << PWM_FIFO_POL_SHIFT) 2065 /* PWRMATCH_CTRL */ 2066 #define PWM_PWRMATCH_CTRL_OFFSET (0x80U) 2067 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT (3U) 2068 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT) 2069 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT (7U) 2070 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT) 2071 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT (11U) 2072 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT) 2073 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT (15U) 2074 #define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT) 2075 /* PWRMATCH_LPRE */ 2076 #define PWM_PWRMATCH_LPRE_OFFSET (0x84U) 2077 #define PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT (0U) 2078 #define PWM_PWRMATCH_LPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT) 2079 #define PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT (16U) 2080 #define PWM_PWRMATCH_LPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT) 2081 /* PWRMATCH_HPRE */ 2082 #define PWM_PWRMATCH_HPRE_OFFSET (0x88U) 2083 #define PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT (0U) 2084 #define PWM_PWRMATCH_HPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT) 2085 #define PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT (16U) 2086 #define PWM_PWRMATCH_HPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT) 2087 /* PWRMATCH_LD */ 2088 #define PWM_PWRMATCH_LD_OFFSET (0x8CU) 2089 #define PWM_PWRMATCH_LD_CNT_MIN_SHIFT (0U) 2090 #define PWM_PWRMATCH_LD_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MIN_SHIFT) 2091 #define PWM_PWRMATCH_LD_CNT_MAX_SHIFT (16U) 2092 #define PWM_PWRMATCH_LD_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MAX_SHIFT) 2093 /* PWRMATCH_HD_ZERO */ 2094 #define PWM_PWRMATCH_HD_ZERO_OFFSET (0x90U) 2095 #define PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT (0U) 2096 #define PWM_PWRMATCH_HD_ZERO_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT) 2097 #define PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT (16U) 2098 #define PWM_PWRMATCH_HD_ZERO_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT) 2099 /* PWRMATCH_HD_ONE */ 2100 #define PWM_PWRMATCH_HD_ONE_OFFSET (0x94U) 2101 #define PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT (0U) 2102 #define PWM_PWRMATCH_HD_ONE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT) 2103 #define PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT (16U) 2104 #define PWM_PWRMATCH_HD_ONE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT) 2105 /* PWRMATCH_VALUE0 */ 2106 #define PWM_PWRMATCH_VALUE0_OFFSET (0x98U) 2107 #define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT (0U) 2108 #define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_MASK \ 2109 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT) 2110 /* PWRMATCH_VALUE1 */ 2111 #define PWM_PWRMATCH_VALUE1_OFFSET (0x9CU) 2112 #define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT (0U) 2113 #define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_MASK \ 2114 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT) 2115 /* PWRMATCH_VALUE2 */ 2116 #define PWM_PWRMATCH_VALUE2_OFFSET (0xA0U) 2117 #define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT (0U) 2118 #define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_MASK \ 2119 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT) 2120 /* PWRMATCH_VALUE3 */ 2121 #define PWM_PWRMATCH_VALUE3_OFFSET (0xA4U) 2122 #define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT (0U) 2123 #define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_MASK \ 2124 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT) 2125 /* PWRMATCH_VALUE4 */ 2126 #define PWM_PWRMATCH_VALUE4_OFFSET (0xA8U) 2127 #define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT (0U) 2128 #define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_MASK \ 2129 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT) 2130 /* PWRMATCH_VALUE5 */ 2131 #define PWM_PWRMATCH_VALUE5_OFFSET (0xACU) 2132 #define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT (0U) 2133 #define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_MASK \ 2134 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT) 2135 /* PWRMATCH_VALUE6 */ 2136 #define PWM_PWRMATCH_VALUE6_OFFSET (0xB0U) 2137 #define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT (0U) 2138 #define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_MASK \ 2139 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT) 2140 /* PWRMATCH_VALUE7 */ 2141 #define PWM_PWRMATCH_VALUE7_OFFSET (0xB4U) 2142 #define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT (0U) 2143 #define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_MASK \ 2144 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT) 2145 /* PWRMATCH_VALUE8 */ 2146 #define PWM_PWRMATCH_VALUE8_OFFSET (0xB8U) 2147 #define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT (0U) 2148 #define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_MASK \ 2149 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT) 2150 /* PWRMATCH_VALUE9 */ 2151 #define PWM_PWRMATCH_VALUE9_OFFSET (0xBCU) 2152 #define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT (0U) 2153 #define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_MASK \ 2154 (0xFFFFFFFFU << PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT) 2155 /* PWM3_PWRCAPTURE_VALUE */ 2156 #define PWM_PWM3_PWRCAPTURE_VALUE_OFFSET (0xCCU) 2157 #define PWM_PWM3_PWRCAPTURE_VALUE (0x0U) 2158 #define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT (0U) 2159 #define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_MASK \ 2160 (0xFFFFFFFFU << PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT) 2161 /* FILTER_CTRL */ 2162 #define PWM_FILTER_CTRL_OFFSET (0xD0U) 2163 #define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT (0U) 2164 #define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT) 2165 #define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT (1U) 2166 #define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT) 2167 #define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT (2U) 2168 #define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT) 2169 #define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT (3U) 2170 #define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT) 2171 #define PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT (4U) 2172 #define PWM_FILTER_CTRL_FILTER_NUMBER_MASK (0x1FFU << PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT) 2173 /******************************************SPI*******************************************/ 2174 /* CTRLR0 */ 2175 #define SPI_CTRLR0_OFFSET (0x0U) 2176 #define SPI_CTRLR0_DFS_SHIFT (0U) 2177 #define SPI_CTRLR0_DFS_MASK (0x3U << SPI_CTRLR0_DFS_SHIFT) 2178 #define SPI_CTRLR0_CFS_SHIFT (2U) 2179 #define SPI_CTRLR0_CFS_MASK (0xFU << SPI_CTRLR0_CFS_SHIFT) 2180 #define SPI_CTRLR0_SCPH_SHIFT (6U) 2181 #define SPI_CTRLR0_SCPH_MASK (0x1U << SPI_CTRLR0_SCPH_SHIFT) 2182 #define SPI_CTRLR0_SCPOL_SHIFT (7U) 2183 #define SPI_CTRLR0_SCPOL_MASK (0x1U << SPI_CTRLR0_SCPOL_SHIFT) 2184 #define SPI_CTRLR0_CSM_SHIFT (8U) 2185 #define SPI_CTRLR0_CSM_MASK (0x3U << SPI_CTRLR0_CSM_SHIFT) 2186 #define SPI_CTRLR0_SSD_SHIFT (10U) 2187 #define SPI_CTRLR0_SSD_MASK (0x1U << SPI_CTRLR0_SSD_SHIFT) 2188 #define SPI_CTRLR0_EM_SHIFT (11U) 2189 #define SPI_CTRLR0_EM_MASK (0x1U << SPI_CTRLR0_EM_SHIFT) 2190 #define SPI_CTRLR0_FBM_SHIFT (12U) 2191 #define SPI_CTRLR0_FBM_MASK (0x1U << SPI_CTRLR0_FBM_SHIFT) 2192 #define SPI_CTRLR0_BHT_SHIFT (13U) 2193 #define SPI_CTRLR0_BHT_MASK (0x1U << SPI_CTRLR0_BHT_SHIFT) 2194 #define SPI_CTRLR0_RSD_SHIFT (14U) 2195 #define SPI_CTRLR0_RSD_MASK (0x3U << SPI_CTRLR0_RSD_SHIFT) 2196 #define SPI_CTRLR0_FRF_SHIFT (16U) 2197 #define SPI_CTRLR0_FRF_MASK (0x3U << SPI_CTRLR0_FRF_SHIFT) 2198 #define SPI_CTRLR0_XFM_SHIFT (18U) 2199 #define SPI_CTRLR0_XFM_MASK (0x3U << SPI_CTRLR0_XFM_SHIFT) 2200 #define SPI_CTRLR0_OPM_SHIFT (20U) 2201 #define SPI_CTRLR0_OPM_MASK (0x1U << SPI_CTRLR0_OPM_SHIFT) 2202 #define SPI_CTRLR0_MTM_SHIFT (21U) 2203 #define SPI_CTRLR0_MTM_MASK (0x1U << SPI_CTRLR0_MTM_SHIFT) 2204 #define SPI_CTRLR0_SOI_SHIFT (23U) 2205 #define SPI_CTRLR0_SOI_MASK (0x3U << SPI_CTRLR0_SOI_SHIFT) 2206 #define SPI_CTRLR0_LBK_SHIFT (25U) 2207 #define SPI_CTRLR0_LBK_MASK (0x1U << SPI_CTRLR0_LBK_SHIFT) 2208 /* CTRLR1 */ 2209 #define SPI_CTRLR1_OFFSET (0x4U) 2210 #define SPI_CTRLR1_NDM_SHIFT (0U) 2211 #define SPI_CTRLR1_NDM_MASK (0xFFFFFFFFU << SPI_CTRLR1_NDM_SHIFT) 2212 /* ENR */ 2213 #define SPI_ENR_OFFSET (0x8U) 2214 #define SPI_ENR_ENR_SHIFT (0U) 2215 #define SPI_ENR_ENR_MASK (0x1U << SPI_ENR_ENR_SHIFT) 2216 /* SER */ 2217 #define SPI_SER_OFFSET (0xCU) 2218 #define SPI_SER_SER_SHIFT (0U) 2219 #define SPI_SER_SER_MASK (0x3U << SPI_SER_SER_SHIFT) 2220 /* BAUDR */ 2221 #define SPI_BAUDR_OFFSET (0x10U) 2222 #define SPI_BAUDR_BAUDR_SHIFT (0U) 2223 #define SPI_BAUDR_BAUDR_MASK (0xFFFFU << SPI_BAUDR_BAUDR_SHIFT) 2224 /* TXFTLR */ 2225 #define SPI_TXFTLR_OFFSET (0x14U) 2226 #define SPI_TXFTLR_TXFTLR_SHIFT (0U) 2227 #define SPI_TXFTLR_TXFTLR_MASK (0x3FU << SPI_TXFTLR_TXFTLR_SHIFT) 2228 /* RXFTLR */ 2229 #define SPI_RXFTLR_OFFSET (0x18U) 2230 #define SPI_RXFTLR_RXFTLR_SHIFT (0U) 2231 #define SPI_RXFTLR_RXFTLR_MASK (0x3FU << SPI_RXFTLR_RXFTLR_SHIFT) 2232 /* TXFLR */ 2233 #define SPI_TXFLR_OFFSET (0x1CU) 2234 #define SPI_TXFLR (0x0U) 2235 #define SPI_TXFLR_TXFLR_SHIFT (0U) 2236 #define SPI_TXFLR_TXFLR_MASK (0x7FU << SPI_TXFLR_TXFLR_SHIFT) 2237 /* RXFLR */ 2238 #define SPI_RXFLR_OFFSET (0x20U) 2239 #define SPI_RXFLR (0x0U) 2240 #define SPI_RXFLR_RXFLR_SHIFT (0U) 2241 #define SPI_RXFLR_RXFLR_MASK (0x7FU << SPI_RXFLR_RXFLR_SHIFT) 2242 /* SR */ 2243 #define SPI_SR_OFFSET (0x24U) 2244 #define SPI_SR_BSF_SHIFT (0U) 2245 #define SPI_SR_BSF_MASK (0x1U << SPI_SR_BSF_SHIFT) 2246 #define SPI_SR_TFF_SHIFT (1U) 2247 #define SPI_SR_TFF_MASK (0x1U << SPI_SR_TFF_SHIFT) 2248 #define SPI_SR_TFE_SHIFT (2U) 2249 #define SPI_SR_TFE_MASK (0x1U << SPI_SR_TFE_SHIFT) 2250 #define SPI_SR_RFE_SHIFT (3U) 2251 #define SPI_SR_RFE_MASK (0x1U << SPI_SR_RFE_SHIFT) 2252 #define SPI_SR_RFF_SHIFT (4U) 2253 #define SPI_SR_RFF_MASK (0x1U << SPI_SR_RFF_SHIFT) 2254 #define SPI_SR_STB_SHIFT (5U) 2255 #define SPI_SR_STB_MASK (0x1U << SPI_SR_STB_SHIFT) 2256 #define SPI_SR_SSI_SHIFT (6U) 2257 #define SPI_SR_SSI_MASK (0x1U << SPI_SR_SSI_SHIFT) 2258 /* IPR */ 2259 #define SPI_IPR_OFFSET (0x28U) 2260 #define SPI_IPR_IPR_SHIFT (0U) 2261 #define SPI_IPR_IPR_MASK (0x1U << SPI_IPR_IPR_SHIFT) 2262 /* IMR */ 2263 #define SPI_IMR_OFFSET (0x2CU) 2264 #define SPI_IMR_TFEIM_SHIFT (0U) 2265 #define SPI_IMR_TFEIM_MASK (0x1U << SPI_IMR_TFEIM_SHIFT) 2266 #define SPI_IMR_TFOIM_SHIFT (1U) 2267 #define SPI_IMR_TFOIM_MASK (0x1U << SPI_IMR_TFOIM_SHIFT) 2268 #define SPI_IMR_RFUIM_SHIFT (2U) 2269 #define SPI_IMR_RFUIM_MASK (0x1U << SPI_IMR_RFUIM_SHIFT) 2270 #define SPI_IMR_RFOIM_SHIFT (3U) 2271 #define SPI_IMR_RFOIM_MASK (0x1U << SPI_IMR_RFOIM_SHIFT) 2272 #define SPI_IMR_RFFIM_SHIFT (4U) 2273 #define SPI_IMR_RFFIM_MASK (0x1U << SPI_IMR_RFFIM_SHIFT) 2274 #define SPI_IMR_TOIM_SHIFT (5U) 2275 #define SPI_IMR_TOIM_MASK (0x1U << SPI_IMR_TOIM_SHIFT) 2276 #define SPI_IMR_SSPIM_SHIFT (6U) 2277 #define SPI_IMR_SSPIM_MASK (0x1U << SPI_IMR_SSPIM_SHIFT) 2278 #define SPI_IMR_TXFIM_SHIFT (7U) 2279 #define SPI_IMR_TXFIM_MASK (0x1U << SPI_IMR_TXFIM_SHIFT) 2280 /* ISR */ 2281 #define SPI_ISR_OFFSET (0x30U) 2282 #define SPI_ISR_TFEIS_SHIFT (0U) 2283 #define SPI_ISR_TFEIS_MASK (0x1U << SPI_ISR_TFEIS_SHIFT) 2284 #define SPI_ISR_TFOIS_SHIFT (1U) 2285 #define SPI_ISR_TFOIS_MASK (0x1U << SPI_ISR_TFOIS_SHIFT) 2286 #define SPI_ISR_RFUIS_SHIFT (2U) 2287 #define SPI_ISR_RFUIS_MASK (0x1U << SPI_ISR_RFUIS_SHIFT) 2288 #define SPI_ISR_RFOIS_SHIFT (3U) 2289 #define SPI_ISR_RFOIS_MASK (0x1U << SPI_ISR_RFOIS_SHIFT) 2290 #define SPI_ISR_RFFIS_SHIFT (4U) 2291 #define SPI_ISR_RFFIS_MASK (0x1U << SPI_ISR_RFFIS_SHIFT) 2292 #define SPI_ISR_TOIS_SHIFT (5U) 2293 #define SPI_ISR_TOIS_MASK (0x1U << SPI_ISR_TOIS_SHIFT) 2294 #define SPI_ISR_SSPIS_SHIFT (6U) 2295 #define SPI_ISR_SSPIS_MASK (0x1U << SPI_ISR_SSPIS_SHIFT) 2296 #define SPI_ISR_TXFIS_SHIFT (7U) 2297 #define SPI_ISR_TXFIS_MASK (0x1U << SPI_ISR_TXFIS_SHIFT) 2298 /* RISR */ 2299 #define SPI_RISR_OFFSET (0x34U) 2300 #define SPI_RISR_TFERIS_SHIFT (0U) 2301 #define SPI_RISR_TFERIS_MASK (0x1U << SPI_RISR_TFERIS_SHIFT) 2302 #define SPI_RISR_TFORIS_SHIFT (1U) 2303 #define SPI_RISR_TFORIS_MASK (0x1U << SPI_RISR_TFORIS_SHIFT) 2304 #define SPI_RISR_RFURIS_SHIFT (2U) 2305 #define SPI_RISR_RFURIS_MASK (0x1U << SPI_RISR_RFURIS_SHIFT) 2306 #define SPI_RISR_RFORIS_SHIFT (3U) 2307 #define SPI_RISR_RFORIS_MASK (0x1U << SPI_RISR_RFORIS_SHIFT) 2308 #define SPI_RISR_RFFRIS_SHIFT (4U) 2309 #define SPI_RISR_RFFRIS_MASK (0x1U << SPI_RISR_RFFRIS_SHIFT) 2310 #define SPI_RISR_TORIS_SHIFT (5U) 2311 #define SPI_RISR_TORIS_MASK (0x1U << SPI_RISR_TORIS_SHIFT) 2312 #define SPI_RISR_SSPRIS_SHIFT (6U) 2313 #define SPI_RISR_SSPRIS_MASK (0x1U << SPI_RISR_SSPRIS_SHIFT) 2314 #define SPI_RISR_TXFRIS_SHIFT (7U) 2315 #define SPI_RISR_TXFRIS_MASK (0x1U << SPI_RISR_TXFRIS_SHIFT) 2316 /* ICR */ 2317 #define SPI_ICR_OFFSET (0x38U) 2318 #define SPI_ICR_CCI_SHIFT (0U) 2319 #define SPI_ICR_CCI_MASK (0x1U << SPI_ICR_CCI_SHIFT) 2320 #define SPI_ICR_CRFUI_SHIFT (1U) 2321 #define SPI_ICR_CRFUI_MASK (0x1U << SPI_ICR_CRFUI_SHIFT) 2322 #define SPI_ICR_CRFOI_SHIFT (2U) 2323 #define SPI_ICR_CRFOI_MASK (0x1U << SPI_ICR_CRFOI_SHIFT) 2324 #define SPI_ICR_CTFOI_SHIFT (3U) 2325 #define SPI_ICR_CTFOI_MASK (0x1U << SPI_ICR_CTFOI_SHIFT) 2326 #define SPI_ICR_CTOI_SHIFT (4U) 2327 #define SPI_ICR_CTOI_MASK (0x1U << SPI_ICR_CTOI_SHIFT) 2328 #define SPI_ICR_CSSPI_SHIFT (5U) 2329 #define SPI_ICR_CSSPI_MASK (0x1U << SPI_ICR_CSSPI_SHIFT) 2330 #define SPI_ICR_CTXFI_SHIFT (6U) 2331 #define SPI_ICR_CTXFI_MASK (0x1U << SPI_ICR_CTXFI_SHIFT) 2332 /* DMACR */ 2333 #define SPI_DMACR_OFFSET (0x3CU) 2334 #define SPI_DMACR_RDE_SHIFT (0U) 2335 #define SPI_DMACR_RDE_MASK (0x1U << SPI_DMACR_RDE_SHIFT) 2336 #define SPI_DMACR_TDE_SHIFT (1U) 2337 #define SPI_DMACR_TDE_MASK (0x1U << SPI_DMACR_TDE_SHIFT) 2338 /* DMATDLR */ 2339 #define SPI_DMATDLR_OFFSET (0x40U) 2340 #define SPI_DMATDLR_TDL_SHIFT (0U) 2341 #define SPI_DMATDLR_TDL_MASK (0x3FU << SPI_DMATDLR_TDL_SHIFT) 2342 /* DMARDLR */ 2343 #define SPI_DMARDLR_OFFSET (0x44U) 2344 #define SPI_DMARDLR_RDL_SHIFT (0U) 2345 #define SPI_DMARDLR_RDL_MASK (0x3FU << SPI_DMARDLR_RDL_SHIFT) 2346 /* TIMEOUT */ 2347 #define SPI_TIMEOUT_OFFSET (0x4CU) 2348 #define SPI_TIMEOUT_TOV_SHIFT (0U) 2349 #define SPI_TIMEOUT_TOV_MASK (0xFFFFU << SPI_TIMEOUT_TOV_SHIFT) 2350 #define SPI_TIMEOUT_TOE_SHIFT (16U) 2351 #define SPI_TIMEOUT_TOE_MASK (0x1U << SPI_TIMEOUT_TOE_SHIFT) 2352 /* BYPASS */ 2353 #define SPI_BYPASS_OFFSET (0x50U) 2354 #define SPI_BYPASS_BYEN_SHIFT (0U) 2355 #define SPI_BYPASS_BYEN_MASK (0x1U << SPI_BYPASS_BYEN_SHIFT) 2356 #define SPI_BYPASS_FBM_SHIFT (1U) 2357 #define SPI_BYPASS_FBM_MASK (0x1U << SPI_BYPASS_FBM_SHIFT) 2358 #define SPI_BYPASS_END_SHIFT (2U) 2359 #define SPI_BYPASS_END_MASK (0x1U << SPI_BYPASS_END_SHIFT) 2360 #define SPI_BYPASS_RXCP_SHIFT (3U) 2361 #define SPI_BYPASS_RXCP_MASK (0x1U << SPI_BYPASS_RXCP_SHIFT) 2362 #define SPI_BYPASS_TXCP_SHIFT (4U) 2363 #define SPI_BYPASS_TXCP_MASK (0x1U << SPI_BYPASS_TXCP_SHIFT) 2364 /* TXDR */ 2365 #define SPI_TXDR_OFFSET (0x400U) 2366 #define SPI_TXDR_TXDR_SHIFT (0U) 2367 #define SPI_TXDR_TXDR_MASK (0xFFFFU << SPI_TXDR_TXDR_SHIFT) 2368 /* RXDR */ 2369 #define SPI_RXDR_OFFSET (0x800U) 2370 #define SPI_RXDR_RXDR_SHIFT (0U) 2371 #define SPI_RXDR_RXDR_MASK (0xFFFFU << SPI_RXDR_RXDR_SHIFT) 2372 /***************************************EFUSE_CTL****************************************/ 2373 /* MOD */ 2374 #define EFUSE_CTL_MOD_OFFSET (0x0U) 2375 #define EFUSE_CTL_MOD_WORK_MOD_SHIFT (0U) 2376 #define EFUSE_CTL_MOD_WORK_MOD_MASK (0x1U << EFUSE_CTL_MOD_WORK_MOD_SHIFT) 2377 #define EFUSE_CTL_MOD_CSB_POL_SHIFT (1U) 2378 #define EFUSE_CTL_MOD_CSB_POL_MASK (0x1U << EFUSE_CTL_MOD_CSB_POL_SHIFT) 2379 #define EFUSE_CTL_MOD_PGENB_POL_SHIFT (2U) 2380 #define EFUSE_CTL_MOD_PGENB_POL_MASK (0x1U << EFUSE_CTL_MOD_PGENB_POL_SHIFT) 2381 #define EFUSE_CTL_MOD_LOAD_POL_SHIFT (3U) 2382 #define EFUSE_CTL_MOD_LOAD_POL_MASK (0x1U << EFUSE_CTL_MOD_LOAD_POL_SHIFT) 2383 #define EFUSE_CTL_MOD_STROBE_POL_SHIFT (4U) 2384 #define EFUSE_CTL_MOD_STROBE_POL_MASK (0x1U << EFUSE_CTL_MOD_STROBE_POL_SHIFT) 2385 #define EFUSE_CTL_MOD_PG_EN_USER_SHIFT (5U) 2386 #define EFUSE_CTL_MOD_PG_EN_USER_MASK (0x1U << EFUSE_CTL_MOD_PG_EN_USER_SHIFT) 2387 #define EFUSE_CTL_MOD_RD_ENB_USER_SHIFT (6U) 2388 #define EFUSE_CTL_MOD_RD_ENB_USER_MASK (0x1U << EFUSE_CTL_MOD_RD_ENB_USER_SHIFT) 2389 /* RD_MASK */ 2390 #define EFUSE_CTL_RD_MASK_OFFSET (0x4U) 2391 #define EFUSE_CTL_RD_MASK_RD_MASK_SHIFT (0U) 2392 #define EFUSE_CTL_RD_MASK_RD_MASK_MASK (0xFFFFFFFFU << EFUSE_CTL_RD_MASK_RD_MASK_SHIFT) 2393 /* PG_MASK */ 2394 #define EFUSE_CTL_PG_MASK_OFFSET (0x8U) 2395 #define EFUSE_CTL_PG_MASK_PG_MASK_SHIFT (0U) 2396 #define EFUSE_CTL_PG_MASK_PG_MASK_MASK (0xFFFFFFFFU << EFUSE_CTL_PG_MASK_PG_MASK_SHIFT) 2397 /* INT_CON */ 2398 #define EFUSE_CTL_INT_CON_OFFSET (0x14U) 2399 #define EFUSE_CTL_INT_CON_FINISH_INT_EN_SHIFT (0U) 2400 #define EFUSE_CTL_INT_CON_FINISH_INT_EN_MASK (0x1U << EFUSE_CTL_INT_CON_FINISH_INT_EN_SHIFT) 2401 #define EFUSE_CTL_INT_CON_AUTO_RD_MASK_INT_EN_SHIFT (7U) 2402 #define EFUSE_CTL_INT_CON_AUTO_RD_MASK_INT_EN_MASK (0x1U << EFUSE_CTL_INT_CON_AUTO_RD_MASK_INT_EN_SHIFT) 2403 #define EFUSE_CTL_INT_CON_AUTO_PG_MASK_INT_EN_SHIFT (8U) 2404 #define EFUSE_CTL_INT_CON_AUTO_PG_MASK_INT_EN_MASK (0x1U << EFUSE_CTL_INT_CON_AUTO_PG_MASK_INT_EN_SHIFT) 2405 #define EFUSE_CTL_INT_CON_USER_RD_MASK_INT_EN_SHIFT (11U) 2406 #define EFUSE_CTL_INT_CON_USER_RD_MASK_INT_EN_MASK (0x1U << EFUSE_CTL_INT_CON_USER_RD_MASK_INT_EN_SHIFT) 2407 #define EFUSE_CTL_INT_CON_USER_PG_MASK_INT_EN_SHIFT (12U) 2408 #define EFUSE_CTL_INT_CON_USER_PG_MASK_INT_EN_MASK (0x1U << EFUSE_CTL_INT_CON_USER_PG_MASK_INT_EN_SHIFT) 2409 /* INT_STATUS */ 2410 #define EFUSE_CTL_INT_STATUS_OFFSET (0x18U) 2411 #define EFUSE_CTL_INT_STATUS_FINISH_INT_SHIFT (0U) 2412 #define EFUSE_CTL_INT_STATUS_FINISH_INT_MASK (0x1U << EFUSE_CTL_INT_STATUS_FINISH_INT_SHIFT) 2413 #define EFUSE_CTL_INT_STATUS_AUTO_RD_MASK_INT_SHIFT (7U) 2414 #define EFUSE_CTL_INT_STATUS_AUTO_RD_MASK_INT_MASK (0x1U << EFUSE_CTL_INT_STATUS_AUTO_RD_MASK_INT_SHIFT) 2415 #define EFUSE_CTL_INT_STATUS_AUTO_PG_MASK_INT_SHIFT (8U) 2416 #define EFUSE_CTL_INT_STATUS_AUTO_PG_MASK_INT_MASK (0x1U << EFUSE_CTL_INT_STATUS_AUTO_PG_MASK_INT_SHIFT) 2417 #define EFUSE_CTL_INT_STATUS_USER_RD_MASK_INT_SHIFT (11U) 2418 #define EFUSE_CTL_INT_STATUS_USER_RD_MASK_INT_MASK (0x1U << EFUSE_CTL_INT_STATUS_USER_RD_MASK_INT_SHIFT) 2419 #define EFUSE_CTL_INT_STATUS_USER_PG_MASK_INT_SHIFT (12U) 2420 #define EFUSE_CTL_INT_STATUS_USER_PG_MASK_INT_MASK (0x1U << EFUSE_CTL_INT_STATUS_USER_PG_MASK_INT_SHIFT) 2421 /* USER_CTRL */ 2422 #define EFUSE_CTL_USER_CTRL_OFFSET (0x1CU) 2423 #define EFUSE_CTL_USER_CTRL_CSB_USER_SHIFT (0U) 2424 #define EFUSE_CTL_USER_CTRL_CSB_USER_MASK (0x1U << EFUSE_CTL_USER_CTRL_CSB_USER_SHIFT) 2425 #define EFUSE_CTL_USER_CTRL_STROBE_USER_SHIFT (1U) 2426 #define EFUSE_CTL_USER_CTRL_STROBE_USER_MASK (0x1U << EFUSE_CTL_USER_CTRL_STROBE_USER_SHIFT) 2427 #define EFUSE_CTL_USER_CTRL_LOAD_USER_SHIFT (2U) 2428 #define EFUSE_CTL_USER_CTRL_LOAD_USER_MASK (0x1U << EFUSE_CTL_USER_CTRL_LOAD_USER_SHIFT) 2429 #define EFUSE_CTL_USER_CTRL_PGENB_USER_SHIFT (3U) 2430 #define EFUSE_CTL_USER_CTRL_PGENB_USER_MASK (0x1U << EFUSE_CTL_USER_CTRL_PGENB_USER_SHIFT) 2431 #define EFUSE_CTL_USER_CTRL_ADDR_USER_SHIFT (16U) 2432 #define EFUSE_CTL_USER_CTRL_ADDR_USER_MASK (0x3FFU << EFUSE_CTL_USER_CTRL_ADDR_USER_SHIFT) 2433 /* DOUT */ 2434 #define EFUSE_CTL_DOUT_OFFSET (0x20U) 2435 #define EFUSE_CTL_DOUT (0x0U) 2436 #define EFUSE_CTL_DOUT_DOUT_SHIFT (0U) 2437 #define EFUSE_CTL_DOUT_DOUT_MASK (0xFFU << EFUSE_CTL_DOUT_DOUT_SHIFT) 2438 /* AUTO_CTRL */ 2439 #define EFUSE_CTL_AUTO_CTRL_OFFSET (0x24U) 2440 #define EFUSE_CTL_AUTO_CTRL_ENB_SHIFT (0U) 2441 #define EFUSE_CTL_AUTO_CTRL_ENB_MASK (0x1U << EFUSE_CTL_AUTO_CTRL_ENB_SHIFT) 2442 #define EFUSE_CTL_AUTO_CTRL_PG_R_SHIFT (1U) 2443 #define EFUSE_CTL_AUTO_CTRL_PG_R_MASK (0x1U << EFUSE_CTL_AUTO_CTRL_PG_R_SHIFT) 2444 #define EFUSE_CTL_AUTO_CTRL_ADDR_AUTO_SHIFT (16U) 2445 #define EFUSE_CTL_AUTO_CTRL_ADDR_AUTO_MASK (0x3FFU << EFUSE_CTL_AUTO_CTRL_ADDR_AUTO_SHIFT) 2446 /* T_CSB_P */ 2447 #define EFUSE_CTL_T_CSB_P_OFFSET (0x28U) 2448 #define EFUSE_CTL_T_CSB_P_T_CSB_P_L_SHIFT (0U) 2449 #define EFUSE_CTL_T_CSB_P_T_CSB_P_L_MASK (0x7FFU << EFUSE_CTL_T_CSB_P_T_CSB_P_L_SHIFT) 2450 #define EFUSE_CTL_T_CSB_P_T_CSB_P_S_SHIFT (16U) 2451 #define EFUSE_CTL_T_CSB_P_T_CSB_P_S_MASK (0xFU << EFUSE_CTL_T_CSB_P_T_CSB_P_S_SHIFT) 2452 /* T_PGENB_P */ 2453 #define EFUSE_CTL_T_PGENB_P_OFFSET (0x2CU) 2454 #define EFUSE_CTL_T_PGENB_P_T_PGENB_P_L_SHIFT (0U) 2455 #define EFUSE_CTL_T_PGENB_P_T_PGENB_P_L_MASK (0x7FFU << EFUSE_CTL_T_PGENB_P_T_PGENB_P_L_SHIFT) 2456 #define EFUSE_CTL_T_PGENB_P_T_PGENB_P_S_SHIFT (16U) 2457 #define EFUSE_CTL_T_PGENB_P_T_PGENB_P_S_MASK (0xFU << EFUSE_CTL_T_PGENB_P_T_PGENB_P_S_SHIFT) 2458 /* T_LOAD_P */ 2459 #define EFUSE_CTL_T_LOAD_P_OFFSET (0x30U) 2460 #define EFUSE_CTL_T_LOAD_P_T_LOAD_P_L_SHIFT (0U) 2461 #define EFUSE_CTL_T_LOAD_P_T_LOAD_P_L_MASK (0x7FFU << EFUSE_CTL_T_LOAD_P_T_LOAD_P_L_SHIFT) 2462 #define EFUSE_CTL_T_LOAD_P_T_LOAD_P_S_SHIFT (16U) 2463 #define EFUSE_CTL_T_LOAD_P_T_LOAD_P_S_MASK (0xFU << EFUSE_CTL_T_LOAD_P_T_LOAD_P_S_SHIFT) 2464 /* T_ADDR_P */ 2465 #define EFUSE_CTL_T_ADDR_P_OFFSET (0x34U) 2466 #define EFUSE_CTL_T_ADDR_P_T_ADDR_P_L_SHIFT (0U) 2467 #define EFUSE_CTL_T_ADDR_P_T_ADDR_P_L_MASK (0x7FFU << EFUSE_CTL_T_ADDR_P_T_ADDR_P_L_SHIFT) 2468 #define EFUSE_CTL_T_ADDR_P_T_ADDR_P_S_SHIFT (16U) 2469 #define EFUSE_CTL_T_ADDR_P_T_ADDR_P_S_MASK (0xFU << EFUSE_CTL_T_ADDR_P_T_ADDR_P_S_SHIFT) 2470 /* T_STROBE_P */ 2471 #define EFUSE_CTL_T_STROBE_P_OFFSET (0x38U) 2472 #define EFUSE_CTL_T_STROBE_P_T_STROBE_P_L_SHIFT (0U) 2473 #define EFUSE_CTL_T_STROBE_P_T_STROBE_P_L_MASK (0x7FFU << EFUSE_CTL_T_STROBE_P_T_STROBE_P_L_SHIFT) 2474 #define EFUSE_CTL_T_STROBE_P_T_STROBE_P_S_SHIFT (16U) 2475 #define EFUSE_CTL_T_STROBE_P_T_STROBE_P_S_MASK (0xFFU << EFUSE_CTL_T_STROBE_P_T_STROBE_P_S_SHIFT) 2476 /* T_CSB_R */ 2477 #define EFUSE_CTL_T_CSB_R_OFFSET (0x3CU) 2478 #define EFUSE_CTL_T_CSB_R_T_CSB_R_L_SHIFT (0U) 2479 #define EFUSE_CTL_T_CSB_R_T_CSB_R_L_MASK (0x3FFU << EFUSE_CTL_T_CSB_R_T_CSB_R_L_SHIFT) 2480 #define EFUSE_CTL_T_CSB_R_T_CSB_R_S_SHIFT (16U) 2481 #define EFUSE_CTL_T_CSB_R_T_CSB_R_S_MASK (0xFU << EFUSE_CTL_T_CSB_R_T_CSB_R_S_SHIFT) 2482 /* T_PGENB_R */ 2483 #define EFUSE_CTL_T_PGENB_R_OFFSET (0x40U) 2484 #define EFUSE_CTL_T_PGENB_R_T_PGENB_R_L_SHIFT (0U) 2485 #define EFUSE_CTL_T_PGENB_R_T_PGENB_R_L_MASK (0x3FFU << EFUSE_CTL_T_PGENB_R_T_PGENB_R_L_SHIFT) 2486 #define EFUSE_CTL_T_PGENB_R_T_PGENB_R_S_SHIFT (16U) 2487 #define EFUSE_CTL_T_PGENB_R_T_PGENB_R_S_MASK (0xFU << EFUSE_CTL_T_PGENB_R_T_PGENB_R_S_SHIFT) 2488 /* T_LOAD_R */ 2489 #define EFUSE_CTL_T_LOAD_R_OFFSET (0x44U) 2490 #define EFUSE_CTL_T_LOAD_R_T_LOAD_R_L_SHIFT (0U) 2491 #define EFUSE_CTL_T_LOAD_R_T_LOAD_R_L_MASK (0x3FFU << EFUSE_CTL_T_LOAD_R_T_LOAD_R_L_SHIFT) 2492 #define EFUSE_CTL_T_LOAD_R_T_LOAD_R_S_SHIFT (16U) 2493 #define EFUSE_CTL_T_LOAD_R_T_LOAD_R_S_MASK (0xFU << EFUSE_CTL_T_LOAD_R_T_LOAD_R_S_SHIFT) 2494 /* T_ADDR_R */ 2495 #define EFUSE_CTL_T_ADDR_R_OFFSET (0x48U) 2496 #define EFUSE_CTL_T_ADDR_R_T_ADDR_R_L_SHIFT (0U) 2497 #define EFUSE_CTL_T_ADDR_R_T_ADDR_R_L_MASK (0x3FFU << EFUSE_CTL_T_ADDR_R_T_ADDR_R_L_SHIFT) 2498 #define EFUSE_CTL_T_ADDR_R_T_ADDR_R_S_SHIFT (16U) 2499 #define EFUSE_CTL_T_ADDR_R_T_ADDR_R_S_MASK (0xFU << EFUSE_CTL_T_ADDR_R_T_ADDR_R_S_SHIFT) 2500 /* T_STROBE_R */ 2501 #define EFUSE_CTL_T_STROBE_R_OFFSET (0x4CU) 2502 #define EFUSE_CTL_T_STROBE_R_T_STROBE_R_L_SHIFT (0U) 2503 #define EFUSE_CTL_T_STROBE_R_T_STROBE_R_L_MASK (0x3FFU << EFUSE_CTL_T_STROBE_R_T_STROBE_R_L_SHIFT) 2504 #define EFUSE_CTL_T_STROBE_R_T_STROBE_R_S_SHIFT (16U) 2505 #define EFUSE_CTL_T_STROBE_R_T_STROBE_R_S_MASK (0xFU << EFUSE_CTL_T_STROBE_R_T_STROBE_R_S_SHIFT) 2506 /* REVISION */ 2507 #define EFUSE_CTL_REVISION_OFFSET (0x50U) 2508 #define EFUSE_CTL_REVISION_REVISION_SHIFT (0U) 2509 #define EFUSE_CTL_REVISION_REVISION_MASK (0xFFU << EFUSE_CTL_REVISION_REVISION_SHIFT) 2510 /******************************************MBOX******************************************/ 2511 /* A2B_INTEN */ 2512 #define MBOX_A2B_INTEN_OFFSET (0x0U) 2513 #define MBOX_A2B_INTEN_INT0_SHIFT (0U) 2514 #define MBOX_A2B_INTEN_INT0_MASK (0x1U << MBOX_A2B_INTEN_INT0_SHIFT) 2515 #define MBOX_A2B_INTEN_INT1_SHIFT (1U) 2516 #define MBOX_A2B_INTEN_INT1_MASK (0x1U << MBOX_A2B_INTEN_INT1_SHIFT) 2517 #define MBOX_A2B_INTEN_INT2_SHIFT (2U) 2518 #define MBOX_A2B_INTEN_INT2_MASK (0x1U << MBOX_A2B_INTEN_INT2_SHIFT) 2519 #define MBOX_A2B_INTEN_INT3_SHIFT (3U) 2520 #define MBOX_A2B_INTEN_INT3_MASK (0x1U << MBOX_A2B_INTEN_INT3_SHIFT) 2521 /* A2B_STATUS */ 2522 #define MBOX_A2B_STATUS_OFFSET (0x4U) 2523 #define MBOX_A2B_STATUS_INT0_SHIFT (0U) 2524 #define MBOX_A2B_STATUS_INT0_MASK (0x1U << MBOX_A2B_STATUS_INT0_SHIFT) 2525 #define MBOX_A2B_STATUS_INT1_SHIFT (1U) 2526 #define MBOX_A2B_STATUS_INT1_MASK (0x1U << MBOX_A2B_STATUS_INT1_SHIFT) 2527 #define MBOX_A2B_STATUS_INT2_SHIFT (2U) 2528 #define MBOX_A2B_STATUS_INT2_MASK (0x1U << MBOX_A2B_STATUS_INT2_SHIFT) 2529 #define MBOX_A2B_STATUS_INT3_SHIFT (3U) 2530 #define MBOX_A2B_STATUS_INT3_MASK (0x1U << MBOX_A2B_STATUS_INT3_SHIFT) 2531 /* A2B_CMD_0 */ 2532 #define MBOX_A2B_CMD_0_OFFSET (0x8U) 2533 #define MBOX_A2B_CMD_0_COMMAND_SHIFT (0U) 2534 #define MBOX_A2B_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_0_COMMAND_SHIFT) 2535 /* A2B_DAT_0 */ 2536 #define MBOX_A2B_DAT_0_OFFSET (0xCU) 2537 #define MBOX_A2B_DAT_0_DATA_SHIFT (0U) 2538 #define MBOX_A2B_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_0_DATA_SHIFT) 2539 /* A2B_CMD_1 */ 2540 #define MBOX_A2B_CMD_1_OFFSET (0x10U) 2541 #define MBOX_A2B_CMD_1_COMMAND_SHIFT (0U) 2542 #define MBOX_A2B_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_1_COMMAND_SHIFT) 2543 /* A2B_DAT_1 */ 2544 #define MBOX_A2B_DAT_1_OFFSET (0x14U) 2545 #define MBOX_A2B_DAT_1_DATA_SHIFT (0U) 2546 #define MBOX_A2B_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_1_DATA_SHIFT) 2547 /* A2B_CMD_2 */ 2548 #define MBOX_A2B_CMD_2_OFFSET (0x18U) 2549 #define MBOX_A2B_CMD_2_COMMAND_SHIFT (0U) 2550 #define MBOX_A2B_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_2_COMMAND_SHIFT) 2551 /* A2B_DAT_2 */ 2552 #define MBOX_A2B_DAT_2_OFFSET (0x1CU) 2553 #define MBOX_A2B_DAT_2_DATA_SHIFT (0U) 2554 #define MBOX_A2B_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_2_DATA_SHIFT) 2555 /* A2B_CMD_3 */ 2556 #define MBOX_A2B_CMD_3_OFFSET (0x20U) 2557 #define MBOX_A2B_CMD_3_COMMAND_SHIFT (0U) 2558 #define MBOX_A2B_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_3_COMMAND_SHIFT) 2559 /* A2B_DAT_3 */ 2560 #define MBOX_A2B_DAT_3_OFFSET (0x24U) 2561 #define MBOX_A2B_DAT_3_DATA_SHIFT (0U) 2562 #define MBOX_A2B_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_3_DATA_SHIFT) 2563 /* B2A_INTEN */ 2564 #define MBOX_B2A_INTEN_OFFSET (0x28U) 2565 #define MBOX_B2A_INTEN_INT0_SHIFT (0U) 2566 #define MBOX_B2A_INTEN_INT0_MASK (0x1U << MBOX_B2A_INTEN_INT0_SHIFT) 2567 #define MBOX_B2A_INTEN_INT1_SHIFT (1U) 2568 #define MBOX_B2A_INTEN_INT1_MASK (0x1U << MBOX_B2A_INTEN_INT1_SHIFT) 2569 #define MBOX_B2A_INTEN_INT2_SHIFT (2U) 2570 #define MBOX_B2A_INTEN_INT2_MASK (0x1U << MBOX_B2A_INTEN_INT2_SHIFT) 2571 #define MBOX_B2A_INTEN_INT3_SHIFT (3U) 2572 #define MBOX_B2A_INTEN_INT3_MASK (0x1U << MBOX_B2A_INTEN_INT3_SHIFT) 2573 /* B2A_STATUS */ 2574 #define MBOX_B2A_STATUS_OFFSET (0x2CU) 2575 #define MBOX_B2A_STATUS_INT0_SHIFT (0U) 2576 #define MBOX_B2A_STATUS_INT0_MASK (0x1U << MBOX_B2A_STATUS_INT0_SHIFT) 2577 #define MBOX_B2A_STATUS_INT1_SHIFT (1U) 2578 #define MBOX_B2A_STATUS_INT1_MASK (0x1U << MBOX_B2A_STATUS_INT1_SHIFT) 2579 #define MBOX_B2A_STATUS_INT2_SHIFT (2U) 2580 #define MBOX_B2A_STATUS_INT2_MASK (0x1U << MBOX_B2A_STATUS_INT2_SHIFT) 2581 #define MBOX_B2A_STATUS_INT3_SHIFT (3U) 2582 #define MBOX_B2A_STATUS_INT3_MASK (0x1U << MBOX_B2A_STATUS_INT3_SHIFT) 2583 /* B2A_CMD_0 */ 2584 #define MBOX_B2A_CMD_0_OFFSET (0x30U) 2585 #define MBOX_B2A_CMD_0_COMMAND_SHIFT (0U) 2586 #define MBOX_B2A_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_0_COMMAND_SHIFT) 2587 /* B2A_DAT_0 */ 2588 #define MBOX_B2A_DAT_0_OFFSET (0x34U) 2589 #define MBOX_B2A_DAT_0_DATA_SHIFT (0U) 2590 #define MBOX_B2A_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_0_DATA_SHIFT) 2591 /* B2A_CMD_1 */ 2592 #define MBOX_B2A_CMD_1_OFFSET (0x38U) 2593 #define MBOX_B2A_CMD_1_COMMAND_SHIFT (0U) 2594 #define MBOX_B2A_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_1_COMMAND_SHIFT) 2595 /* B2A_DAT_1 */ 2596 #define MBOX_B2A_DAT_1_OFFSET (0x3CU) 2597 #define MBOX_B2A_DAT_1_DATA_SHIFT (0U) 2598 #define MBOX_B2A_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_1_DATA_SHIFT) 2599 /* B2A_CMD_2 */ 2600 #define MBOX_B2A_CMD_2_OFFSET (0x40U) 2601 #define MBOX_B2A_CMD_2_COMMAND_SHIFT (0U) 2602 #define MBOX_B2A_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_2_COMMAND_SHIFT) 2603 /* B2A_DAT_2 */ 2604 #define MBOX_B2A_DAT_2_OFFSET (0x44U) 2605 #define MBOX_B2A_DAT_2_DATA_SHIFT (0U) 2606 #define MBOX_B2A_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_2_DATA_SHIFT) 2607 /* B2A_CMD_3 */ 2608 #define MBOX_B2A_CMD_3_OFFSET (0x48U) 2609 #define MBOX_B2A_CMD_3_COMMAND_SHIFT (0U) 2610 #define MBOX_B2A_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_3_COMMAND_SHIFT) 2611 /* B2A_DAT_3 */ 2612 #define MBOX_B2A_DAT_3_OFFSET (0x4CU) 2613 #define MBOX_B2A_DAT_3_DATA_SHIFT (0U) 2614 #define MBOX_B2A_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_3_DATA_SHIFT) 2615 /* ATOMIC_LOCK_00 */ 2616 #define MBOX_ATOMIC_LOCK_00_OFFSET (0x100U) 2617 #define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT (0U) 2618 #define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_MASK (0x1U << MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT) 2619 /* ATOMIC_LOCK_01 */ 2620 #define MBOX_ATOMIC_LOCK_01_OFFSET (0x104U) 2621 #define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT (0U) 2622 #define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_MASK (0x1U << MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT) 2623 /* ATOMIC_LOCK_02 */ 2624 #define MBOX_ATOMIC_LOCK_02_OFFSET (0x108U) 2625 #define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT (0U) 2626 #define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_MASK (0x1U << MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT) 2627 /* ATOMIC_LOCK_03 */ 2628 #define MBOX_ATOMIC_LOCK_03_OFFSET (0x10CU) 2629 #define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT (0U) 2630 #define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_MASK (0x1U << MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT) 2631 /* ATOMIC_LOCK_04 */ 2632 #define MBOX_ATOMIC_LOCK_04_OFFSET (0x110U) 2633 #define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT (0U) 2634 #define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_MASK (0x1U << MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT) 2635 /* ATOMIC_LOCK_05 */ 2636 #define MBOX_ATOMIC_LOCK_05_OFFSET (0x114U) 2637 #define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT (0U) 2638 #define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_MASK (0x1U << MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT) 2639 /* ATOMIC_LOCK_06 */ 2640 #define MBOX_ATOMIC_LOCK_06_OFFSET (0x118U) 2641 #define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT (0U) 2642 #define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_MASK (0x1U << MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT) 2643 /* ATOMIC_LOCK_07 */ 2644 #define MBOX_ATOMIC_LOCK_07_OFFSET (0x11CU) 2645 #define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT (0U) 2646 #define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_MASK (0x1U << MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT) 2647 /* ATOMIC_LOCK_08 */ 2648 #define MBOX_ATOMIC_LOCK_08_OFFSET (0x120U) 2649 #define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT (0U) 2650 #define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_MASK (0x1U << MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT) 2651 /* ATOMIC_LOCK_09 */ 2652 #define MBOX_ATOMIC_LOCK_09_OFFSET (0x124U) 2653 #define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT (0U) 2654 #define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_MASK (0x1U << MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT) 2655 /* ATOMIC_LOCK_10 */ 2656 #define MBOX_ATOMIC_LOCK_10_OFFSET (0x128U) 2657 #define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT (0U) 2658 #define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_MASK (0x1U << MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT) 2659 /* ATOMIC_LOCK_11 */ 2660 #define MBOX_ATOMIC_LOCK_11_OFFSET (0x12CU) 2661 #define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT (0U) 2662 #define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_MASK (0x1U << MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT) 2663 /* ATOMIC_LOCK_12 */ 2664 #define MBOX_ATOMIC_LOCK_12_OFFSET (0x130U) 2665 #define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT (0U) 2666 #define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_MASK (0x1U << MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT) 2667 /* ATOMIC_LOCK_13 */ 2668 #define MBOX_ATOMIC_LOCK_13_OFFSET (0x134U) 2669 #define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT (0U) 2670 #define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_MASK (0x1U << MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT) 2671 /* ATOMIC_LOCK_14 */ 2672 #define MBOX_ATOMIC_LOCK_14_OFFSET (0x138U) 2673 #define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT (0U) 2674 #define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_MASK (0x1U << MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT) 2675 /* ATOMIC_LOCK_15 */ 2676 #define MBOX_ATOMIC_LOCK_15_OFFSET (0x13CU) 2677 #define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT (0U) 2678 #define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_MASK (0x1U << MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT) 2679 /* ATOMIC_LOCK_16 */ 2680 #define MBOX_ATOMIC_LOCK_16_OFFSET (0x140U) 2681 #define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT (0U) 2682 #define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_MASK (0x1U << MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT) 2683 /* ATOMIC_LOCK_17 */ 2684 #define MBOX_ATOMIC_LOCK_17_OFFSET (0x144U) 2685 #define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT (0U) 2686 #define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_MASK (0x1U << MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT) 2687 /* ATOMIC_LOCK_18 */ 2688 #define MBOX_ATOMIC_LOCK_18_OFFSET (0x148U) 2689 #define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT (0U) 2690 #define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_MASK (0x1U << MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT) 2691 /* ATOMIC_LOCK_19 */ 2692 #define MBOX_ATOMIC_LOCK_19_OFFSET (0x14CU) 2693 #define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT (0U) 2694 #define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_MASK (0x1U << MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT) 2695 /* ATOMIC_LOCK_20 */ 2696 #define MBOX_ATOMIC_LOCK_20_OFFSET (0x150U) 2697 #define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT (0U) 2698 #define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_MASK (0x1U << MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT) 2699 /* ATOMIC_LOCK_21 */ 2700 #define MBOX_ATOMIC_LOCK_21_OFFSET (0x154U) 2701 #define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT (0U) 2702 #define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_MASK (0x1U << MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT) 2703 /* ATOMIC_LOCK_22 */ 2704 #define MBOX_ATOMIC_LOCK_22_OFFSET (0x158U) 2705 #define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT (0U) 2706 #define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_MASK (0x1U << MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT) 2707 /* ATOMIC_LOCK_23 */ 2708 #define MBOX_ATOMIC_LOCK_23_OFFSET (0x15CU) 2709 #define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT (0U) 2710 #define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_MASK (0x1U << MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT) 2711 /* ATOMIC_LOCK_24 */ 2712 #define MBOX_ATOMIC_LOCK_24_OFFSET (0x160U) 2713 #define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT (0U) 2714 #define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_MASK (0x1U << MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT) 2715 /* ATOMIC_LOCK_25 */ 2716 #define MBOX_ATOMIC_LOCK_25_OFFSET (0x164U) 2717 #define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT (0U) 2718 #define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_MASK (0x1U << MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT) 2719 /* ATOMIC_LOCK_26 */ 2720 #define MBOX_ATOMIC_LOCK_26_OFFSET (0x168U) 2721 #define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT (0U) 2722 #define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_MASK (0x1U << MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT) 2723 /* ATOMIC_LOCK_27 */ 2724 #define MBOX_ATOMIC_LOCK_27_OFFSET (0x16CU) 2725 #define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT (0U) 2726 #define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_MASK (0x1U << MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT) 2727 /* ATOMIC_LOCK_28 */ 2728 #define MBOX_ATOMIC_LOCK_28_OFFSET (0x170U) 2729 #define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT (0U) 2730 #define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_MASK (0x1U << MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT) 2731 /* ATOMIC_LOCK_29 */ 2732 #define MBOX_ATOMIC_LOCK_29_OFFSET (0x174U) 2733 #define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT (0U) 2734 #define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_MASK (0x1U << MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT) 2735 /* ATOMIC_LOCK_30 */ 2736 #define MBOX_ATOMIC_LOCK_30_OFFSET (0x178U) 2737 #define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT (0U) 2738 #define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_MASK (0x1U << MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT) 2739 /* ATOMIC_LOCK_31 */ 2740 #define MBOX_ATOMIC_LOCK_31_OFFSET (0x17CU) 2741 #define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT (0U) 2742 #define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_MASK (0x1U << MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT) 2743 /*****************************************SARADC*****************************************/ 2744 /* DATA */ 2745 #define SARADC_DATA_OFFSET (0x0U) 2746 #define SARADC_DATA (0x0U) 2747 #define SARADC_DATA_ADC_DATA_SHIFT (0U) 2748 #define SARADC_DATA_ADC_DATA_MASK (0x3FFU << SARADC_DATA_ADC_DATA_SHIFT) 2749 /* STAS */ 2750 #define SARADC_STAS_OFFSET (0x4U) 2751 #define SARADC_STAS (0x0U) 2752 #define SARADC_STAS_ADC_STATUS_SHIFT (0U) 2753 #define SARADC_STAS_ADC_STATUS_MASK (0x1U << SARADC_STAS_ADC_STATUS_SHIFT) 2754 /* CTRL */ 2755 #define SARADC_CTRL_OFFSET (0x8U) 2756 #define SARADC_CTRL_ADC_INPUT_SRC_SEL_SHIFT (0U) 2757 #define SARADC_CTRL_ADC_INPUT_SRC_SEL_MASK (0x7U << SARADC_CTRL_ADC_INPUT_SRC_SEL_SHIFT) 2758 #define SARADC_CTRL_ADC_POWER_CTRL_SHIFT (3U) 2759 #define SARADC_CTRL_ADC_POWER_CTRL_MASK (0x1U << SARADC_CTRL_ADC_POWER_CTRL_SHIFT) 2760 #define SARADC_CTRL_INT_EN_SHIFT (5U) 2761 #define SARADC_CTRL_INT_EN_MASK (0x1U << SARADC_CTRL_INT_EN_SHIFT) 2762 #define SARADC_CTRL_INT_STATUS_SHIFT (6U) 2763 #define SARADC_CTRL_INT_STATUS_MASK (0x1U << SARADC_CTRL_INT_STATUS_SHIFT) 2764 /* DLY_PU_SOC */ 2765 #define SARADC_DLY_PU_SOC_OFFSET (0xCU) 2766 #define SARADC_DLY_PU_SOC_DLY_PU_SOC_SHIFT (0U) 2767 #define SARADC_DLY_PU_SOC_DLY_PU_SOC_MASK (0x3FU << SARADC_DLY_PU_SOC_DLY_PU_SOC_SHIFT) 2768 /******************************************INTC******************************************/ 2769 /* IRQ_INTEN_L */ 2770 #define INTC_IRQ_INTEN_L_OFFSET (0x0U) 2771 #define INTC_IRQ_INTEN_L_IRQ_INTEN_L_SHIFT (0U) 2772 #define INTC_IRQ_INTEN_L_IRQ_INTEN_L_MASK (0xFFFFFFFFU << INTC_IRQ_INTEN_L_IRQ_INTEN_L_SHIFT) 2773 /* IRQ_INTEN_H */ 2774 #define INTC_IRQ_INTEN_H_OFFSET (0x4U) 2775 #define INTC_IRQ_INTEN_H_IRQ_INTEN_H_SHIFT (0U) 2776 #define INTC_IRQ_INTEN_H_IRQ_INTEN_H_MASK (0xFFFFFFFFU << INTC_IRQ_INTEN_H_IRQ_INTEN_H_SHIFT) 2777 /* IRQ_INTMASK_L */ 2778 #define INTC_IRQ_INTMASK_L_OFFSET (0x8U) 2779 #define INTC_IRQ_INTMASK_L_IRQ_INTMASK_L_SHIFT (0U) 2780 #define INTC_IRQ_INTMASK_L_IRQ_INTMASK_L_MASK (0xFFFFFFFFU << INTC_IRQ_INTMASK_L_IRQ_INTMASK_L_SHIFT) 2781 /* IRQ_INTMASK_H */ 2782 #define INTC_IRQ_INTMASK_H_OFFSET (0xCU) 2783 #define INTC_IRQ_INTMASK_H_IRQ_INTMASK_H_SHIFT (0U) 2784 #define INTC_IRQ_INTMASK_H_IRQ_INTMASK_H_MASK (0xFFFFFFFFU << INTC_IRQ_INTMASK_H_IRQ_INTMASK_H_SHIFT) 2785 /* IRQ_INTFORCE_L */ 2786 #define INTC_IRQ_INTFORCE_L_OFFSET (0x10U) 2787 #define INTC_IRQ_INTFORCE_L_IRQ_INTFORCE_L_SHIFT (0U) 2788 #define INTC_IRQ_INTFORCE_L_IRQ_INTFORCE_L_MASK (0xFFFFFFFFU << INTC_IRQ_INTFORCE_L_IRQ_INTFORCE_L_SHIFT) 2789 /* IRQ_INTFORCE_H */ 2790 #define INTC_IRQ_INTFORCE_H_OFFSET (0x14U) 2791 #define INTC_IRQ_INTFORCE_H_IRQ_INTFORCE_H_SHIFT (0U) 2792 #define INTC_IRQ_INTFORCE_H_IRQ_INTFORCE_H_MASK (0xFFFFFFFFU << INTC_IRQ_INTFORCE_H_IRQ_INTFORCE_H_SHIFT) 2793 /* IRQ_RAWSTATUS_L */ 2794 #define INTC_IRQ_RAWSTATUS_L_OFFSET (0x18U) 2795 #define INTC_IRQ_RAWSTATUS_L (0x0U) 2796 #define INTC_IRQ_RAWSTATUS_L_IRQ_RAWSTATUS_L_SHIFT (0U) 2797 #define INTC_IRQ_RAWSTATUS_L_IRQ_RAWSTATUS_L_MASK (0xFFFFFFFFU << INTC_IRQ_RAWSTATUS_L_IRQ_RAWSTATUS_L_SHIFT) 2798 /* IRQ_RAWSTATUS_H */ 2799 #define INTC_IRQ_RAWSTATUS_H_OFFSET (0x1CU) 2800 #define INTC_IRQ_RAWSTATUS_H (0x0U) 2801 #define INTC_IRQ_RAWSTATUS_H_IRQ_RAWSTATUS_H_SHIFT (0U) 2802 #define INTC_IRQ_RAWSTATUS_H_IRQ_RAWSTATUS_H_MASK (0xFFFFFFFFU << INTC_IRQ_RAWSTATUS_H_IRQ_RAWSTATUS_H_SHIFT) 2803 /* IRQ_STATUS_L */ 2804 #define INTC_IRQ_STATUS_L_OFFSET (0x20U) 2805 #define INTC_IRQ_STATUS_L (0x0U) 2806 #define INTC_IRQ_STATUS_L_IRQ_STATUS_L_SHIFT (0U) 2807 #define INTC_IRQ_STATUS_L_IRQ_STATUS_L_MASK (0xFFFFFFFFU << INTC_IRQ_STATUS_L_IRQ_STATUS_L_SHIFT) 2808 /* IRQ_STATUS_H */ 2809 #define INTC_IRQ_STATUS_H_OFFSET (0x24U) 2810 #define INTC_IRQ_STATUS_H (0x0U) 2811 #define INTC_IRQ_STATUS_H_IRQ_STATUS_H_SHIFT (0U) 2812 #define INTC_IRQ_STATUS_H_IRQ_STATUS_H_MASK (0xFFFFFFFFU << INTC_IRQ_STATUS_H_IRQ_STATUS_H_SHIFT) 2813 /* IRQ_MASKSTATUS_L */ 2814 #define INTC_IRQ_MASKSTATUS_L_OFFSET (0x28U) 2815 #define INTC_IRQ_MASKSTATUS_L (0x0U) 2816 #define INTC_IRQ_MASKSTATUS_L_IRQ_MASKSTATUS_L_SHIFT (0U) 2817 #define INTC_IRQ_MASKSTATUS_L_IRQ_MASKSTATUS_L_MASK \ 2818 (0xFFFFFFFFU << INTC_IRQ_MASKSTATUS_L_IRQ_MASKSTATUS_L_SHIFT) 2819 /* IRQ_MASKSTATUS_H */ 2820 #define INTC_IRQ_MASKSTATUS_H_OFFSET (0x2CU) 2821 #define INTC_IRQ_MASKSTATUS_H (0x0U) 2822 #define INTC_IRQ_MASKSTATUS_H_IRQ_MASKSTATUS_H_SHIFT (0U) 2823 #define INTC_IRQ_MASKSTATUS_H_IRQ_MASKSTATUS_H_MASK \ 2824 (0xFFFFFFFFU << INTC_IRQ_MASKSTATUS_H_IRQ_MASKSTATUS_H_SHIFT) 2825 /* IRQ_FINALSTATUS_L */ 2826 #define INTC_IRQ_FINALSTATUS_L_OFFSET (0x30U) 2827 #define INTC_IRQ_FINALSTATUS_L (0x0U) 2828 #define INTC_IRQ_FINALSTATUS_L_IRQ_FINALSTATUS_L_SHIFT (0U) 2829 #define INTC_IRQ_FINALSTATUS_L_IRQ_FINALSTATUS_L_MASK \ 2830 (0xFFFFFFFFU << INTC_IRQ_FINALSTATUS_L_IRQ_FINALSTATUS_L_SHIFT) 2831 /* IRQ_FINALSTATUS_H */ 2832 #define INTC_IRQ_FINALSTATUS_H_OFFSET (0x34U) 2833 #define INTC_IRQ_FINALSTATUS_H (0x0U) 2834 #define INTC_IRQ_FINALSTATUS_H_IRQ_FINALSTATUS_H_SHIFT (0U) 2835 #define INTC_IRQ_FINALSTATUS_H_IRQ_FINALSTATUS_H_MASK \ 2836 (0xFFFFFFFFU << INTC_IRQ_FINALSTATUS_H_IRQ_FINALSTATUS_H_SHIFT) 2837 /* FIQ_INTEN */ 2838 #define INTC_FIQ_INTEN_OFFSET (0xC0U) 2839 #define INTC_FIQ_INTEN_FIQ_INTEN_SHIFT (0U) 2840 #define INTC_FIQ_INTEN_FIQ_INTEN_MASK (0x3U << INTC_FIQ_INTEN_FIQ_INTEN_SHIFT) 2841 /* FIQ_INTMASK */ 2842 #define INTC_FIQ_INTMASK_OFFSET (0xC4U) 2843 #define INTC_FIQ_INTMASK_FIQ_INTMASK_SHIFT (0U) 2844 #define INTC_FIQ_INTMASK_FIQ_INTMASK_MASK (0x3U << INTC_FIQ_INTMASK_FIQ_INTMASK_SHIFT) 2845 /* FIQ_INTFORCE */ 2846 #define INTC_FIQ_INTFORCE_OFFSET (0xC8U) 2847 #define INTC_FIQ_INTFORCE_FIQ_INTFORCE_SHIFT (0U) 2848 #define INTC_FIQ_INTFORCE_FIQ_INTFORCE_MASK (0x3U << INTC_FIQ_INTFORCE_FIQ_INTFORCE_SHIFT) 2849 /* FIQ_RAWSTATUS */ 2850 #define INTC_FIQ_RAWSTATUS_OFFSET (0xCCU) 2851 #define INTC_FIQ_RAWSTATUS (0x0U) 2852 #define INTC_FIQ_RAWSTATUS_FIQ_RAWSTATUS_SHIFT (0U) 2853 #define INTC_FIQ_RAWSTATUS_FIQ_RAWSTATUS_MASK (0x3U << INTC_FIQ_RAWSTATUS_FIQ_RAWSTATUS_SHIFT) 2854 /* FIQ_STATUS */ 2855 #define INTC_FIQ_STATUS_OFFSET (0xD0U) 2856 #define INTC_FIQ_STATUS (0x0U) 2857 #define INTC_FIQ_STATUS_FIQ_STATUS_SHIFT (0U) 2858 #define INTC_FIQ_STATUS_FIQ_STATUS_MASK (0x3U << INTC_FIQ_STATUS_FIQ_STATUS_SHIFT) 2859 /* FIQ_FINALSTATUS */ 2860 #define INTC_FIQ_FINALSTATUS_OFFSET (0xD4U) 2861 #define INTC_FIQ_FINALSTATUS (0x0U) 2862 #define INTC_FIQ_FINALSTATUS_FIQ_FINALSTATUS_SHIFT (0U) 2863 #define INTC_FIQ_FINALSTATUS_FIQ_FINALSTATUS_MASK (0x3U << INTC_FIQ_FINALSTATUS_FIQ_FINALSTATUS_SHIFT) 2864 /* IRQ_PLEVEL */ 2865 #define INTC_IRQ_PLEVEL_OFFSET (0xD8U) 2866 #define INTC_IRQ_PLEVEL_IRQ_PLEVEL_SHIFT (0U) 2867 #define INTC_IRQ_PLEVEL_IRQ_PLEVEL_MASK (0xFU << INTC_IRQ_PLEVEL_IRQ_PLEVEL_SHIFT) 2868 /* IRQ_PR_OFFSET */ 2869 #define INTC_IRQ_PR_OFFSET_OFFSET (0xE8U) 2870 #define INTC_IRQ_PR_OFFSET_IRQ_PR_OFFSET_SHIFT (0U) 2871 #define INTC_IRQ_PR_OFFSET_IRQ_PR_OFFSET_MASK (0xFU << INTC_IRQ_PR_OFFSET_IRQ_PR_OFFSET_SHIFT) 2872 /* AHB_ICTL_COMP_VERSION */ 2873 #define INTC_AHB_ICTL_COMP_VERSION_OFFSET (0x3F8U) 2874 #define INTC_AHB_ICTL_COMP_VERSION (0x3230342AU) 2875 #define INTC_AHB_ICTL_COMP_VERSION_AHB_ICTL_COMP_VERSION_SHIFT (0U) 2876 #define INTC_AHB_ICTL_COMP_VERSION_AHB_ICTL_COMP_VERSION_MASK \ 2877 (0xFFFFFFFFU << INTC_AHB_ICTL_COMP_VERSION_AHB_ICTL_COMP_VERSION_SHIFT) 2878 /* ICTL_COMP_TYPE */ 2879 #define INTC_ICTL_COMP_TYPE_OFFSET (0x3FCU) 2880 #define INTC_ICTL_COMP_TYPE (0x44571120U) 2881 #define INTC_ICTL_COMP_TYPE_ICTL_COMP_TYPE_SHIFT (0U) 2882 #define INTC_ICTL_COMP_TYPE_ICTL_COMP_TYPE_MASK (0xFFFFFFFFU << INTC_ICTL_COMP_TYPE_ICTL_COMP_TYPE_SHIFT) 2883 /******************************************DMA*******************************************/ 2884 /* SAR0 */ 2885 #define DMA_SAR0_OFFSET (0x0U) 2886 #define DMA_SAR0_SAR_SHIFT (0U) 2887 #define DMA_SAR0_SAR_MASK (0xFFFFFFFFU << DMA_SAR0_SAR_SHIFT) 2888 /* DAR0 */ 2889 #define DMA_DAR0_OFFSET (0x8U) 2890 #define DMA_DAR0_DAR_SHIFT (0U) 2891 #define DMA_DAR0_DAR_MASK (0xFFFFFFFFU << DMA_DAR0_DAR_SHIFT) 2892 /* LLP0 */ 2893 #define DMA_LLP0_OFFSET (0x10U) 2894 #define DMA_LLP0_LMS_SHIFT (0U) 2895 #define DMA_LLP0_LMS_MASK (0x3U << DMA_LLP0_LMS_SHIFT) 2896 #define DMA_LLP0_LOC_SHIFT (2U) 2897 #define DMA_LLP0_LOC_MASK (0x3FFFFFFFU << DMA_LLP0_LOC_SHIFT) 2898 /* CTL0 */ 2899 #define DMA_CTL0_OFFSET (0x18U) 2900 #define DMA_CTL0_INT_EN_SHIFT (0U) 2901 #define DMA_CTL0_INT_EN_MASK (0x1U << DMA_CTL0_INT_EN_SHIFT) 2902 #define DMA_CTL0_DST_TR_WIDTH_SHIFT (1U) 2903 #define DMA_CTL0_DST_TR_WIDTH_MASK (0x7U << DMA_CTL0_DST_TR_WIDTH_SHIFT) 2904 #define DMA_CTL0_SRC_TR_WIDTH_SHIFT (4U) 2905 #define DMA_CTL0_SRC_TR_WIDTH_MASK (0x7U << DMA_CTL0_SRC_TR_WIDTH_SHIFT) 2906 #define DMA_CTL0_DINC_SHIFT (7U) 2907 #define DMA_CTL0_DINC_MASK (0x3U << DMA_CTL0_DINC_SHIFT) 2908 #define DMA_CTL0_SINC_SHIFT (9U) 2909 #define DMA_CTL0_SINC_MASK (0x3U << DMA_CTL0_SINC_SHIFT) 2910 #define DMA_CTL0_DEST_MSIZE_SHIFT (11U) 2911 #define DMA_CTL0_DEST_MSIZE_MASK (0x7U << DMA_CTL0_DEST_MSIZE_SHIFT) 2912 #define DMA_CTL0_SRC_MSIZE_SHIFT (14U) 2913 #define DMA_CTL0_SRC_MSIZE_MASK (0x7U << DMA_CTL0_SRC_MSIZE_SHIFT) 2914 #define DMA_CTL0_SRC_GATHER_EN_SHIFT (17U) 2915 #define DMA_CTL0_SRC_GATHER_EN_MASK (0x1U << DMA_CTL0_SRC_GATHER_EN_SHIFT) 2916 #define DMA_CTL0_DST_SCATTER_EN_SHIFT (18U) 2917 #define DMA_CTL0_DST_SCATTER_EN_MASK (0x1U << DMA_CTL0_DST_SCATTER_EN_SHIFT) 2918 #define DMA_CTL0_TT_FC_SHIFT (20U) 2919 #define DMA_CTL0_TT_FC_MASK (0x7U << DMA_CTL0_TT_FC_SHIFT) 2920 #define DMA_CTL0_DMS_SHIFT (23U) 2921 #define DMA_CTL0_DMS_MASK (0x3U << DMA_CTL0_DMS_SHIFT) 2922 #define DMA_CTL0_SMS_SHIFT (25U) 2923 #define DMA_CTL0_SMS_MASK (0x3U << DMA_CTL0_SMS_SHIFT) 2924 #define DMA_CTL0_LLP_DST_EN_SHIFT (27U) 2925 #define DMA_CTL0_LLP_DST_EN_MASK (0x1U << DMA_CTL0_LLP_DST_EN_SHIFT) 2926 #define DMA_CTL0_LLP_SRC_EN_SHIFT (28U) 2927 #define DMA_CTL0_LLP_SRC_EN_MASK (0x1U << DMA_CTL0_LLP_SRC_EN_SHIFT) 2928 #define DMA_CTL0_BLOCK_TS_SHIFT (32U) 2929 #define DMA_CTL0_BLOCK_TS_MASK (0xFFFU << DMA_CTL0_BLOCK_TS_SHIFT) 2930 #define DMA_CTL0_DONE_SHIFT (44U) 2931 #define DMA_CTL0_DONE_MASK (0x1U << DMA_CTL0_DONE_SHIFT) 2932 /* CTL_HI */ 2933 #define DMA_CTL_HI_OFFSET (0x1CU) 2934 #define DMA_CTL_HI_FIELD001_SHIFT (0U) 2935 #define DMA_CTL_HI_FIELD001_MASK (0xFFFFFFFFU << DMA_CTL_HI_FIELD001_SHIFT) 2936 /* SSTAT0 */ 2937 #define DMA_SSTAT0_OFFSET (0x20U) 2938 #define DMA_SSTAT0_SSTAT_SHIFT (0U) 2939 #define DMA_SSTAT0_SSTAT_MASK (0xFFFFFFFFU << DMA_SSTAT0_SSTAT_SHIFT) 2940 /* DSTAT0 */ 2941 #define DMA_DSTAT0_OFFSET (0x28U) 2942 #define DMA_DSTAT0_DSTAT_SHIFT (0U) 2943 #define DMA_DSTAT0_DSTAT_MASK (0xFFFFFFFFU << DMA_DSTAT0_DSTAT_SHIFT) 2944 /* SSTATAR0 */ 2945 #define DMA_SSTATAR0_OFFSET (0x30U) 2946 #define DMA_SSTATAR0_SSTATAR_SHIFT (0U) 2947 #define DMA_SSTATAR0_SSTATAR_MASK (0xFFFFFFFFU << DMA_SSTATAR0_SSTATAR_SHIFT) 2948 /* DSTATAR0 */ 2949 #define DMA_DSTATAR0_OFFSET (0x38U) 2950 #define DMA_DSTATAR0_DSTATAR_SHIFT (0U) 2951 #define DMA_DSTATAR0_DSTATAR_MASK (0xFFFFFFFFU << DMA_DSTATAR0_DSTATAR_SHIFT) 2952 /* CFG0 */ 2953 #define DMA_CFG0_OFFSET (0x40U) 2954 #define DMA_CFG0_CH_PRIOR_SHIFT (5U) 2955 #define DMA_CFG0_CH_PRIOR_MASK (0x7U << DMA_CFG0_CH_PRIOR_SHIFT) 2956 #define DMA_CFG0_CH_SUSP_SHIFT (8U) 2957 #define DMA_CFG0_CH_SUSP_MASK (0x1U << DMA_CFG0_CH_SUSP_SHIFT) 2958 #define DMA_CFG0_FIFO_EMPTY_SHIFT (9U) 2959 #define DMA_CFG0_FIFO_EMPTY_MASK (0x1U << DMA_CFG0_FIFO_EMPTY_SHIFT) 2960 #define DMA_CFG0_HS_SEL_DST_SHIFT (10U) 2961 #define DMA_CFG0_HS_SEL_DST_MASK (0x1U << DMA_CFG0_HS_SEL_DST_SHIFT) 2962 #define DMA_CFG0_HS_SEL_SRC_SHIFT (11U) 2963 #define DMA_CFG0_HS_SEL_SRC_MASK (0x1U << DMA_CFG0_HS_SEL_SRC_SHIFT) 2964 #define DMA_CFG0_LOCK_CH_L_SHIFT (12U) 2965 #define DMA_CFG0_LOCK_CH_L_MASK (0x3U << DMA_CFG0_LOCK_CH_L_SHIFT) 2966 #define DMA_CFG0_LOCK_B_L_SHIFT (14U) 2967 #define DMA_CFG0_LOCK_B_L_MASK (0x3U << DMA_CFG0_LOCK_B_L_SHIFT) 2968 #define DMA_CFG0_LOCK_CH_SHIFT (16U) 2969 #define DMA_CFG0_LOCK_CH_MASK (0x1U << DMA_CFG0_LOCK_CH_SHIFT) 2970 #define DMA_CFG0_LOCK_B_SHIFT (17U) 2971 #define DMA_CFG0_LOCK_B_MASK (0x1U << DMA_CFG0_LOCK_B_SHIFT) 2972 #define DMA_CFG0_DST_HS_POL_SHIFT (18U) 2973 #define DMA_CFG0_DST_HS_POL_MASK (0x1U << DMA_CFG0_DST_HS_POL_SHIFT) 2974 #define DMA_CFG0_SRC_HS_POL_SHIFT (19U) 2975 #define DMA_CFG0_SRC_HS_POL_MASK (0x1U << DMA_CFG0_SRC_HS_POL_SHIFT) 2976 #define DMA_CFG0_MAX_ABRST_SHIFT (20U) 2977 #define DMA_CFG0_MAX_ABRST_MASK (0x3FFU << DMA_CFG0_MAX_ABRST_SHIFT) 2978 #define DMA_CFG0_RELOAD_SRC_SHIFT (30U) 2979 #define DMA_CFG0_RELOAD_SRC_MASK (0x1U << DMA_CFG0_RELOAD_SRC_SHIFT) 2980 #define DMA_CFG0_RELOAD_DST_SHIFT (31U) 2981 #define DMA_CFG0_RELOAD_DST_MASK (0x1U << DMA_CFG0_RELOAD_DST_SHIFT) 2982 #define DMA_CFG0_FCMODE_SHIFT (32U) 2983 #define DMA_CFG0_FCMODE_MASK (0x1U << DMA_CFG0_FCMODE_SHIFT) 2984 #define DMA_CFG0_FIFO_MODE_SHIFT (33U) 2985 #define DMA_CFG0_FIFO_MODE_MASK (0x1U << DMA_CFG0_FIFO_MODE_SHIFT) 2986 #define DMA_CFG0_PROTCTL_SHIFT (34U) 2987 #define DMA_CFG0_PROTCTL_MASK (0x7U << DMA_CFG0_PROTCTL_SHIFT) 2988 #define DMA_CFG0_DS_UPD_EN_SHIFT (37U) 2989 #define DMA_CFG0_DS_UPD_EN_MASK (0x1U << DMA_CFG0_DS_UPD_EN_SHIFT) 2990 #define DMA_CFG0_SS_UPD_EN_SHIFT (38U) 2991 #define DMA_CFG0_SS_UPD_EN_MASK (0x1U << DMA_CFG0_SS_UPD_EN_SHIFT) 2992 #define DMA_CFG0_SRC_PER_SHIFT (39U) 2993 #define DMA_CFG0_SRC_PER_MASK (0xFU << DMA_CFG0_SRC_PER_SHIFT) 2994 #define DMA_CFG0_DEST_PER_SHIFT (43U) 2995 #define DMA_CFG0_DEST_PER_MASK (0xFU << DMA_CFG0_DEST_PER_SHIFT) 2996 /* CFG_HI */ 2997 #define DMA_CFG_HI_OFFSET (0x44U) 2998 #define DMA_CFG_HI_FIELD001_SHIFT (0U) 2999 #define DMA_CFG_HI_FIELD001_MASK (0xFFFFFFFFU << DMA_CFG_HI_FIELD001_SHIFT) 3000 /* SGR0 */ 3001 #define DMA_SGR0_OFFSET (0x48U) 3002 #define DMA_SGR0_SGI_SHIFT (0U) 3003 #define DMA_SGR0_SGI_MASK (0xFFFFFU << DMA_SGR0_SGI_SHIFT) 3004 #define DMA_SGR0_SGC_SHIFT (20U) 3005 #define DMA_SGR0_SGC_MASK (0xFFFU << DMA_SGR0_SGC_SHIFT) 3006 /* DSR0 */ 3007 #define DMA_DSR0_OFFSET (0x50U) 3008 #define DMA_DSR0_DSI_SHIFT (0U) 3009 #define DMA_DSR0_DSI_MASK (0xFFFFFU << DMA_DSR0_DSI_SHIFT) 3010 #define DMA_DSR0_DSC_SHIFT (20U) 3011 #define DMA_DSR0_DSC_MASK (0xFFFU << DMA_DSR0_DSC_SHIFT) 3012 /* RESERVED0054 */ 3013 #define DMA_RESERVED0054_OFFSET (0x54U) 3014 /* SAR1 */ 3015 #define DMA_SAR1_OFFSET (0x58U) 3016 #define DMA_SAR1_SAR_SHIFT (0U) 3017 #define DMA_SAR1_SAR_MASK (0xFFFFFFFFU << DMA_SAR1_SAR_SHIFT) 3018 /* DAR1 */ 3019 #define DMA_DAR1_OFFSET (0x60U) 3020 #define DMA_DAR1_DAR_SHIFT (0U) 3021 #define DMA_DAR1_DAR_MASK (0xFFFFFFFFU << DMA_DAR1_DAR_SHIFT) 3022 /* LLP1 */ 3023 #define DMA_LLP1_OFFSET (0x68U) 3024 #define DMA_LLP1_LMS_SHIFT (0U) 3025 #define DMA_LLP1_LMS_MASK (0x3U << DMA_LLP1_LMS_SHIFT) 3026 #define DMA_LLP1_LOC_SHIFT (2U) 3027 #define DMA_LLP1_LOC_MASK (0x3FFFFFFFU << DMA_LLP1_LOC_SHIFT) 3028 /* CTL1 */ 3029 #define DMA_CTL1_OFFSET (0x70U) 3030 #define DMA_CTL1_INT_EN_SHIFT (0U) 3031 #define DMA_CTL1_INT_EN_MASK (0x1U << DMA_CTL1_INT_EN_SHIFT) 3032 #define DMA_CTL1_DST_TR_WIDTH_SHIFT (1U) 3033 #define DMA_CTL1_DST_TR_WIDTH_MASK (0x7U << DMA_CTL1_DST_TR_WIDTH_SHIFT) 3034 #define DMA_CTL1_SRC_TR_WIDTH_SHIFT (4U) 3035 #define DMA_CTL1_SRC_TR_WIDTH_MASK (0x7U << DMA_CTL1_SRC_TR_WIDTH_SHIFT) 3036 #define DMA_CTL1_DINC_SHIFT (7U) 3037 #define DMA_CTL1_DINC_MASK (0x3U << DMA_CTL1_DINC_SHIFT) 3038 #define DMA_CTL1_SINC_SHIFT (9U) 3039 #define DMA_CTL1_SINC_MASK (0x3U << DMA_CTL1_SINC_SHIFT) 3040 #define DMA_CTL1_DEST_MSIZE_SHIFT (11U) 3041 #define DMA_CTL1_DEST_MSIZE_MASK (0x7U << DMA_CTL1_DEST_MSIZE_SHIFT) 3042 #define DMA_CTL1_SRC_MSIZE_SHIFT (14U) 3043 #define DMA_CTL1_SRC_MSIZE_MASK (0x7U << DMA_CTL1_SRC_MSIZE_SHIFT) 3044 #define DMA_CTL1_SRC_GATHER_EN_SHIFT (17U) 3045 #define DMA_CTL1_SRC_GATHER_EN_MASK (0x1U << DMA_CTL1_SRC_GATHER_EN_SHIFT) 3046 #define DMA_CTL1_DST_SCATTER_EN_SHIFT (18U) 3047 #define DMA_CTL1_DST_SCATTER_EN_MASK (0x1U << DMA_CTL1_DST_SCATTER_EN_SHIFT) 3048 #define DMA_CTL1_TT_FC_SHIFT (20U) 3049 #define DMA_CTL1_TT_FC_MASK (0x7U << DMA_CTL1_TT_FC_SHIFT) 3050 #define DMA_CTL1_DMS_SHIFT (23U) 3051 #define DMA_CTL1_DMS_MASK (0x3U << DMA_CTL1_DMS_SHIFT) 3052 #define DMA_CTL1_SMS_SHIFT (25U) 3053 #define DMA_CTL1_SMS_MASK (0x3U << DMA_CTL1_SMS_SHIFT) 3054 #define DMA_CTL1_LLP_DST_EN_SHIFT (27U) 3055 #define DMA_CTL1_LLP_DST_EN_MASK (0x1U << DMA_CTL1_LLP_DST_EN_SHIFT) 3056 #define DMA_CTL1_LLP_SRC_EN_SHIFT (28U) 3057 #define DMA_CTL1_LLP_SRC_EN_MASK (0x1U << DMA_CTL1_LLP_SRC_EN_SHIFT) 3058 #define DMA_CTL1_BLOCK_TS_SHIFT (32U) 3059 #define DMA_CTL1_BLOCK_TS_MASK (0xFFFU << DMA_CTL1_BLOCK_TS_SHIFT) 3060 #define DMA_CTL1_DONE_SHIFT (44U) 3061 #define DMA_CTL1_DONE_MASK (0x1U << DMA_CTL1_DONE_SHIFT) 3062 /* SSTAT1 */ 3063 #define DMA_SSTAT1_OFFSET (0x78U) 3064 #define DMA_SSTAT1_SSTAT_SHIFT (0U) 3065 #define DMA_SSTAT1_SSTAT_MASK (0xFFFFFFFFU << DMA_SSTAT1_SSTAT_SHIFT) 3066 /* DSTAT1 */ 3067 #define DMA_DSTAT1_OFFSET (0x80U) 3068 #define DMA_DSTAT1_DSTAT_SHIFT (0U) 3069 #define DMA_DSTAT1_DSTAT_MASK (0xFFFFFFFFU << DMA_DSTAT1_DSTAT_SHIFT) 3070 /* SSTATAR1 */ 3071 #define DMA_SSTATAR1_OFFSET (0x88U) 3072 #define DMA_SSTATAR1_SSTATAR_SHIFT (0U) 3073 #define DMA_SSTATAR1_SSTATAR_MASK (0xFFFFFFFFU << DMA_SSTATAR1_SSTATAR_SHIFT) 3074 /* DSTATAR1 */ 3075 #define DMA_DSTATAR1_OFFSET (0x90U) 3076 #define DMA_DSTATAR1_DSTATAR_SHIFT (0U) 3077 #define DMA_DSTATAR1_DSTATAR_MASK (0xFFFFFFFFU << DMA_DSTATAR1_DSTATAR_SHIFT) 3078 /* CFG1 */ 3079 #define DMA_CFG1_OFFSET (0x98U) 3080 #define DMA_CFG1_CH_PRIOR_SHIFT (5U) 3081 #define DMA_CFG1_CH_PRIOR_MASK (0x7U << DMA_CFG1_CH_PRIOR_SHIFT) 3082 #define DMA_CFG1_CH_SUSP_SHIFT (8U) 3083 #define DMA_CFG1_CH_SUSP_MASK (0x1U << DMA_CFG1_CH_SUSP_SHIFT) 3084 #define DMA_CFG1_FIFO_EMPTY_SHIFT (9U) 3085 #define DMA_CFG1_FIFO_EMPTY_MASK (0x1U << DMA_CFG1_FIFO_EMPTY_SHIFT) 3086 #define DMA_CFG1_HS_SEL_DST_SHIFT (10U) 3087 #define DMA_CFG1_HS_SEL_DST_MASK (0x1U << DMA_CFG1_HS_SEL_DST_SHIFT) 3088 #define DMA_CFG1_HS_SEL_SRC_SHIFT (11U) 3089 #define DMA_CFG1_HS_SEL_SRC_MASK (0x1U << DMA_CFG1_HS_SEL_SRC_SHIFT) 3090 #define DMA_CFG1_LOCK_CH_L_SHIFT (12U) 3091 #define DMA_CFG1_LOCK_CH_L_MASK (0x3U << DMA_CFG1_LOCK_CH_L_SHIFT) 3092 #define DMA_CFG1_LOCK_B_L_SHIFT (14U) 3093 #define DMA_CFG1_LOCK_B_L_MASK (0x3U << DMA_CFG1_LOCK_B_L_SHIFT) 3094 #define DMA_CFG1_LOCK_CH_SHIFT (16U) 3095 #define DMA_CFG1_LOCK_CH_MASK (0x1U << DMA_CFG1_LOCK_CH_SHIFT) 3096 #define DMA_CFG1_LOCK_B_SHIFT (17U) 3097 #define DMA_CFG1_LOCK_B_MASK (0x1U << DMA_CFG1_LOCK_B_SHIFT) 3098 #define DMA_CFG1_DST_HS_POL_SHIFT (18U) 3099 #define DMA_CFG1_DST_HS_POL_MASK (0x1U << DMA_CFG1_DST_HS_POL_SHIFT) 3100 #define DMA_CFG1_SRC_HS_POL_SHIFT (19U) 3101 #define DMA_CFG1_SRC_HS_POL_MASK (0x1U << DMA_CFG1_SRC_HS_POL_SHIFT) 3102 #define DMA_CFG1_MAX_ABRST_SHIFT (20U) 3103 #define DMA_CFG1_MAX_ABRST_MASK (0x3FFU << DMA_CFG1_MAX_ABRST_SHIFT) 3104 #define DMA_CFG1_RELOAD_SRC_SHIFT (30U) 3105 #define DMA_CFG1_RELOAD_SRC_MASK (0x1U << DMA_CFG1_RELOAD_SRC_SHIFT) 3106 #define DMA_CFG1_RELOAD_DST_SHIFT (31U) 3107 #define DMA_CFG1_RELOAD_DST_MASK (0x1U << DMA_CFG1_RELOAD_DST_SHIFT) 3108 #define DMA_CFG1_FCMODE_SHIFT (32U) 3109 #define DMA_CFG1_FCMODE_MASK (0x1U << DMA_CFG1_FCMODE_SHIFT) 3110 #define DMA_CFG1_FIFO_MODE_SHIFT (33U) 3111 #define DMA_CFG1_FIFO_MODE_MASK (0x1U << DMA_CFG1_FIFO_MODE_SHIFT) 3112 #define DMA_CFG1_PROTCTL_SHIFT (34U) 3113 #define DMA_CFG1_PROTCTL_MASK (0x7U << DMA_CFG1_PROTCTL_SHIFT) 3114 #define DMA_CFG1_DS_UPD_EN_SHIFT (37U) 3115 #define DMA_CFG1_DS_UPD_EN_MASK (0x1U << DMA_CFG1_DS_UPD_EN_SHIFT) 3116 #define DMA_CFG1_SS_UPD_EN_SHIFT (38U) 3117 #define DMA_CFG1_SS_UPD_EN_MASK (0x1U << DMA_CFG1_SS_UPD_EN_SHIFT) 3118 #define DMA_CFG1_SRC_PER_SHIFT (39U) 3119 #define DMA_CFG1_SRC_PER_MASK (0xFU << DMA_CFG1_SRC_PER_SHIFT) 3120 #define DMA_CFG1_DEST_PER_SHIFT (43U) 3121 #define DMA_CFG1_DEST_PER_MASK (0xFU << DMA_CFG1_DEST_PER_SHIFT) 3122 /* SGR1 */ 3123 #define DMA_SGR1_OFFSET (0xA0U) 3124 #define DMA_SGR1_SGI_SHIFT (0U) 3125 #define DMA_SGR1_SGI_MASK (0xFFFFFU << DMA_SGR1_SGI_SHIFT) 3126 #define DMA_SGR1_SGC_SHIFT (20U) 3127 #define DMA_SGR1_SGC_MASK (0xFFFU << DMA_SGR1_SGC_SHIFT) 3128 /* DSR1 */ 3129 #define DMA_DSR1_OFFSET (0xA8U) 3130 #define DMA_DSR1_DSI_SHIFT (0U) 3131 #define DMA_DSR1_DSI_MASK (0xFFFFFU << DMA_DSR1_DSI_SHIFT) 3132 #define DMA_DSR1_DSC_SHIFT (20U) 3133 #define DMA_DSR1_DSC_MASK (0xFFFU << DMA_DSR1_DSC_SHIFT) 3134 /* RESERVED00AC */ 3135 #define DMA_RESERVED00AC_OFFSET (0xACU) 3136 /* SAR2 */ 3137 #define DMA_SAR2_OFFSET (0xB0U) 3138 #define DMA_SAR2_SAR_SHIFT (0U) 3139 #define DMA_SAR2_SAR_MASK (0xFFFFFFFFU << DMA_SAR2_SAR_SHIFT) 3140 /* DAR2 */ 3141 #define DMA_DAR2_OFFSET (0xB8U) 3142 #define DMA_DAR2_DAR_SHIFT (0U) 3143 #define DMA_DAR2_DAR_MASK (0xFFFFFFFFU << DMA_DAR2_DAR_SHIFT) 3144 /* LLP2 */ 3145 #define DMA_LLP2_OFFSET (0xC0U) 3146 #define DMA_LLP2_LMS_SHIFT (0U) 3147 #define DMA_LLP2_LMS_MASK (0x3U << DMA_LLP2_LMS_SHIFT) 3148 #define DMA_LLP2_LOC_SHIFT (2U) 3149 #define DMA_LLP2_LOC_MASK (0x3FFFFFFFU << DMA_LLP2_LOC_SHIFT) 3150 /* CTL2 */ 3151 #define DMA_CTL2_OFFSET (0xC8U) 3152 #define DMA_CTL2_INT_EN_SHIFT (0U) 3153 #define DMA_CTL2_INT_EN_MASK (0x1U << DMA_CTL2_INT_EN_SHIFT) 3154 #define DMA_CTL2_DST_TR_WIDTH_SHIFT (1U) 3155 #define DMA_CTL2_DST_TR_WIDTH_MASK (0x7U << DMA_CTL2_DST_TR_WIDTH_SHIFT) 3156 #define DMA_CTL2_SRC_TR_WIDTH_SHIFT (4U) 3157 #define DMA_CTL2_SRC_TR_WIDTH_MASK (0x7U << DMA_CTL2_SRC_TR_WIDTH_SHIFT) 3158 #define DMA_CTL2_DINC_SHIFT (7U) 3159 #define DMA_CTL2_DINC_MASK (0x3U << DMA_CTL2_DINC_SHIFT) 3160 #define DMA_CTL2_SINC_SHIFT (9U) 3161 #define DMA_CTL2_SINC_MASK (0x3U << DMA_CTL2_SINC_SHIFT) 3162 #define DMA_CTL2_DEST_MSIZE_SHIFT (11U) 3163 #define DMA_CTL2_DEST_MSIZE_MASK (0x7U << DMA_CTL2_DEST_MSIZE_SHIFT) 3164 #define DMA_CTL2_SRC_MSIZE_SHIFT (14U) 3165 #define DMA_CTL2_SRC_MSIZE_MASK (0x7U << DMA_CTL2_SRC_MSIZE_SHIFT) 3166 #define DMA_CTL2_SRC_GATHER_EN_SHIFT (17U) 3167 #define DMA_CTL2_SRC_GATHER_EN_MASK (0x1U << DMA_CTL2_SRC_GATHER_EN_SHIFT) 3168 #define DMA_CTL2_DST_SCATTER_EN_SHIFT (18U) 3169 #define DMA_CTL2_DST_SCATTER_EN_MASK (0x1U << DMA_CTL2_DST_SCATTER_EN_SHIFT) 3170 #define DMA_CTL2_TT_FC_SHIFT (20U) 3171 #define DMA_CTL2_TT_FC_MASK (0x7U << DMA_CTL2_TT_FC_SHIFT) 3172 #define DMA_CTL2_DMS_SHIFT (23U) 3173 #define DMA_CTL2_DMS_MASK (0x3U << DMA_CTL2_DMS_SHIFT) 3174 #define DMA_CTL2_SMS_SHIFT (25U) 3175 #define DMA_CTL2_SMS_MASK (0x3U << DMA_CTL2_SMS_SHIFT) 3176 #define DMA_CTL2_LLP_DST_EN_SHIFT (27U) 3177 #define DMA_CTL2_LLP_DST_EN_MASK (0x1U << DMA_CTL2_LLP_DST_EN_SHIFT) 3178 #define DMA_CTL2_LLP_SRC_EN_SHIFT (28U) 3179 #define DMA_CTL2_LLP_SRC_EN_MASK (0x1U << DMA_CTL2_LLP_SRC_EN_SHIFT) 3180 #define DMA_CTL2_BLOCK_TS_SHIFT (32U) 3181 #define DMA_CTL2_BLOCK_TS_MASK (0xFFFU << DMA_CTL2_BLOCK_TS_SHIFT) 3182 #define DMA_CTL2_DONE_SHIFT (44U) 3183 #define DMA_CTL2_DONE_MASK (0x1U << DMA_CTL2_DONE_SHIFT) 3184 /* SSTAT2 */ 3185 #define DMA_SSTAT2_OFFSET (0xD0U) 3186 #define DMA_SSTAT2_SSTAT_SHIFT (0U) 3187 #define DMA_SSTAT2_SSTAT_MASK (0xFFFFFFFFU << DMA_SSTAT2_SSTAT_SHIFT) 3188 /* DSTAT2 */ 3189 #define DMA_DSTAT2_OFFSET (0xD8U) 3190 #define DMA_DSTAT2_DSTAT_SHIFT (0U) 3191 #define DMA_DSTAT2_DSTAT_MASK (0xFFFFFFFFU << DMA_DSTAT2_DSTAT_SHIFT) 3192 /* SSTATAR2 */ 3193 #define DMA_SSTATAR2_OFFSET (0xE0U) 3194 #define DMA_SSTATAR2_SSTATAR_SHIFT (0U) 3195 #define DMA_SSTATAR2_SSTATAR_MASK (0xFFFFFFFFU << DMA_SSTATAR2_SSTATAR_SHIFT) 3196 /* DSTATAR2 */ 3197 #define DMA_DSTATAR2_OFFSET (0xE8U) 3198 #define DMA_DSTATAR2_DSTATAR_SHIFT (0U) 3199 #define DMA_DSTATAR2_DSTATAR_MASK (0xFFFFFFFFU << DMA_DSTATAR2_DSTATAR_SHIFT) 3200 /* CFG2 */ 3201 #define DMA_CFG2_OFFSET (0xF0U) 3202 #define DMA_CFG2_CH_PRIOR_SHIFT (5U) 3203 #define DMA_CFG2_CH_PRIOR_MASK (0x7U << DMA_CFG2_CH_PRIOR_SHIFT) 3204 #define DMA_CFG2_CH_SUSP_SHIFT (8U) 3205 #define DMA_CFG2_CH_SUSP_MASK (0x1U << DMA_CFG2_CH_SUSP_SHIFT) 3206 #define DMA_CFG2_FIFO_EMPTY_SHIFT (9U) 3207 #define DMA_CFG2_FIFO_EMPTY_MASK (0x1U << DMA_CFG2_FIFO_EMPTY_SHIFT) 3208 #define DMA_CFG2_HS_SEL_DST_SHIFT (10U) 3209 #define DMA_CFG2_HS_SEL_DST_MASK (0x1U << DMA_CFG2_HS_SEL_DST_SHIFT) 3210 #define DMA_CFG2_HS_SEL_SRC_SHIFT (11U) 3211 #define DMA_CFG2_HS_SEL_SRC_MASK (0x1U << DMA_CFG2_HS_SEL_SRC_SHIFT) 3212 #define DMA_CFG2_LOCK_CH_L_SHIFT (12U) 3213 #define DMA_CFG2_LOCK_CH_L_MASK (0x3U << DMA_CFG2_LOCK_CH_L_SHIFT) 3214 #define DMA_CFG2_LOCK_B_L_SHIFT (14U) 3215 #define DMA_CFG2_LOCK_B_L_MASK (0x3U << DMA_CFG2_LOCK_B_L_SHIFT) 3216 #define DMA_CFG2_LOCK_CH_SHIFT (16U) 3217 #define DMA_CFG2_LOCK_CH_MASK (0x1U << DMA_CFG2_LOCK_CH_SHIFT) 3218 #define DMA_CFG2_LOCK_B_SHIFT (17U) 3219 #define DMA_CFG2_LOCK_B_MASK (0x1U << DMA_CFG2_LOCK_B_SHIFT) 3220 #define DMA_CFG2_DST_HS_POL_SHIFT (18U) 3221 #define DMA_CFG2_DST_HS_POL_MASK (0x1U << DMA_CFG2_DST_HS_POL_SHIFT) 3222 #define DMA_CFG2_SRC_HS_POL_SHIFT (19U) 3223 #define DMA_CFG2_SRC_HS_POL_MASK (0x1U << DMA_CFG2_SRC_HS_POL_SHIFT) 3224 #define DMA_CFG2_MAX_ABRST_SHIFT (20U) 3225 #define DMA_CFG2_MAX_ABRST_MASK (0x3FFU << DMA_CFG2_MAX_ABRST_SHIFT) 3226 #define DMA_CFG2_RELOAD_SRC_SHIFT (30U) 3227 #define DMA_CFG2_RELOAD_SRC_MASK (0x1U << DMA_CFG2_RELOAD_SRC_SHIFT) 3228 #define DMA_CFG2_RELOAD_DST_SHIFT (31U) 3229 #define DMA_CFG2_RELOAD_DST_MASK (0x1U << DMA_CFG2_RELOAD_DST_SHIFT) 3230 #define DMA_CFG2_FCMODE_SHIFT (32U) 3231 #define DMA_CFG2_FCMODE_MASK (0x1U << DMA_CFG2_FCMODE_SHIFT) 3232 #define DMA_CFG2_FIFO_MODE_SHIFT (33U) 3233 #define DMA_CFG2_FIFO_MODE_MASK (0x1U << DMA_CFG2_FIFO_MODE_SHIFT) 3234 #define DMA_CFG2_PROTCTL_SHIFT (34U) 3235 #define DMA_CFG2_PROTCTL_MASK (0x7U << DMA_CFG2_PROTCTL_SHIFT) 3236 #define DMA_CFG2_DS_UPD_EN_SHIFT (37U) 3237 #define DMA_CFG2_DS_UPD_EN_MASK (0x1U << DMA_CFG2_DS_UPD_EN_SHIFT) 3238 #define DMA_CFG2_SS_UPD_EN_SHIFT (38U) 3239 #define DMA_CFG2_SS_UPD_EN_MASK (0x1U << DMA_CFG2_SS_UPD_EN_SHIFT) 3240 #define DMA_CFG2_SRC_PER_SHIFT (39U) 3241 #define DMA_CFG2_SRC_PER_MASK (0xFU << DMA_CFG2_SRC_PER_SHIFT) 3242 #define DMA_CFG2_DEST_PER_SHIFT (43U) 3243 #define DMA_CFG2_DEST_PER_MASK (0xFU << DMA_CFG2_DEST_PER_SHIFT) 3244 /* SGR2 */ 3245 #define DMA_SGR2_OFFSET (0xF8U) 3246 #define DMA_SGR2_SGI_SHIFT (0U) 3247 #define DMA_SGR2_SGI_MASK (0xFFFFFU << DMA_SGR2_SGI_SHIFT) 3248 #define DMA_SGR2_SGC_SHIFT (20U) 3249 #define DMA_SGR2_SGC_MASK (0xFFFU << DMA_SGR2_SGC_SHIFT) 3250 /* DSR2 */ 3251 #define DMA_DSR2_OFFSET (0x100U) 3252 #define DMA_DSR2_DSI_SHIFT (0U) 3253 #define DMA_DSR2_DSI_MASK (0xFFFFFU << DMA_DSR2_DSI_SHIFT) 3254 #define DMA_DSR2_DSC_SHIFT (20U) 3255 #define DMA_DSR2_DSC_MASK (0xFFFU << DMA_DSR2_DSC_SHIFT) 3256 /* RESERVED0104 */ 3257 #define DMA_RESERVED0104_OFFSET (0x104U) 3258 /* SAR3 */ 3259 #define DMA_SAR3_OFFSET (0x108U) 3260 #define DMA_SAR3_SAR_SHIFT (0U) 3261 #define DMA_SAR3_SAR_MASK (0xFFFFFFFFU << DMA_SAR3_SAR_SHIFT) 3262 /* DAR3 */ 3263 #define DMA_DAR3_OFFSET (0x110U) 3264 #define DMA_DAR3_DAR_SHIFT (0U) 3265 #define DMA_DAR3_DAR_MASK (0xFFFFFFFFU << DMA_DAR3_DAR_SHIFT) 3266 /* LLP3 */ 3267 #define DMA_LLP3_OFFSET (0x118U) 3268 #define DMA_LLP3_LMS_SHIFT (0U) 3269 #define DMA_LLP3_LMS_MASK (0x3U << DMA_LLP3_LMS_SHIFT) 3270 #define DMA_LLP3_LOC_SHIFT (2U) 3271 #define DMA_LLP3_LOC_MASK (0x3FFFFFFFU << DMA_LLP3_LOC_SHIFT) 3272 /* CTL3 */ 3273 #define DMA_CTL3_OFFSET (0x120U) 3274 #define DMA_CTL3_INT_EN_SHIFT (0U) 3275 #define DMA_CTL3_INT_EN_MASK (0x1U << DMA_CTL3_INT_EN_SHIFT) 3276 #define DMA_CTL3_DST_TR_WIDTH_SHIFT (1U) 3277 #define DMA_CTL3_DST_TR_WIDTH_MASK (0x7U << DMA_CTL3_DST_TR_WIDTH_SHIFT) 3278 #define DMA_CTL3_SRC_TR_WIDTH_SHIFT (4U) 3279 #define DMA_CTL3_SRC_TR_WIDTH_MASK (0x7U << DMA_CTL3_SRC_TR_WIDTH_SHIFT) 3280 #define DMA_CTL3_DINC_SHIFT (7U) 3281 #define DMA_CTL3_DINC_MASK (0x3U << DMA_CTL3_DINC_SHIFT) 3282 #define DMA_CTL3_SINC_SHIFT (9U) 3283 #define DMA_CTL3_SINC_MASK (0x3U << DMA_CTL3_SINC_SHIFT) 3284 #define DMA_CTL3_DEST_MSIZE_SHIFT (11U) 3285 #define DMA_CTL3_DEST_MSIZE_MASK (0x7U << DMA_CTL3_DEST_MSIZE_SHIFT) 3286 #define DMA_CTL3_SRC_MSIZE_SHIFT (14U) 3287 #define DMA_CTL3_SRC_MSIZE_MASK (0x7U << DMA_CTL3_SRC_MSIZE_SHIFT) 3288 #define DMA_CTL3_SRC_GATHER_EN_SHIFT (17U) 3289 #define DMA_CTL3_SRC_GATHER_EN_MASK (0x1U << DMA_CTL3_SRC_GATHER_EN_SHIFT) 3290 #define DMA_CTL3_DST_SCATTER_EN_SHIFT (18U) 3291 #define DMA_CTL3_DST_SCATTER_EN_MASK (0x1U << DMA_CTL3_DST_SCATTER_EN_SHIFT) 3292 #define DMA_CTL3_TT_FC_SHIFT (20U) 3293 #define DMA_CTL3_TT_FC_MASK (0x7U << DMA_CTL3_TT_FC_SHIFT) 3294 #define DMA_CTL3_DMS_SHIFT (23U) 3295 #define DMA_CTL3_DMS_MASK (0x3U << DMA_CTL3_DMS_SHIFT) 3296 #define DMA_CTL3_SMS_SHIFT (25U) 3297 #define DMA_CTL3_SMS_MASK (0x3U << DMA_CTL3_SMS_SHIFT) 3298 #define DMA_CTL3_LLP_DST_EN_SHIFT (27U) 3299 #define DMA_CTL3_LLP_DST_EN_MASK (0x1U << DMA_CTL3_LLP_DST_EN_SHIFT) 3300 #define DMA_CTL3_LLP_SRC_EN_SHIFT (28U) 3301 #define DMA_CTL3_LLP_SRC_EN_MASK (0x1U << DMA_CTL3_LLP_SRC_EN_SHIFT) 3302 #define DMA_CTL3_BLOCK_TS_SHIFT (32U) 3303 #define DMA_CTL3_BLOCK_TS_MASK (0xFFFU << DMA_CTL3_BLOCK_TS_SHIFT) 3304 #define DMA_CTL3_DONE_SHIFT (44U) 3305 #define DMA_CTL3_DONE_MASK (0x1U << DMA_CTL3_DONE_SHIFT) 3306 /* SSTAT3 */ 3307 #define DMA_SSTAT3_OFFSET (0x128U) 3308 #define DMA_SSTAT3_SSTAT_SHIFT (0U) 3309 #define DMA_SSTAT3_SSTAT_MASK (0xFFFFFFFFU << DMA_SSTAT3_SSTAT_SHIFT) 3310 /* DSTAT3 */ 3311 #define DMA_DSTAT3_OFFSET (0x130U) 3312 #define DMA_DSTAT3_DSTAT_SHIFT (0U) 3313 #define DMA_DSTAT3_DSTAT_MASK (0xFFFFFFFFU << DMA_DSTAT3_DSTAT_SHIFT) 3314 /* SSTATAR3 */ 3315 #define DMA_SSTATAR3_OFFSET (0x138U) 3316 #define DMA_SSTATAR3_SSTATAR_SHIFT (0U) 3317 #define DMA_SSTATAR3_SSTATAR_MASK (0xFFFFFFFFU << DMA_SSTATAR3_SSTATAR_SHIFT) 3318 /* DSTATAR3 */ 3319 #define DMA_DSTATAR3_OFFSET (0x140U) 3320 #define DMA_DSTATAR3_DSTATAR_SHIFT (0U) 3321 #define DMA_DSTATAR3_DSTATAR_MASK (0xFFFFFFFFU << DMA_DSTATAR3_DSTATAR_SHIFT) 3322 /* CFG3 */ 3323 #define DMA_CFG3_OFFSET (0x148U) 3324 #define DMA_CFG3_CH_PRIOR_SHIFT (5U) 3325 #define DMA_CFG3_CH_PRIOR_MASK (0x7U << DMA_CFG3_CH_PRIOR_SHIFT) 3326 #define DMA_CFG3_CH_SUSP_SHIFT (8U) 3327 #define DMA_CFG3_CH_SUSP_MASK (0x1U << DMA_CFG3_CH_SUSP_SHIFT) 3328 #define DMA_CFG3_FIFO_EMPTY_SHIFT (9U) 3329 #define DMA_CFG3_FIFO_EMPTY_MASK (0x1U << DMA_CFG3_FIFO_EMPTY_SHIFT) 3330 #define DMA_CFG3_HS_SEL_DST_SHIFT (10U) 3331 #define DMA_CFG3_HS_SEL_DST_MASK (0x1U << DMA_CFG3_HS_SEL_DST_SHIFT) 3332 #define DMA_CFG3_HS_SEL_SRC_SHIFT (11U) 3333 #define DMA_CFG3_HS_SEL_SRC_MASK (0x1U << DMA_CFG3_HS_SEL_SRC_SHIFT) 3334 #define DMA_CFG3_LOCK_CH_L_SHIFT (12U) 3335 #define DMA_CFG3_LOCK_CH_L_MASK (0x3U << DMA_CFG3_LOCK_CH_L_SHIFT) 3336 #define DMA_CFG3_LOCK_B_L_SHIFT (14U) 3337 #define DMA_CFG3_LOCK_B_L_MASK (0x3U << DMA_CFG3_LOCK_B_L_SHIFT) 3338 #define DMA_CFG3_LOCK_CH_SHIFT (16U) 3339 #define DMA_CFG3_LOCK_CH_MASK (0x1U << DMA_CFG3_LOCK_CH_SHIFT) 3340 #define DMA_CFG3_LOCK_B_SHIFT (17U) 3341 #define DMA_CFG3_LOCK_B_MASK (0x1U << DMA_CFG3_LOCK_B_SHIFT) 3342 #define DMA_CFG3_DST_HS_POL_SHIFT (18U) 3343 #define DMA_CFG3_DST_HS_POL_MASK (0x1U << DMA_CFG3_DST_HS_POL_SHIFT) 3344 #define DMA_CFG3_SRC_HS_POL_SHIFT (19U) 3345 #define DMA_CFG3_SRC_HS_POL_MASK (0x1U << DMA_CFG3_SRC_HS_POL_SHIFT) 3346 #define DMA_CFG3_MAX_ABRST_SHIFT (20U) 3347 #define DMA_CFG3_MAX_ABRST_MASK (0x3FFU << DMA_CFG3_MAX_ABRST_SHIFT) 3348 #define DMA_CFG3_RELOAD_SRC_SHIFT (30U) 3349 #define DMA_CFG3_RELOAD_SRC_MASK (0x1U << DMA_CFG3_RELOAD_SRC_SHIFT) 3350 #define DMA_CFG3_RELOAD_DST_SHIFT (31U) 3351 #define DMA_CFG3_RELOAD_DST_MASK (0x1U << DMA_CFG3_RELOAD_DST_SHIFT) 3352 #define DMA_CFG3_FCMODE_SHIFT (32U) 3353 #define DMA_CFG3_FCMODE_MASK (0x1U << DMA_CFG3_FCMODE_SHIFT) 3354 #define DMA_CFG3_FIFO_MODE_SHIFT (33U) 3355 #define DMA_CFG3_FIFO_MODE_MASK (0x1U << DMA_CFG3_FIFO_MODE_SHIFT) 3356 #define DMA_CFG3_PROTCTL_SHIFT (34U) 3357 #define DMA_CFG3_PROTCTL_MASK (0x7U << DMA_CFG3_PROTCTL_SHIFT) 3358 #define DMA_CFG3_DS_UPD_EN_SHIFT (37U) 3359 #define DMA_CFG3_DS_UPD_EN_MASK (0x1U << DMA_CFG3_DS_UPD_EN_SHIFT) 3360 #define DMA_CFG3_SS_UPD_EN_SHIFT (38U) 3361 #define DMA_CFG3_SS_UPD_EN_MASK (0x1U << DMA_CFG3_SS_UPD_EN_SHIFT) 3362 #define DMA_CFG3_SRC_PER_SHIFT (39U) 3363 #define DMA_CFG3_SRC_PER_MASK (0xFU << DMA_CFG3_SRC_PER_SHIFT) 3364 #define DMA_CFG3_DEST_PER_SHIFT (43U) 3365 #define DMA_CFG3_DEST_PER_MASK (0xFU << DMA_CFG3_DEST_PER_SHIFT) 3366 /* SGR3 */ 3367 #define DMA_SGR3_OFFSET (0x150U) 3368 #define DMA_SGR3_SGI_SHIFT (0U) 3369 #define DMA_SGR3_SGI_MASK (0xFFFFFU << DMA_SGR3_SGI_SHIFT) 3370 #define DMA_SGR3_SGC_SHIFT (20U) 3371 #define DMA_SGR3_SGC_MASK (0xFFFU << DMA_SGR3_SGC_SHIFT) 3372 /* DSR3 */ 3373 #define DMA_DSR3_OFFSET (0x158U) 3374 #define DMA_DSR3_DSI_SHIFT (0U) 3375 #define DMA_DSR3_DSI_MASK (0xFFFFFU << DMA_DSR3_DSI_SHIFT) 3376 #define DMA_DSR3_DSC_SHIFT (20U) 3377 #define DMA_DSR3_DSC_MASK (0xFFFU << DMA_DSR3_DSC_SHIFT) 3378 /* RESERVED015C */ 3379 #define DMA_RESERVED015C_OFFSET (0x15CU) 3380 /* SAR4 */ 3381 #define DMA_SAR4_OFFSET (0x160U) 3382 #define DMA_SAR4_SAR_SHIFT (0U) 3383 #define DMA_SAR4_SAR_MASK (0xFFFFFFFFU << DMA_SAR4_SAR_SHIFT) 3384 /* DAR4 */ 3385 #define DMA_DAR4_OFFSET (0x168U) 3386 #define DMA_DAR4_DAR_SHIFT (0U) 3387 #define DMA_DAR4_DAR_MASK (0xFFFFFFFFU << DMA_DAR4_DAR_SHIFT) 3388 /* LLP4 */ 3389 #define DMA_LLP4_OFFSET (0x170U) 3390 #define DMA_LLP4_LMS_SHIFT (0U) 3391 #define DMA_LLP4_LMS_MASK (0x3U << DMA_LLP4_LMS_SHIFT) 3392 #define DMA_LLP4_LOC_SHIFT (2U) 3393 #define DMA_LLP4_LOC_MASK (0x3FFFFFFFU << DMA_LLP4_LOC_SHIFT) 3394 /* CTL4 */ 3395 #define DMA_CTL4_OFFSET (0x178U) 3396 #define DMA_CTL4_INT_EN_SHIFT (0U) 3397 #define DMA_CTL4_INT_EN_MASK (0x1U << DMA_CTL4_INT_EN_SHIFT) 3398 #define DMA_CTL4_DST_TR_WIDTH_SHIFT (1U) 3399 #define DMA_CTL4_DST_TR_WIDTH_MASK (0x7U << DMA_CTL4_DST_TR_WIDTH_SHIFT) 3400 #define DMA_CTL4_SRC_TR_WIDTH_SHIFT (4U) 3401 #define DMA_CTL4_SRC_TR_WIDTH_MASK (0x7U << DMA_CTL4_SRC_TR_WIDTH_SHIFT) 3402 #define DMA_CTL4_DINC_SHIFT (7U) 3403 #define DMA_CTL4_DINC_MASK (0x3U << DMA_CTL4_DINC_SHIFT) 3404 #define DMA_CTL4_SINC_SHIFT (9U) 3405 #define DMA_CTL4_SINC_MASK (0x3U << DMA_CTL4_SINC_SHIFT) 3406 #define DMA_CTL4_DEST_MSIZE_SHIFT (11U) 3407 #define DMA_CTL4_DEST_MSIZE_MASK (0x7U << DMA_CTL4_DEST_MSIZE_SHIFT) 3408 #define DMA_CTL4_SRC_MSIZE_SHIFT (14U) 3409 #define DMA_CTL4_SRC_MSIZE_MASK (0x7U << DMA_CTL4_SRC_MSIZE_SHIFT) 3410 #define DMA_CTL4_SRC_GATHER_EN_SHIFT (17U) 3411 #define DMA_CTL4_SRC_GATHER_EN_MASK (0x1U << DMA_CTL4_SRC_GATHER_EN_SHIFT) 3412 #define DMA_CTL4_DST_SCATTER_EN_SHIFT (18U) 3413 #define DMA_CTL4_DST_SCATTER_EN_MASK (0x1U << DMA_CTL4_DST_SCATTER_EN_SHIFT) 3414 #define DMA_CTL4_TT_FC_SHIFT (20U) 3415 #define DMA_CTL4_TT_FC_MASK (0x7U << DMA_CTL4_TT_FC_SHIFT) 3416 #define DMA_CTL4_DMS_SHIFT (23U) 3417 #define DMA_CTL4_DMS_MASK (0x3U << DMA_CTL4_DMS_SHIFT) 3418 #define DMA_CTL4_SMS_SHIFT (25U) 3419 #define DMA_CTL4_SMS_MASK (0x3U << DMA_CTL4_SMS_SHIFT) 3420 #define DMA_CTL4_LLP_DST_EN_SHIFT (27U) 3421 #define DMA_CTL4_LLP_DST_EN_MASK (0x1U << DMA_CTL4_LLP_DST_EN_SHIFT) 3422 #define DMA_CTL4_LLP_SRC_EN_SHIFT (28U) 3423 #define DMA_CTL4_LLP_SRC_EN_MASK (0x1U << DMA_CTL4_LLP_SRC_EN_SHIFT) 3424 #define DMA_CTL4_BLOCK_TS_SHIFT (32U) 3425 #define DMA_CTL4_BLOCK_TS_MASK (0xFFFU << DMA_CTL4_BLOCK_TS_SHIFT) 3426 #define DMA_CTL4_DONE_SHIFT (44U) 3427 #define DMA_CTL4_DONE_MASK (0x1U << DMA_CTL4_DONE_SHIFT) 3428 /* SSTAT4 */ 3429 #define DMA_SSTAT4_OFFSET (0x180U) 3430 #define DMA_SSTAT4_SSTAT_SHIFT (0U) 3431 #define DMA_SSTAT4_SSTAT_MASK (0xFFFFFFFFU << DMA_SSTAT4_SSTAT_SHIFT) 3432 /* DSTAT4 */ 3433 #define DMA_DSTAT4_OFFSET (0x188U) 3434 #define DMA_DSTAT4_DSTAT_SHIFT (0U) 3435 #define DMA_DSTAT4_DSTAT_MASK (0xFFFFFFFFU << DMA_DSTAT4_DSTAT_SHIFT) 3436 /* SSTATAR4 */ 3437 #define DMA_SSTATAR4_OFFSET (0x190U) 3438 #define DMA_SSTATAR4_SSTATAR_SHIFT (0U) 3439 #define DMA_SSTATAR4_SSTATAR_MASK (0xFFFFFFFFU << DMA_SSTATAR4_SSTATAR_SHIFT) 3440 /* DSTATAR4 */ 3441 #define DMA_DSTATAR4_OFFSET (0x198U) 3442 #define DMA_DSTATAR4_DSTATAR_SHIFT (0U) 3443 #define DMA_DSTATAR4_DSTATAR_MASK (0xFFFFFFFFU << DMA_DSTATAR4_DSTATAR_SHIFT) 3444 /* CFG4 */ 3445 #define DMA_CFG4_OFFSET (0x1A0U) 3446 #define DMA_CFG4_CH_PRIOR_SHIFT (5U) 3447 #define DMA_CFG4_CH_PRIOR_MASK (0x7U << DMA_CFG4_CH_PRIOR_SHIFT) 3448 #define DMA_CFG4_CH_SUSP_SHIFT (8U) 3449 #define DMA_CFG4_CH_SUSP_MASK (0x1U << DMA_CFG4_CH_SUSP_SHIFT) 3450 #define DMA_CFG4_FIFO_EMPTY_SHIFT (9U) 3451 #define DMA_CFG4_FIFO_EMPTY_MASK (0x1U << DMA_CFG4_FIFO_EMPTY_SHIFT) 3452 #define DMA_CFG4_HS_SEL_DST_SHIFT (10U) 3453 #define DMA_CFG4_HS_SEL_DST_MASK (0x1U << DMA_CFG4_HS_SEL_DST_SHIFT) 3454 #define DMA_CFG4_HS_SEL_SRC_SHIFT (11U) 3455 #define DMA_CFG4_HS_SEL_SRC_MASK (0x1U << DMA_CFG4_HS_SEL_SRC_SHIFT) 3456 #define DMA_CFG4_LOCK_CH_L_SHIFT (12U) 3457 #define DMA_CFG4_LOCK_CH_L_MASK (0x3U << DMA_CFG4_LOCK_CH_L_SHIFT) 3458 #define DMA_CFG4_LOCK_B_L_SHIFT (14U) 3459 #define DMA_CFG4_LOCK_B_L_MASK (0x3U << DMA_CFG4_LOCK_B_L_SHIFT) 3460 #define DMA_CFG4_LOCK_CH_SHIFT (16U) 3461 #define DMA_CFG4_LOCK_CH_MASK (0x1U << DMA_CFG4_LOCK_CH_SHIFT) 3462 #define DMA_CFG4_LOCK_B_SHIFT (17U) 3463 #define DMA_CFG4_LOCK_B_MASK (0x1U << DMA_CFG4_LOCK_B_SHIFT) 3464 #define DMA_CFG4_DST_HS_POL_SHIFT (18U) 3465 #define DMA_CFG4_DST_HS_POL_MASK (0x1U << DMA_CFG4_DST_HS_POL_SHIFT) 3466 #define DMA_CFG4_SRC_HS_POL_SHIFT (19U) 3467 #define DMA_CFG4_SRC_HS_POL_MASK (0x1U << DMA_CFG4_SRC_HS_POL_SHIFT) 3468 #define DMA_CFG4_MAX_ABRST_SHIFT (20U) 3469 #define DMA_CFG4_MAX_ABRST_MASK (0x3FFU << DMA_CFG4_MAX_ABRST_SHIFT) 3470 #define DMA_CFG4_RELOAD_SRC_SHIFT (30U) 3471 #define DMA_CFG4_RELOAD_SRC_MASK (0x1U << DMA_CFG4_RELOAD_SRC_SHIFT) 3472 #define DMA_CFG4_RELOAD_DST_SHIFT (31U) 3473 #define DMA_CFG4_RELOAD_DST_MASK (0x1U << DMA_CFG4_RELOAD_DST_SHIFT) 3474 #define DMA_CFG4_FCMODE_SHIFT (32U) 3475 #define DMA_CFG4_FCMODE_MASK (0x1U << DMA_CFG4_FCMODE_SHIFT) 3476 #define DMA_CFG4_FIFO_MODE_SHIFT (33U) 3477 #define DMA_CFG4_FIFO_MODE_MASK (0x1U << DMA_CFG4_FIFO_MODE_SHIFT) 3478 #define DMA_CFG4_PROTCTL_SHIFT (34U) 3479 #define DMA_CFG4_PROTCTL_MASK (0x7U << DMA_CFG4_PROTCTL_SHIFT) 3480 #define DMA_CFG4_DS_UPD_EN_SHIFT (37U) 3481 #define DMA_CFG4_DS_UPD_EN_MASK (0x1U << DMA_CFG4_DS_UPD_EN_SHIFT) 3482 #define DMA_CFG4_SS_UPD_EN_SHIFT (38U) 3483 #define DMA_CFG4_SS_UPD_EN_MASK (0x1U << DMA_CFG4_SS_UPD_EN_SHIFT) 3484 #define DMA_CFG4_SRC_PER_SHIFT (39U) 3485 #define DMA_CFG4_SRC_PER_MASK (0xFU << DMA_CFG4_SRC_PER_SHIFT) 3486 #define DMA_CFG4_DEST_PER_SHIFT (43U) 3487 #define DMA_CFG4_DEST_PER_MASK (0xFU << DMA_CFG4_DEST_PER_SHIFT) 3488 /* SGR4 */ 3489 #define DMA_SGR4_OFFSET (0x1A8U) 3490 #define DMA_SGR4_SGI_SHIFT (0U) 3491 #define DMA_SGR4_SGI_MASK (0xFFFFFU << DMA_SGR4_SGI_SHIFT) 3492 #define DMA_SGR4_SGC_SHIFT (20U) 3493 #define DMA_SGR4_SGC_MASK (0xFFFU << DMA_SGR4_SGC_SHIFT) 3494 /* DSR4 */ 3495 #define DMA_DSR4_OFFSET (0x1B0U) 3496 #define DMA_DSR4_DSI_SHIFT (0U) 3497 #define DMA_DSR4_DSI_MASK (0xFFFFFU << DMA_DSR4_DSI_SHIFT) 3498 #define DMA_DSR4_DSC_SHIFT (20U) 3499 #define DMA_DSR4_DSC_MASK (0xFFFU << DMA_DSR4_DSC_SHIFT) 3500 /* RESERVED01B4 */ 3501 #define DMA_RESERVED01B4_OFFSET (0x1B4U) 3502 /* SAR5 */ 3503 #define DMA_SAR5_OFFSET (0x1B8U) 3504 #define DMA_SAR5_SAR_SHIFT (0U) 3505 #define DMA_SAR5_SAR_MASK (0xFFFFFFFFU << DMA_SAR5_SAR_SHIFT) 3506 /* DAR5 */ 3507 #define DMA_DAR5_OFFSET (0x1C0U) 3508 #define DMA_DAR5_DAR_SHIFT (0U) 3509 #define DMA_DAR5_DAR_MASK (0xFFFFFFFFU << DMA_DAR5_DAR_SHIFT) 3510 /* LLP5 */ 3511 #define DMA_LLP5_OFFSET (0x1C8U) 3512 #define DMA_LLP5_LMS_SHIFT (0U) 3513 #define DMA_LLP5_LMS_MASK (0x3U << DMA_LLP5_LMS_SHIFT) 3514 #define DMA_LLP5_LOC_SHIFT (2U) 3515 #define DMA_LLP5_LOC_MASK (0x3FFFFFFFU << DMA_LLP5_LOC_SHIFT) 3516 /* CTL5 */ 3517 #define DMA_CTL5_OFFSET (0x1D0U) 3518 #define DMA_CTL5_INT_EN_SHIFT (0U) 3519 #define DMA_CTL5_INT_EN_MASK (0x1U << DMA_CTL5_INT_EN_SHIFT) 3520 #define DMA_CTL5_DST_TR_WIDTH_SHIFT (1U) 3521 #define DMA_CTL5_DST_TR_WIDTH_MASK (0x7U << DMA_CTL5_DST_TR_WIDTH_SHIFT) 3522 #define DMA_CTL5_SRC_TR_WIDTH_SHIFT (4U) 3523 #define DMA_CTL5_SRC_TR_WIDTH_MASK (0x7U << DMA_CTL5_SRC_TR_WIDTH_SHIFT) 3524 #define DMA_CTL5_DINC_SHIFT (7U) 3525 #define DMA_CTL5_DINC_MASK (0x3U << DMA_CTL5_DINC_SHIFT) 3526 #define DMA_CTL5_SINC_SHIFT (9U) 3527 #define DMA_CTL5_SINC_MASK (0x3U << DMA_CTL5_SINC_SHIFT) 3528 #define DMA_CTL5_DEST_MSIZE_SHIFT (11U) 3529 #define DMA_CTL5_DEST_MSIZE_MASK (0x7U << DMA_CTL5_DEST_MSIZE_SHIFT) 3530 #define DMA_CTL5_SRC_MSIZE_SHIFT (14U) 3531 #define DMA_CTL5_SRC_MSIZE_MASK (0x7U << DMA_CTL5_SRC_MSIZE_SHIFT) 3532 #define DMA_CTL5_SRC_GATHER_EN_SHIFT (17U) 3533 #define DMA_CTL5_SRC_GATHER_EN_MASK (0x1U << DMA_CTL5_SRC_GATHER_EN_SHIFT) 3534 #define DMA_CTL5_DST_SCATTER_EN_SHIFT (18U) 3535 #define DMA_CTL5_DST_SCATTER_EN_MASK (0x1U << DMA_CTL5_DST_SCATTER_EN_SHIFT) 3536 #define DMA_CTL5_TT_FC_SHIFT (20U) 3537 #define DMA_CTL5_TT_FC_MASK (0x7U << DMA_CTL5_TT_FC_SHIFT) 3538 #define DMA_CTL5_DMS_SHIFT (23U) 3539 #define DMA_CTL5_DMS_MASK (0x3U << DMA_CTL5_DMS_SHIFT) 3540 #define DMA_CTL5_SMS_SHIFT (25U) 3541 #define DMA_CTL5_SMS_MASK (0x3U << DMA_CTL5_SMS_SHIFT) 3542 #define DMA_CTL5_LLP_DST_EN_SHIFT (27U) 3543 #define DMA_CTL5_LLP_DST_EN_MASK (0x1U << DMA_CTL5_LLP_DST_EN_SHIFT) 3544 #define DMA_CTL5_LLP_SRC_EN_SHIFT (28U) 3545 #define DMA_CTL5_LLP_SRC_EN_MASK (0x1U << DMA_CTL5_LLP_SRC_EN_SHIFT) 3546 #define DMA_CTL5_BLOCK_TS_SHIFT (32U) 3547 #define DMA_CTL5_BLOCK_TS_MASK (0xFFFU << DMA_CTL5_BLOCK_TS_SHIFT) 3548 #define DMA_CTL5_DONE_SHIFT (44U) 3549 #define DMA_CTL5_DONE_MASK (0x1U << DMA_CTL5_DONE_SHIFT) 3550 /* SSTAT5 */ 3551 #define DMA_SSTAT5_OFFSET (0x1D8U) 3552 #define DMA_SSTAT5_SSTAT_SHIFT (0U) 3553 #define DMA_SSTAT5_SSTAT_MASK (0xFFFFFFFFU << DMA_SSTAT5_SSTAT_SHIFT) 3554 /* DSTAT5 */ 3555 #define DMA_DSTAT5_OFFSET (0x1E0U) 3556 #define DMA_DSTAT5_DSTAT_SHIFT (0U) 3557 #define DMA_DSTAT5_DSTAT_MASK (0xFFFFFFFFU << DMA_DSTAT5_DSTAT_SHIFT) 3558 /* SSTATAR5 */ 3559 #define DMA_SSTATAR5_OFFSET (0x1E8U) 3560 #define DMA_SSTATAR5_SSTATAR_SHIFT (0U) 3561 #define DMA_SSTATAR5_SSTATAR_MASK (0xFFFFFFFFU << DMA_SSTATAR5_SSTATAR_SHIFT) 3562 /* DSTATAR5 */ 3563 #define DMA_DSTATAR5_OFFSET (0x1F0U) 3564 #define DMA_DSTATAR5_DSTATAR_SHIFT (0U) 3565 #define DMA_DSTATAR5_DSTATAR_MASK (0xFFFFFFFFU << DMA_DSTATAR5_DSTATAR_SHIFT) 3566 /* CFG5 */ 3567 #define DMA_CFG5_OFFSET (0x1F8U) 3568 #define DMA_CFG5_CH_PRIOR_SHIFT (5U) 3569 #define DMA_CFG5_CH_PRIOR_MASK (0x7U << DMA_CFG5_CH_PRIOR_SHIFT) 3570 #define DMA_CFG5_CH_SUSP_SHIFT (8U) 3571 #define DMA_CFG5_CH_SUSP_MASK (0x1U << DMA_CFG5_CH_SUSP_SHIFT) 3572 #define DMA_CFG5_FIFO_EMPTY_SHIFT (9U) 3573 #define DMA_CFG5_FIFO_EMPTY_MASK (0x1U << DMA_CFG5_FIFO_EMPTY_SHIFT) 3574 #define DMA_CFG5_HS_SEL_DST_SHIFT (10U) 3575 #define DMA_CFG5_HS_SEL_DST_MASK (0x1U << DMA_CFG5_HS_SEL_DST_SHIFT) 3576 #define DMA_CFG5_HS_SEL_SRC_SHIFT (11U) 3577 #define DMA_CFG5_HS_SEL_SRC_MASK (0x1U << DMA_CFG5_HS_SEL_SRC_SHIFT) 3578 #define DMA_CFG5_LOCK_CH_L_SHIFT (12U) 3579 #define DMA_CFG5_LOCK_CH_L_MASK (0x3U << DMA_CFG5_LOCK_CH_L_SHIFT) 3580 #define DMA_CFG5_LOCK_B_L_SHIFT (14U) 3581 #define DMA_CFG5_LOCK_B_L_MASK (0x3U << DMA_CFG5_LOCK_B_L_SHIFT) 3582 #define DMA_CFG5_LOCK_CH_SHIFT (16U) 3583 #define DMA_CFG5_LOCK_CH_MASK (0x1U << DMA_CFG5_LOCK_CH_SHIFT) 3584 #define DMA_CFG5_LOCK_B_SHIFT (17U) 3585 #define DMA_CFG5_LOCK_B_MASK (0x1U << DMA_CFG5_LOCK_B_SHIFT) 3586 #define DMA_CFG5_DST_HS_POL_SHIFT (18U) 3587 #define DMA_CFG5_DST_HS_POL_MASK (0x1U << DMA_CFG5_DST_HS_POL_SHIFT) 3588 #define DMA_CFG5_SRC_HS_POL_SHIFT (19U) 3589 #define DMA_CFG5_SRC_HS_POL_MASK (0x1U << DMA_CFG5_SRC_HS_POL_SHIFT) 3590 #define DMA_CFG5_MAX_ABRST_SHIFT (20U) 3591 #define DMA_CFG5_MAX_ABRST_MASK (0x3FFU << DMA_CFG5_MAX_ABRST_SHIFT) 3592 #define DMA_CFG5_RELOAD_SRC_SHIFT (30U) 3593 #define DMA_CFG5_RELOAD_SRC_MASK (0x1U << DMA_CFG5_RELOAD_SRC_SHIFT) 3594 #define DMA_CFG5_RELOAD_DST_SHIFT (31U) 3595 #define DMA_CFG5_RELOAD_DST_MASK (0x1U << DMA_CFG5_RELOAD_DST_SHIFT) 3596 #define DMA_CFG5_FCMODE_SHIFT (32U) 3597 #define DMA_CFG5_FCMODE_MASK (0x1U << DMA_CFG5_FCMODE_SHIFT) 3598 #define DMA_CFG5_FIFO_MODE_SHIFT (33U) 3599 #define DMA_CFG5_FIFO_MODE_MASK (0x1U << DMA_CFG5_FIFO_MODE_SHIFT) 3600 #define DMA_CFG5_PROTCTL_SHIFT (34U) 3601 #define DMA_CFG5_PROTCTL_MASK (0x7U << DMA_CFG5_PROTCTL_SHIFT) 3602 #define DMA_CFG5_DS_UPD_EN_SHIFT (37U) 3603 #define DMA_CFG5_DS_UPD_EN_MASK (0x1U << DMA_CFG5_DS_UPD_EN_SHIFT) 3604 #define DMA_CFG5_SS_UPD_EN_SHIFT (38U) 3605 #define DMA_CFG5_SS_UPD_EN_MASK (0x1U << DMA_CFG5_SS_UPD_EN_SHIFT) 3606 #define DMA_CFG5_SRC_PER_SHIFT (39U) 3607 #define DMA_CFG5_SRC_PER_MASK (0xFU << DMA_CFG5_SRC_PER_SHIFT) 3608 #define DMA_CFG5_DEST_PER_SHIFT (43U) 3609 #define DMA_CFG5_DEST_PER_MASK (0xFU << DMA_CFG5_DEST_PER_SHIFT) 3610 /* SGR5 */ 3611 #define DMA_SGR5_OFFSET (0x200U) 3612 #define DMA_SGR5_SGI_SHIFT (0U) 3613 #define DMA_SGR5_SGI_MASK (0xFFFFFU << DMA_SGR5_SGI_SHIFT) 3614 #define DMA_SGR5_SGC_SHIFT (20U) 3615 #define DMA_SGR5_SGC_MASK (0xFFFU << DMA_SGR5_SGC_SHIFT) 3616 /* DSR5 */ 3617 #define DMA_DSR5_OFFSET (0x208U) 3618 #define DMA_DSR5_DSI_SHIFT (0U) 3619 #define DMA_DSR5_DSI_MASK (0xFFFFFU << DMA_DSR5_DSI_SHIFT) 3620 #define DMA_DSR5_DSC_SHIFT (20U) 3621 #define DMA_DSR5_DSC_MASK (0xFFFU << DMA_DSR5_DSC_SHIFT) 3622 /* RESERVED020C */ 3623 #define DMA_RESERVED020C_OFFSET (0x20CU) 3624 /* RAWTFR */ 3625 #define DMA_RAWTFR_OFFSET (0x2C0U) 3626 #define DMA_RAWTFR_RAW_SHIFT (0U) 3627 #define DMA_RAWTFR_RAW_MASK (0x3FU << DMA_RAWTFR_RAW_SHIFT) 3628 /* RAWBLOCK */ 3629 #define DMA_RAWBLOCK_OFFSET (0x2C8U) 3630 #define DMA_RAWBLOCK_RAW_SHIFT (0U) 3631 #define DMA_RAWBLOCK_RAW_MASK (0x3FU << DMA_RAWBLOCK_RAW_SHIFT) 3632 /* RAWSRCTRAN */ 3633 #define DMA_RAWSRCTRAN_OFFSET (0x2D0U) 3634 #define DMA_RAWSRCTRAN_RAW_SHIFT (0U) 3635 #define DMA_RAWSRCTRAN_RAW_MASK (0x3FU << DMA_RAWSRCTRAN_RAW_SHIFT) 3636 /* RAWDSTTRAN */ 3637 #define DMA_RAWDSTTRAN_OFFSET (0x2D8U) 3638 #define DMA_RAWDSTTRAN_RAW_SHIFT (0U) 3639 #define DMA_RAWDSTTRAN_RAW_MASK (0x3FU << DMA_RAWDSTTRAN_RAW_SHIFT) 3640 /* RAWERR */ 3641 #define DMA_RAWERR_OFFSET (0x2E0U) 3642 #define DMA_RAWERR_RAW_SHIFT (0U) 3643 #define DMA_RAWERR_RAW_MASK (0x3FU << DMA_RAWERR_RAW_SHIFT) 3644 /* RESERVED02E4 */ 3645 #define DMA_RESERVED02E4_OFFSET (0x2E4U) 3646 /* STATUSTFR */ 3647 #define DMA_STATUSTFR_OFFSET (0x2E8U) 3648 #define DMA_STATUSTFR (0x0U) 3649 #define DMA_STATUSTFR_STATUS_SHIFT (0U) 3650 #define DMA_STATUSTFR_STATUS_MASK (0x3FU << DMA_STATUSTFR_STATUS_SHIFT) 3651 /* STATUSBLOCK */ 3652 #define DMA_STATUSBLOCK_OFFSET (0x2F0U) 3653 #define DMA_STATUSBLOCK (0x0U) 3654 #define DMA_STATUSBLOCK_STATUS_SHIFT (0U) 3655 #define DMA_STATUSBLOCK_STATUS_MASK (0x3FU << DMA_STATUSBLOCK_STATUS_SHIFT) 3656 /* STATUSSRCTRAN */ 3657 #define DMA_STATUSSRCTRAN_OFFSET (0x2F8U) 3658 #define DMA_STATUSSRCTRAN (0x0U) 3659 #define DMA_STATUSSRCTRAN_STATUS_SHIFT (0U) 3660 #define DMA_STATUSSRCTRAN_STATUS_MASK (0x3FU << DMA_STATUSSRCTRAN_STATUS_SHIFT) 3661 /* STATUSDSTTRAN */ 3662 #define DMA_STATUSDSTTRAN_OFFSET (0x300U) 3663 #define DMA_STATUSDSTTRAN (0x0U) 3664 #define DMA_STATUSDSTTRAN_STATUS_SHIFT (0U) 3665 #define DMA_STATUSDSTTRAN_STATUS_MASK (0x3FU << DMA_STATUSDSTTRAN_STATUS_SHIFT) 3666 /* STATUSERR */ 3667 #define DMA_STATUSERR_OFFSET (0x308U) 3668 #define DMA_STATUSERR (0x0U) 3669 #define DMA_STATUSERR_STATUS_SHIFT (0U) 3670 #define DMA_STATUSERR_STATUS_MASK (0x3FU << DMA_STATUSERR_STATUS_SHIFT) 3671 /* RESERVED030C */ 3672 #define DMA_RESERVED030C_OFFSET (0x30CU) 3673 /* MASKTFR */ 3674 #define DMA_MASKTFR_OFFSET (0x310U) 3675 #define DMA_MASKTFR_INT_MASK_SHIFT (0U) 3676 #define DMA_MASKTFR_INT_MASK_MASK (0x3FU << DMA_MASKTFR_INT_MASK_SHIFT) 3677 #define DMA_MASKTFR_INT_MASK_WE_SHIFT (8U) 3678 #define DMA_MASKTFR_INT_MASK_WE_MASK (0x3FU << DMA_MASKTFR_INT_MASK_WE_SHIFT) 3679 /* MASKBLOCK */ 3680 #define DMA_MASKBLOCK_OFFSET (0x318U) 3681 #define DMA_MASKBLOCK_INT_MASK_SHIFT (0U) 3682 #define DMA_MASKBLOCK_INT_MASK_MASK (0x3FU << DMA_MASKBLOCK_INT_MASK_SHIFT) 3683 #define DMA_MASKBLOCK_INT_MASK_WE_SHIFT (8U) 3684 #define DMA_MASKBLOCK_INT_MASK_WE_MASK (0x3FU << DMA_MASKBLOCK_INT_MASK_WE_SHIFT) 3685 /* MASKSRCTRAN */ 3686 #define DMA_MASKSRCTRAN_OFFSET (0x320U) 3687 #define DMA_MASKSRCTRAN_INT_MASK_SHIFT (0U) 3688 #define DMA_MASKSRCTRAN_INT_MASK_MASK (0x3FU << DMA_MASKSRCTRAN_INT_MASK_SHIFT) 3689 #define DMA_MASKSRCTRAN_INT_MASK_WE_SHIFT (8U) 3690 #define DMA_MASKSRCTRAN_INT_MASK_WE_MASK (0x3FU << DMA_MASKSRCTRAN_INT_MASK_WE_SHIFT) 3691 /* MASKDSTTRAN */ 3692 #define DMA_MASKDSTTRAN_OFFSET (0x328U) 3693 #define DMA_MASKDSTTRAN_INT_MASK_SHIFT (0U) 3694 #define DMA_MASKDSTTRAN_INT_MASK_MASK (0x3FU << DMA_MASKDSTTRAN_INT_MASK_SHIFT) 3695 #define DMA_MASKDSTTRAN_INT_MASK_WE_SHIFT (8U) 3696 #define DMA_MASKDSTTRAN_INT_MASK_WE_MASK (0x3FU << DMA_MASKDSTTRAN_INT_MASK_WE_SHIFT) 3697 /* MASKERR */ 3698 #define DMA_MASKERR_OFFSET (0x330U) 3699 #define DMA_MASKERR_INT_MASK_SHIFT (0U) 3700 #define DMA_MASKERR_INT_MASK_MASK (0x3FU << DMA_MASKERR_INT_MASK_SHIFT) 3701 #define DMA_MASKERR_INT_MASK_WE_SHIFT (8U) 3702 #define DMA_MASKERR_INT_MASK_WE_MASK (0x3FU << DMA_MASKERR_INT_MASK_WE_SHIFT) 3703 /* RESERVED0334 */ 3704 #define DMA_RESERVED0334_OFFSET (0x334U) 3705 /* CLEARTFR */ 3706 #define DMA_CLEARTFR_OFFSET (0x338U) 3707 #define DMA_CLEARTFR_CLEAR_SHIFT (0U) 3708 #define DMA_CLEARTFR_CLEAR_MASK (0x3FU << DMA_CLEARTFR_CLEAR_SHIFT) 3709 /* CLEARBLOCK */ 3710 #define DMA_CLEARBLOCK_OFFSET (0x340U) 3711 #define DMA_CLEARBLOCK_CLEAR_SHIFT (0U) 3712 #define DMA_CLEARBLOCK_CLEAR_MASK (0x3FU << DMA_CLEARBLOCK_CLEAR_SHIFT) 3713 /* CLEARSRCTRAN */ 3714 #define DMA_CLEARSRCTRAN_OFFSET (0x348U) 3715 #define DMA_CLEARSRCTRAN_CLEAR_SHIFT (0U) 3716 #define DMA_CLEARSRCTRAN_CLEAR_MASK (0x3FU << DMA_CLEARSRCTRAN_CLEAR_SHIFT) 3717 /* CLEARDSTTRAN */ 3718 #define DMA_CLEARDSTTRAN_OFFSET (0x350U) 3719 #define DMA_CLEARDSTTRAN_CLEAR_SHIFT (0U) 3720 #define DMA_CLEARDSTTRAN_CLEAR_MASK (0x3FU << DMA_CLEARDSTTRAN_CLEAR_SHIFT) 3721 /* CLEARERR */ 3722 #define DMA_CLEARERR_OFFSET (0x358U) 3723 #define DMA_CLEARERR_CLEAR_SHIFT (0U) 3724 #define DMA_CLEARERR_CLEAR_MASK (0x3FU << DMA_CLEARERR_CLEAR_SHIFT) 3725 /* RESERVED035C */ 3726 #define DMA_RESERVED035C_OFFSET (0x35CU) 3727 /* STATUSINT */ 3728 #define DMA_STATUSINT_OFFSET (0x360U) 3729 #define DMA_STATUSINT (0x0U) 3730 #define DMA_STATUSINT_TFR_SHIFT (0U) 3731 #define DMA_STATUSINT_TFR_MASK (0x1U << DMA_STATUSINT_TFR_SHIFT) 3732 #define DMA_STATUSINT_BLOCK_SHIFT (1U) 3733 #define DMA_STATUSINT_BLOCK_MASK (0x1U << DMA_STATUSINT_BLOCK_SHIFT) 3734 #define DMA_STATUSINT_SRCT_SHIFT (2U) 3735 #define DMA_STATUSINT_SRCT_MASK (0x1U << DMA_STATUSINT_SRCT_SHIFT) 3736 #define DMA_STATUSINT_DSTT_SHIFT (3U) 3737 #define DMA_STATUSINT_DSTT_MASK (0x1U << DMA_STATUSINT_DSTT_SHIFT) 3738 #define DMA_STATUSINT_ERR_SHIFT (4U) 3739 #define DMA_STATUSINT_ERR_MASK (0x1U << DMA_STATUSINT_ERR_SHIFT) 3740 /* DMACFGREG */ 3741 #define DMA_DMACFGREG_OFFSET (0x398U) 3742 #define DMA_DMACFGREG_DMA_EN_SHIFT (0U) 3743 #define DMA_DMACFGREG_DMA_EN_MASK (0x1U << DMA_DMACFGREG_DMA_EN_SHIFT) 3744 /* CHENREG */ 3745 #define DMA_CHENREG_OFFSET (0x3A0U) 3746 #define DMA_CHENREG_CH_EN_SHIFT (0U) 3747 #define DMA_CHENREG_CH_EN_MASK (0x3FU << DMA_CHENREG_CH_EN_SHIFT) 3748 #define DMA_CHENREG_CH_EN_WE_SHIFT (8U) 3749 #define DMA_CHENREG_CH_EN_WE_MASK (0x3FU << DMA_CHENREG_CH_EN_WE_SHIFT) 3750 /******************************************FSPI******************************************/ 3751 /* CTRL0 */ 3752 #define FSPI_CTRL0_OFFSET (0x0U) 3753 #define FSPI_CTRL0_SPIM_SHIFT (0U) 3754 #define FSPI_CTRL0_SPIM_MASK (0x1U << FSPI_CTRL0_SPIM_SHIFT) 3755 #define FSPI_CTRL0_SHIFTPHASE_SHIFT (1U) 3756 #define FSPI_CTRL0_SHIFTPHASE_MASK (0x1U << FSPI_CTRL0_SHIFTPHASE_SHIFT) 3757 #define FSPI_CTRL0_IDLE_CYCLE_SHIFT (4U) 3758 #define FSPI_CTRL0_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL0_IDLE_CYCLE_SHIFT) 3759 #define FSPI_CTRL0_CMDB_SHIFT (8U) 3760 #define FSPI_CTRL0_CMDB_MASK (0x3U << FSPI_CTRL0_CMDB_SHIFT) 3761 #define FSPI_CTRL0_ADRB_SHIFT (10U) 3762 #define FSPI_CTRL0_ADRB_MASK (0x3U << FSPI_CTRL0_ADRB_SHIFT) 3763 #define FSPI_CTRL0_DATB_SHIFT (12U) 3764 #define FSPI_CTRL0_DATB_MASK (0x3U << FSPI_CTRL0_DATB_SHIFT) 3765 /* IMR */ 3766 #define FSPI_IMR_OFFSET (0x4U) 3767 #define FSPI_IMR_RXFM_SHIFT (0U) 3768 #define FSPI_IMR_RXFM_MASK (0x1U << FSPI_IMR_RXFM_SHIFT) 3769 #define FSPI_IMR_RXUM_SHIFT (1U) 3770 #define FSPI_IMR_RXUM_MASK (0x1U << FSPI_IMR_RXUM_SHIFT) 3771 #define FSPI_IMR_TXOM_SHIFT (2U) 3772 #define FSPI_IMR_TXOM_MASK (0x1U << FSPI_IMR_TXOM_SHIFT) 3773 #define FSPI_IMR_TXEM_SHIFT (3U) 3774 #define FSPI_IMR_TXEM_MASK (0x1U << FSPI_IMR_TXEM_SHIFT) 3775 #define FSPI_IMR_TRANSM_SHIFT (4U) 3776 #define FSPI_IMR_TRANSM_MASK (0x1U << FSPI_IMR_TRANSM_SHIFT) 3777 #define FSPI_IMR_AHBM_SHIFT (5U) 3778 #define FSPI_IMR_AHBM_MASK (0x1U << FSPI_IMR_AHBM_SHIFT) 3779 #define FSPI_IMR_NSPIM_SHIFT (6U) 3780 #define FSPI_IMR_NSPIM_MASK (0x1U << FSPI_IMR_NSPIM_SHIFT) 3781 #define FSPI_IMR_DMAM_SHIFT (7U) 3782 #define FSPI_IMR_DMAM_MASK (0x1U << FSPI_IMR_DMAM_SHIFT) 3783 #define FSPI_IMR_STPOLLM_SHIFT (8U) 3784 #define FSPI_IMR_STPOLLM_MASK (0x1U << FSPI_IMR_STPOLLM_SHIFT) 3785 /* ICLR */ 3786 #define FSPI_ICLR_OFFSET (0x8U) 3787 #define FSPI_ICLR_RXFC_SHIFT (0U) 3788 #define FSPI_ICLR_RXFC_MASK (0x1U << FSPI_ICLR_RXFC_SHIFT) 3789 #define FSPI_ICLR_RXUC_SHIFT (1U) 3790 #define FSPI_ICLR_RXUC_MASK (0x1U << FSPI_ICLR_RXUC_SHIFT) 3791 #define FSPI_ICLR_TXOC_SHIFT (2U) 3792 #define FSPI_ICLR_TXOC_MASK (0x1U << FSPI_ICLR_TXOC_SHIFT) 3793 #define FSPI_ICLR_TXEC_SHIFT (3U) 3794 #define FSPI_ICLR_TXEC_MASK (0x1U << FSPI_ICLR_TXEC_SHIFT) 3795 #define FSPI_ICLR_TRANSC_SHIFT (4U) 3796 #define FSPI_ICLR_TRANSC_MASK (0x1U << FSPI_ICLR_TRANSC_SHIFT) 3797 #define FSPI_ICLR_AHBC_SHIFT (5U) 3798 #define FSPI_ICLR_AHBC_MASK (0x1U << FSPI_ICLR_AHBC_SHIFT) 3799 #define FSPI_ICLR_NSPIC_SHIFT (6U) 3800 #define FSPI_ICLR_NSPIC_MASK (0x1U << FSPI_ICLR_NSPIC_SHIFT) 3801 #define FSPI_ICLR_DMAC_SHIFT (7U) 3802 #define FSPI_ICLR_DMAC_MASK (0x1U << FSPI_ICLR_DMAC_SHIFT) 3803 #define FSPI_ICLR_STPOLLC_SHIFT (8U) 3804 #define FSPI_ICLR_STPOLLC_MASK (0x1U << FSPI_ICLR_STPOLLC_SHIFT) 3805 /* FTLR */ 3806 #define FSPI_FTLR_OFFSET (0xCU) 3807 #define FSPI_FTLR_TXFTLR_SHIFT (0U) 3808 #define FSPI_FTLR_TXFTLR_MASK (0xFFU << FSPI_FTLR_TXFTLR_SHIFT) 3809 #define FSPI_FTLR_RXFTLR_SHIFT (8U) 3810 #define FSPI_FTLR_RXFTLR_MASK (0xFFU << FSPI_FTLR_RXFTLR_SHIFT) 3811 /* RCVR */ 3812 #define FSPI_RCVR_OFFSET (0x10U) 3813 #define FSPI_RCVR_RCVR_SHIFT (0U) 3814 #define FSPI_RCVR_RCVR_MASK (0x1U << FSPI_RCVR_RCVR_SHIFT) 3815 /* AX0 */ 3816 #define FSPI_AX0_OFFSET (0x14U) 3817 #define FSPI_AX0_AX_SHIFT (0U) 3818 #define FSPI_AX0_AX_MASK (0xFFU << FSPI_AX0_AX_SHIFT) 3819 /* ABIT0 */ 3820 #define FSPI_ABIT0_OFFSET (0x18U) 3821 #define FSPI_ABIT0_ABIT_SHIFT (0U) 3822 #define FSPI_ABIT0_ABIT_MASK (0x1FU << FSPI_ABIT0_ABIT_SHIFT) 3823 /* ISR */ 3824 #define FSPI_ISR_OFFSET (0x1CU) 3825 #define FSPI_ISR_RXFS_SHIFT (0U) 3826 #define FSPI_ISR_RXFS_MASK (0x1U << FSPI_ISR_RXFS_SHIFT) 3827 #define FSPI_ISR_RXUS_SHIFT (1U) 3828 #define FSPI_ISR_RXUS_MASK (0x1U << FSPI_ISR_RXUS_SHIFT) 3829 #define FSPI_ISR_TXOS_SHIFT (2U) 3830 #define FSPI_ISR_TXOS_MASK (0x1U << FSPI_ISR_TXOS_SHIFT) 3831 #define FSPI_ISR_TXES_SHIFT (3U) 3832 #define FSPI_ISR_TXES_MASK (0x1U << FSPI_ISR_TXES_SHIFT) 3833 #define FSPI_ISR_TRANSS_SHIFT (4U) 3834 #define FSPI_ISR_TRANSS_MASK (0x1U << FSPI_ISR_TRANSS_SHIFT) 3835 #define FSPI_ISR_AHBS_SHIFT (5U) 3836 #define FSPI_ISR_AHBS_MASK (0x1U << FSPI_ISR_AHBS_SHIFT) 3837 #define FSPI_ISR_NSPIS_SHIFT (6U) 3838 #define FSPI_ISR_NSPIS_MASK (0x1U << FSPI_ISR_NSPIS_SHIFT) 3839 #define FSPI_ISR_DMAS_SHIFT (7U) 3840 #define FSPI_ISR_DMAS_MASK (0x1U << FSPI_ISR_DMAS_SHIFT) 3841 #define FSPI_ISR_STPOLLS_SHIFT (8U) 3842 #define FSPI_ISR_STPOLLS_MASK (0x1U << FSPI_ISR_STPOLLS_SHIFT) 3843 /* FSR */ 3844 #define FSPI_FSR_OFFSET (0x20U) 3845 #define FSPI_FSR_TXFS_SHIFT (0U) 3846 #define FSPI_FSR_TXFS_MASK (0x1U << FSPI_FSR_TXFS_SHIFT) 3847 #define FSPI_FSR_TXES_SHIFT (1U) 3848 #define FSPI_FSR_TXES_MASK (0x1U << FSPI_FSR_TXES_SHIFT) 3849 #define FSPI_FSR_RXES_SHIFT (2U) 3850 #define FSPI_FSR_RXES_MASK (0x1U << FSPI_FSR_RXES_SHIFT) 3851 #define FSPI_FSR_RXFS_SHIFT (3U) 3852 #define FSPI_FSR_RXFS_MASK (0x1U << FSPI_FSR_RXFS_SHIFT) 3853 #define FSPI_FSR_TXWLVL_SHIFT (8U) 3854 #define FSPI_FSR_TXWLVL_MASK (0x1FU << FSPI_FSR_TXWLVL_SHIFT) 3855 #define FSPI_FSR_RXWLVL_SHIFT (16U) 3856 #define FSPI_FSR_RXWLVL_MASK (0x1FU << FSPI_FSR_RXWLVL_SHIFT) 3857 /* SR */ 3858 #define FSPI_SR_OFFSET (0x24U) 3859 #define FSPI_SR (0x0U) 3860 #define FSPI_SR_SR_SHIFT (0U) 3861 #define FSPI_SR_SR_MASK (0x1U << FSPI_SR_SR_SHIFT) 3862 /* RISR */ 3863 #define FSPI_RISR_OFFSET (0x28U) 3864 #define FSPI_RISR (0x0U) 3865 #define FSPI_RISR_RXFS_SHIFT (0U) 3866 #define FSPI_RISR_RXFS_MASK (0x1U << FSPI_RISR_RXFS_SHIFT) 3867 #define FSPI_RISR_RXUS_SHIFT (1U) 3868 #define FSPI_RISR_RXUS_MASK (0x1U << FSPI_RISR_RXUS_SHIFT) 3869 #define FSPI_RISR_TXOS_SHIFT (2U) 3870 #define FSPI_RISR_TXOS_MASK (0x1U << FSPI_RISR_TXOS_SHIFT) 3871 #define FSPI_RISR_TXES_SHIFT (3U) 3872 #define FSPI_RISR_TXES_MASK (0x1U << FSPI_RISR_TXES_SHIFT) 3873 #define FSPI_RISR_TRANSS_SHIFT (4U) 3874 #define FSPI_RISR_TRANSS_MASK (0x1U << FSPI_RISR_TRANSS_SHIFT) 3875 #define FSPI_RISR_AHBS_SHIFT (5U) 3876 #define FSPI_RISR_AHBS_MASK (0x1U << FSPI_RISR_AHBS_SHIFT) 3877 #define FSPI_RISR_NSPIS_SHIFT (6U) 3878 #define FSPI_RISR_NSPIS_MASK (0x1U << FSPI_RISR_NSPIS_SHIFT) 3879 #define FSPI_RISR_DMAS_SHIFT (7U) 3880 #define FSPI_RISR_DMAS_MASK (0x1U << FSPI_RISR_DMAS_SHIFT) 3881 #define FSPI_RISR_STPOLLS_SHIFT (8U) 3882 #define FSPI_RISR_STPOLLS_MASK (0x1U << FSPI_RISR_STPOLLS_SHIFT) 3883 /* VER */ 3884 #define FSPI_VER_OFFSET (0x2CU) 3885 #define FSPI_VER (0x3U) 3886 #define FSPI_VER_VER_SHIFT (0U) 3887 #define FSPI_VER_VER_MASK (0xFFFFU << FSPI_VER_VER_SHIFT) 3888 /* QOP */ 3889 #define FSPI_QOP_OFFSET (0x30U) 3890 #define FSPI_QOP_SO123_SHIFT (0U) 3891 #define FSPI_QOP_SO123_MASK (0x1U << FSPI_QOP_SO123_SHIFT) 3892 #define FSPI_QOP_SO123BP_SHIFT (1U) 3893 #define FSPI_QOP_SO123BP_MASK (0x1U << FSPI_QOP_SO123BP_SHIFT) 3894 /* EXT_CTRL */ 3895 #define FSPI_EXT_CTRL_OFFSET (0x34U) 3896 #define FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT (0U) 3897 #define FSPI_EXT_CTRL_CS_DESEL_CTRL_MASK (0xFU << FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT) 3898 #define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT (4U) 3899 #define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT) 3900 #define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT (8U) 3901 #define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT) 3902 #define FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT (13U) 3903 #define FSPI_EXT_CTRL_TRANS_INT_MODE_MASK (0x1U << FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT) 3904 #define FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT (14U) 3905 #define FSPI_EXT_CTRL_SR_GEN_MODE_MASK (0x1U << FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT) 3906 /* POLL_CTRL */ 3907 #define FSPI_POLL_CTRL_OFFSET (0x38U) 3908 #define FSPI_POLL_CTRL_ST_POLL_EN_SHIFT (0U) 3909 #define FSPI_POLL_CTRL_ST_POLL_EN_MASK (0x1U << FSPI_POLL_CTRL_ST_POLL_EN_SHIFT) 3910 #define FSPI_POLL_CTRL_POLL_DLY_EN_SHIFT (1U) 3911 #define FSPI_POLL_CTRL_POLL_DLY_EN_MASK (0x1U << FSPI_POLL_CTRL_POLL_DLY_EN_SHIFT) 3912 #define FSPI_POLL_CTRL_ST_POLL_CMD_PARA_SHIFT (8U) 3913 #define FSPI_POLL_CTRL_ST_POLL_CMD_PARA_MASK (0xFFU << FSPI_POLL_CTRL_ST_POLL_CMD_PARA_SHIFT) 3914 #define FSPI_POLL_CTRL_ST_POLL_EXPECT_DATA_SHIFT (16U) 3915 #define FSPI_POLL_CTRL_ST_POLL_EXPECT_DATA_MASK (0xFFU << FSPI_POLL_CTRL_ST_POLL_EXPECT_DATA_SHIFT) 3916 #define FSPI_POLL_CTRL_ST_POLL_BIT_COMP_EN_SHIFT (24U) 3917 #define FSPI_POLL_CTRL_ST_POLL_BIT_COMP_EN_MASK (0xFFU << FSPI_POLL_CTRL_ST_POLL_BIT_COMP_EN_SHIFT) 3918 /* DLL_CTRL0 */ 3919 #define FSPI_DLL_CTRL0_OFFSET (0x3CU) 3920 #define FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT (0U) 3921 #define FSPI_DLL_CTRL0_SMP_DLL_CFG_MASK (0xFFU << FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT) 3922 #define FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT (8U) 3923 #define FSPI_DLL_CTRL0_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT) 3924 /* HRDYMASK */ 3925 #define FSPI_HRDYMASK_OFFSET (0x40U) 3926 #define FSPI_HRDYMASK_HRDYMASK_SHIFT (0U) 3927 #define FSPI_HRDYMASK_HRDYMASK_MASK (0x1U << FSPI_HRDYMASK_HRDYMASK_SHIFT) 3928 /* EXT_AX */ 3929 #define FSPI_EXT_AX_OFFSET (0x44U) 3930 #define FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT (0U) 3931 #define FSPI_EXT_AX_AX_CANCEL_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT) 3932 #define FSPI_EXT_AX_AX_SETUP_PAT_SHIFT (8U) 3933 #define FSPI_EXT_AX_AX_SETUP_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT) 3934 /* SCLK_INATM_CNT */ 3935 #define FSPI_SCLK_INATM_CNT_OFFSET (0x48U) 3936 #define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT (0U) 3937 #define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_MASK (0xFFFFFFFFU << FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT) 3938 /* AUTO_RF_CNT */ 3939 #define FSPI_AUTO_RF_CNT_OFFSET (0x4CU) 3940 #define FSPI_AUTO_RF_CNT_AUTO_RF_CNT_SHIFT (0U) 3941 #define FSPI_AUTO_RF_CNT_AUTO_RF_CNT_MASK (0xFFFFFFFFU << FSPI_AUTO_RF_CNT_AUTO_RF_CNT_SHIFT) 3942 /* XMMC_WCMD0 */ 3943 #define FSPI_XMMC_WCMD0_OFFSET (0x50U) 3944 #define FSPI_XMMC_WCMD0_CMD_SHIFT (0U) 3945 #define FSPI_XMMC_WCMD0_CMD_MASK (0xFFU << FSPI_XMMC_WCMD0_CMD_SHIFT) 3946 #define FSPI_XMMC_WCMD0_DUMM_SHIFT (8U) 3947 #define FSPI_XMMC_WCMD0_DUMM_MASK (0xFU << FSPI_XMMC_WCMD0_DUMM_SHIFT) 3948 #define FSPI_XMMC_WCMD0_CONT_SHIFT (13U) 3949 #define FSPI_XMMC_WCMD0_CONT_MASK (0x1U << FSPI_XMMC_WCMD0_CONT_SHIFT) 3950 #define FSPI_XMMC_WCMD0_ADDRB_SHIFT (14U) 3951 #define FSPI_XMMC_WCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD0_ADDRB_SHIFT) 3952 /* XMMC_RCMD0 */ 3953 #define FSPI_XMMC_RCMD0_OFFSET (0x54U) 3954 #define FSPI_XMMC_RCMD0_CMD_SHIFT (0U) 3955 #define FSPI_XMMC_RCMD0_CMD_MASK (0xFFU << FSPI_XMMC_RCMD0_CMD_SHIFT) 3956 #define FSPI_XMMC_RCMD0_DUMM_SHIFT (8U) 3957 #define FSPI_XMMC_RCMD0_DUMM_MASK (0xFU << FSPI_XMMC_RCMD0_DUMM_SHIFT) 3958 #define FSPI_XMMC_RCMD0_CONT_SHIFT (13U) 3959 #define FSPI_XMMC_RCMD0_CONT_MASK (0x1U << FSPI_XMMC_RCMD0_CONT_SHIFT) 3960 #define FSPI_XMMC_RCMD0_ADDRB_SHIFT (14U) 3961 #define FSPI_XMMC_RCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD0_ADDRB_SHIFT) 3962 /* XMMC_CTRL */ 3963 #define FSPI_XMMC_CTRL_OFFSET (0x58U) 3964 #define FSPI_XMMC_CTRL_DEV_HWEN_SHIFT (5U) 3965 #define FSPI_XMMC_CTRL_DEV_HWEN_MASK (0x1U << FSPI_XMMC_CTRL_DEV_HWEN_SHIFT) 3966 #define FSPI_XMMC_CTRL_PFT_EN_SHIFT (6U) 3967 #define FSPI_XMMC_CTRL_PFT_EN_MASK (0x1U << FSPI_XMMC_CTRL_PFT_EN_SHIFT) 3968 /* MODE */ 3969 #define FSPI_MODE_OFFSET (0x5CU) 3970 #define FSPI_MODE_XMMC_MODE_EN_SHIFT (0U) 3971 #define FSPI_MODE_XMMC_MODE_EN_MASK (0x1U << FSPI_MODE_XMMC_MODE_EN_SHIFT) 3972 /* DEVRGN */ 3973 #define FSPI_DEVRGN_OFFSET (0x60U) 3974 #define FSPI_DEVRGN_RSIZE_SHIFT (0U) 3975 #define FSPI_DEVRGN_RSIZE_MASK (0x1FU << FSPI_DEVRGN_RSIZE_SHIFT) 3976 /* DEVSIZE0 */ 3977 #define FSPI_DEVSIZE0_OFFSET (0x64U) 3978 #define FSPI_DEVSIZE0_DSIZE_SHIFT (0U) 3979 #define FSPI_DEVSIZE0_DSIZE_MASK (0x1FU << FSPI_DEVSIZE0_DSIZE_SHIFT) 3980 /* TME0 */ 3981 #define FSPI_TME0_OFFSET (0x68U) 3982 #define FSPI_TME0_AUTO_RF_EN_SHIFT (0U) 3983 #define FSPI_TME0_AUTO_RF_EN_MASK (0x1U << FSPI_TME0_AUTO_RF_EN_SHIFT) 3984 #define FSPI_TME0_SCLK_INATM_EN_SHIFT (1U) 3985 #define FSPI_TME0_SCLK_INATM_EN_MASK (0x1U << FSPI_TME0_SCLK_INATM_EN_SHIFT) 3986 /* POLLDLY_CTRL */ 3987 #define FSPI_POLLDLY_CTRL_OFFSET (0x6CU) 3988 #define FSPI_POLLDLY_CTRL_CNT_SHIFT (0U) 3989 #define FSPI_POLLDLY_CTRL_CNT_MASK (0x7FFFFFFFU << FSPI_POLLDLY_CTRL_CNT_SHIFT) 3990 #define FSPI_POLLDLY_CTRL_POLLDLY_IP_SHIFT (31U) 3991 #define FSPI_POLLDLY_CTRL_POLLDLY_IP_MASK (0x1U << FSPI_POLLDLY_CTRL_POLLDLY_IP_SHIFT) 3992 /* DMATR */ 3993 #define FSPI_DMATR_OFFSET (0x80U) 3994 #define FSPI_DMATR_DMATR_SHIFT (0U) 3995 #define FSPI_DMATR_DMATR_MASK (0x1U << FSPI_DMATR_DMATR_SHIFT) 3996 /* DMAADDR */ 3997 #define FSPI_DMAADDR_OFFSET (0x84U) 3998 #define FSPI_DMAADDR_DMAADDR_SHIFT (0U) 3999 #define FSPI_DMAADDR_DMAADDR_MASK (0xFFFFFFFFU << FSPI_DMAADDR_DMAADDR_SHIFT) 4000 /* POLL_DATA */ 4001 #define FSPI_POLL_DATA_OFFSET (0x90U) 4002 #define FSPI_POLL_DATA (0x0U) 4003 #define FSPI_POLL_DATA_POLL_DATA_SHIFT (0U) 4004 #define FSPI_POLL_DATA_POLL_DATA_MASK (0xFFU << FSPI_POLL_DATA_POLL_DATA_SHIFT) 4005 #define FSPI_POLL_DATA_POLL_STA_SHIFT (8U) 4006 #define FSPI_POLL_DATA_POLL_STA_MASK (0x1U << FSPI_POLL_DATA_POLL_STA_SHIFT) 4007 /* XMMCSR */ 4008 #define FSPI_XMMCSR_OFFSET (0x94U) 4009 #define FSPI_XMMCSR_SLOPOVER0_SHIFT (0U) 4010 #define FSPI_XMMCSR_SLOPOVER0_MASK (0x1U << FSPI_XMMCSR_SLOPOVER0_SHIFT) 4011 #define FSPI_XMMCSR_SLOPOVER1_SHIFT (1U) 4012 #define FSPI_XMMCSR_SLOPOVER1_MASK (0x1U << FSPI_XMMCSR_SLOPOVER1_SHIFT) 4013 /* CMD */ 4014 #define FSPI_CMD_OFFSET (0x100U) 4015 #define FSPI_CMD_CMD_SHIFT (0U) 4016 #define FSPI_CMD_CMD_MASK (0xFFU << FSPI_CMD_CMD_SHIFT) 4017 #define FSPI_CMD_DUMM_SHIFT (8U) 4018 #define FSPI_CMD_DUMM_MASK (0xFU << FSPI_CMD_DUMM_SHIFT) 4019 #define FSPI_CMD_WR_SHIFT (12U) 4020 #define FSPI_CMD_WR_MASK (0x1U << FSPI_CMD_WR_SHIFT) 4021 #define FSPI_CMD_CONT_SHIFT (13U) 4022 #define FSPI_CMD_CONT_MASK (0x1U << FSPI_CMD_CONT_SHIFT) 4023 #define FSPI_CMD_ADDRB_SHIFT (14U) 4024 #define FSPI_CMD_ADDRB_MASK (0x3U << FSPI_CMD_ADDRB_SHIFT) 4025 #define FSPI_CMD_TRB_SHIFT (16U) 4026 #define FSPI_CMD_TRB_MASK (0x3FFFU << FSPI_CMD_TRB_SHIFT) 4027 #define FSPI_CMD_CS_SHIFT (30U) 4028 #define FSPI_CMD_CS_MASK (0x3U << FSPI_CMD_CS_SHIFT) 4029 /* ADDR */ 4030 #define FSPI_ADDR_OFFSET (0x104U) 4031 #define FSPI_ADDR_ADDR_SHIFT (0U) 4032 #define FSPI_ADDR_ADDR_MASK (0xFFFFFFFFU << FSPI_ADDR_ADDR_SHIFT) 4033 /* DATA */ 4034 #define FSPI_DATA_OFFSET (0x108U) 4035 #define FSPI_DATA_DATA_SHIFT (0U) 4036 #define FSPI_DATA_DATA_MASK (0xFFFFFFFFU << FSPI_DATA_DATA_SHIFT) 4037 /* CTRL1 */ 4038 #define FSPI_CTRL1_OFFSET (0x200U) 4039 #define FSPI_CTRL1_SPIM_SHIFT (0U) 4040 #define FSPI_CTRL1_SPIM_MASK (0x1U << FSPI_CTRL1_SPIM_SHIFT) 4041 #define FSPI_CTRL1_SHIFTPHASE_SHIFT (1U) 4042 #define FSPI_CTRL1_SHIFTPHASE_MASK (0x1U << FSPI_CTRL1_SHIFTPHASE_SHIFT) 4043 #define FSPI_CTRL1_IDLE_CYCLE_SHIFT (4U) 4044 #define FSPI_CTRL1_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL1_IDLE_CYCLE_SHIFT) 4045 #define FSPI_CTRL1_CMDB_SHIFT (8U) 4046 #define FSPI_CTRL1_CMDB_MASK (0x3U << FSPI_CTRL1_CMDB_SHIFT) 4047 #define FSPI_CTRL1_ADRB_SHIFT (10U) 4048 #define FSPI_CTRL1_ADRB_MASK (0x3U << FSPI_CTRL1_ADRB_SHIFT) 4049 #define FSPI_CTRL1_DATB_SHIFT (12U) 4050 #define FSPI_CTRL1_DATB_MASK (0x3U << FSPI_CTRL1_DATB_SHIFT) 4051 /* AX1 */ 4052 #define FSPI_AX1_OFFSET (0x214U) 4053 #define FSPI_AX1_AX_SHIFT (0U) 4054 #define FSPI_AX1_AX_MASK (0xFFU << FSPI_AX1_AX_SHIFT) 4055 /* ABIT1 */ 4056 #define FSPI_ABIT1_OFFSET (0x218U) 4057 #define FSPI_ABIT1_ABIT_SHIFT (0U) 4058 #define FSPI_ABIT1_ABIT_MASK (0x1FU << FSPI_ABIT1_ABIT_SHIFT) 4059 /* DLL_CTRL1 */ 4060 #define FSPI_DLL_CTRL1_OFFSET (0x23CU) 4061 #define FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT (0U) 4062 #define FSPI_DLL_CTRL1_SMP_DLL_CFG_MASK (0xFFU << FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT) 4063 #define FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT (8U) 4064 #define FSPI_DLL_CTRL1_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT) 4065 /* XMMC_WCMD1 */ 4066 #define FSPI_XMMC_WCMD1_OFFSET (0x250U) 4067 #define FSPI_XMMC_WCMD1_CMD_SHIFT (0U) 4068 #define FSPI_XMMC_WCMD1_CMD_MASK (0xFFU << FSPI_XMMC_WCMD1_CMD_SHIFT) 4069 #define FSPI_XMMC_WCMD1_DUMM_SHIFT (8U) 4070 #define FSPI_XMMC_WCMD1_DUMM_MASK (0xFU << FSPI_XMMC_WCMD1_DUMM_SHIFT) 4071 #define FSPI_XMMC_WCMD1_CONT_SHIFT (13U) 4072 #define FSPI_XMMC_WCMD1_CONT_MASK (0x1U << FSPI_XMMC_WCMD1_CONT_SHIFT) 4073 #define FSPI_XMMC_WCMD1_ADDRB_SHIFT (14U) 4074 #define FSPI_XMMC_WCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD1_ADDRB_SHIFT) 4075 /* XMMC_RCMD1 */ 4076 #define FSPI_XMMC_RCMD1_OFFSET (0x254U) 4077 #define FSPI_XMMC_RCMD1_CMD_SHIFT (0U) 4078 #define FSPI_XMMC_RCMD1_CMD_MASK (0xFFU << FSPI_XMMC_RCMD1_CMD_SHIFT) 4079 #define FSPI_XMMC_RCMD1_DUMM_SHIFT (8U) 4080 #define FSPI_XMMC_RCMD1_DUMM_MASK (0xFU << FSPI_XMMC_RCMD1_DUMM_SHIFT) 4081 #define FSPI_XMMC_RCMD1_CONT_SHIFT (13U) 4082 #define FSPI_XMMC_RCMD1_CONT_MASK (0x1U << FSPI_XMMC_RCMD1_CONT_SHIFT) 4083 #define FSPI_XMMC_RCMD1_ADDRB_SHIFT (14U) 4084 #define FSPI_XMMC_RCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD1_ADDRB_SHIFT) 4085 /* DEVSIZE1 */ 4086 #define FSPI_DEVSIZE1_OFFSET (0x264U) 4087 #define FSPI_DEVSIZE1_DSIZE_SHIFT (0U) 4088 #define FSPI_DEVSIZE1_DSIZE_MASK (0x1FU << FSPI_DEVSIZE1_DSIZE_SHIFT) 4089 /* TME1 */ 4090 #define FSPI_TME1_OFFSET (0x268U) 4091 #define FSPI_TME1_AUTO_RF_EN_SHIFT (0U) 4092 #define FSPI_TME1_AUTO_RF_EN_MASK (0x1U << FSPI_TME1_AUTO_RF_EN_SHIFT) 4093 #define FSPI_TME1_SCLK_INATM_EN_SHIFT (1U) 4094 #define FSPI_TME1_SCLK_INATM_EN_MASK (0x1U << FSPI_TME1_SCLK_INATM_EN_SHIFT) 4095 /*****************************************ICACHE*****************************************/ 4096 /* CACHE_CTRL */ 4097 #define ICACHE_CACHE_CTRL_OFFSET (0x0U) 4098 #define ICACHE_CACHE_CTRL_CACHE_EN_SHIFT (0U) 4099 #define ICACHE_CACHE_CTRL_CACHE_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_EN_SHIFT) 4100 #define ICACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT (1U) 4101 #define ICACHE_CACHE_CTRL_CACHE_WT_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT) 4102 #define ICACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT (2U) 4103 #define ICACHE_CACHE_CTRL_CACHE_HB_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT) 4104 #define ICACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT (3U) 4105 #define ICACHE_CACHE_CTRL_CACHE_STB_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT) 4106 #define ICACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT (4U) 4107 #define ICACHE_CACHE_CTRL_CACHE_FLUSH_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT) 4108 #define ICACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT (5U) 4109 #define ICACHE_CACHE_CTRL_CACHE_PMU_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT) 4110 #define ICACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT (6U) 4111 #define ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT) 4112 #define ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT (7U) 4113 #define ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK (0x1U << ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT) 4114 #define ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT (8U) 4115 #define ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_MASK (0x7U << ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) 4116 #define ICACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT (12U) 4117 #define ICACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT) 4118 #define ICACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT (13U) 4119 #define ICACHE_CACHE_CTRL_CACHE_PF_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT) 4120 /* CACHE_MAINTAIN0 */ 4121 #define ICACHE_CACHE_MAINTAIN0_OFFSET (0x4U) 4122 #define ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT (0U) 4123 #define ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK (0x1U << ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT) 4124 #define ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT (1U) 4125 #define ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_MASK (0x3U << ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT) 4126 #define ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT (5U) 4127 #define ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK (0x7FFFFFFU << ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT) 4128 /* CACHE_MAINTAIN1 */ 4129 #define ICACHE_CACHE_MAINTAIN1_OFFSET (0x8U) 4130 #define ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT (0U) 4131 #define ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_MASK (0xFFFFU << ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT) 4132 /* STB_TIMEOUT_CTRL */ 4133 #define ICACHE_STB_TIMEOUT_CTRL_OFFSET (0xCU) 4134 #define ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT (0U) 4135 #define ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_MASK \ 4136 (0x7FFFFU << ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT) 4137 /* CACHE_INT_EN */ 4138 #define ICACHE_CACHE_INT_EN_OFFSET (0x20U) 4139 #define ICACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT (0U) 4140 #define ICACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK (0x1U << ICACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT) 4141 /* CACHE_INT_ST */ 4142 #define ICACHE_CACHE_INT_ST_OFFSET (0x24U) 4143 #define ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT (0U) 4144 #define ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK (0x1U << ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT) 4145 /* CACHE_ERR_HADDR */ 4146 #define ICACHE_CACHE_ERR_HADDR_OFFSET (0x28U) 4147 #define ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT (0U) 4148 #define ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_MASK (0x1U << ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT) 4149 /* CACHE_STATUS */ 4150 #define ICACHE_CACHE_STATUS_OFFSET (0x30U) 4151 #define ICACHE_CACHE_STATUS (0x0U) 4152 #define ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT (0U) 4153 #define ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT) 4154 #define ICACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT (1U) 4155 #define ICACHE_CACHE_STATUS_CACHE_M_BUSY_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT) 4156 #define ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT (2U) 4157 #define ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT) 4158 /* PMU_RD_NUM_CNT */ 4159 #define ICACHE_PMU_RD_NUM_CNT_OFFSET (0x40U) 4160 #define ICACHE_PMU_RD_NUM_CNT (0x0U) 4161 #define ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT (0U) 4162 #define ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT) 4163 /* PMU_WR_NUM_CNT */ 4164 #define ICACHE_PMU_WR_NUM_CNT_OFFSET (0x44U) 4165 #define ICACHE_PMU_WR_NUM_CNT (0x0U) 4166 #define ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT (0U) 4167 #define ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT) 4168 /* PMU_SRAM_RD_HIT_CNT */ 4169 #define ICACHE_PMU_SRAM_RD_HIT_CNT_OFFSET (0x48U) 4170 #define ICACHE_PMU_SRAM_RD_HIT_CNT (0x0U) 4171 #define ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT (0U) 4172 #define ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_MASK \ 4173 (0xFFFFFFFFU << ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT) 4174 /* PMU_HB_RD_HIT_CNT */ 4175 #define ICACHE_PMU_HB_RD_HIT_CNT_OFFSET (0x4CU) 4176 #define ICACHE_PMU_HB_RD_HIT_CNT (0x0U) 4177 #define ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT (0U) 4178 #define ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_MASK \ 4179 (0xFFFFFFFFU << ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT) 4180 /* PMU_STB_RD_HIT_CNT */ 4181 #define ICACHE_PMU_STB_RD_HIT_CNT_OFFSET (0x50U) 4182 #define ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT (0U) 4183 #define ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_MASK \ 4184 (0xFFFFFFFFU << ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT) 4185 /* PMU_RD_HIT_CNT */ 4186 #define ICACHE_PMU_RD_HIT_CNT_OFFSET (0x54U) 4187 #define ICACHE_PMU_RD_HIT_CNT (0x0U) 4188 #define ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT (0U) 4189 #define ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT) 4190 /* PMU_WR_HIT_CNT */ 4191 #define ICACHE_PMU_WR_HIT_CNT_OFFSET (0x58U) 4192 #define ICACHE_PMU_WR_HIT_CNT (0x0U) 4193 #define ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT (0U) 4194 #define ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT) 4195 /* PMU_RD_MISS_PENALTY_CNT */ 4196 #define ICACHE_PMU_RD_MISS_PENALTY_CNT_OFFSET (0x5CU) 4197 #define ICACHE_PMU_RD_MISS_PENALTY_CNT (0x0U) 4198 #define ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT (0U) 4199 #define ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_MASK \ 4200 (0xFFFFFFFFU << ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT) 4201 /* PMU_WR_MISS_PENALTY_CNT */ 4202 #define ICACHE_PMU_WR_MISS_PENALTY_CNT_OFFSET (0x60U) 4203 #define ICACHE_PMU_WR_MISS_PENALTY_CNT (0x0U) 4204 #define ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT (0U) 4205 #define ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_MASK \ 4206 (0xFFFFFFFFU << ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT) 4207 /* PMU_RD_LAT_CNT */ 4208 #define ICACHE_PMU_RD_LAT_CNT_OFFSET (0x64U) 4209 #define ICACHE_PMU_RD_LAT_CNT (0x0U) 4210 #define ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) 4211 #define ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) 4212 /* PMU_WR_LAT_CNT */ 4213 #define ICACHE_PMU_WR_LAT_CNT_OFFSET (0x68U) 4214 #define ICACHE_PMU_WR_LAT_CNT (0x0U) 4215 #define ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) 4216 #define ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) 4217 /* REVISION */ 4218 #define ICACHE_REVISION_OFFSET (0xF0U) 4219 #define ICACHE_REVISION (0x100U) 4220 #define ICACHE_REVISION_REVISION_SHIFT (0U) 4221 #define ICACHE_REVISION_REVISION_MASK (0xFFFFFFFFU << ICACHE_REVISION_REVISION_SHIFT) 4222 /*****************************************DCACHE*****************************************/ 4223 /* CACHE_CTRL */ 4224 #define DCACHE_CACHE_CTRL_OFFSET (0x0U) 4225 #define DCACHE_CACHE_CTRL_CACHE_EN_SHIFT (0U) 4226 #define DCACHE_CACHE_CTRL_CACHE_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_EN_SHIFT) 4227 #define DCACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT (1U) 4228 #define DCACHE_CACHE_CTRL_CACHE_WT_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT) 4229 #define DCACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT (2U) 4230 #define DCACHE_CACHE_CTRL_CACHE_HB_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT) 4231 #define DCACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT (3U) 4232 #define DCACHE_CACHE_CTRL_CACHE_STB_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT) 4233 #define DCACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT (4U) 4234 #define DCACHE_CACHE_CTRL_CACHE_FLUSH_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT) 4235 #define DCACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT (5U) 4236 #define DCACHE_CACHE_CTRL_CACHE_PMU_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT) 4237 #define DCACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT (6U) 4238 #define DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT) 4239 #define DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT (7U) 4240 #define DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK (0x1U << DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT) 4241 #define DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT (8U) 4242 #define DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_MASK (0x7U << DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) 4243 #define DCACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT (12U) 4244 #define DCACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT) 4245 #define DCACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT (13U) 4246 #define DCACHE_CACHE_CTRL_CACHE_PF_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT) 4247 /* CACHE_MAINTAIN0 */ 4248 #define DCACHE_CACHE_MAINTAIN0_OFFSET (0x4U) 4249 #define DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT (0U) 4250 #define DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK (0x1U << DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT) 4251 #define DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT (1U) 4252 #define DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_MASK (0x3U << DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT) 4253 #define DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT (5U) 4254 #define DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK (0x7FFFFFFU << DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT) 4255 /* CACHE_MAINTAIN1 */ 4256 #define DCACHE_CACHE_MAINTAIN1_OFFSET (0x8U) 4257 #define DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT (0U) 4258 #define DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_MASK (0xFFFFU << DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT) 4259 /* STB_TIMEOUT_CTRL */ 4260 #define DCACHE_STB_TIMEOUT_CTRL_OFFSET (0xCU) 4261 #define DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT (0U) 4262 #define DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_MASK \ 4263 (0x7FFFFU << DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT) 4264 /* CACHE_INT_EN */ 4265 #define DCACHE_CACHE_INT_EN_OFFSET (0x20U) 4266 #define DCACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT (0U) 4267 #define DCACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK (0x1U << DCACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT) 4268 /* CACHE_INT_ST */ 4269 #define DCACHE_CACHE_INT_ST_OFFSET (0x24U) 4270 #define DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT (0U) 4271 #define DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK (0x1U << DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT) 4272 /* CACHE_ERR_HADDR */ 4273 #define DCACHE_CACHE_ERR_HADDR_OFFSET (0x28U) 4274 #define DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT (0U) 4275 #define DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_MASK (0x1U << DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT) 4276 /* CACHE_STATUS */ 4277 #define DCACHE_CACHE_STATUS_OFFSET (0x30U) 4278 #define DCACHE_CACHE_STATUS (0x0U) 4279 #define DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT (0U) 4280 #define DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT) 4281 #define DCACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT (1U) 4282 #define DCACHE_CACHE_STATUS_CACHE_M_BUSY_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT) 4283 #define DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT (2U) 4284 #define DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT) 4285 /* PMU_RD_NUM_CNT */ 4286 #define DCACHE_PMU_RD_NUM_CNT_OFFSET (0x40U) 4287 #define DCACHE_PMU_RD_NUM_CNT (0x0U) 4288 #define DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT (0U) 4289 #define DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT) 4290 /* PMU_WR_NUM_CNT */ 4291 #define DCACHE_PMU_WR_NUM_CNT_OFFSET (0x44U) 4292 #define DCACHE_PMU_WR_NUM_CNT (0x0U) 4293 #define DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT (0U) 4294 #define DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT) 4295 /* PMU_SRAM_RD_HIT_CNT */ 4296 #define DCACHE_PMU_SRAM_RD_HIT_CNT_OFFSET (0x48U) 4297 #define DCACHE_PMU_SRAM_RD_HIT_CNT (0x0U) 4298 #define DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT (0U) 4299 #define DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_MASK \ 4300 (0xFFFFFFFFU << DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT) 4301 /* PMU_HB_RD_HIT_CNT */ 4302 #define DCACHE_PMU_HB_RD_HIT_CNT_OFFSET (0x4CU) 4303 #define DCACHE_PMU_HB_RD_HIT_CNT (0x0U) 4304 #define DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT (0U) 4305 #define DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_MASK \ 4306 (0xFFFFFFFFU << DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT) 4307 /* PMU_STB_RD_HIT_CNT */ 4308 #define DCACHE_PMU_STB_RD_HIT_CNT_OFFSET (0x50U) 4309 #define DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT (0U) 4310 #define DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_MASK \ 4311 (0xFFFFFFFFU << DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT) 4312 /* PMU_RD_HIT_CNT */ 4313 #define DCACHE_PMU_RD_HIT_CNT_OFFSET (0x54U) 4314 #define DCACHE_PMU_RD_HIT_CNT (0x0U) 4315 #define DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT (0U) 4316 #define DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT) 4317 /* PMU_WR_HIT_CNT */ 4318 #define DCACHE_PMU_WR_HIT_CNT_OFFSET (0x58U) 4319 #define DCACHE_PMU_WR_HIT_CNT (0x0U) 4320 #define DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT (0U) 4321 #define DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT) 4322 /* PMU_RD_MISS_PENALTY_CNT */ 4323 #define DCACHE_PMU_RD_MISS_PENALTY_CNT_OFFSET (0x5CU) 4324 #define DCACHE_PMU_RD_MISS_PENALTY_CNT (0x0U) 4325 #define DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT (0U) 4326 #define DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_MASK \ 4327 (0xFFFFFFFFU << DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT) 4328 /* PMU_WR_MISS_PENALTY_CNT */ 4329 #define DCACHE_PMU_WR_MISS_PENALTY_CNT_OFFSET (0x60U) 4330 #define DCACHE_PMU_WR_MISS_PENALTY_CNT (0x0U) 4331 #define DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT (0U) 4332 #define DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_MASK \ 4333 (0xFFFFFFFFU << DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT) 4334 /* PMU_RD_LAT_CNT */ 4335 #define DCACHE_PMU_RD_LAT_CNT_OFFSET (0x64U) 4336 #define DCACHE_PMU_RD_LAT_CNT (0x0U) 4337 #define DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) 4338 #define DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) 4339 /* PMU_WR_LAT_CNT */ 4340 #define DCACHE_PMU_WR_LAT_CNT_OFFSET (0x68U) 4341 #define DCACHE_PMU_WR_LAT_CNT (0x0U) 4342 #define DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) 4343 #define DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) 4344 /* REVISION */ 4345 #define DCACHE_REVISION_OFFSET (0xF0U) 4346 #define DCACHE_REVISION (0x100U) 4347 #define DCACHE_REVISION_REVISION_SHIFT (0U) 4348 #define DCACHE_REVISION_REVISION_MASK (0xFFFFFFFFU << DCACHE_REVISION_REVISION_SHIFT) 4349 /******************************************VOP*******************************************/ 4350 /* CON */ 4351 #define VOP_CON_OFFSET (0x0U) 4352 #define VOP_CON_SW_MCU_IDLE_DIR_SHIFT (0U) 4353 #define VOP_CON_SW_MCU_IDLE_DIR_MASK (0x1U << VOP_CON_SW_MCU_IDLE_DIR_SHIFT) 4354 #define VOP_CON_SW_MCU_WR_PHASE_SHIFT (1U) 4355 #define VOP_CON_SW_MCU_WR_PHASE_MASK (0x3U << VOP_CON_SW_MCU_WR_PHASE_SHIFT) 4356 #define VOP_CON_SW_MCU_BITS_SHIFT (3U) 4357 #define VOP_CON_SW_MCU_BITS_MASK (0x1U << VOP_CON_SW_MCU_BITS_SHIFT) 4358 #define VOP_CON_SW_MCU_HW_SWAP_SHIFT (4U) 4359 #define VOP_CON_SW_MCU_HW_SWAP_MASK (0x1U << VOP_CON_SW_MCU_HW_SWAP_SHIFT) 4360 #define VOP_CON_SW_MCU_BYTE_SWAP_SHIFT (5U) 4361 #define VOP_CON_SW_MCU_BYTE_SWAP_MASK (0x1U << VOP_CON_SW_MCU_BYTE_SWAP_SHIFT) 4362 #define VOP_CON_SW_MCU_Y2R_MODE_SHIFT (6U) 4363 #define VOP_CON_SW_MCU_Y2R_MODE_MASK (0x3U << VOP_CON_SW_MCU_Y2R_MODE_SHIFT) 4364 #define VOP_CON_SW_MCU_INPUT_FORMAT_SHIFT (8U) 4365 #define VOP_CON_SW_MCU_INPUT_FORMAT_MASK (0x1U << VOP_CON_SW_MCU_INPUT_FORMAT_SHIFT) 4366 #define VOP_CON_SW_MCU_UV_SWAP_SHIFT (9U) 4367 #define VOP_CON_SW_MCU_UV_SWAP_MASK (0x1U << VOP_CON_SW_MCU_UV_SWAP_SHIFT) 4368 #define VOP_CON_SW_DITHER_DOWN_EN_SHIFT (10U) 4369 #define VOP_CON_SW_DITHER_DOWN_EN_MASK (0x1U << VOP_CON_SW_DITHER_DOWN_EN_SHIFT) 4370 #define VOP_CON_SW_WDATA_BYPASS_EN_SHIFT (11U) 4371 #define VOP_CON_SW_WDATA_BYPASS_EN_MASK (0x1U << VOP_CON_SW_WDATA_BYPASS_EN_SHIFT) 4372 #define VOP_CON_SW_AUTO_CKG_SHIFT (12U) 4373 #define VOP_CON_SW_AUTO_CKG_MASK (0x1U << VOP_CON_SW_AUTO_CKG_SHIFT) 4374 #define VOP_CON_SW_MCU_BURST_SHIFT (13U) 4375 #define VOP_CON_SW_MCU_BURST_MASK (0x7U << VOP_CON_SW_MCU_BURST_SHIFT) 4376 /* VERSION */ 4377 #define VOP_VERSION_OFFSET (0x4U) 4378 #define VOP_VERSION (0x0U) 4379 #define VOP_VERSION_SW_MCU_VERSION_SHIFT (0U) 4380 #define VOP_VERSION_SW_MCU_VERSION_MASK (0xFFFFFFFFU << VOP_VERSION_SW_MCU_VERSION_SHIFT) 4381 /* TIMING */ 4382 #define VOP_TIMING_OFFSET (0x8U) 4383 #define VOP_TIMING_SW_MCU_RWCS_SHIFT (0U) 4384 #define VOP_TIMING_SW_MCU_RWCS_MASK (0x1FU << VOP_TIMING_SW_MCU_RWCS_SHIFT) 4385 #define VOP_TIMING_SW_MCU_RWPW_SHIFT (5U) 4386 #define VOP_TIMING_SW_MCU_RWPW_MASK (0x3FU << VOP_TIMING_SW_MCU_RWPW_SHIFT) 4387 #define VOP_TIMING_SW_MCU_CSRW_SHIFT (12U) 4388 #define VOP_TIMING_SW_MCU_CSRW_MASK (0xFU << VOP_TIMING_SW_MCU_CSRW_SHIFT) 4389 /* LCD_SIZE */ 4390 #define VOP_LCD_SIZE_OFFSET (0xCU) 4391 #define VOP_LCD_SIZE_SW_MCU_LCD_WIDTH_SHIFT (0U) 4392 #define VOP_LCD_SIZE_SW_MCU_LCD_WIDTH_MASK (0x1FFU << VOP_LCD_SIZE_SW_MCU_LCD_WIDTH_SHIFT) 4393 #define VOP_LCD_SIZE_SW_MCU_LCD_HEIGHT_SHIFT (12U) 4394 #define VOP_LCD_SIZE_SW_MCU_LCD_HEIGHT_MASK (0x1FFU << VOP_LCD_SIZE_SW_MCU_LCD_HEIGHT_SHIFT) 4395 /* FIFO_WATERMARK */ 4396 #define VOP_FIFO_WATERMARK_OFFSET (0x10U) 4397 #define VOP_FIFO_WATERMARK_SW_ALMOST_FULL_WATERMARK_SHIFT (0U) 4398 #define VOP_FIFO_WATERMARK_SW_ALMOST_FULL_WATERMARK_MASK \ 4399 (0x1FU << VOP_FIFO_WATERMARK_SW_ALMOST_FULL_WATERMARK_SHIFT) 4400 #define VOP_FIFO_WATERMARK_SW_ALMOST_EMPTY_WATERMARK_SHIFT (8U) 4401 #define VOP_FIFO_WATERMARK_SW_ALMOST_EMPTY_WATERMARK_MASK \ 4402 (0x1FU << VOP_FIFO_WATERMARK_SW_ALMOST_EMPTY_WATERMARK_SHIFT) 4403 /* SRT */ 4404 #define VOP_SRT_OFFSET (0x14U) 4405 #define VOP_SRT_SW_SOFT_RESET_SHIFT (0U) 4406 #define VOP_SRT_SW_SOFT_RESET_MASK (0x1U << VOP_SRT_SW_SOFT_RESET_SHIFT) 4407 /* INT_EN */ 4408 #define VOP_INT_EN_OFFSET (0x18U) 4409 #define VOP_INT_EN_SW_INT_EN_FRAME_DONE_SHIFT (0U) 4410 #define VOP_INT_EN_SW_INT_EN_FRAME_DONE_MASK (0x1U << VOP_INT_EN_SW_INT_EN_FRAME_DONE_SHIFT) 4411 #define VOP_INT_EN_SW_INT_EN_FIFO_EMPTY_SHIFT (1U) 4412 #define VOP_INT_EN_SW_INT_EN_FIFO_EMPTY_MASK (0x1U << VOP_INT_EN_SW_INT_EN_FIFO_EMPTY_SHIFT) 4413 #define VOP_INT_EN_SW_INT_EN_FIFO_FULL_SHIFT (2U) 4414 #define VOP_INT_EN_SW_INT_EN_FIFO_FULL_MASK (0x1U << VOP_INT_EN_SW_INT_EN_FIFO_FULL_SHIFT) 4415 /* INT_CLEAR */ 4416 #define VOP_INT_CLEAR_OFFSET (0x1CU) 4417 #define VOP_INT_CLEAR_SW_INT_CLEAR_FRAME_DONE_SHIFT (0U) 4418 #define VOP_INT_CLEAR_SW_INT_CLEAR_FRAME_DONE_MASK (0x1U << VOP_INT_CLEAR_SW_INT_CLEAR_FRAME_DONE_SHIFT) 4419 #define VOP_INT_CLEAR_SW_INT_CLEAR_FIFO_EMPTY_SHIFT (1U) 4420 #define VOP_INT_CLEAR_SW_INT_CLEAR_FIFO_EMPTY_MASK (0x1U << VOP_INT_CLEAR_SW_INT_CLEAR_FIFO_EMPTY_SHIFT) 4421 #define VOP_INT_CLEAR_SW_INT_CLEAR_FIFO_FULL_SHIFT (2U) 4422 #define VOP_INT_CLEAR_SW_INT_CLEAR_FIFO_FULL_MASK (0x1U << VOP_INT_CLEAR_SW_INT_CLEAR_FIFO_FULL_SHIFT) 4423 /* INT_STATUS */ 4424 #define VOP_INT_STATUS_OFFSET (0x20U) 4425 #define VOP_INT_STATUS_SW_INT_FRAME_DONE_SHIFT (0U) 4426 #define VOP_INT_STATUS_SW_INT_FRAME_DONE_MASK (0x1U << VOP_INT_STATUS_SW_INT_FRAME_DONE_SHIFT) 4427 #define VOP_INT_STATUS_SW_INT_FIFO_EMPTY_SHIFT (1U) 4428 #define VOP_INT_STATUS_SW_INT_FIFO_EMPTY_MASK (0x1U << VOP_INT_STATUS_SW_INT_FIFO_EMPTY_SHIFT) 4429 #define VOP_INT_STATUS_SW_INT_FIFO_FULL_SHIFT (2U) 4430 #define VOP_INT_STATUS_SW_INT_FIFO_FULL_MASK (0x1U << VOP_INT_STATUS_SW_INT_FIFO_FULL_SHIFT) 4431 #define VOP_INT_STATUS_SW_INT_RAW_FRAME_DONE_SHIFT (3U) 4432 #define VOP_INT_STATUS_SW_INT_RAW_FRAME_DONE_MASK (0x1U << VOP_INT_STATUS_SW_INT_RAW_FRAME_DONE_SHIFT) 4433 #define VOP_INT_STATUS_SW_INT_RAW_FIFO_EMPTY_SHIFT (4U) 4434 #define VOP_INT_STATUS_SW_INT_RAW_FIFO_EMPTY_MASK (0x1U << VOP_INT_STATUS_SW_INT_RAW_FIFO_EMPTY_SHIFT) 4435 #define VOP_INT_STATUS_SW_INT_RAW_FIFO_FULL_SHIFT (5U) 4436 #define VOP_INT_STATUS_SW_INT_RAW_FIFO_FULL_MASK (0x1U << VOP_INT_STATUS_SW_INT_RAW_FIFO_FULL_SHIFT) 4437 /* STATUS */ 4438 #define VOP_STATUS_OFFSET (0x24U) 4439 #define VOP_STATUS_SW_MCU_WORKING_SHIFT (0U) 4440 #define VOP_STATUS_SW_MCU_WORKING_MASK (0x1U << VOP_STATUS_SW_MCU_WORKING_SHIFT) 4441 #define VOP_STATUS_SW_MCU_CURRENT_ROW_SHIFT (4U) 4442 #define VOP_STATUS_SW_MCU_CURRENT_ROW_MASK (0x1FFU << VOP_STATUS_SW_MCU_CURRENT_ROW_SHIFT) 4443 #define VOP_STATUS_SW_MCU_CURRENT_LINE_SHIFT (16U) 4444 #define VOP_STATUS_SW_MCU_CURRENT_LINE_MASK (0x1FFU << VOP_STATUS_SW_MCU_CURRENT_LINE_SHIFT) 4445 /* CMD */ 4446 #define VOP_CMD_OFFSET (0x28U) 4447 #define VOP_CMD_MCU_CMD_LOW_BITS_SHIFT (0U) 4448 #define VOP_CMD_MCU_CMD_LOW_BITS_MASK (0xFFU << VOP_CMD_MCU_CMD_LOW_BITS_SHIFT) 4449 #define VOP_CMD_MCU_CMD_HIGH_BITS_SHIFT (8U) 4450 #define VOP_CMD_MCU_CMD_HIGH_BITS_MASK (0xFFFFFFU << VOP_CMD_MCU_CMD_HIGH_BITS_SHIFT) 4451 /* DATA */ 4452 #define VOP_DATA_OFFSET (0x2CU) 4453 #define VOP_DATA_MCU_DATA_LOW_BITS_SHIFT (0U) 4454 #define VOP_DATA_MCU_DATA_LOW_BITS_MASK (0xFFU << VOP_DATA_MCU_DATA_LOW_BITS_SHIFT) 4455 #define VOP_DATA_MCU_DATA_HIGH_BITS_SHIFT (8U) 4456 #define VOP_DATA_MCU_DATA_HIGH_BITS_MASK (0xFFFFFFU << VOP_DATA_MCU_DATA_HIGH_BITS_SHIFT) 4457 /* START */ 4458 #define VOP_START_OFFSET (0x30U) 4459 #define VOP_START_SW_MCU_START_SHIFT (0U) 4460 #define VOP_START_SW_MCU_START_MASK (0x1U << VOP_START_SW_MCU_START_SHIFT) 4461 /****************************************AUDIOPWM****************************************/ 4462 /* VERSION */ 4463 #define AUDIOPWM_VERSION_OFFSET (0x0U) 4464 #define AUDIOPWM_VERSION (0x1000000U) 4465 #define AUDIOPWM_VERSION_VERSION_SHIFT (0U) 4466 #define AUDIOPWM_VERSION_VERSION_MASK (0xFFFFFFFFU << AUDIOPWM_VERSION_VERSION_SHIFT) 4467 /* XFER */ 4468 #define AUDIOPWM_XFER_OFFSET (0x4U) 4469 #define AUDIOPWM_XFER_START_SHIFT (0U) 4470 #define AUDIOPWM_XFER_START_MASK (0x1U << AUDIOPWM_XFER_START_SHIFT) 4471 #define AUDIOPWM_XFER_LSTOP_SHIFT (1U) 4472 #define AUDIOPWM_XFER_LSTOP_MASK (0x1U << AUDIOPWM_XFER_LSTOP_SHIFT) 4473 /* SRC_CFG */ 4474 #define AUDIOPWM_SRC_CFG_OFFSET (0x8U) 4475 #define AUDIOPWM_SRC_CFG_WIDTH_SHIFT (0U) 4476 #define AUDIOPWM_SRC_CFG_WIDTH_MASK (0x1FU << AUDIOPWM_SRC_CFG_WIDTH_SHIFT) 4477 #define AUDIOPWM_SRC_CFG_ALIGN_SHIFT (5U) 4478 #define AUDIOPWM_SRC_CFG_ALIGN_MASK (0x1U << AUDIOPWM_SRC_CFG_ALIGN_SHIFT) 4479 #define AUDIOPWM_SRC_CFG_HALF_EN_SHIFT (6U) 4480 #define AUDIOPWM_SRC_CFG_HALF_EN_MASK (0x1U << AUDIOPWM_SRC_CFG_HALF_EN_SHIFT) 4481 /* PWM_CFG */ 4482 #define AUDIOPWM_PWM_CFG_OFFSET (0x10U) 4483 #define AUDIOPWM_PWM_CFG_INTERP_RATE_SHIFT (0U) 4484 #define AUDIOPWM_PWM_CFG_INTERP_RATE_MASK (0xFU << AUDIOPWM_PWM_CFG_INTERP_RATE_SHIFT) 4485 #define AUDIOPWM_PWM_CFG_LINEAR_INTERP_EN_SHIFT (4U) 4486 #define AUDIOPWM_PWM_CFG_LINEAR_INTERP_EN_MASK (0x1U << AUDIOPWM_PWM_CFG_LINEAR_INTERP_EN_SHIFT) 4487 #define AUDIOPWM_PWM_CFG_OUT_SWAP_SHIFT (5U) 4488 #define AUDIOPWM_PWM_CFG_OUT_SWAP_MASK (0x1U << AUDIOPWM_PWM_CFG_OUT_SWAP_SHIFT) 4489 #define AUDIOPWM_PWM_CFG_LEFT_DIS_SHIFT (6U) 4490 #define AUDIOPWM_PWM_CFG_LEFT_DIS_MASK (0x1U << AUDIOPWM_PWM_CFG_LEFT_DIS_SHIFT) 4491 #define AUDIOPWM_PWM_CFG_RIGHT_DIS_SHIFT (7U) 4492 #define AUDIOPWM_PWM_CFG_RIGHT_DIS_MASK (0x1U << AUDIOPWM_PWM_CFG_RIGHT_DIS_SHIFT) 4493 #define AUDIOPWM_PWM_CFG_SAMPLE_WIDTH_SHIFT (8U) 4494 #define AUDIOPWM_PWM_CFG_SAMPLE_WIDTH_MASK (0x3U << AUDIOPWM_PWM_CFG_SAMPLE_WIDTH_SHIFT) 4495 /* PWM_ST */ 4496 #define AUDIOPWM_PWM_ST_OFFSET (0x14U) 4497 #define AUDIOPWM_PWM_ST (0x0U) 4498 #define AUDIOPWM_PWM_ST_FIFO_BUSY_SHIFT (0U) 4499 #define AUDIOPWM_PWM_ST_FIFO_BUSY_MASK (0x1U << AUDIOPWM_PWM_ST_FIFO_BUSY_SHIFT) 4500 #define AUDIOPWM_PWM_ST_PWM_BUSY_SHIFT (1U) 4501 #define AUDIOPWM_PWM_ST_PWM_BUSY_MASK (0x1U << AUDIOPWM_PWM_ST_PWM_BUSY_SHIFT) 4502 /* PWM_BUF_01 */ 4503 #define AUDIOPWM_PWM_BUF_01_OFFSET (0x18U) 4504 #define AUDIOPWM_PWM_BUF_01 (0x0U) 4505 #define AUDIOPWM_PWM_BUF_01_PWM_BUF_0_SHIFT (0U) 4506 #define AUDIOPWM_PWM_BUF_01_PWM_BUF_0_MASK (0x7FFU << AUDIOPWM_PWM_BUF_01_PWM_BUF_0_SHIFT) 4507 #define AUDIOPWM_PWM_BUF_01_PWM_BUF_1_SHIFT (16U) 4508 #define AUDIOPWM_PWM_BUF_01_PWM_BUF_1_MASK (0x7FFU << AUDIOPWM_PWM_BUF_01_PWM_BUF_1_SHIFT) 4509 /* PWM_BUF_23 */ 4510 #define AUDIOPWM_PWM_BUF_23_OFFSET (0x1CU) 4511 #define AUDIOPWM_PWM_BUF_23 (0x0U) 4512 #define AUDIOPWM_PWM_BUF_23_PWM_BUF_2_SHIFT (0U) 4513 #define AUDIOPWM_PWM_BUF_23_PWM_BUF_2_MASK (0x7FFU << AUDIOPWM_PWM_BUF_23_PWM_BUF_2_SHIFT) 4514 #define AUDIOPWM_PWM_BUF_23_PWM_BUF_3_SHIFT (16U) 4515 #define AUDIOPWM_PWM_BUF_23_PWM_BUF_3_MASK (0x7FFU << AUDIOPWM_PWM_BUF_23_PWM_BUF_3_SHIFT) 4516 /* FIFO_CFG */ 4517 #define AUDIOPWM_FIFO_CFG_OFFSET (0x20U) 4518 #define AUDIOPWM_FIFO_CFG_DMA_WATERMARK_SHIFT (0U) 4519 #define AUDIOPWM_FIFO_CFG_DMA_WATERMARK_MASK (0x1FU << AUDIOPWM_FIFO_CFG_DMA_WATERMARK_SHIFT) 4520 #define AUDIOPWM_FIFO_CFG_DMA_EN_SHIFT (7U) 4521 #define AUDIOPWM_FIFO_CFG_DMA_EN_MASK (0x1U << AUDIOPWM_FIFO_CFG_DMA_EN_SHIFT) 4522 #define AUDIOPWM_FIFO_CFG_ALMOST_FULL_WATERMARK_SHIFT (8U) 4523 #define AUDIOPWM_FIFO_CFG_ALMOST_FULL_WATERMARK_MASK (0x1FU << AUDIOPWM_FIFO_CFG_ALMOST_FULL_WATERMARK_SHIFT) 4524 /* FIFO_LVL */ 4525 #define AUDIOPWM_FIFO_LVL_OFFSET (0x24U) 4526 #define AUDIOPWM_FIFO_LVL (0x0U) 4527 #define AUDIOPWM_FIFO_LVL_FIFO_SPACE2FULL_SHIFT (0U) 4528 #define AUDIOPWM_FIFO_LVL_FIFO_SPACE2FULL_MASK (0x3FU << AUDIOPWM_FIFO_LVL_FIFO_SPACE2FULL_SHIFT) 4529 /* FIFO_INT_EN */ 4530 #define AUDIOPWM_FIFO_INT_EN_OFFSET (0x28U) 4531 #define AUDIOPWM_FIFO_INT_EN_FULL_INT_EN_SHIFT (0U) 4532 #define AUDIOPWM_FIFO_INT_EN_FULL_INT_EN_MASK (0x1U << AUDIOPWM_FIFO_INT_EN_FULL_INT_EN_SHIFT) 4533 #define AUDIOPWM_FIFO_INT_EN_OVERRUN_INT_EN_SHIFT (1U) 4534 #define AUDIOPWM_FIFO_INT_EN_OVERRUN_INT_EN_MASK (0x1U << AUDIOPWM_FIFO_INT_EN_OVERRUN_INT_EN_SHIFT) 4535 #define AUDIOPWM_FIFO_INT_EN_EMPTY_INT_EN_SHIFT (2U) 4536 #define AUDIOPWM_FIFO_INT_EN_EMPTY_INT_EN_MASK (0x1U << AUDIOPWM_FIFO_INT_EN_EMPTY_INT_EN_SHIFT) 4537 /* FIFO_INT_ST */ 4538 #define AUDIOPWM_FIFO_INT_ST_OFFSET (0x2CU) 4539 #define AUDIOPWM_FIFO_INT_ST_FULL_INT_ST_SHIFT (0U) 4540 #define AUDIOPWM_FIFO_INT_ST_FULL_INT_ST_MASK (0x1U << AUDIOPWM_FIFO_INT_ST_FULL_INT_ST_SHIFT) 4541 #define AUDIOPWM_FIFO_INT_ST_OVERRUN_INT_ST_SHIFT (1U) 4542 #define AUDIOPWM_FIFO_INT_ST_OVERRUN_INT_ST_MASK (0x1U << AUDIOPWM_FIFO_INT_ST_OVERRUN_INT_ST_SHIFT) 4543 #define AUDIOPWM_FIFO_INT_ST_EMPTY_INT_ST_SHIFT (2U) 4544 #define AUDIOPWM_FIFO_INT_ST_EMPTY_INT_ST_MASK (0x1U << AUDIOPWM_FIFO_INT_ST_EMPTY_INT_ST_SHIFT) 4545 /* FIFO_ENTRY */ 4546 #define AUDIOPWM_FIFO_ENTRY_OFFSET (0x80U) 4547 #define AUDIOPWM_FIFO_ENTRY_FIFO_DATA_ENTRY_SHIFT (0U) 4548 #define AUDIOPWM_FIFO_ENTRY_FIFO_DATA_ENTRY_MASK (0xFFFFFFFFU << AUDIOPWM_FIFO_ENTRY_FIFO_DATA_ENTRY_SHIFT) 4549 /****************************************HYPERBUS****************************************/ 4550 /* CSR */ 4551 #define HYPERBUS_CSR_OFFSET (0x0U) 4552 #define HYPERBUS_CSR (0x0U) 4553 #define HYPERBUS_CSR_RACT_SHIFT (0U) 4554 #define HYPERBUS_CSR_RACT_MASK (0x1U << HYPERBUS_CSR_RACT_SHIFT) 4555 #define HYPERBUS_CSR_RDECERR_SHIFT (8U) 4556 #define HYPERBUS_CSR_RDECERR_MASK (0x1U << HYPERBUS_CSR_RDECERR_SHIFT) 4557 #define HYPERBUS_CSR_RTRSERR_SHIFT (9U) 4558 #define HYPERBUS_CSR_RTRSERR_MASK (0x1U << HYPERBUS_CSR_RTRSERR_SHIFT) 4559 #define HYPERBUS_CSR_RRSTOERR_SHIFT (10U) 4560 #define HYPERBUS_CSR_RRSTOERR_MASK (0x1U << HYPERBUS_CSR_RRSTOERR_SHIFT) 4561 #define HYPERBUS_CSR_RDSSTALL_SHIFT (11U) 4562 #define HYPERBUS_CSR_RDSSTALL_MASK (0x1U << HYPERBUS_CSR_RDSSTALL_SHIFT) 4563 #define HYPERBUS_CSR_WACT_SHIFT (16U) 4564 #define HYPERBUS_CSR_WACT_MASK (0x1U << HYPERBUS_CSR_WACT_SHIFT) 4565 #define HYPERBUS_CSR_WDECERR_SHIFT (24U) 4566 #define HYPERBUS_CSR_WDECERR_MASK (0x1U << HYPERBUS_CSR_WDECERR_SHIFT) 4567 #define HYPERBUS_CSR_WTRSERR_SHIFT (25U) 4568 #define HYPERBUS_CSR_WTRSERR_MASK (0x1U << HYPERBUS_CSR_WTRSERR_SHIFT) 4569 #define HYPERBUS_CSR_WRSTOERR_SHIFT (26U) 4570 #define HYPERBUS_CSR_WRSTOERR_MASK (0x1U << HYPERBUS_CSR_WRSTOERR_SHIFT) 4571 /* IEN */ 4572 #define HYPERBUS_IEN_OFFSET (0x4U) 4573 #define HYPERBUS_IEN_RPCINTE_SHIFT (0U) 4574 #define HYPERBUS_IEN_RPCINTE_MASK (0x1U << HYPERBUS_IEN_RPCINTE_SHIFT) 4575 #define HYPERBUS_IEN_NTP_SHIFT (31U) 4576 #define HYPERBUS_IEN_NTP_MASK (0x1U << HYPERBUS_IEN_NTP_SHIFT) 4577 /* ISR */ 4578 #define HYPERBUS_ISR_OFFSET (0x8U) 4579 #define HYPERBUS_ISR_RPCINTS_SHIFT (0U) 4580 #define HYPERBUS_ISR_RPCINTS_MASK (0x1U << HYPERBUS_ISR_RPCINTS_SHIFT) 4581 /* MBR0 */ 4582 #define HYPERBUS_MBR0_OFFSET (0x10U) 4583 #define HYPERBUS_MBR0_BADDR_SHIFT (0U) 4584 #define HYPERBUS_MBR0_BADDR_MASK (0xFFFFFFFFU << HYPERBUS_MBR0_BADDR_SHIFT) 4585 /* MBR1 */ 4586 #define HYPERBUS_MBR1_OFFSET (0x14U) 4587 #define HYPERBUS_MBR1_BADDR_SHIFT (0U) 4588 #define HYPERBUS_MBR1_BADDR_MASK (0xFFFFFFFFU << HYPERBUS_MBR1_BADDR_SHIFT) 4589 /* MCR0 */ 4590 #define HYPERBUS_MCR0_OFFSET (0x20U) 4591 #define HYPERBUS_MCR0_WRAPSIZE_SHIFT (0U) 4592 #define HYPERBUS_MCR0_WRAPSIZE_MASK (0x3U << HYPERBUS_MCR0_WRAPSIZE_SHIFT) 4593 #define HYPERBUS_MCR0_DEVTYPE_SHIFT (4U) 4594 #define HYPERBUS_MCR0_DEVTYPE_MASK (0x1U << HYPERBUS_MCR0_DEVTYPE_SHIFT) 4595 #define HYPERBUS_MCR0_CRT_SHIFT (5U) 4596 #define HYPERBUS_MCR0_CRT_MASK (0x1U << HYPERBUS_MCR0_CRT_SHIFT) 4597 #define HYPERBUS_MCR0_ACS_SHIFT (16U) 4598 #define HYPERBUS_MCR0_ACS_MASK (0x1U << HYPERBUS_MCR0_ACS_SHIFT) 4599 #define HYPERBUS_MCR0_TCMO_SHIFT (17U) 4600 #define HYPERBUS_MCR0_TCMO_MASK (0x1U << HYPERBUS_MCR0_TCMO_SHIFT) 4601 #define HYPERBUS_MCR0_MAXLEN_SHIFT (18U) 4602 #define HYPERBUS_MCR0_MAXLEN_MASK (0x1FFU << HYPERBUS_MCR0_MAXLEN_SHIFT) 4603 #define HYPERBUS_MCR0_MAXEN_SHIFT (31U) 4604 #define HYPERBUS_MCR0_MAXEN_MASK (0x1U << HYPERBUS_MCR0_MAXEN_SHIFT) 4605 /* MCR1 */ 4606 #define HYPERBUS_MCR1_OFFSET (0x24U) 4607 #define HYPERBUS_MCR1_WRAPSIZE_SHIFT (0U) 4608 #define HYPERBUS_MCR1_WRAPSIZE_MASK (0x3U << HYPERBUS_MCR1_WRAPSIZE_SHIFT) 4609 #define HYPERBUS_MCR1_DEVTYPE_SHIFT (4U) 4610 #define HYPERBUS_MCR1_DEVTYPE_MASK (0x1U << HYPERBUS_MCR1_DEVTYPE_SHIFT) 4611 #define HYPERBUS_MCR1_CRT_SHIFT (5U) 4612 #define HYPERBUS_MCR1_CRT_MASK (0x1U << HYPERBUS_MCR1_CRT_SHIFT) 4613 #define HYPERBUS_MCR1_ACS_SHIFT (16U) 4614 #define HYPERBUS_MCR1_ACS_MASK (0x1U << HYPERBUS_MCR1_ACS_SHIFT) 4615 #define HYPERBUS_MCR1_TCMO_SHIFT (17U) 4616 #define HYPERBUS_MCR1_TCMO_MASK (0x1U << HYPERBUS_MCR1_TCMO_SHIFT) 4617 #define HYPERBUS_MCR1_MAXLEN_SHIFT (18U) 4618 #define HYPERBUS_MCR1_MAXLEN_MASK (0x1FFU << HYPERBUS_MCR1_MAXLEN_SHIFT) 4619 #define HYPERBUS_MCR1_MAXEN_SHIFT (31U) 4620 #define HYPERBUS_MCR1_MAXEN_MASK (0x1U << HYPERBUS_MCR1_MAXEN_SHIFT) 4621 /* MTR0 */ 4622 #define HYPERBUS_MTR0_OFFSET (0x30U) 4623 #define HYPERBUS_MTR0_LTCY_SHIFT (0U) 4624 #define HYPERBUS_MTR0_LTCY_MASK (0xFU << HYPERBUS_MTR0_LTCY_SHIFT) 4625 #define HYPERBUS_MTR0_WCSH_SHIFT (8U) 4626 #define HYPERBUS_MTR0_WCSH_MASK (0xFU << HYPERBUS_MTR0_WCSH_SHIFT) 4627 #define HYPERBUS_MTR0_RCSH_SHIFT (12U) 4628 #define HYPERBUS_MTR0_RCSH_MASK (0xFU << HYPERBUS_MTR0_RCSH_SHIFT) 4629 #define HYPERBUS_MTR0_WCSS_SHIFT (16U) 4630 #define HYPERBUS_MTR0_WCSS_MASK (0xFU << HYPERBUS_MTR0_WCSS_SHIFT) 4631 #define HYPERBUS_MTR0_RCSS_SHIFT (20U) 4632 #define HYPERBUS_MTR0_RCSS_MASK (0xFU << HYPERBUS_MTR0_RCSS_SHIFT) 4633 #define HYPERBUS_MTR0_WCSHI_SHIFT (24U) 4634 #define HYPERBUS_MTR0_WCSHI_MASK (0xFU << HYPERBUS_MTR0_WCSHI_SHIFT) 4635 #define HYPERBUS_MTR0_RCSHI_SHIFT (28U) 4636 #define HYPERBUS_MTR0_RCSHI_MASK (0xFU << HYPERBUS_MTR0_RCSHI_SHIFT) 4637 /* MTR1 */ 4638 #define HYPERBUS_MTR1_OFFSET (0x34U) 4639 #define HYPERBUS_MTR1_LTCY_SHIFT (0U) 4640 #define HYPERBUS_MTR1_LTCY_MASK (0xFU << HYPERBUS_MTR1_LTCY_SHIFT) 4641 #define HYPERBUS_MTR1_WCSH_SHIFT (8U) 4642 #define HYPERBUS_MTR1_WCSH_MASK (0xFU << HYPERBUS_MTR1_WCSH_SHIFT) 4643 #define HYPERBUS_MTR1_RCSH_SHIFT (12U) 4644 #define HYPERBUS_MTR1_RCSH_MASK (0xFU << HYPERBUS_MTR1_RCSH_SHIFT) 4645 #define HYPERBUS_MTR1_WCSS_SHIFT (16U) 4646 #define HYPERBUS_MTR1_WCSS_MASK (0xFU << HYPERBUS_MTR1_WCSS_SHIFT) 4647 #define HYPERBUS_MTR1_RCSS_SHIFT (20U) 4648 #define HYPERBUS_MTR1_RCSS_MASK (0xFU << HYPERBUS_MTR1_RCSS_SHIFT) 4649 #define HYPERBUS_MTR1_WCSHI_SHIFT (24U) 4650 #define HYPERBUS_MTR1_WCSHI_MASK (0xFU << HYPERBUS_MTR1_WCSHI_SHIFT) 4651 #define HYPERBUS_MTR1_RCSHI_SHIFT (28U) 4652 #define HYPERBUS_MTR1_RCSHI_MASK (0xFU << HYPERBUS_MTR1_RCSHI_SHIFT) 4653 /* GPOR */ 4654 #define HYPERBUS_GPOR_OFFSET (0x40U) 4655 #define HYPERBUS_GPOR_GPO_SHIFT (0U) 4656 #define HYPERBUS_GPOR_GPO_MASK (0x3U << HYPERBUS_GPOR_GPO_SHIFT) 4657 /* WPR */ 4658 #define HYPERBUS_WPR_OFFSET (0x44U) 4659 #define HYPERBUS_WPR_WP_SHIFT (0U) 4660 #define HYPERBUS_WPR_WP_MASK (0x1U << HYPERBUS_WPR_WP_SHIFT) 4661 /* LBR */ 4662 #define HYPERBUS_LBR_OFFSET (0x48U) 4663 #define HYPERBUS_LBR_LOOPBACK_SHIFT (0U) 4664 #define HYPERBUS_LBR_LOOPBACK_MASK (0x1U << HYPERBUS_LBR_LOOPBACK_SHIFT) 4665 /* TAR */ 4666 #define HYPERBUS_TAR_OFFSET (0x4CU) 4667 #define HYPERBUS_TAR_WTA_SHIFT (0U) 4668 #define HYPERBUS_TAR_WTA_MASK (0x3U << HYPERBUS_TAR_WTA_SHIFT) 4669 #define HYPERBUS_TAR_RTA_SHIFT (4U) 4670 #define HYPERBUS_TAR_RTA_MASK (0x3U << HYPERBUS_TAR_RTA_SHIFT) 4671 /* RWDSIC */ 4672 #define HYPERBUS_RWDSIC_OFFSET (0x50U) 4673 #define HYPERBUS_RWDSIC_RXSTART_CTRL_SHIFT (0U) 4674 #define HYPERBUS_RWDSIC_RXSTART_CTRL_MASK (0x1U << HYPERBUS_RWDSIC_RXSTART_CTRL_SHIFT) 4675 #define HYPERBUS_RWDSIC_RXEND_CTRL_SHIFT (1U) 4676 #define HYPERBUS_RWDSIC_RXEND_CTRL_MASK (0x1U << HYPERBUS_RWDSIC_RXEND_CTRL_SHIFT) 4677 /* CA2RSVD */ 4678 #define HYPERBUS_CA2RSVD_OFFSET (0x54U) 4679 #define HYPERBUS_CA2RSVD_CA2_DATA_SHIFT (3U) 4680 #define HYPERBUS_CA2RSVD_CA2_DATA_MASK (0x1FFFU << HYPERBUS_CA2RSVD_CA2_DATA_SHIFT) 4681 /* SPCSR */ 4682 #define HYPERBUS_SPCSR_OFFSET (0x58U) 4683 #define HYPERBUS_SPCSR_W955D8_CON_SHIFT (0U) 4684 #define HYPERBUS_SPCSR_W955D8_CON_MASK (0x3U << HYPERBUS_SPCSR_W955D8_CON_SHIFT) 4685 /******************************************PMU*******************************************/ 4686 /* WAKEUP_CFG */ 4687 #define PMU_WAKEUP_CFG_OFFSET (0x0U) 4688 #define PMU_WAKEUP_CFG_M4_INT_EN_SHIFT (0U) 4689 #define PMU_WAKEUP_CFG_M4_INT_EN_MASK (0x1U << PMU_WAKEUP_CFG_M4_INT_EN_SHIFT) 4690 #define PMU_WAKEUP_CFG_M0_INT_EN_SHIFT (1U) 4691 #define PMU_WAKEUP_CFG_M0_INT_EN_MASK (0x1U << PMU_WAKEUP_CFG_M0_INT_EN_SHIFT) 4692 #define PMU_WAKEUP_CFG_TIMEOUT_EN_SHIFT (2U) 4693 #define PMU_WAKEUP_CFG_TIMEOUT_EN_MASK (0x1U << PMU_WAKEUP_CFG_TIMEOUT_EN_SHIFT) 4694 /* PWRDN_ST */ 4695 #define PMU_PWRDN_ST_OFFSET (0x4U) 4696 #define PMU_PWRDN_ST_RPU_SLEEP_READY_SHIFT (0U) 4697 #define PMU_PWRDN_ST_RPU_SLEEP_READY_MASK (0x1U << PMU_PWRDN_ST_RPU_SLEEP_READY_SHIFT) 4698 #define PMU_PWRDN_ST_M4_SLEEP_SHIFT (1U) 4699 #define PMU_PWRDN_ST_M4_SLEEP_MASK (0x1U << PMU_PWRDN_ST_M4_SLEEP_SHIFT) 4700 #define PMU_PWRDN_ST_M0_SLEEP_SHIFT (2U) 4701 #define PMU_PWRDN_ST_M0_SLEEP_MASK (0x1U << PMU_PWRDN_ST_M0_SLEEP_SHIFT) 4702 #define PMU_PWRDN_ST_M4_DBGPWRUPREQ_SHIFT (3U) 4703 #define PMU_PWRDN_ST_M4_DBGPWRUPREQ_MASK (0x1U << PMU_PWRDN_ST_M4_DBGPWRUPREQ_SHIFT) 4704 #define PMU_PWRDN_ST_M0_DBGPWRUPREQ_SHIFT (4U) 4705 #define PMU_PWRDN_ST_M0_DBGPWRUPREQ_MASK (0x1U << PMU_PWRDN_ST_M0_DBGPWRUPREQ_SHIFT) 4706 #define PMU_PWRDN_ST_LPW_SLEEP_NOW_SHIFT (5U) 4707 #define PMU_PWRDN_ST_LPW_SLEEP_NOW_MASK (0x1U << PMU_PWRDN_ST_LPW_SLEEP_NOW_SHIFT) 4708 #define PMU_PWRDN_ST_LPW_SLEEP_STATE_SHIFT (6U) 4709 #define PMU_PWRDN_ST_LPW_SLEEP_STATE_MASK (0x1U << PMU_PWRDN_ST_LPW_SLEEP_STATE_SHIFT) 4710 #define PMU_PWRDN_ST_PD_LPW_DWN_STAT_SHIFT (7U) 4711 #define PMU_PWRDN_ST_PD_LPW_DWN_STAT_MASK (0x1U << PMU_PWRDN_ST_PD_LPW_DWN_STAT_SHIFT) 4712 #define PMU_PWRDN_ST_PD_PERI_DWN_STAT_SHIFT (8U) 4713 #define PMU_PWRDN_ST_PD_PERI_DWN_STAT_MASK (0x1U << PMU_PWRDN_ST_PD_PERI_DWN_STAT_SHIFT) 4714 #define PMU_PWRDN_ST_PD_MCU_DWN_STAT_SHIFT (9U) 4715 #define PMU_PWRDN_ST_PD_MCU_DWN_STAT_MASK (0x1U << PMU_PWRDN_ST_PD_MCU_DWN_STAT_SHIFT) 4716 /* PWRMODE_CON */ 4717 #define PMU_PWRMODE_CON_OFFSET (0x8U) 4718 #define PMU_PWRMODE_CON_POWER_MODE_EN_SHIFT (0U) 4719 #define PMU_PWRMODE_CON_POWER_MODE_EN_MASK (0x1U << PMU_PWRMODE_CON_POWER_MODE_EN_SHIFT) 4720 #define PMU_PWRMODE_CON_CLR_WIFI_SHIFT (1U) 4721 #define PMU_PWRMODE_CON_CLR_WIFI_MASK (0x1U << PMU_PWRMODE_CON_CLR_WIFI_SHIFT) 4722 #define PMU_PWRMODE_CON_CLR_PERI_SHIFT (2U) 4723 #define PMU_PWRMODE_CON_CLR_PERI_MASK (0x1U << PMU_PWRMODE_CON_CLR_PERI_SHIFT) 4724 #define PMU_PWRMODE_CON_CLR_MCU_SHIFT (3U) 4725 #define PMU_PWRMODE_CON_CLR_MCU_MASK (0x1U << PMU_PWRMODE_CON_CLR_MCU_SHIFT) 4726 #define PMU_PWRMODE_CON_CLR_TOP_SHIFT (4U) 4727 #define PMU_PWRMODE_CON_CLR_TOP_MASK (0x1U << PMU_PWRMODE_CON_CLR_TOP_SHIFT) 4728 #define PMU_PWRMODE_CON_NOC_AUTO_CON_WIFI_SHIFT (5U) 4729 #define PMU_PWRMODE_CON_NOC_AUTO_CON_WIFI_MASK (0x1U << PMU_PWRMODE_CON_NOC_AUTO_CON_WIFI_SHIFT) 4730 #define PMU_PWRMODE_CON_NOC_AUTO_CON_PERI_SHIFT (6U) 4731 #define PMU_PWRMODE_CON_NOC_AUTO_CON_PERI_MASK (0x1U << PMU_PWRMODE_CON_NOC_AUTO_CON_PERI_SHIFT) 4732 #define PMU_PWRMODE_CON_NOC_AUTO_CON_MCU_SHIFT (7U) 4733 #define PMU_PWRMODE_CON_NOC_AUTO_CON_MCU_MASK (0x1U << PMU_PWRMODE_CON_NOC_AUTO_CON_MCU_SHIFT) 4734 #define PMU_PWRMODE_CON_NOC_AUTO_CON_TOP_SHIFT (8U) 4735 #define PMU_PWRMODE_CON_NOC_AUTO_CON_TOP_MASK (0x1U << PMU_PWRMODE_CON_NOC_AUTO_CON_TOP_SHIFT) 4736 #define PMU_PWRMODE_CON_CLK_CORE_SRC_GATE_SHIFT (9U) 4737 #define PMU_PWRMODE_CON_CLK_CORE_SRC_GATE_MASK (0x1U << PMU_PWRMODE_CON_CLK_CORE_SRC_GATE_SHIFT) 4738 #define PMU_PWRMODE_CON_CLK_TOP_SRC_GATE_SHIFT (10U) 4739 #define PMU_PWRMODE_CON_CLK_TOP_SRC_GATE_MASK (0x1U << PMU_PWRMODE_CON_CLK_TOP_SRC_GATE_SHIFT) 4740 #define PMU_PWRMODE_CON_PMU_USE_LF_SHIFT (11U) 4741 #define PMU_PWRMODE_CON_PMU_USE_LF_MASK (0x1U << PMU_PWRMODE_CON_PMU_USE_LF_SHIFT) 4742 #define PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_SHIFT (12U) 4743 #define PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_MASK (0x1U << PMU_PWRMODE_CON_GLOBAL_INT_DISABLE_SHIFT) 4744 #define PMU_PWRMODE_CON_MCU_PD_EN_SHIFT (13U) 4745 #define PMU_PWRMODE_CON_MCU_PD_EN_MASK (0x1U << PMU_PWRMODE_CON_MCU_PD_EN_SHIFT) 4746 #define PMU_PWRMODE_CON_RF_RESET_EN_SHIFT (14U) 4747 #define PMU_PWRMODE_CON_RF_RESET_EN_MASK (0x1U << PMU_PWRMODE_CON_RF_RESET_EN_SHIFT) 4748 #define PMU_PWRMODE_CON_AON_RESET_EN_SHIFT (15U) 4749 #define PMU_PWRMODE_CON_AON_RESET_EN_MASK (0x1U << PMU_PWRMODE_CON_AON_RESET_EN_SHIFT) 4750 #define PMU_PWRMODE_CON_OSC_DIS_SHIFT (16U) 4751 #define PMU_PWRMODE_CON_OSC_DIS_MASK (0x1U << PMU_PWRMODE_CON_OSC_DIS_SHIFT) 4752 #define PMU_PWRMODE_CON_RF_VDD18_DIS_SHIFT (17U) 4753 #define PMU_PWRMODE_CON_RF_VDD18_DIS_MASK (0x1U << PMU_PWRMODE_CON_RF_VDD18_DIS_SHIFT) 4754 #define PMU_PWRMODE_CON_WAIT_WAKEUP_BEGIN_SHIFT (18U) 4755 #define PMU_PWRMODE_CON_WAIT_WAKEUP_BEGIN_MASK (0x1U << PMU_PWRMODE_CON_WAIT_WAKEUP_BEGIN_SHIFT) 4756 #define PMU_PWRMODE_CON_OSC_40M_GATE_EN_SHIFT (19U) 4757 #define PMU_PWRMODE_CON_OSC_40M_GATE_EN_MASK (0x1U << PMU_PWRMODE_CON_OSC_40M_GATE_EN_SHIFT) 4758 #define PMU_PWRMODE_CON_PLL_PD_EN_SHIFT (20U) 4759 #define PMU_PWRMODE_CON_PLL_PD_EN_MASK (0x1U << PMU_PWRMODE_CON_PLL_PD_EN_SHIFT) 4760 #define PMU_PWRMODE_CON_GPLL_PD_EN_SHIFT (21U) 4761 #define PMU_PWRMODE_CON_GPLL_PD_EN_MASK (0x1U << PMU_PWRMODE_CON_GPLL_PD_EN_SHIFT) 4762 #define PMU_PWRMODE_CON_VPLL_PD_EN_SHIFT (22U) 4763 #define PMU_PWRMODE_CON_VPLL_PD_EN_MASK (0x1U << PMU_PWRMODE_CON_VPLL_PD_EN_SHIFT) 4764 #define PMU_PWRMODE_CON_PMU_SLEEP_POL_SHIFT (23U) 4765 #define PMU_PWRMODE_CON_PMU_SLEEP_POL_MASK (0x1U << PMU_PWRMODE_CON_PMU_SLEEP_POL_SHIFT) 4766 /* SFT_CON */ 4767 #define PMU_SFT_CON_OFFSET (0xCU) 4768 #define PMU_SFT_CON_IDLE_REQ_WIFI_CFG_SHIFT (0U) 4769 #define PMU_SFT_CON_IDLE_REQ_WIFI_CFG_MASK (0x1U << PMU_SFT_CON_IDLE_REQ_WIFI_CFG_SHIFT) 4770 #define PMU_SFT_CON_IDLE_REQ_PERI_CFG_SHIFT (1U) 4771 #define PMU_SFT_CON_IDLE_REQ_PERI_CFG_MASK (0x1U << PMU_SFT_CON_IDLE_REQ_PERI_CFG_SHIFT) 4772 #define PMU_SFT_CON_IDLE_REQ_MCU_CFG_SHIFT (2U) 4773 #define PMU_SFT_CON_IDLE_REQ_MCU_CFG_MASK (0x1U << PMU_SFT_CON_IDLE_REQ_MCU_CFG_SHIFT) 4774 #define PMU_SFT_CON_IDLE_REQ_TOP_CFG_SHIFT (3U) 4775 #define PMU_SFT_CON_IDLE_REQ_TOP_CFG_MASK (0x1U << PMU_SFT_CON_IDLE_REQ_TOP_CFG_SHIFT) 4776 #define PMU_SFT_CON_M4_CLK_SRC_GATING_CFG_SHIFT (4U) 4777 #define PMU_SFT_CON_M4_CLK_SRC_GATING_CFG_MASK (0x1U << PMU_SFT_CON_M4_CLK_SRC_GATING_CFG_SHIFT) 4778 #define PMU_SFT_CON_LF_ENA_CFG_SHIFT (5U) 4779 #define PMU_SFT_CON_LF_ENA_CFG_MASK (0x1U << PMU_SFT_CON_LF_ENA_CFG_SHIFT) 4780 #define PMU_SFT_CON_LF_MODE_CFG_SHIFT (6U) 4781 #define PMU_SFT_CON_LF_MODE_CFG_MASK (0x1U << PMU_SFT_CON_LF_MODE_CFG_SHIFT) 4782 #define PMU_SFT_CON_OSC_40_GATE_CFG_SHIFT (8U) 4783 #define PMU_SFT_CON_OSC_40_GATE_CFG_MASK (0x1U << PMU_SFT_CON_OSC_40_GATE_CFG_SHIFT) 4784 #define PMU_SFT_CON_PD_PERI_PWRDWN_CFG_SHIFT (9U) 4785 #define PMU_SFT_CON_PD_PERI_PWRDWN_CFG_MASK (0x1U << PMU_SFT_CON_PD_PERI_PWRDWN_CFG_SHIFT) 4786 #define PMU_SFT_CON_PD_MCU_PWRDWN_CFG_SHIFT (10U) 4787 #define PMU_SFT_CON_PD_MCU_PWRDWN_CFG_MASK (0x1U << PMU_SFT_CON_PD_MCU_PWRDWN_CFG_SHIFT) 4788 #define PMU_SFT_CON_GPLL_PD_CFG_SHIFT (11U) 4789 #define PMU_SFT_CON_GPLL_PD_CFG_MASK (0x1U << PMU_SFT_CON_GPLL_PD_CFG_SHIFT) 4790 #define PMU_SFT_CON_VPLL_PD_CFG_SHIFT (12U) 4791 #define PMU_SFT_CON_VPLL_PD_CFG_MASK (0x1U << PMU_SFT_CON_VPLL_PD_CFG_SHIFT) 4792 #define PMU_SFT_CON_RF_RESETN_CFG_SHIFT (13U) 4793 #define PMU_SFT_CON_RF_RESETN_CFG_MASK (0x1U << PMU_SFT_CON_RF_RESETN_CFG_SHIFT) 4794 #define PMU_SFT_CON_RF_XO_CFG_SHIFT (15U) 4795 #define PMU_SFT_CON_RF_XO_CFG_MASK (0x1U << PMU_SFT_CON_RF_XO_CFG_SHIFT) 4796 #define PMU_SFT_CON_PMU_LF_SWITCH_CFG_SHIFT (17U) 4797 #define PMU_SFT_CON_PMU_LF_SWITCH_CFG_MASK (0x1U << PMU_SFT_CON_PMU_LF_SWITCH_CFG_SHIFT) 4798 #define PMU_SFT_CON_PLL_LF_SWITCH_CFG_SHIFT (18U) 4799 #define PMU_SFT_CON_PLL_LF_SWITCH_CFG_MASK (0x1U << PMU_SFT_CON_PLL_LF_SWITCH_CFG_SHIFT) 4800 #define PMU_SFT_CON_SRAM_NAP_CFG_SHIFT (20U) 4801 #define PMU_SFT_CON_SRAM_NAP_CFG_MASK (0xFU << PMU_SFT_CON_SRAM_NAP_CFG_SHIFT) 4802 #define PMU_SFT_CON_SRAM_RET_CFG_SHIFT (24U) 4803 #define PMU_SFT_CON_SRAM_RET_CFG_MASK (0xFU << PMU_SFT_CON_SRAM_RET_CFG_SHIFT) 4804 #define PMU_SFT_CON_SRAM_PSD_CFG_SHIFT (28U) 4805 #define PMU_SFT_CON_SRAM_PSD_CFG_MASK (0xFU << PMU_SFT_CON_SRAM_PSD_CFG_SHIFT) 4806 /* INT_CON */ 4807 #define PMU_INT_CON_OFFSET (0x10U) 4808 #define PMU_INT_CON_PMU_INT_EN_SHIFT (0U) 4809 #define PMU_INT_CON_PMU_INT_EN_MASK (0x1U << PMU_INT_CON_PMU_INT_EN_SHIFT) 4810 #define PMU_INT_CON_PWRMODE_WAKEUP_INT_EN_SHIFT (1U) 4811 #define PMU_INT_CON_PWRMODE_WAKEUP_INT_EN_MASK (0x1U << PMU_INT_CON_PWRMODE_WAKEUP_INT_EN_SHIFT) 4812 #define PMU_INT_CON_WAKEUP_M4_INT_EN_SHIFT (2U) 4813 #define PMU_INT_CON_WAKEUP_M4_INT_EN_MASK (0x1U << PMU_INT_CON_WAKEUP_M4_INT_EN_SHIFT) 4814 #define PMU_INT_CON_WAKEUP_M0_INT_EN_SHIFT (3U) 4815 #define PMU_INT_CON_WAKEUP_M0_INT_EN_MASK (0x1U << PMU_INT_CON_WAKEUP_M0_INT_EN_SHIFT) 4816 #define PMU_INT_CON_WAKEUP_TIMEOUT_INT_EN_SHIFT (4U) 4817 #define PMU_INT_CON_WAKEUP_TIMEOUT_INT_EN_MASK (0x1U << PMU_INT_CON_WAKEUP_TIMEOUT_INT_EN_SHIFT) 4818 #define PMU_INT_CON_WIFI_PWR_SWITCH_INT_EN_SHIFT (5U) 4819 #define PMU_INT_CON_WIFI_PWR_SWITCH_INT_EN_MASK (0x1U << PMU_INT_CON_WIFI_PWR_SWITCH_INT_EN_SHIFT) 4820 #define PMU_INT_CON_PERI_PWR_SWITCH_INT_EN_SHIFT (6U) 4821 #define PMU_INT_CON_PERI_PWR_SWITCH_INT_EN_MASK (0x1U << PMU_INT_CON_PERI_PWR_SWITCH_INT_EN_SHIFT) 4822 #define PMU_INT_CON_MCU_PWR_SWITCH_INT_EN_SHIFT (7U) 4823 #define PMU_INT_CON_MCU_PWR_SWITCH_INT_EN_MASK (0x1U << PMU_INT_CON_MCU_PWR_SWITCH_INT_EN_SHIFT) 4824 /* INT_ST */ 4825 #define PMU_INT_ST_OFFSET (0x14U) 4826 #define PMU_INT_ST_PWRMODE_WAKEUP_STATUS_SHIFT (1U) 4827 #define PMU_INT_ST_PWRMODE_WAKEUP_STATUS_MASK (0x1U << PMU_INT_ST_PWRMODE_WAKEUP_STATUS_SHIFT) 4828 #define PMU_INT_ST_WAKEUP_M4_STATUS_SHIFT (2U) 4829 #define PMU_INT_ST_WAKEUP_M4_STATUS_MASK (0x1U << PMU_INT_ST_WAKEUP_M4_STATUS_SHIFT) 4830 #define PMU_INT_ST_WAKEUP_INT_M0_STATUS_SHIFT (3U) 4831 #define PMU_INT_ST_WAKEUP_INT_M0_STATUS_MASK (0x1U << PMU_INT_ST_WAKEUP_INT_M0_STATUS_SHIFT) 4832 #define PMU_INT_ST_WAKEUP_TIMOUT_STATUS_SHIFT (4U) 4833 #define PMU_INT_ST_WAKEUP_TIMOUT_STATUS_MASK (0x1U << PMU_INT_ST_WAKEUP_TIMOUT_STATUS_SHIFT) 4834 #define PMU_INT_ST_WIFI_POWER_SWITCH_WAKEUP_STATUS_SHIFT (5U) 4835 #define PMU_INT_ST_WIFI_POWER_SWITCH_WAKEUP_STATUS_MASK (0x1U << PMU_INT_ST_WIFI_POWER_SWITCH_WAKEUP_STATUS_SHIFT) 4836 #define PMU_INT_ST_PERI_POWER_SWITCH_WAKEUP_STATUS_SHIFT (6U) 4837 #define PMU_INT_ST_PERI_POWER_SWITCH_WAKEUP_STATUS_MASK (0x1U << PMU_INT_ST_PERI_POWER_SWITCH_WAKEUP_STATUS_SHIFT) 4838 #define PMU_INT_ST_MCU_POWER_SWITCH_WAKEUP_STATUS_SHIFT (7U) 4839 #define PMU_INT_ST_MCU_POWER_SWITCH_WAKEUP_STATUS_MASK (0x1U << PMU_INT_ST_MCU_POWER_SWITCH_WAKEUP_STATUS_SHIFT) 4840 /* BUS_IDLE_ST */ 4841 #define PMU_BUS_IDLE_ST_OFFSET (0x18U) 4842 #define PMU_BUS_IDLE_ST_IDLE_ACK_WIFI_SHIFT (0U) 4843 #define PMU_BUS_IDLE_ST_IDLE_ACK_WIFI_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_ACK_WIFI_SHIFT) 4844 #define PMU_BUS_IDLE_ST_IDLE_ACK_PERI_SHIFT (1U) 4845 #define PMU_BUS_IDLE_ST_IDLE_ACK_PERI_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_ACK_PERI_SHIFT) 4846 #define PMU_BUS_IDLE_ST_IDLE_ACK_MCU_SHIFT (2U) 4847 #define PMU_BUS_IDLE_ST_IDLE_ACK_MCU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_ACK_MCU_SHIFT) 4848 #define PMU_BUS_IDLE_ST_IDLE_ACK_TOP_SHIFT (3U) 4849 #define PMU_BUS_IDLE_ST_IDLE_ACK_TOP_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_ACK_TOP_SHIFT) 4850 #define PMU_BUS_IDLE_ST_IDLE_LPW_SHIFT (16U) 4851 #define PMU_BUS_IDLE_ST_IDLE_LPW_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_LPW_SHIFT) 4852 #define PMU_BUS_IDLE_ST_IDLE_PERI_SHIFT (17U) 4853 #define PMU_BUS_IDLE_ST_IDLE_PERI_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PERI_SHIFT) 4854 #define PMU_BUS_IDLE_ST_IDLE_MCU_SHIFT (18U) 4855 #define PMU_BUS_IDLE_ST_IDLE_MCU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_MCU_SHIFT) 4856 #define PMU_BUS_IDLE_ST_IDLE_TOP_SHIFT (19U) 4857 #define PMU_BUS_IDLE_ST_IDLE_TOP_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_TOP_SHIFT) 4858 /* POWER_ST */ 4859 #define PMU_POWER_ST_OFFSET (0x1CU) 4860 #define PMU_POWER_ST_POWER_STATE_SHIFT (0U) 4861 #define PMU_POWER_ST_POWER_STATE_MASK (0x1FU << PMU_POWER_ST_POWER_STATE_SHIFT) 4862 /* OSC_CNT */ 4863 #define PMU_OSC_CNT_OFFSET (0x20U) 4864 #define PMU_OSC_CNT_PMU_OSC_CNT_SHIFT (0U) 4865 #define PMU_OSC_CNT_PMU_OSC_CNT_MASK (0xFFFFFU << PMU_OSC_CNT_PMU_OSC_CNT_SHIFT) 4866 /* PLLLOCK_CNT */ 4867 #define PMU_PLLLOCK_CNT_OFFSET (0x24U) 4868 #define PMU_PLLLOCK_CNT_PMU_OSC_CNT_SHIFT (0U) 4869 #define PMU_PLLLOCK_CNT_PMU_OSC_CNT_MASK (0xFFFFFU << PMU_PLLLOCK_CNT_PMU_OSC_CNT_SHIFT) 4870 /* PLLRST_CNT */ 4871 #define PMU_PLLRST_CNT_OFFSET (0x28U) 4872 #define PMU_PLLRST_CNT_PMU_OSC_CNT_SHIFT (0U) 4873 #define PMU_PLLRST_CNT_PMU_OSC_CNT_MASK (0xFFFFFU << PMU_PLLRST_CNT_PMU_OSC_CNT_SHIFT) 4874 /* RET_CON */ 4875 #define PMU_RET_CON_OFFSET (0x2CU) 4876 #define PMU_RET_CON_SRAM_PSD_EN_SHIFT (0U) 4877 #define PMU_RET_CON_SRAM_PSD_EN_MASK (0xFU << PMU_RET_CON_SRAM_PSD_EN_SHIFT) 4878 #define PMU_RET_CON_SRAM_RET_EN_SHIFT (4U) 4879 #define PMU_RET_CON_SRAM_RET_EN_MASK (0xFU << PMU_RET_CON_SRAM_RET_EN_SHIFT) 4880 #define PMU_RET_CON_SRAM_NAP_EN_SHIFT (8U) 4881 #define PMU_RET_CON_SRAM_NAP_EN_MASK (0xFU << PMU_RET_CON_SRAM_NAP_EN_SHIFT) 4882 /* INFO_TX_CON */ 4883 #define PMU_INFO_TX_CON_OFFSET (0x30U) 4884 #define PMU_INFO_TX_CON_INFO_TX_EN_SHIFT (0U) 4885 #define PMU_INFO_TX_CON_INFO_TX_EN_MASK (0x1U << PMU_INFO_TX_CON_INFO_TX_EN_SHIFT) 4886 #define PMU_INFO_TX_CON_INFO_TX_MODE_SHIFT (4U) 4887 #define PMU_INFO_TX_CON_INFO_TX_MODE_MASK (0x7U << PMU_INFO_TX_CON_INFO_TX_MODE_SHIFT) 4888 #define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT (8U) 4889 #define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_MASK (0xFFU << PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT) 4890 /* SYS_REG0 */ 4891 #define PMU_SYS_REG0_OFFSET (0x40U) 4892 #define PMU_SYS_REG0_SYSTEM_REGISTERS0_SHIFT (0U) 4893 #define PMU_SYS_REG0_SYSTEM_REGISTERS0_MASK (0xFFFFFFFFU << PMU_SYS_REG0_SYSTEM_REGISTERS0_SHIFT) 4894 /* SYS_REG1 */ 4895 #define PMU_SYS_REG1_OFFSET (0x44U) 4896 #define PMU_SYS_REG1_SYSTEM_REGISTERS1_SHIFT (0U) 4897 #define PMU_SYS_REG1_SYSTEM_REGISTERS1_MASK (0xFFFFFFFFU << PMU_SYS_REG1_SYSTEM_REGISTERS1_SHIFT) 4898 /* SYS_REG2 */ 4899 #define PMU_SYS_REG2_OFFSET (0x48U) 4900 #define PMU_SYS_REG2_SYSTEM_REGISTERS2_SHIFT (0U) 4901 #define PMU_SYS_REG2_SYSTEM_REGISTERS2_MASK (0xFFFFFFFFU << PMU_SYS_REG2_SYSTEM_REGISTERS2_SHIFT) 4902 /* SYS_REG3 */ 4903 #define PMU_SYS_REG3_OFFSET (0x4CU) 4904 #define PMU_SYS_REG3_SYSTEM_REGISTERS3_SHIFT (0U) 4905 #define PMU_SYS_REG3_SYSTEM_REGISTERS3_MASK (0xFFFFFFFFU << PMU_SYS_REG3_SYSTEM_REGISTERS3_SHIFT) 4906 /* TIMEOUT_CNT */ 4907 #define PMU_TIMEOUT_CNT_OFFSET (0x80U) 4908 #define PMU_TIMEOUT_CNT_TIMEOUT_COUNT_SHIFT (0U) 4909 #define PMU_TIMEOUT_CNT_TIMEOUT_COUNT_MASK (0xFFFFFFFFU << PMU_TIMEOUT_CNT_TIMEOUT_COUNT_SHIFT) 4910 /******************************************GPIO******************************************/ 4911 /* SWPORT_DR_L */ 4912 #define GPIO_SWPORT_DR_L_OFFSET (0x0U) 4913 #define GPIO_SWPORT_DR_L_GPIO_SWPORT_DR_LOW_SHIFT (0U) 4914 #define GPIO_SWPORT_DR_L_GPIO_SWPORT_DR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DR_L_GPIO_SWPORT_DR_LOW_SHIFT) 4915 /* SWPORT_DR_H */ 4916 #define GPIO_SWPORT_DR_H_OFFSET (0x4U) 4917 #define GPIO_SWPORT_DR_H_GPIO_SWPORT_DR_HIGH_SHIFT (0U) 4918 #define GPIO_SWPORT_DR_H_GPIO_SWPORT_DR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DR_H_GPIO_SWPORT_DR_HIGH_SHIFT) 4919 /* SWPORT_DDR_L */ 4920 #define GPIO_SWPORT_DDR_L_OFFSET (0x8U) 4921 #define GPIO_SWPORT_DDR_L_GPIO_SWPORT_DDR_LOW_SHIFT (0U) 4922 #define GPIO_SWPORT_DDR_L_GPIO_SWPORT_DDR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DDR_L_GPIO_SWPORT_DDR_LOW_SHIFT) 4923 /* SWPORT_DDR_H */ 4924 #define GPIO_SWPORT_DDR_H_OFFSET (0xCU) 4925 #define GPIO_SWPORT_DDR_H_GPIO_SWPORT_DDR_HIGH_SHIFT (0U) 4926 #define GPIO_SWPORT_DDR_H_GPIO_SWPORT_DDR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DDR_H_GPIO_SWPORT_DDR_HIGH_SHIFT) 4927 /* INT_EN_L */ 4928 #define GPIO_INT_EN_L_OFFSET (0x10U) 4929 #define GPIO_INT_EN_L_GPIO_INT_EN_LOW_SHIFT (0U) 4930 #define GPIO_INT_EN_L_GPIO_INT_EN_LOW_MASK (0xFFFFU << GPIO_INT_EN_L_GPIO_INT_EN_LOW_SHIFT) 4931 /* INT_EN_H */ 4932 #define GPIO_INT_EN_H_OFFSET (0x14U) 4933 #define GPIO_INT_EN_H_GPIO_INT_EN_HIGH_SHIFT (0U) 4934 #define GPIO_INT_EN_H_GPIO_INT_EN_HIGH_MASK (0xFFFFU << GPIO_INT_EN_H_GPIO_INT_EN_HIGH_SHIFT) 4935 /* INT_MASK_L */ 4936 #define GPIO_INT_MASK_L_OFFSET (0x18U) 4937 #define GPIO_INT_MASK_L_GPIO_INT_MASK_LOW_SHIFT (0U) 4938 #define GPIO_INT_MASK_L_GPIO_INT_MASK_LOW_MASK (0xFFFFU << GPIO_INT_MASK_L_GPIO_INT_MASK_LOW_SHIFT) 4939 /* INT_MASK_H */ 4940 #define GPIO_INT_MASK_H_OFFSET (0x1CU) 4941 #define GPIO_INT_MASK_H_GPIO_INT_MASK_HIGH_SHIFT (0U) 4942 #define GPIO_INT_MASK_H_GPIO_INT_MASK_HIGH_MASK (0xFFFFU << GPIO_INT_MASK_H_GPIO_INT_MASK_HIGH_SHIFT) 4943 /* INT_TYPE_L */ 4944 #define GPIO_INT_TYPE_L_OFFSET (0x20U) 4945 #define GPIO_INT_TYPE_L_GPIO_INT_TYPE_LOW_SHIFT (0U) 4946 #define GPIO_INT_TYPE_L_GPIO_INT_TYPE_LOW_MASK (0xFFFFU << GPIO_INT_TYPE_L_GPIO_INT_TYPE_LOW_SHIFT) 4947 /* INT_TYPE_H */ 4948 #define GPIO_INT_TYPE_H_OFFSET (0x24U) 4949 #define GPIO_INT_TYPE_H_GPIO_INT_TYPE_HIGH_SHIFT (0U) 4950 #define GPIO_INT_TYPE_H_GPIO_INT_TYPE_HIGH_MASK (0xFFFFU << GPIO_INT_TYPE_H_GPIO_INT_TYPE_HIGH_SHIFT) 4951 /* INT_POLARITY_L */ 4952 #define GPIO_INT_POLARITY_L_OFFSET (0x28U) 4953 #define GPIO_INT_POLARITY_L_GPIO_INT_POLARITY_LOW_SHIFT (0U) 4954 #define GPIO_INT_POLARITY_L_GPIO_INT_POLARITY_LOW_MASK \ 4955 (0xFFFFU << GPIO_INT_POLARITY_L_GPIO_INT_POLARITY_LOW_SHIFT) 4956 /* INT_POLARITY_H */ 4957 #define GPIO_INT_POLARITY_H_OFFSET (0x2CU) 4958 #define GPIO_INT_POLARITY_H_GPIO_INT_POLARITY_HIGH_SHIFT (0U) 4959 #define GPIO_INT_POLARITY_H_GPIO_INT_POLARITY_HIGH_MASK \ 4960 (0xFFFFU << GPIO_INT_POLARITY_H_GPIO_INT_POLARITY_HIGH_SHIFT) 4961 /* INT_BOTHEDGE_L */ 4962 #define GPIO_INT_BOTHEDGE_L_OFFSET (0x30U) 4963 #define GPIO_INT_BOTHEDGE_L_GPIO_INT_BOTHEDGE_LOW_SHIFT (0U) 4964 #define GPIO_INT_BOTHEDGE_L_GPIO_INT_BOTHEDGE_LOW_MASK \ 4965 (0xFFFFU << GPIO_INT_BOTHEDGE_L_GPIO_INT_BOTHEDGE_LOW_SHIFT) 4966 /* INT_BOTHEDGE_H */ 4967 #define GPIO_INT_BOTHEDGE_H_OFFSET (0x34U) 4968 #define GPIO_INT_BOTHEDGE_H_GPIO_INT_BOTHEDGE_HIGH_SHIFT (0U) 4969 #define GPIO_INT_BOTHEDGE_H_GPIO_INT_BOTHEDGE_HIGH_MASK \ 4970 (0xFFFFU << GPIO_INT_BOTHEDGE_H_GPIO_INT_BOTHEDGE_HIGH_SHIFT) 4971 /* DEBOUNCE_L */ 4972 #define GPIO_DEBOUNCE_L_OFFSET (0x38U) 4973 #define GPIO_DEBOUNCE_L_GPIO_DEBOUNCE_LOW_SHIFT (0U) 4974 #define GPIO_DEBOUNCE_L_GPIO_DEBOUNCE_LOW_MASK (0xFFFFU << GPIO_DEBOUNCE_L_GPIO_DEBOUNCE_LOW_SHIFT) 4975 /* DEBOUNCE_H */ 4976 #define GPIO_DEBOUNCE_H_OFFSET (0x3CU) 4977 #define GPIO_DEBOUNCE_H_GPIO_DEBOUNCE_HIGH_SHIFT (0U) 4978 #define GPIO_DEBOUNCE_H_GPIO_DEBOUNCE_HIGH_MASK (0xFFFFU << GPIO_DEBOUNCE_H_GPIO_DEBOUNCE_HIGH_SHIFT) 4979 /* DBCLK_DIV_EN_L */ 4980 #define GPIO_DBCLK_DIV_EN_L_OFFSET (0x40U) 4981 #define GPIO_DBCLK_DIV_EN_L_GPIO_DBCLK_DIV_EN_LOW_SHIFT (0U) 4982 #define GPIO_DBCLK_DIV_EN_L_GPIO_DBCLK_DIV_EN_LOW_MASK \ 4983 (0xFFFFU << GPIO_DBCLK_DIV_EN_L_GPIO_DBCLK_DIV_EN_LOW_SHIFT) 4984 /* DBCLK_DIV_EN_H */ 4985 #define GPIO_DBCLK_DIV_EN_H_OFFSET (0x44U) 4986 #define GPIO_DBCLK_DIV_EN_H_GPIO_DBCLK_DIV_EN_HIGH_SHIFT (0U) 4987 #define GPIO_DBCLK_DIV_EN_H_GPIO_DBCLK_DIV_EN_HIGH_MASK \ 4988 (0xFFFFU << GPIO_DBCLK_DIV_EN_H_GPIO_DBCLK_DIV_EN_HIGH_SHIFT) 4989 /* DBCLK_DIV_CON */ 4990 #define GPIO_DBCLK_DIV_CON_OFFSET (0x48U) 4991 #define GPIO_DBCLK_DIV_CON_GPIO_DBCLK_DIV_CON_SHIFT (0U) 4992 #define GPIO_DBCLK_DIV_CON_GPIO_DBCLK_DIV_CON_MASK (0xFFFFFFU << GPIO_DBCLK_DIV_CON_GPIO_DBCLK_DIV_CON_SHIFT) 4993 /* INT_STATUS */ 4994 #define GPIO_INT_STATUS_OFFSET (0x50U) 4995 #define GPIO_INT_STATUS (0x0U) 4996 #define GPIO_INT_STATUS_GPIO_INT_STATUS_SHIFT (0U) 4997 #define GPIO_INT_STATUS_GPIO_INT_STATUS_MASK (0xFFFFFFFFU << GPIO_INT_STATUS_GPIO_INT_STATUS_SHIFT) 4998 /* INT_RAWSTATUS */ 4999 #define GPIO_INT_RAWSTATUS_OFFSET (0x58U) 5000 #define GPIO_INT_RAWSTATUS (0x0U) 5001 #define GPIO_INT_RAWSTATUS_GPIO_INT_RAWSTATUS_SHIFT (0U) 5002 #define GPIO_INT_RAWSTATUS_GPIO_INT_RAWSTATUS_MASK \ 5003 (0xFFFFFFFFU << GPIO_INT_RAWSTATUS_GPIO_INT_RAWSTATUS_SHIFT) 5004 /* PORT_EOI_L */ 5005 #define GPIO_PORT_EOI_L_OFFSET (0x60U) 5006 #define GPIO_PORT_EOI_L_GPIO_PORT_EOI_LOW_SHIFT (0U) 5007 #define GPIO_PORT_EOI_L_GPIO_PORT_EOI_LOW_MASK (0xFFFFU << GPIO_PORT_EOI_L_GPIO_PORT_EOI_LOW_SHIFT) 5008 /* PORT_EOI_H */ 5009 #define GPIO_PORT_EOI_H_OFFSET (0x64U) 5010 #define GPIO_PORT_EOI_H_GPIO_PORT_EOI_HIGH_SHIFT (0U) 5011 #define GPIO_PORT_EOI_H_GPIO_PORT_EOI_HIGH_MASK (0xFFFFU << GPIO_PORT_EOI_H_GPIO_PORT_EOI_HIGH_SHIFT) 5012 /* EXT_PORT */ 5013 #define GPIO_EXT_PORT_OFFSET (0x70U) 5014 #define GPIO_EXT_PORT (0x0U) 5015 #define GPIO_EXT_PORT_GPIO_EXT_PORT_SHIFT (0U) 5016 #define GPIO_EXT_PORT_GPIO_EXT_PORT_MASK (0xFFFFFFFFU << GPIO_EXT_PORT_GPIO_EXT_PORT_SHIFT) 5017 /* VER_ID */ 5018 #define GPIO_VER_ID_OFFSET (0x78U) 5019 #define GPIO_VER_ID (0x1000C2BU) 5020 #define GPIO_VER_ID_GPIO_VER_ID_SHIFT (0U) 5021 #define GPIO_VER_ID_GPIO_VER_ID_MASK (0xFFFFFFFFU << GPIO_VER_ID_GPIO_VER_ID_SHIFT) 5022 /****************************************ACDCDIG*****************************************/ 5023 /* SYSCTRL0 */ 5024 #define ACDCDIG_SYSCTRL0_OFFSET (0x0U) 5025 #define ACDCDIG_SYSCTRL0_SYNC_SEL_SHIFT (1U) 5026 #define ACDCDIG_SYSCTRL0_SYNC_SEL_MASK (0x1U << ACDCDIG_SYSCTRL0_SYNC_SEL_SHIFT) 5027 #define ACDCDIG_SYSCTRL0_CLK_SEL_SHIFT (2U) 5028 #define ACDCDIG_SYSCTRL0_CLK_SEL_MASK (0x1U << ACDCDIG_SYSCTRL0_CLK_SEL_SHIFT) 5029 #define ACDCDIG_SYSCTRL0_GLB_CKE_SHIFT (3U) 5030 #define ACDCDIG_SYSCTRL0_GLB_CKE_MASK (0x1U << ACDCDIG_SYSCTRL0_GLB_CKE_SHIFT) 5031 /* ADCVUCTL */ 5032 #define ACDCDIG_ADCVUCTL_OFFSET (0x40U) 5033 #define ACDCDIG_ADCVUCTL_ADC_ZDT_SHIFT (0U) 5034 #define ACDCDIG_ADCVUCTL_ADC_ZDT_MASK (0x1U << ACDCDIG_ADCVUCTL_ADC_ZDT_SHIFT) 5035 #define ACDCDIG_ADCVUCTL_ADC_FADE_SHIFT (1U) 5036 #define ACDCDIG_ADCVUCTL_ADC_FADE_MASK (0x1U << ACDCDIG_ADCVUCTL_ADC_FADE_SHIFT) 5037 #define ACDCDIG_ADCVUCTL_ADC_BYPS_SHIFT (2U) 5038 #define ACDCDIG_ADCVUCTL_ADC_BYPS_MASK (0x1U << ACDCDIG_ADCVUCTL_ADC_BYPS_SHIFT) 5039 /* ADCVUCTIME */ 5040 #define ACDCDIG_ADCVUCTIME_OFFSET (0x44U) 5041 #define ACDCDIG_ADCVUCTIME_ADC_VUCT_SHIFT (0U) 5042 #define ACDCDIG_ADCVUCTIME_ADC_VUCT_MASK (0xFFU << ACDCDIG_ADCVUCTIME_ADC_VUCT_SHIFT) 5043 /* ADCDIGEN */ 5044 #define ACDCDIG_ADCDIGEN_OFFSET (0x48U) 5045 #define ACDCDIG_ADCDIGEN_ADCEN_L0R1_SHIFT (0U) 5046 #define ACDCDIG_ADCDIGEN_ADCEN_L0R1_MASK (0x1U << ACDCDIG_ADCDIGEN_ADCEN_L0R1_SHIFT) 5047 #define ACDCDIG_ADCDIGEN_ADCEN_L2_SHIFT (1U) 5048 #define ACDCDIG_ADCDIGEN_ADCEN_L2_MASK (0x1U << ACDCDIG_ADCDIGEN_ADCEN_L2_SHIFT) 5049 #define ACDCDIG_ADCDIGEN_ADC_GLBEN_SHIFT (4U) 5050 #define ACDCDIG_ADCDIGEN_ADC_GLBEN_MASK (0x1U << ACDCDIG_ADCDIGEN_ADC_GLBEN_SHIFT) 5051 /* ADCCLKCTRL */ 5052 #define ACDCDIG_ADCCLKCTRL_OFFSET (0x4CU) 5053 #define ACDCDIG_ADCCLKCTRL_ADC_SYNC_STATUS_SHIFT (0U) 5054 #define ACDCDIG_ADCCLKCTRL_ADC_SYNC_STATUS_MASK (0x1U << ACDCDIG_ADCCLKCTRL_ADC_SYNC_STATUS_SHIFT) 5055 #define ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_SHIFT (1U) 5056 #define ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_MASK (0x1U << ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_SHIFT) 5057 #define ACDCDIG_ADCCLKCTRL_FILTER_GATE_EN_SHIFT (2U) 5058 #define ACDCDIG_ADCCLKCTRL_FILTER_GATE_EN_MASK (0x1U << ACDCDIG_ADCCLKCTRL_FILTER_GATE_EN_SHIFT) 5059 #define ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_SHIFT (3U) 5060 #define ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_MASK (0x1U << ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_SHIFT) 5061 #define ACDCDIG_ADCCLKCTRL_I2STX_CKE_SHIFT (4U) 5062 #define ACDCDIG_ADCCLKCTRL_I2STX_CKE_MASK (0x1U << ACDCDIG_ADCCLKCTRL_I2STX_CKE_SHIFT) 5063 #define ACDCDIG_ADCCLKCTRL_ADC_CKE_SHIFT (5U) 5064 #define ACDCDIG_ADCCLKCTRL_ADC_CKE_MASK (0x1U << ACDCDIG_ADCCLKCTRL_ADC_CKE_SHIFT) 5065 #define ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_SHIFT (6U) 5066 #define ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_MASK (0x3U << ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_SHIFT) 5067 /* ADCINT_DIV */ 5068 #define ACDCDIG_ADCINT_DIV_OFFSET (0x54U) 5069 #define ACDCDIG_ADCINT_DIV_INT_DIV_CON_SHIFT (0U) 5070 #define ACDCDIG_ADCINT_DIV_INT_DIV_CON_MASK (0xFFU << ACDCDIG_ADCINT_DIV_INT_DIV_CON_SHIFT) 5071 /* ADCSCLKTXINT_DIV */ 5072 #define ACDCDIG_ADCSCLKTXINT_DIV_OFFSET (0x6CU) 5073 #define ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV_SHIFT (0U) 5074 #define ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV_MASK (0xFFU << ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV_SHIFT) 5075 /* ADCCFG1 */ 5076 #define ACDCDIG_ADCCFG1_OFFSET (0x84U) 5077 #define ACDCDIG_ADCCFG1_FIR_COM_BPS_SHIFT (0U) 5078 #define ACDCDIG_ADCCFG1_FIR_COM_BPS_MASK (0x1U << ACDCDIG_ADCCFG1_FIR_COM_BPS_SHIFT) 5079 #define ACDCDIG_ADCCFG1_SIG_SCALE_MODE_SHIFT (1U) 5080 #define ACDCDIG_ADCCFG1_SIG_SCALE_MODE_MASK (0x1U << ACDCDIG_ADCCFG1_SIG_SCALE_MODE_SHIFT) 5081 #define ACDCDIG_ADCCFG1_ADCSRT_SHIFT (2U) 5082 #define ACDCDIG_ADCCFG1_ADCSRT_MASK (0x7U << ACDCDIG_ADCCFG1_ADCSRT_SHIFT) 5083 /* ADCVOLL0 */ 5084 #define ACDCDIG_ADCVOLL0_OFFSET (0x88U) 5085 #define ACDCDIG_ADCVOLL0_ADCLV0_SHIFT (0U) 5086 #define ACDCDIG_ADCVOLL0_ADCLV0_MASK (0xFFU << ACDCDIG_ADCVOLL0_ADCLV0_SHIFT) 5087 /* ADCVOLL1 */ 5088 #define ACDCDIG_ADCVOLL1_OFFSET (0x8CU) 5089 #define ACDCDIG_ADCVOLL1_ADCLV1_SHIFT (0U) 5090 #define ACDCDIG_ADCVOLL1_ADCLV1_MASK (0xFFU << ACDCDIG_ADCVOLL1_ADCLV1_SHIFT) 5091 /* ADCVOLR0 */ 5092 #define ACDCDIG_ADCVOLR0_OFFSET (0x98U) 5093 #define ACDCDIG_ADCVOLR0_ADCRV0_SHIFT (0U) 5094 #define ACDCDIG_ADCVOLR0_ADCRV0_MASK (0xFFU << ACDCDIG_ADCVOLR0_ADCRV0_SHIFT) 5095 /* ADCVOGP */ 5096 #define ACDCDIG_ADCVOGP_OFFSET (0xA8U) 5097 #define ACDCDIG_ADCVOGP_VOLGPL0_SHIFT (0U) 5098 #define ACDCDIG_ADCVOGP_VOLGPL0_MASK (0x1U << ACDCDIG_ADCVOGP_VOLGPL0_SHIFT) 5099 #define ACDCDIG_ADCVOGP_VOLGPR1_SHIFT (1U) 5100 #define ACDCDIG_ADCVOGP_VOLGPR1_MASK (0x1U << ACDCDIG_ADCVOGP_VOLGPR1_SHIFT) 5101 #define ACDCDIG_ADCVOGP_VOLGPL2_SHIFT (2U) 5102 #define ACDCDIG_ADCVOGP_VOLGPL2_MASK (0x1U << ACDCDIG_ADCVOGP_VOLGPL2_SHIFT) 5103 /* ADCRVOLL0 */ 5104 #define ACDCDIG_ADCRVOLL0_OFFSET (0xACU) 5105 #define ACDCDIG_ADCRVOLL0 (0xFFU) 5106 #define ACDCDIG_ADCRVOLL0_RVOLL0_SHIFT (0U) 5107 #define ACDCDIG_ADCRVOLL0_RVOLL0_MASK (0xFFU << ACDCDIG_ADCRVOLL0_RVOLL0_SHIFT) 5108 /* ADCRVOLL1 */ 5109 #define ACDCDIG_ADCRVOLL1_OFFSET (0xB0U) 5110 #define ACDCDIG_ADCRVOLL1 (0xFFU) 5111 #define ACDCDIG_ADCRVOLL1_RVOLL1_SHIFT (0U) 5112 #define ACDCDIG_ADCRVOLL1_RVOLL1_MASK (0xFFU << ACDCDIG_ADCRVOLL1_RVOLL1_SHIFT) 5113 /* ADCRVOLR0 */ 5114 #define ACDCDIG_ADCRVOLR0_OFFSET (0xBCU) 5115 #define ACDCDIG_ADCRVOLR0 (0xFFU) 5116 #define ACDCDIG_ADCRVOLR0_RVOLR0_SHIFT (0U) 5117 #define ACDCDIG_ADCRVOLR0_RVOLR0_MASK (0xFFU << ACDCDIG_ADCRVOLR0_RVOLR0_SHIFT) 5118 /* ADCALC0 */ 5119 #define ACDCDIG_ADCALC0_OFFSET (0xCCU) 5120 #define ACDCDIG_ADCALC0_ALCL0_SHIFT (0U) 5121 #define ACDCDIG_ADCALC0_ALCL0_MASK (0x1U << ACDCDIG_ADCALC0_ALCL0_SHIFT) 5122 #define ACDCDIG_ADCALC0_ALCR1_SHIFT (1U) 5123 #define ACDCDIG_ADCALC0_ALCR1_MASK (0x1U << ACDCDIG_ADCALC0_ALCR1_SHIFT) 5124 #define ACDCDIG_ADCALC0_ALCL2_SHIFT (2U) 5125 #define ACDCDIG_ADCALC0_ALCL2_MASK (0x1U << ACDCDIG_ADCALC0_ALCL2_SHIFT) 5126 /* ADCALC1 */ 5127 #define ACDCDIG_ADCALC1_OFFSET (0xD0U) 5128 #define ACDCDIG_ADCALC1_ALCRRATE_SHIFT (0U) 5129 #define ACDCDIG_ADCALC1_ALCRRATE_MASK (0xFU << ACDCDIG_ADCALC1_ALCRRATE_SHIFT) 5130 #define ACDCDIG_ADCALC1_ALCARATE_SHIFT (4U) 5131 #define ACDCDIG_ADCALC1_ALCARATE_MASK (0xFU << ACDCDIG_ADCALC1_ALCARATE_SHIFT) 5132 /* ADCALC2 */ 5133 #define ACDCDIG_ADCALC2_OFFSET (0xD4U) 5134 #define ACDCDIG_ADCALC2_ALCMIN_SHIFT (0U) 5135 #define ACDCDIG_ADCALC2_ALCMIN_MASK (0x7U << ACDCDIG_ADCALC2_ALCMIN_SHIFT) 5136 #define ACDCDIG_ADCALC2_ALCMAX_SHIFT (4U) 5137 #define ACDCDIG_ADCALC2_ALCMAX_MASK (0x7U << ACDCDIG_ADCALC2_ALCMAX_SHIFT) 5138 /* ADCNG */ 5139 #define ACDCDIG_ADCNG_OFFSET (0xD8U) 5140 #define ACDCDIG_ADCNG_NGDLY_SHIFT (0U) 5141 #define ACDCDIG_ADCNG_NGDLY_MASK (0x3U << ACDCDIG_ADCNG_NGDLY_SHIFT) 5142 #define ACDCDIG_ADCNG_NGGATE_SHIFT (2U) 5143 #define ACDCDIG_ADCNG_NGGATE_MASK (0x7U << ACDCDIG_ADCNG_NGGATE_SHIFT) 5144 #define ACDCDIG_ADCNG_NGBOOST_SHIFT (5U) 5145 #define ACDCDIG_ADCNG_NGBOOST_MASK (0x1U << ACDCDIG_ADCNG_NGBOOST_SHIFT) 5146 #define ACDCDIG_ADCNG_NGEN_SHIFT (6U) 5147 #define ACDCDIG_ADCNG_NGEN_MASK (0x1U << ACDCDIG_ADCNG_NGEN_SHIFT) 5148 #define ACDCDIG_ADCNG_NGCHL_SHIFT (7U) 5149 #define ACDCDIG_ADCNG_NGCHL_MASK (0x1U << ACDCDIG_ADCNG_NGCHL_SHIFT) 5150 /* ADCNGST */ 5151 #define ACDCDIG_ADCNGST_OFFSET (0xDCU) 5152 #define ACDCDIG_ADCNGST (0x0U) 5153 #define ACDCDIG_ADCNGST_NGSTL0R1_SHIFT (0U) 5154 #define ACDCDIG_ADCNGST_NGSTL0R1_MASK (0x1U << ACDCDIG_ADCNGST_NGSTL0R1_SHIFT) 5155 #define ACDCDIG_ADCNGST_NGSTL2_SHIFT (1U) 5156 #define ACDCDIG_ADCNGST_NGSTL2_MASK (0x1U << ACDCDIG_ADCNGST_NGSTL2_SHIFT) 5157 /* ADCHPFEN */ 5158 #define ACDCDIG_ADCHPFEN_OFFSET (0xE0U) 5159 #define ACDCDIG_ADCHPFEN_HPFEN_L0_SHIFT (0U) 5160 #define ACDCDIG_ADCHPFEN_HPFEN_L0_MASK (0x1U << ACDCDIG_ADCHPFEN_HPFEN_L0_SHIFT) 5161 #define ACDCDIG_ADCHPFEN_HPFEN_R1_SHIFT (1U) 5162 #define ACDCDIG_ADCHPFEN_HPFEN_R1_MASK (0x1U << ACDCDIG_ADCHPFEN_HPFEN_R1_SHIFT) 5163 #define ACDCDIG_ADCHPFEN_HPFEN_L2_SHIFT (2U) 5164 #define ACDCDIG_ADCHPFEN_HPFEN_L2_MASK (0x1U << ACDCDIG_ADCHPFEN_HPFEN_L2_SHIFT) 5165 /* ADCHPFCF */ 5166 #define ACDCDIG_ADCHPFCF_OFFSET (0xE4U) 5167 #define ACDCDIG_ADCHPFCF_HPFCF_SHIFT (0U) 5168 #define ACDCDIG_ADCHPFCF_HPFCF_MASK (0x3U << ACDCDIG_ADCHPFCF_HPFCF_SHIFT) 5169 /* ADCPGL0 */ 5170 #define ACDCDIG_ADCPGL0_OFFSET (0xECU) 5171 #define ACDCDIG_ADCPGL0_PGA_L0_SHIFT (0U) 5172 #define ACDCDIG_ADCPGL0_PGA_L0_MASK (0xFU << ACDCDIG_ADCPGL0_PGA_L0_SHIFT) 5173 /* ADCPGL1 */ 5174 #define ACDCDIG_ADCPGL1_OFFSET (0xF0U) 5175 #define ACDCDIG_ADCPGL1_PGA_L1_SHIFT (0U) 5176 #define ACDCDIG_ADCPGL1_PGA_L1_MASK (0xFU << ACDCDIG_ADCPGL1_PGA_L1_SHIFT) 5177 /* ADCPGR0 */ 5178 #define ACDCDIG_ADCPGR0_OFFSET (0xFCU) 5179 #define ACDCDIG_ADCPGR0_PGA_R0_SHIFT (0U) 5180 #define ACDCDIG_ADCPGR0_PGA_R0_MASK (0xFU << ACDCDIG_ADCPGR0_PGA_R0_SHIFT) 5181 /* ADCLILMT1 */ 5182 #define ACDCDIG_ADCLILMT1_OFFSET (0x10CU) 5183 #define ACDCDIG_ADCLILMT1_MIN_LILMT_SHIFT (0U) 5184 #define ACDCDIG_ADCLILMT1_MIN_LILMT_MASK (0x7U << ACDCDIG_ADCLILMT1_MIN_LILMT_SHIFT) 5185 #define ACDCDIG_ADCLILMT1_MAX_LILMT_SHIFT (4U) 5186 #define ACDCDIG_ADCLILMT1_MAX_LILMT_MASK (0x7U << ACDCDIG_ADCLILMT1_MAX_LILMT_SHIFT) 5187 #define ACDCDIG_ADCLILMT1_LMT_EN_SHIFT (7U) 5188 #define ACDCDIG_ADCLILMT1_LMT_EN_MASK (0x1U << ACDCDIG_ADCLILMT1_LMT_EN_SHIFT) 5189 /* ADCLILMT2 */ 5190 #define ACDCDIG_ADCLILMT2_OFFSET (0x110U) 5191 #define ACDCDIG_ADCLILMT2_RLS_RATE_SHIFT (0U) 5192 #define ACDCDIG_ADCLILMT2_RLS_RATE_MASK (0xFU << ACDCDIG_ADCLILMT2_RLS_RATE_SHIFT) 5193 #define ACDCDIG_ADCLILMT2_ATK_RATE_SHIFT (4U) 5194 #define ACDCDIG_ADCLILMT2_ATK_RATE_MASK (0xFU << ACDCDIG_ADCLILMT2_ATK_RATE_SHIFT) 5195 /* ADCDMICNG1 */ 5196 #define ACDCDIG_ADCDMICNG1_OFFSET (0x114U) 5197 #define ACDCDIG_ADCDMICNG1_NGDLY_LI_SHIFT (0U) 5198 #define ACDCDIG_ADCDMICNG1_NGDLY_LI_MASK (0x3U << ACDCDIG_ADCDMICNG1_NGDLY_LI_SHIFT) 5199 #define ACDCDIG_ADCDMICNG1_NGGATE_LI_SHIFT (2U) 5200 #define ACDCDIG_ADCDMICNG1_NGGATE_LI_MASK (0x7U << ACDCDIG_ADCDMICNG1_NGGATE_LI_SHIFT) 5201 #define ACDCDIG_ADCDMICNG1_NGBOOST_LI_SHIFT (5U) 5202 #define ACDCDIG_ADCDMICNG1_NGBOOST_LI_MASK (0x1U << ACDCDIG_ADCDMICNG1_NGBOOST_LI_SHIFT) 5203 #define ACDCDIG_ADCDMICNG1_NGEN_LI_SHIFT (6U) 5204 #define ACDCDIG_ADCDMICNG1_NGEN_LI_MASK (0x1U << ACDCDIG_ADCDMICNG1_NGEN_LI_SHIFT) 5205 #define ACDCDIG_ADCDMICNG1_NGCHL_LI_SHIFT (7U) 5206 #define ACDCDIG_ADCDMICNG1_NGCHL_LI_MASK (0x1U << ACDCDIG_ADCDMICNG1_NGCHL_LI_SHIFT) 5207 /* ADCDMICNG2 */ 5208 #define ACDCDIG_ADCDMICNG2_OFFSET (0x118U) 5209 #define ACDCDIG_ADCDMICNG2 (0x0U) 5210 #define ACDCDIG_ADCDMICNG2_NGVALID_LI_L0R1_SHIFT (0U) 5211 #define ACDCDIG_ADCDMICNG2_NGVALID_LI_L0R1_MASK (0x1U << ACDCDIG_ADCDMICNG2_NGVALID_LI_L0R1_SHIFT) 5212 #define ACDCDIG_ADCDMICNG2_NGVALID_LI_L2_SHIFT (1U) 5213 #define ACDCDIG_ADCDMICNG2_NGVALID_LI_L2_MASK (0x1U << ACDCDIG_ADCDMICNG2_NGVALID_LI_L2_SHIFT) 5214 /* DACVUCTL */ 5215 #define ACDCDIG_DACVUCTL_OFFSET (0x140U) 5216 #define ACDCDIG_DACVUCTL_DAC_ZDT_SHIFT (0U) 5217 #define ACDCDIG_DACVUCTL_DAC_ZDT_MASK (0x1U << ACDCDIG_DACVUCTL_DAC_ZDT_SHIFT) 5218 #define ACDCDIG_DACVUCTL_DAC_FADE_SHIFT (1U) 5219 #define ACDCDIG_DACVUCTL_DAC_FADE_MASK (0x1U << ACDCDIG_DACVUCTL_DAC_FADE_SHIFT) 5220 #define ACDCDIG_DACVUCTL_DAC_BYPS_SHIFT (2U) 5221 #define ACDCDIG_DACVUCTL_DAC_BYPS_MASK (0x1U << ACDCDIG_DACVUCTL_DAC_BYPS_SHIFT) 5222 /* DACVUCTIME */ 5223 #define ACDCDIG_DACVUCTIME_OFFSET (0x144U) 5224 #define ACDCDIG_DACVUCTIME_DAC_VUCT_SHIFT (0U) 5225 #define ACDCDIG_DACVUCTIME_DAC_VUCT_MASK (0xFFU << ACDCDIG_DACVUCTIME_DAC_VUCT_SHIFT) 5226 /* DACDIGEN */ 5227 #define ACDCDIG_DACDIGEN_OFFSET (0x148U) 5228 #define ACDCDIG_DACDIGEN_DACEN_L0_SHIFT (0U) 5229 #define ACDCDIG_DACDIGEN_DACEN_L0_MASK (0x1U << ACDCDIG_DACDIGEN_DACEN_L0_SHIFT) 5230 #define ACDCDIG_DACDIGEN_DAC_GLBEN_SHIFT (4U) 5231 #define ACDCDIG_DACDIGEN_DAC_GLBEN_MASK (0x1U << ACDCDIG_DACDIGEN_DAC_GLBEN_SHIFT) 5232 /* DACCLKCTRL */ 5233 #define ACDCDIG_DACCLKCTRL_OFFSET (0x14CU) 5234 #define ACDCDIG_DACCLKCTRL_DAC_SYNC_STATUS_SHIFT (1U) 5235 #define ACDCDIG_DACCLKCTRL_DAC_SYNC_STATUS_MASK (0x1U << ACDCDIG_DACCLKCTRL_DAC_SYNC_STATUS_SHIFT) 5236 #define ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_SHIFT (2U) 5237 #define ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_MASK (0x1U << ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_SHIFT) 5238 #define ACDCDIG_DACCLKCTRL_CKE_BCLKRX_SHIFT (3U) 5239 #define ACDCDIG_DACCLKCTRL_CKE_BCLKRX_MASK (0x1U << ACDCDIG_DACCLKCTRL_CKE_BCLKRX_SHIFT) 5240 #define ACDCDIG_DACCLKCTRL_I2SRX_CKE_SHIFT (4U) 5241 #define ACDCDIG_DACCLKCTRL_I2SRX_CKE_MASK (0x1U << ACDCDIG_DACCLKCTRL_I2SRX_CKE_SHIFT) 5242 #define ACDCDIG_DACCLKCTRL_DAC_CKE_SHIFT (5U) 5243 #define ACDCDIG_DACCLKCTRL_DAC_CKE_MASK (0x1U << ACDCDIG_DACCLKCTRL_DAC_CKE_SHIFT) 5244 /* DACINT_DIV */ 5245 #define ACDCDIG_DACINT_DIV_OFFSET (0x154U) 5246 #define ACDCDIG_DACINT_DIV_INT_DIV_CON_SHIFT (0U) 5247 #define ACDCDIG_DACINT_DIV_INT_DIV_CON_MASK (0xFFU << ACDCDIG_DACINT_DIV_INT_DIV_CON_SHIFT) 5248 /* DACSCLKRXINT_DIV */ 5249 #define ACDCDIG_DACSCLKRXINT_DIV_OFFSET (0x16CU) 5250 #define ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV_SHIFT (0U) 5251 #define ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV_MASK (0xFFU << ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV_SHIFT) 5252 /* DACCFG1 */ 5253 #define ACDCDIG_DACCFG1_OFFSET (0x184U) 5254 #define ACDCDIG_DACCFG1_DACSRT_SHIFT (2U) 5255 #define ACDCDIG_DACCFG1_DACSRT_MASK (0x7U << ACDCDIG_DACCFG1_DACSRT_SHIFT) 5256 /* DACMUTE */ 5257 #define ACDCDIG_DACMUTE_OFFSET (0x188U) 5258 #define ACDCDIG_DACMUTE_DACMT_SHIFT (0U) 5259 #define ACDCDIG_DACMUTE_DACMT_MASK (0x1U << ACDCDIG_DACMUTE_DACMT_SHIFT) 5260 #define ACDCDIG_DACMUTE_DACUNMT_SHIFT (1U) 5261 #define ACDCDIG_DACMUTE_DACUNMT_MASK (0x1U << ACDCDIG_DACMUTE_DACUNMT_SHIFT) 5262 /* DACMUTEST */ 5263 #define ACDCDIG_DACMUTEST_OFFSET (0x18CU) 5264 #define ACDCDIG_DACMUTEST (0x0U) 5265 #define ACDCDIG_DACMUTEST_MUTEST_L0_SHIFT (0U) 5266 #define ACDCDIG_DACMUTEST_MUTEST_L0_MASK (0x1U << ACDCDIG_DACMUTEST_MUTEST_L0_SHIFT) 5267 #define ACDCDIG_DACMUTEST_UNMUTEST_L0_SHIFT (4U) 5268 #define ACDCDIG_DACMUTEST_UNMUTEST_L0_MASK (0x1U << ACDCDIG_DACMUTEST_UNMUTEST_L0_SHIFT) 5269 /* DACVOLL0 */ 5270 #define ACDCDIG_DACVOLL0_OFFSET (0x190U) 5271 #define ACDCDIG_DACVOLL0_DACLV0_SHIFT (0U) 5272 #define ACDCDIG_DACVOLL0_DACLV0_MASK (0xFFU << ACDCDIG_DACVOLL0_DACLV0_SHIFT) 5273 /* DACVOGP */ 5274 #define ACDCDIG_DACVOGP_OFFSET (0x1B0U) 5275 #define ACDCDIG_DACVOGP_VOLGPL0_SHIFT (0U) 5276 #define ACDCDIG_DACVOGP_VOLGPL0_MASK (0x1U << ACDCDIG_DACVOGP_VOLGPL0_SHIFT) 5277 /* DACRVOLL0 */ 5278 #define ACDCDIG_DACRVOLL0_OFFSET (0x1B4U) 5279 #define ACDCDIG_DACRVOLL0 (0xFFU) 5280 #define ACDCDIG_DACRVOLL0_RVOLL0_SHIFT (0U) 5281 #define ACDCDIG_DACRVOLL0_RVOLL0_MASK (0xFFU << ACDCDIG_DACRVOLL0_RVOLL0_SHIFT) 5282 /* DACLMT0 */ 5283 #define ACDCDIG_DACLMT0_OFFSET (0x1D4U) 5284 #define ACDCDIG_DACLMT0_LIMDCT_SHIFT (0U) 5285 #define ACDCDIG_DACLMT0_LIMDCT_MASK (0x1U << ACDCDIG_DACLMT0_LIMDCT_SHIFT) 5286 #define ACDCDIG_DACLMT0_LIMEN_SHIFT (1U) 5287 #define ACDCDIG_DACLMT0_LIMEN_MASK (0x1U << ACDCDIG_DACLMT0_LIMEN_SHIFT) 5288 /* DACLMT1 */ 5289 #define ACDCDIG_DACLMT1_OFFSET (0x1D8U) 5290 #define ACDCDIG_DACLMT1_RLS_RATE_SHIFT (0U) 5291 #define ACDCDIG_DACLMT1_RLS_RATE_MASK (0xFU << ACDCDIG_DACLMT1_RLS_RATE_SHIFT) 5292 #define ACDCDIG_DACLMT1_ATK_RATE_SHIFT (4U) 5293 #define ACDCDIG_DACLMT1_ATK_RATE_MASK (0xFU << ACDCDIG_DACLMT1_ATK_RATE_SHIFT) 5294 /* DACLMT2 */ 5295 #define ACDCDIG_DACLMT2_OFFSET (0x1DCU) 5296 #define ACDCDIG_DACLMT2_MIN_LILMT_SHIFT (0U) 5297 #define ACDCDIG_DACLMT2_MIN_LILMT_MASK (0x7U << ACDCDIG_DACLMT2_MIN_LILMT_SHIFT) 5298 #define ACDCDIG_DACLMT2_MAX_LILMT_SHIFT (4U) 5299 #define ACDCDIG_DACLMT2_MAX_LILMT_MASK (0x7U << ACDCDIG_DACLMT2_MAX_LILMT_SHIFT) 5300 /* DACMIXCTRLL */ 5301 #define ACDCDIG_DACMIXCTRLL_OFFSET (0x1E0U) 5302 #define ACDCDIG_DACMIXCTRLL_MIXMODE_L0_SHIFT (0U) 5303 #define ACDCDIG_DACMIXCTRLL_MIXMODE_L0_MASK (0x3U << ACDCDIG_DACMIXCTRLL_MIXMODE_L0_SHIFT) 5304 /* DACHPF */ 5305 #define ACDCDIG_DACHPF_OFFSET (0x1E8U) 5306 #define ACDCDIG_DACHPF_HPFEN_L0_SHIFT (0U) 5307 #define ACDCDIG_DACHPF_HPFEN_L0_MASK (0x1U << ACDCDIG_DACHPF_HPFEN_L0_SHIFT) 5308 #define ACDCDIG_DACHPF_HPFCF_SHIFT (4U) 5309 #define ACDCDIG_DACHPF_HPFCF_MASK (0x3U << ACDCDIG_DACHPF_HPFCF_SHIFT) 5310 /* I2C_FLT_CON0 */ 5311 #define ACDCDIG_I2C_FLT_CON0_OFFSET (0x280U) 5312 #define ACDCDIG_I2C_FLT_CON0_FLT_F_SHIFT (0U) 5313 #define ACDCDIG_I2C_FLT_CON0_FLT_F_MASK (0xFU << ACDCDIG_I2C_FLT_CON0_FLT_F_SHIFT) 5314 #define ACDCDIG_I2C_FLT_CON0_FLT_R_SHIFT (4U) 5315 #define ACDCDIG_I2C_FLT_CON0_FLT_R_MASK (0xFU << ACDCDIG_I2C_FLT_CON0_FLT_R_SHIFT) 5316 /* I2C_FLT_CON1 */ 5317 #define ACDCDIG_I2C_FLT_CON1_OFFSET (0x284U) 5318 #define ACDCDIG_I2C_FLT_CON1_SLV_HOLD_SCL_TH_SHIFT (0U) 5319 #define ACDCDIG_I2C_FLT_CON1_SLV_HOLD_SCL_TH_MASK (0xFU << ACDCDIG_I2C_FLT_CON1_SLV_HOLD_SCL_TH_SHIFT) 5320 #define ACDCDIG_I2C_FLT_CON1_FLT_EN_SHIFT (4U) 5321 #define ACDCDIG_I2C_FLT_CON1_FLT_EN_MASK (0x1U << ACDCDIG_I2C_FLT_CON1_FLT_EN_SHIFT) 5322 #define ACDCDIG_I2C_FLT_CON1_NAK_RELEASE_SCL_SHIFT (5U) 5323 #define ACDCDIG_I2C_FLT_CON1_NAK_RELEASE_SCL_MASK (0x1U << ACDCDIG_I2C_FLT_CON1_NAK_RELEASE_SCL_SHIFT) 5324 #define ACDCDIG_I2C_FLT_CON1_H0_CHECK_SCL_SHIFT (6U) 5325 #define ACDCDIG_I2C_FLT_CON1_H0_CHECK_SCL_MASK (0x1U << ACDCDIG_I2C_FLT_CON1_H0_CHECK_SCL_SHIFT) 5326 /* I2C_CON0 */ 5327 #define ACDCDIG_I2C_CON0_OFFSET (0x288U) 5328 #define ACDCDIG_I2C_CON0_I2C_EN_SHIFT (0U) 5329 #define ACDCDIG_I2C_CON0_I2C_EN_MASK (0x1U << ACDCDIG_I2C_CON0_I2C_EN_SHIFT) 5330 #define ACDCDIG_I2C_CON0_I2C_MODE_SHIFT (1U) 5331 #define ACDCDIG_I2C_CON0_I2C_MODE_MASK (0x3U << ACDCDIG_I2C_CON0_I2C_MODE_SHIFT) 5332 #define ACDCDIG_I2C_CON0_ACT2NAK_SHIFT (6U) 5333 #define ACDCDIG_I2C_CON0_ACT2NAK_MASK (0x1U << ACDCDIG_I2C_CON0_ACT2NAK_SHIFT) 5334 /* I2C_CON1 */ 5335 #define ACDCDIG_I2C_CON1_OFFSET (0x28CU) 5336 #define ACDCDIG_I2C_CON1_DATA_UPD_ST_SHIFT (0U) 5337 #define ACDCDIG_I2C_CON1_DATA_UPD_ST_MASK (0xFU << ACDCDIG_I2C_CON1_DATA_UPD_ST_SHIFT) 5338 #define ACDCDIG_I2C_CON1_START_SETUP_SHIFT (4U) 5339 #define ACDCDIG_I2C_CON1_START_SETUP_MASK (0x3U << ACDCDIG_I2C_CON1_START_SETUP_SHIFT) 5340 #define ACDCDIG_I2C_CON1_STOP_SETUP_SHIFT (6U) 5341 #define ACDCDIG_I2C_CON1_STOP_SETUP_MASK (0x3U << ACDCDIG_I2C_CON1_STOP_SETUP_SHIFT) 5342 /* I2C_CLKDIVL0 */ 5343 #define ACDCDIG_I2C_CLKDIVL0_OFFSET (0x290U) 5344 #define ACDCDIG_I2C_CLKDIVL0_CLKDIVL0_SHIFT (0U) 5345 #define ACDCDIG_I2C_CLKDIVL0_CLKDIVL0_MASK (0xFFU << ACDCDIG_I2C_CLKDIVL0_CLKDIVL0_SHIFT) 5346 /* I2C_CLKDIVL1 */ 5347 #define ACDCDIG_I2C_CLKDIVL1_OFFSET (0x294U) 5348 #define ACDCDIG_I2C_CLKDIVL1_CLKDIVL1_SHIFT (0U) 5349 #define ACDCDIG_I2C_CLKDIVL1_CLKDIVL1_MASK (0xFFU << ACDCDIG_I2C_CLKDIVL1_CLKDIVL1_SHIFT) 5350 /* I2C_CLKDIVH0 */ 5351 #define ACDCDIG_I2C_CLKDIVH0_OFFSET (0x298U) 5352 #define ACDCDIG_I2C_CLKDIVH0_CLKDIVH0_SHIFT (0U) 5353 #define ACDCDIG_I2C_CLKDIVH0_CLKDIVH0_MASK (0xFFU << ACDCDIG_I2C_CLKDIVH0_CLKDIVH0_SHIFT) 5354 /* I2C_CLKDIVH1 */ 5355 #define ACDCDIG_I2C_CLKDIVH1_OFFSET (0x29CU) 5356 #define ACDCDIG_I2C_CLKDIVH1_CLKDIVH1_SHIFT (0U) 5357 #define ACDCDIG_I2C_CLKDIVH1_CLKDIVH1_MASK (0xFFU << ACDCDIG_I2C_CLKDIVH1_CLKDIVH1_SHIFT) 5358 /* I2C_MAXCNT */ 5359 #define ACDCDIG_I2C_MAXCNT_OFFSET (0x2A0U) 5360 #define ACDCDIG_I2C_MAXCNT_MTXCNT_SHIFT (0U) 5361 #define ACDCDIG_I2C_MAXCNT_MTXCNT_MASK (0x3FU << ACDCDIG_I2C_MAXCNT_MTXCNT_SHIFT) 5362 #define ACDCDIG_I2C_MAXCNT_IDLE_SHIFT (7U) 5363 #define ACDCDIG_I2C_MAXCNT_IDLE_MASK (0x1U << ACDCDIG_I2C_MAXCNT_IDLE_SHIFT) 5364 /* I2C_SCLOE_DB0 */ 5365 #define ACDCDIG_I2C_SCLOE_DB0_OFFSET (0x2A4U) 5366 #define ACDCDIG_I2C_SCLOE_DB0_SCLOEDB0_SHIFT (0U) 5367 #define ACDCDIG_I2C_SCLOE_DB0_SCLOEDB0_MASK (0xFFU << ACDCDIG_I2C_SCLOE_DB0_SCLOEDB0_SHIFT) 5368 /* I2C_SCLOE_DB1 */ 5369 #define ACDCDIG_I2C_SCLOE_DB1_OFFSET (0x2A8U) 5370 #define ACDCDIG_I2C_SCLOE_DB1_SCLOEDB1_SHIFT (0U) 5371 #define ACDCDIG_I2C_SCLOE_DB1_SCLOEDB1_MASK (0xFFU << ACDCDIG_I2C_SCLOE_DB1_SCLOEDB1_SHIFT) 5372 /* I2C_SCLOE_DB2 */ 5373 #define ACDCDIG_I2C_SCLOE_DB2_OFFSET (0x2ACU) 5374 #define ACDCDIG_I2C_SCLOE_DB2_SCLOEDB2_SHIFT (0U) 5375 #define ACDCDIG_I2C_SCLOE_DB2_SCLOEDB2_MASK (0xFFU << ACDCDIG_I2C_SCLOE_DB2_SCLOEDB2_SHIFT) 5376 /* I2C_SCLOE_DB3 */ 5377 #define ACDCDIG_I2C_SCLOE_DB3_OFFSET (0x2B0U) 5378 #define ACDCDIG_I2C_SCLOE_DB3_SCLOEDB3_SHIFT (0U) 5379 #define ACDCDIG_I2C_SCLOE_DB3_SCLOEDB3_MASK (0xFFU << ACDCDIG_I2C_SCLOE_DB3_SCLOEDB3_SHIFT) 5380 /* I2C_TMOUTL */ 5381 #define ACDCDIG_I2C_TMOUTL_OFFSET (0x2B4U) 5382 #define ACDCDIG_I2C_TMOUTL_TMOUTL_SHIFT (0U) 5383 #define ACDCDIG_I2C_TMOUTL_TMOUTL_MASK (0xFFU << ACDCDIG_I2C_TMOUTL_TMOUTL_SHIFT) 5384 /* I2C_TMOUTH */ 5385 #define ACDCDIG_I2C_TMOUTH_OFFSET (0x2B8U) 5386 #define ACDCDIG_I2C_TMOUTH_TMOUTH_SHIFT (0U) 5387 #define ACDCDIG_I2C_TMOUTH_TMOUTH_MASK (0xFFU << ACDCDIG_I2C_TMOUTH_TMOUTH_SHIFT) 5388 /* I2C_DEV_ADDR */ 5389 #define ACDCDIG_I2C_DEV_ADDR_OFFSET (0x2BCU) 5390 #define ACDCDIG_I2C_DEV_ADDR_DEV_ADDR_SHIFT (0U) 5391 #define ACDCDIG_I2C_DEV_ADDR_DEV_ADDR_MASK (0xFFU << ACDCDIG_I2C_DEV_ADDR_DEV_ADDR_SHIFT) 5392 /* I2C_REG_ADDR */ 5393 #define ACDCDIG_I2C_REG_ADDR_OFFSET (0x2C0U) 5394 #define ACDCDIG_I2C_REG_ADDR_REGADDR_SHIFT (0U) 5395 #define ACDCDIG_I2C_REG_ADDR_REGADDR_MASK (0xFFU << ACDCDIG_I2C_REG_ADDR_REGADDR_SHIFT) 5396 /* I2C_STATUS */ 5397 #define ACDCDIG_I2C_STATUS_OFFSET (0x2C4U) 5398 #define ACDCDIG_I2C_STATUS_BTFST_SHIFT (0U) 5399 #define ACDCDIG_I2C_STATUS_BTFST_MASK (0x1U << ACDCDIG_I2C_STATUS_BTFST_SHIFT) 5400 #define ACDCDIG_I2C_STATUS_MBTFST_SHIFT (2U) 5401 #define ACDCDIG_I2C_STATUS_MBTFST_MASK (0x1U << ACDCDIG_I2C_STATUS_MBTFST_SHIFT) 5402 #define ACDCDIG_I2C_STATUS_STARTST_SHIFT (4U) 5403 #define ACDCDIG_I2C_STATUS_STARTST_MASK (0x1U << ACDCDIG_I2C_STATUS_STARTST_SHIFT) 5404 #define ACDCDIG_I2C_STATUS_STOPST_SHIFT (5U) 5405 #define ACDCDIG_I2C_STATUS_STOPST_MASK (0x1U << ACDCDIG_I2C_STATUS_STOPST_SHIFT) 5406 #define ACDCDIG_I2C_STATUS_NAKRCVST_SHIFT (6U) 5407 #define ACDCDIG_I2C_STATUS_NAKRCVST_MASK (0x1U << ACDCDIG_I2C_STATUS_NAKRCVST_SHIFT) 5408 #define ACDCDIG_I2C_STATUS_SLAVEHDSCLST_SHIFT (7U) 5409 #define ACDCDIG_I2C_STATUS_SLAVEHDSCLST_MASK (0x1U << ACDCDIG_I2C_STATUS_SLAVEHDSCLST_SHIFT) 5410 /* I2S_TXCR0 */ 5411 #define ACDCDIG_I2S_TXCR0_OFFSET (0x300U) 5412 #define ACDCDIG_I2S_TXCR0_VDW_SHIFT (0U) 5413 #define ACDCDIG_I2S_TXCR0_VDW_MASK (0x1FU << ACDCDIG_I2S_TXCR0_VDW_SHIFT) 5414 #define ACDCDIG_I2S_TXCR0_TFS_SHIFT (5U) 5415 #define ACDCDIG_I2S_TXCR0_TFS_MASK (0x1U << ACDCDIG_I2S_TXCR0_TFS_SHIFT) 5416 #define ACDCDIG_I2S_TXCR0_PBM_SHIFT (6U) 5417 #define ACDCDIG_I2S_TXCR0_PBM_MASK (0x3U << ACDCDIG_I2S_TXCR0_PBM_SHIFT) 5418 /* I2S_TXCR1 */ 5419 #define ACDCDIG_I2S_TXCR1_OFFSET (0x304U) 5420 #define ACDCDIG_I2S_TXCR1_IBM_SHIFT (0U) 5421 #define ACDCDIG_I2S_TXCR1_IBM_MASK (0x3U << ACDCDIG_I2S_TXCR1_IBM_SHIFT) 5422 #define ACDCDIG_I2S_TXCR1_FBM_SHIFT (2U) 5423 #define ACDCDIG_I2S_TXCR1_FBM_MASK (0x1U << ACDCDIG_I2S_TXCR1_FBM_SHIFT) 5424 #define ACDCDIG_I2S_TXCR1_CEX_SHIFT (4U) 5425 #define ACDCDIG_I2S_TXCR1_CEX_MASK (0x1U << ACDCDIG_I2S_TXCR1_CEX_SHIFT) 5426 #define ACDCDIG_I2S_TXCR1_TCSR_SHIFT (6U) 5427 #define ACDCDIG_I2S_TXCR1_TCSR_MASK (0x3U << ACDCDIG_I2S_TXCR1_TCSR_SHIFT) 5428 /* I2S_TXCR2 */ 5429 #define ACDCDIG_I2S_TXCR2_OFFSET (0x308U) 5430 #define ACDCDIG_I2S_TXCR2_RCNT_SHIFT (0U) 5431 #define ACDCDIG_I2S_TXCR2_RCNT_MASK (0x3FU << ACDCDIG_I2S_TXCR2_RCNT_SHIFT) 5432 /* I2S_RXCR0 */ 5433 #define ACDCDIG_I2S_RXCR0_OFFSET (0x30CU) 5434 #define ACDCDIG_I2S_RXCR0_VDW_SHIFT (0U) 5435 #define ACDCDIG_I2S_RXCR0_VDW_MASK (0x1FU << ACDCDIG_I2S_RXCR0_VDW_SHIFT) 5436 #define ACDCDIG_I2S_RXCR0_TFS_SHIFT (5U) 5437 #define ACDCDIG_I2S_RXCR0_TFS_MASK (0x1U << ACDCDIG_I2S_RXCR0_TFS_SHIFT) 5438 #define ACDCDIG_I2S_RXCR0_PBM_SHIFT (6U) 5439 #define ACDCDIG_I2S_RXCR0_PBM_MASK (0x3U << ACDCDIG_I2S_RXCR0_PBM_SHIFT) 5440 /* I2S_RXCR1 */ 5441 #define ACDCDIG_I2S_RXCR1_OFFSET (0x310U) 5442 #define ACDCDIG_I2S_RXCR1_IBM_SHIFT (0U) 5443 #define ACDCDIG_I2S_RXCR1_IBM_MASK (0x3U << ACDCDIG_I2S_RXCR1_IBM_SHIFT) 5444 #define ACDCDIG_I2S_RXCR1_FBM_SHIFT (2U) 5445 #define ACDCDIG_I2S_RXCR1_FBM_MASK (0x1U << ACDCDIG_I2S_RXCR1_FBM_SHIFT) 5446 #define ACDCDIG_I2S_RXCR1_CEX_SHIFT (4U) 5447 #define ACDCDIG_I2S_RXCR1_CEX_MASK (0x1U << ACDCDIG_I2S_RXCR1_CEX_SHIFT) 5448 #define ACDCDIG_I2S_RXCR1_RCSR_SHIFT (6U) 5449 #define ACDCDIG_I2S_RXCR1_RCSR_MASK (0x3U << ACDCDIG_I2S_RXCR1_RCSR_SHIFT) 5450 /* I2S_CKR0 */ 5451 #define ACDCDIG_I2S_CKR0_OFFSET (0x314U) 5452 #define ACDCDIG_I2S_CKR0_TSD_SHIFT (0U) 5453 #define ACDCDIG_I2S_CKR0_TSD_MASK (0x3U << ACDCDIG_I2S_CKR0_TSD_SHIFT) 5454 #define ACDCDIG_I2S_CKR0_RSD_SHIFT (2U) 5455 #define ACDCDIG_I2S_CKR0_RSD_MASK (0x3U << ACDCDIG_I2S_CKR0_RSD_SHIFT) 5456 /* I2S_CKR1 */ 5457 #define ACDCDIG_I2S_CKR1_OFFSET (0x318U) 5458 #define ACDCDIG_I2S_CKR1_TLP_SHIFT (0U) 5459 #define ACDCDIG_I2S_CKR1_TLP_MASK (0x1U << ACDCDIG_I2S_CKR1_TLP_SHIFT) 5460 #define ACDCDIG_I2S_CKR1_RLP_SHIFT (1U) 5461 #define ACDCDIG_I2S_CKR1_RLP_MASK (0x1U << ACDCDIG_I2S_CKR1_RLP_SHIFT) 5462 #define ACDCDIG_I2S_CKR1_CKP_SHIFT (2U) 5463 #define ACDCDIG_I2S_CKR1_CKP_MASK (0x1U << ACDCDIG_I2S_CKR1_CKP_SHIFT) 5464 #define ACDCDIG_I2S_CKR1_MSS_SHIFT (3U) 5465 #define ACDCDIG_I2S_CKR1_MSS_MASK (0x1U << ACDCDIG_I2S_CKR1_MSS_SHIFT) 5466 /* I2S_XFER */ 5467 #define ACDCDIG_I2S_XFER_OFFSET (0x31CU) 5468 #define ACDCDIG_I2S_XFER_TXS_SHIFT (0U) 5469 #define ACDCDIG_I2S_XFER_TXS_MASK (0x1U << ACDCDIG_I2S_XFER_TXS_SHIFT) 5470 #define ACDCDIG_I2S_XFER_RXS_SHIFT (1U) 5471 #define ACDCDIG_I2S_XFER_RXS_MASK (0x1U << ACDCDIG_I2S_XFER_RXS_SHIFT) 5472 /* I2S_CLR */ 5473 #define ACDCDIG_I2S_CLR_OFFSET (0x320U) 5474 #define ACDCDIG_I2S_CLR_TXC_SHIFT (0U) 5475 #define ACDCDIG_I2S_CLR_TXC_MASK (0x1U << ACDCDIG_I2S_CLR_TXC_SHIFT) 5476 #define ACDCDIG_I2S_CLR_RXC_SHIFT (1U) 5477 #define ACDCDIG_I2S_CLR_RXC_MASK (0x1U << ACDCDIG_I2S_CLR_RXC_SHIFT) 5478 /* VERSION */ 5479 #define ACDCDIG_VERSION_OFFSET (0x380U) 5480 #define ACDCDIG_VERSION (0x2U) 5481 #define ACDCDIG_VERSION_VER_SHIFT (0U) 5482 #define ACDCDIG_VERSION_VER_MASK (0xFFU << ACDCDIG_VERSION_VER_SHIFT) 5483 /******************************************GRF*******************************************/ 5484 /* GPIO0A_IOMUX_L */ 5485 #define GRF_GPIO0A_IOMUX_L_OFFSET (0x0U) 5486 #define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT (0U) 5487 #define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT) 5488 #define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT (4U) 5489 #define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT) 5490 #define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT (8U) 5491 #define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT) 5492 #define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT (12U) 5493 #define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT) 5494 /* GPIO0A_IOMUX_H */ 5495 #define GRF_GPIO0A_IOMUX_H_OFFSET (0x4U) 5496 #define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT (0U) 5497 #define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT) 5498 #define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT (4U) 5499 #define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_MASK (0xFU << GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT) 5500 #define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT (8U) 5501 #define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT) 5502 #define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT (12U) 5503 #define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT) 5504 /* GPIO0B_IOMUX_L */ 5505 #define GRF_GPIO0B_IOMUX_L_OFFSET (0x8U) 5506 #define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT (0U) 5507 #define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT) 5508 #define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT (4U) 5509 #define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT) 5510 #define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT (8U) 5511 #define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT) 5512 #define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT (12U) 5513 #define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT) 5514 /* GPIO0B_IOMUX_H */ 5515 #define GRF_GPIO0B_IOMUX_H_OFFSET (0xCU) 5516 #define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT (0U) 5517 #define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_MASK (0xFU << GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT) 5518 #define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT (4U) 5519 #define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT) 5520 #define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT (8U) 5521 #define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT) 5522 #define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT (12U) 5523 #define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT) 5524 /* GPIO0C_IOMUX_L */ 5525 #define GRF_GPIO0C_IOMUX_L_OFFSET (0x10U) 5526 #define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT (0U) 5527 #define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT) 5528 #define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT (4U) 5529 #define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT) 5530 #define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT (8U) 5531 #define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT) 5532 #define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT (12U) 5533 #define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT) 5534 /* GPIO0C_IOMUX_H */ 5535 #define GRF_GPIO0C_IOMUX_H_OFFSET (0x14U) 5536 #define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT (0U) 5537 #define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT) 5538 #define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT (4U) 5539 #define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT) 5540 #define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT (8U) 5541 #define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT) 5542 #define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT (12U) 5543 #define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_MASK (0xFU << GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT) 5544 /* GPIO0D_IOMUX_L */ 5545 #define GRF_GPIO0D_IOMUX_L_OFFSET (0x18U) 5546 #define GRF_GPIO0D_IOMUX_L_GPIOOD0_SEL_SHIFT (0U) 5547 #define GRF_GPIO0D_IOMUX_L_GPIOOD0_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIOOD0_SEL_SHIFT) 5548 #define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT (4U) 5549 #define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT) 5550 #define GRF_GPIO0D_IOMUX_L_GPIO0D2_SEL_SHIFT (8U) 5551 #define GRF_GPIO0D_IOMUX_L_GPIO0D2_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D2_SEL_SHIFT) 5552 #define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT (12U) 5553 #define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT) 5554 /* GPIO0D_IOMUX_H */ 5555 #define GRF_GPIO0D_IOMUX_H_OFFSET (0x1CU) 5556 #define GRF_GPIO0D_IOMUX_H_GPIOOD4_SEL_SHIFT (0U) 5557 #define GRF_GPIO0D_IOMUX_H_GPIOOD4_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIOOD4_SEL_SHIFT) 5558 #define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT (4U) 5559 #define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT) 5560 #define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT (8U) 5561 #define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT) 5562 /* GPIO1A_IOMUX_L */ 5563 #define GRF_GPIO1A_IOMUX_L_OFFSET (0x20U) 5564 #define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT (0U) 5565 #define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_MASK (0x1U << GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT) 5566 #define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT (4U) 5567 #define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_MASK (0x1U << GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT) 5568 #define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT (8U) 5569 #define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_MASK (0x1U << GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT) 5570 #define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT (12U) 5571 #define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_MASK (0x1U << GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT) 5572 /* GPIO1A_IOMUX_H */ 5573 #define GRF_GPIO1A_IOMUX_H_OFFSET (0x24U) 5574 #define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT (0U) 5575 #define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_MASK (0x1U << GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT) 5576 #define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT (4U) 5577 #define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_MASK (0x1U << GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT) 5578 /* GPIO1B_IOMUX_L */ 5579 #define GRF_GPIO1B_IOMUX_L_OFFSET (0x28U) 5580 #define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT (0U) 5581 #define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_MASK (0x3U << GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT) 5582 #define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT (4U) 5583 #define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_MASK (0x1U << GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT) 5584 #define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT (8U) 5585 #define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_MASK (0x3U << GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT) 5586 #define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT (12U) 5587 #define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_MASK (0x1U << GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT) 5588 /* GPIO1B_IOMUX_H */ 5589 #define GRF_GPIO1B_IOMUX_H_OFFSET (0x2CU) 5590 #define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT (0U) 5591 #define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_MASK (0x3U << GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT) 5592 #define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT (4U) 5593 #define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_MASK (0x1U << GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT) 5594 #define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT (8U) 5595 #define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_MASK (0x3U << GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT) 5596 #define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT (12U) 5597 #define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_MASK (0x3U << GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT) 5598 /* GPIO1C_IOMUX_L */ 5599 #define GRF_GPIO1C_IOMUX_L_OFFSET (0x30U) 5600 #define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT (0U) 5601 #define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_MASK (0x3U << GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT) 5602 #define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT (4U) 5603 #define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_MASK (0x1U << GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT) 5604 #define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT (8U) 5605 #define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_MASK (0x1U << GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT) 5606 #define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT (12U) 5607 #define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_MASK (0x1U << GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT) 5608 /* GPIO1D_IOMUX_L */ 5609 #define GRF_GPIO1D_IOMUX_L_OFFSET (0x38U) 5610 #define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT (0U) 5611 #define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_MASK (0x3U << GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT) 5612 /* GPIO0A_P */ 5613 #define GRF_GPIO0A_P_OFFSET (0x100U) 5614 #define GRF_GPIO0A_P_GPIO0A0_P_SHIFT (0U) 5615 #define GRF_GPIO0A_P_GPIO0A0_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A0_P_SHIFT) 5616 #define GRF_GPIO0A_P_GPIO0A1_P_SHIFT (2U) 5617 #define GRF_GPIO0A_P_GPIO0A1_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A1_P_SHIFT) 5618 #define GRF_GPIO0A_P_GPIO0A2_P_SHIFT (4U) 5619 #define GRF_GPIO0A_P_GPIO0A2_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A2_P_SHIFT) 5620 #define GRF_GPIO0A_P_GPIO0A3_P_SHIFT (6U) 5621 #define GRF_GPIO0A_P_GPIO0A3_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A3_P_SHIFT) 5622 #define GRF_GPIO0A_P_GPIO0A4_P_SHIFT (8U) 5623 #define GRF_GPIO0A_P_GPIO0A4_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A4_P_SHIFT) 5624 #define GRF_GPIO0A_P_GPIO0A5_P_SHIFT (10U) 5625 #define GRF_GPIO0A_P_GPIO0A5_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A5_P_SHIFT) 5626 #define GRF_GPIO0A_P_GPIO0A6_P_SHIFT (12U) 5627 #define GRF_GPIO0A_P_GPIO0A6_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A6_P_SHIFT) 5628 #define GRF_GPIO0A_P_GPIO0A7_P_SHIFT (14U) 5629 #define GRF_GPIO0A_P_GPIO0A7_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A7_P_SHIFT) 5630 /* GPIO0B_P */ 5631 #define GRF_GPIO0B_P_OFFSET (0x104U) 5632 #define GRF_GPIO0B_P_GPIO0B0_P_SHIFT (0U) 5633 #define GRF_GPIO0B_P_GPIO0B0_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B0_P_SHIFT) 5634 #define GRF_GPIO0B_P_GPIO0B1_P_SHIFT (2U) 5635 #define GRF_GPIO0B_P_GPIO0B1_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B1_P_SHIFT) 5636 #define GRF_GPIO0B_P_GPIO0B2_P_SHIFT (4U) 5637 #define GRF_GPIO0B_P_GPIO0B2_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B2_P_SHIFT) 5638 #define GRF_GPIO0B_P_GPIO0B3_P_SHIFT (6U) 5639 #define GRF_GPIO0B_P_GPIO0B3_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B3_P_SHIFT) 5640 #define GRF_GPIO0B_P_GPIO0B4_P_SHIFT (8U) 5641 #define GRF_GPIO0B_P_GPIO0B4_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B4_P_SHIFT) 5642 #define GRF_GPIO0B_P_GPIO0B5_P_SHIFT (10U) 5643 #define GRF_GPIO0B_P_GPIO0B5_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B5_P_SHIFT) 5644 #define GRF_GPIO0B_P_GPIO0B6_P_SHIFT (12U) 5645 #define GRF_GPIO0B_P_GPIO0B6_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B6_P_SHIFT) 5646 #define GRF_GPIO0B_P_GPIO0B7_P_SHIFT (14U) 5647 #define GRF_GPIO0B_P_GPIO0B7_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B7_P_SHIFT) 5648 /* GPIO0C_P */ 5649 #define GRF_GPIO0C_P_OFFSET (0x108U) 5650 #define GRF_GPIO0C_P_GPIO0C0_P_SHIFT (0U) 5651 #define GRF_GPIO0C_P_GPIO0C0_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C0_P_SHIFT) 5652 #define GRF_GPIO0C_P_GPIO0C1_P_SHIFT (2U) 5653 #define GRF_GPIO0C_P_GPIO0C1_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C1_P_SHIFT) 5654 #define GRF_GPIO0C_P_GPIO0C2_P_SHIFT (4U) 5655 #define GRF_GPIO0C_P_GPIO0C2_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C2_P_SHIFT) 5656 #define GRF_GPIO0C_P_GPIO0C3_P_SHIFT (6U) 5657 #define GRF_GPIO0C_P_GPIO0C3_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C3_P_SHIFT) 5658 #define GRF_GPIO0C_P_GPIO0C4_P_SHIFT (8U) 5659 #define GRF_GPIO0C_P_GPIO0C4_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C4_P_SHIFT) 5660 #define GRF_GPIO0C_P_GPIO0C5_P_SHIFT (10U) 5661 #define GRF_GPIO0C_P_GPIO0C5_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C5_P_SHIFT) 5662 #define GRF_GPIO0C_P_GPIO0C6_P_SHIFT (12U) 5663 #define GRF_GPIO0C_P_GPIO0C6_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C6_P_SHIFT) 5664 #define GRF_GPIO0C_P_GPIO0C7_P_SHIFT (14U) 5665 #define GRF_GPIO0C_P_GPIO0C7_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C7_P_SHIFT) 5666 /* GPIO0D_P */ 5667 #define GRF_GPIO0D_P_OFFSET (0x10CU) 5668 #define GRF_GPIO0D_P_GPIO0D0_P_SHIFT (0U) 5669 #define GRF_GPIO0D_P_GPIO0D0_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D0_P_SHIFT) 5670 #define GRF_GPIO0D_P_GPIO0D1_P_SHIFT (2U) 5671 #define GRF_GPIO0D_P_GPIO0D1_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D1_P_SHIFT) 5672 #define GRF_GPIO0D_P_GPIO0D2_P_SHIFT (4U) 5673 #define GRF_GPIO0D_P_GPIO0D2_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D2_P_SHIFT) 5674 #define GRF_GPIO0D_P_GPIO0D3_P_SHIFT (6U) 5675 #define GRF_GPIO0D_P_GPIO0D3_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D3_P_SHIFT) 5676 #define GRF_GPIO0D_P_GPIO0D4_P_SHIFT (8U) 5677 #define GRF_GPIO0D_P_GPIO0D4_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D4_P_SHIFT) 5678 #define GRF_GPIO0D_P_GPIO0D5_P_SHIFT (10U) 5679 #define GRF_GPIO0D_P_GPIO0D5_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D5_P_SHIFT) 5680 #define GRF_GPIO0D_P_GPIO0D6_P_SHIFT (12U) 5681 #define GRF_GPIO0D_P_GPIO0D6_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D6_P_SHIFT) 5682 /* GPIO1A_P */ 5683 #define GRF_GPIO1A_P_OFFSET (0x110U) 5684 #define GRF_GPIO1A_P_GPIO1A0_P_SHIFT (0U) 5685 #define GRF_GPIO1A_P_GPIO1A0_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A0_P_SHIFT) 5686 #define GRF_GPIO1A_P_GPIO1A1_P_SHIFT (2U) 5687 #define GRF_GPIO1A_P_GPIO1A1_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A1_P_SHIFT) 5688 #define GRF_GPIO1A_P_GPIO1A2_P_SHIFT (4U) 5689 #define GRF_GPIO1A_P_GPIO1A2_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A2_P_SHIFT) 5690 #define GRF_GPIO1A_P_GPIO1A3_P_SHIFT (6U) 5691 #define GRF_GPIO1A_P_GPIO1A3_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A3_P_SHIFT) 5692 #define GRF_GPIO1A_P_GPIO1A4_P_SHIFT (8U) 5693 #define GRF_GPIO1A_P_GPIO1A4_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A4_P_SHIFT) 5694 #define GRF_GPIO1A_P_GPIO1A5_P_SHIFT (10U) 5695 #define GRF_GPIO1A_P_GPIO1A5_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A5_P_SHIFT) 5696 /* GPIO1B_P */ 5697 #define GRF_GPIO1B_P_OFFSET (0x114U) 5698 #define GRF_GPIO1B_P_GPIO1B0_P_SHIFT (0U) 5699 #define GRF_GPIO1B_P_GPIO1B0_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B0_P_SHIFT) 5700 #define GRF_GPIO1B_P_GPIO1B1_P_SHIFT (2U) 5701 #define GRF_GPIO1B_P_GPIO1B1_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B1_P_SHIFT) 5702 #define GRF_GPIO1B_P_GPIO1B2_P_SHIFT (4U) 5703 #define GRF_GPIO1B_P_GPIO1B2_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B2_P_SHIFT) 5704 #define GRF_GPIO1B_P_GPIO1B3_P_SHIFT (6U) 5705 #define GRF_GPIO1B_P_GPIO1B3_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B3_P_SHIFT) 5706 #define GRF_GPIO1B_P_GPIO1B4_P_SHIFT (8U) 5707 #define GRF_GPIO1B_P_GPIO1B4_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B4_P_SHIFT) 5708 #define GRF_GPIO1B_P_GPIO1B5_P_SHIFT (10U) 5709 #define GRF_GPIO1B_P_GPIO1B5_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B5_P_SHIFT) 5710 #define GRF_GPIO1B_P_GPIO1B6_P_SHIFT (12U) 5711 #define GRF_GPIO1B_P_GPIO1B6_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B6_P_SHIFT) 5712 #define GRF_GPIO1B_P_GPIO1B7_P_SHIFT (14U) 5713 #define GRF_GPIO1B_P_GPIO1B7_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B7_P_SHIFT) 5714 /* GPIO1C_P */ 5715 #define GRF_GPIO1C_P_OFFSET (0x118U) 5716 #define GRF_GPIO1C_P_GPIO1C0_P_SHIFT (0U) 5717 #define GRF_GPIO1C_P_GPIO1C0_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C0_P_SHIFT) 5718 #define GRF_GPIO1C_P_GPIO1C1_P_SHIFT (2U) 5719 #define GRF_GPIO1C_P_GPIO1C1_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C1_P_SHIFT) 5720 #define GRF_GPIO1C_P_GPIO1C2_P_SHIFT (4U) 5721 #define GRF_GPIO1C_P_GPIO1C2_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C2_P_SHIFT) 5722 #define GRF_GPIO1C_P_GPIO1C3_P_SHIFT (6U) 5723 #define GRF_GPIO1C_P_GPIO1C3_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C3_P_SHIFT) 5724 /* GPIO1D_P */ 5725 #define GRF_GPIO1D_P_OFFSET (0x11CU) 5726 #define GRF_GPIO1D_P_GPIO1D0_P_SHIFT (0U) 5727 #define GRF_GPIO1D_P_GPIO1D0_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D0_P_SHIFT) 5728 /* SOC_CON0 */ 5729 #define GRF_SOC_CON0_OFFSET (0x200U) 5730 #define GRF_SOC_CON0_REMAP_SHIFT (0U) 5731 #define GRF_SOC_CON0_REMAP_MASK (0x1U << GRF_SOC_CON0_REMAP_SHIFT) 5732 #define GRF_SOC_CON0_GRF_CON_M4F_JTAGTCK_GATING_SHIFT (1U) 5733 #define GRF_SOC_CON0_GRF_CON_M4F_JTAGTCK_GATING_MASK (0x1U << GRF_SOC_CON0_GRF_CON_M4F_JTAGTCK_GATING_SHIFT) 5734 #define GRF_SOC_CON0_GRF_CON_M0_JTAGTCK_GATING_SHIFT (2U) 5735 #define GRF_SOC_CON0_GRF_CON_M0_JTAGTCK_GATING_MASK (0x1U << GRF_SOC_CON0_GRF_CON_M0_JTAGTCK_GATING_SHIFT) 5736 #define GRF_SOC_CON0_GRF_CON_DSP_JTAGTCK_GATING_SHIFT (3U) 5737 #define GRF_SOC_CON0_GRF_CON_DSP_JTAGTCK_GATING_MASK (0x1U << GRF_SOC_CON0_GRF_CON_DSP_JTAGTCK_GATING_SHIFT) 5738 #define GRF_SOC_CON0_GRF_CON_HYPERX8_SFC1_SEL_SHIFT (4U) 5739 #define GRF_SOC_CON0_GRF_CON_HYPERX8_SFC1_SEL_MASK (0x1U << GRF_SOC_CON0_GRF_CON_HYPERX8_SFC1_SEL_SHIFT) 5740 #define GRF_SOC_CON0_DSP_TCM_SEL0_SHIFT (5U) 5741 #define GRF_SOC_CON0_DSP_TCM_SEL0_MASK (0x1U << GRF_SOC_CON0_DSP_TCM_SEL0_SHIFT) 5742 #define GRF_SOC_CON0_DSP_TCM_SEL1_SHIFT (6U) 5743 #define GRF_SOC_CON0_DSP_TCM_SEL1_MASK (0x1U << GRF_SOC_CON0_DSP_TCM_SEL1_SHIFT) 5744 #define GRF_SOC_CON0_DSP_TCM_SEL2_SHIFT (7U) 5745 #define GRF_SOC_CON0_DSP_TCM_SEL2_MASK (0x1U << GRF_SOC_CON0_DSP_TCM_SEL2_SHIFT) 5746 #define GRF_SOC_CON0_DSP_TCM_SEL3_SHIFT (8U) 5747 #define GRF_SOC_CON0_DSP_TCM_SEL3_MASK (0x1U << GRF_SOC_CON0_DSP_TCM_SEL3_SHIFT) 5748 /* SOC_CON1 */ 5749 #define GRF_SOC_CON1_OFFSET (0x204U) 5750 #define GRF_SOC_CON1_GRF_MCLKOUT_I2S8CH0_IOE_SHIFT (0U) 5751 #define GRF_SOC_CON1_GRF_MCLKOUT_I2S8CH0_IOE_MASK (0x1U << GRF_SOC_CON1_GRF_MCLKOUT_I2S8CH0_IOE_SHIFT) 5752 #define GRF_SOC_CON1_GRF_SPI0_MULTI_IOFUNC_SRC_SEL_SHIFT (1U) 5753 #define GRF_SOC_CON1_GRF_SPI0_MULTI_IOFUNC_SRC_SEL_MASK (0x1U << GRF_SOC_CON1_GRF_SPI0_MULTI_IOFUNC_SRC_SEL_SHIFT) 5754 #define GRF_SOC_CON1_GRF_SPI1_MULTI_IOFUNC_SRC_SEL_SHIFT (2U) 5755 #define GRF_SOC_CON1_GRF_SPI1_MULTI_IOFUNC_SRC_SEL_MASK (0x3U << GRF_SOC_CON1_GRF_SPI1_MULTI_IOFUNC_SRC_SEL_SHIFT) 5756 #define GRF_SOC_CON1_GRF_PWM0_MULTI_IOFUNC_SRC_SEL_SHIFT (4U) 5757 #define GRF_SOC_CON1_GRF_PWM0_MULTI_IOFUNC_SRC_SEL_MASK (0x1U << GRF_SOC_CON1_GRF_PWM0_MULTI_IOFUNC_SRC_SEL_SHIFT) 5758 #define GRF_SOC_CON1_GRF_PWM1_MULTI_IOFUNC_SRC_SEL_SHIFT (5U) 5759 #define GRF_SOC_CON1_GRF_PWM1_MULTI_IOFUNC_SRC_SEL_MASK (0x1U << GRF_SOC_CON1_GRF_PWM1_MULTI_IOFUNC_SRC_SEL_SHIFT) 5760 #define GRF_SOC_CON1_GRF_I2C0_MULTI_IOFUNC_SRC_SEL_SHIFT (6U) 5761 #define GRF_SOC_CON1_GRF_I2C0_MULTI_IOFUNC_SRC_SEL_MASK (0x3U << GRF_SOC_CON1_GRF_I2C0_MULTI_IOFUNC_SRC_SEL_SHIFT) 5762 #define GRF_SOC_CON1_GRF_I2C1_MULTI_IOFUNC_SRC_SEL_SHIFT (8U) 5763 #define GRF_SOC_CON1_GRF_I2C1_MULTI_IOFUNC_SRC_SEL_MASK (0x3U << GRF_SOC_CON1_GRF_I2C1_MULTI_IOFUNC_SRC_SEL_SHIFT) 5764 #define GRF_SOC_CON1_GRF_PDM_MULTI_IOFUNC_SRC_SEL_SHIFT (10U) 5765 #define GRF_SOC_CON1_GRF_PDM_MULTI_IOFUNC_SRC_SEL_MASK (0x1U << GRF_SOC_CON1_GRF_PDM_MULTI_IOFUNC_SRC_SEL_SHIFT) 5766 #define GRF_SOC_CON1_GRF_CON_VIP_NEG_POS_SEL_SHIFT (11U) 5767 #define GRF_SOC_CON1_GRF_CON_VIP_NEG_POS_SEL_MASK (0x1U << GRF_SOC_CON1_GRF_CON_VIP_NEG_POS_SEL_SHIFT) 5768 #define GRF_SOC_CON1_GRF_I2C2_MULTI_IOFUNC_SRC_SEL_SHIFT (12U) 5769 #define GRF_SOC_CON1_GRF_I2C2_MULTI_IOFUNC_SRC_SEL_MASK (0x1U << GRF_SOC_CON1_GRF_I2C2_MULTI_IOFUNC_SRC_SEL_SHIFT) 5770 #define GRF_SOC_CON1_UART2_CTS_INV_SEL_SHIFT (14U) 5771 #define GRF_SOC_CON1_UART2_CTS_INV_SEL_MASK (0x1U << GRF_SOC_CON1_UART2_CTS_INV_SEL_SHIFT) 5772 #define GRF_SOC_CON1_UART2_RTS_INV_SEL_SHIFT (15U) 5773 #define GRF_SOC_CON1_UART2_RTS_INV_SEL_MASK (0x1U << GRF_SOC_CON1_UART2_RTS_INV_SEL_SHIFT) 5774 /* SOC_CON2 */ 5775 #define GRF_SOC_CON2_OFFSET (0x208U) 5776 #define GRF_SOC_CON2_UART0_CTS_INV_SEL_SHIFT (0U) 5777 #define GRF_SOC_CON2_UART0_CTS_INV_SEL_MASK (0x1U << GRF_SOC_CON2_UART0_CTS_INV_SEL_SHIFT) 5778 #define GRF_SOC_CON2_UART1_CTS_INV_SEL_SHIFT (1U) 5779 #define GRF_SOC_CON2_UART1_CTS_INV_SEL_MASK (0x1U << GRF_SOC_CON2_UART1_CTS_INV_SEL_SHIFT) 5780 #define GRF_SOC_CON2_UART0_RTS_INV_SEL_SHIFT (2U) 5781 #define GRF_SOC_CON2_UART0_RTS_INV_SEL_MASK (0x1U << GRF_SOC_CON2_UART0_RTS_INV_SEL_SHIFT) 5782 #define GRF_SOC_CON2_UART1_RTS_INV_SEL_SHIFT (3U) 5783 #define GRF_SOC_CON2_UART1_RTS_INV_SEL_MASK (0x1U << GRF_SOC_CON2_UART1_RTS_INV_SEL_SHIFT) 5784 #define GRF_SOC_CON2_GRF_PDM_CLK_S_G_SHIFT (4U) 5785 #define GRF_SOC_CON2_GRF_PDM_CLK_S_G_MASK (0x1U << GRF_SOC_CON2_GRF_PDM_CLK_S_G_SHIFT) 5786 #define GRF_SOC_CON2_BOOTROM_MEMAUTO_GATING_EN_SHIFT (6U) 5787 #define GRF_SOC_CON2_BOOTROM_MEMAUTO_GATING_EN_MASK (0x1U << GRF_SOC_CON2_BOOTROM_MEMAUTO_GATING_EN_SHIFT) 5788 #define GRF_SOC_CON2_AHBBUFFER_MEMAUTO_GATING_EN_SHIFT (7U) 5789 #define GRF_SOC_CON2_AHBBUFFER_MEMAUTO_GATING_EN_MASK (0x1U << GRF_SOC_CON2_AHBBUFFER_MEMAUTO_GATING_EN_SHIFT) 5790 #define GRF_SOC_CON2_INTMEM0_MEMAUTO_GATING_EN_SHIFT (9U) 5791 #define GRF_SOC_CON2_INTMEM0_MEMAUTO_GATING_EN_MASK (0x1U << GRF_SOC_CON2_INTMEM0_MEMAUTO_GATING_EN_SHIFT) 5792 #define GRF_SOC_CON2_INTMEM1_MEMAUTO_GATING_EN_SHIFT (10U) 5793 #define GRF_SOC_CON2_INTMEM1_MEMAUTO_GATING_EN_MASK (0x1U << GRF_SOC_CON2_INTMEM1_MEMAUTO_GATING_EN_SHIFT) 5794 #define GRF_SOC_CON2_INTMEM1_VAD_MEMAUTO_GATING_EN_SHIFT (11U) 5795 #define GRF_SOC_CON2_INTMEM1_VAD_MEMAUTO_GATING_EN_MASK (0x1U << GRF_SOC_CON2_INTMEM1_VAD_MEMAUTO_GATING_EN_SHIFT) 5796 #define GRF_SOC_CON2_ICACHE0_FLUSH_REQ_SHIFT (12U) 5797 #define GRF_SOC_CON2_ICACHE0_FLUSH_REQ_MASK (0x1U << GRF_SOC_CON2_ICACHE0_FLUSH_REQ_SHIFT) 5798 #define GRF_SOC_CON2_DCACHE0_FLUSH_REQ_SHIFT (13U) 5799 #define GRF_SOC_CON2_DCACHE0_FLUSH_REQ_MASK (0x1U << GRF_SOC_CON2_DCACHE0_FLUSH_REQ_SHIFT) 5800 #define GRF_SOC_CON2_CAHCE1_FLUSH_REQ_SHIFT (14U) 5801 #define GRF_SOC_CON2_CAHCE1_FLUSH_REQ_MASK (0x1U << GRF_SOC_CON2_CAHCE1_FLUSH_REQ_SHIFT) 5802 /* SOC_CON3 */ 5803 #define GRF_SOC_CON3_OFFSET (0x20CU) 5804 #define GRF_SOC_CON3_GRF_CON_RDS_DELAY_ADJ_SHIFT (0U) 5805 #define GRF_SOC_CON3_GRF_CON_RDS_DELAY_ADJ_MASK (0xFFU << GRF_SOC_CON3_GRF_CON_RDS_DELAY_ADJ_SHIFT) 5806 #define GRF_SOC_CON3_GRF_RDS_CLK_SMP_SEL_SHIFT (8U) 5807 #define GRF_SOC_CON3_GRF_RDS_CLK_SMP_SEL_MASK (0x1U << GRF_SOC_CON3_GRF_RDS_CLK_SMP_SEL_SHIFT) 5808 #define GRF_SOC_CON3_GRF_RPC_INITIAL_STATE_SHIFT (9U) 5809 #define GRF_SOC_CON3_GRF_RPC_INITIAL_STATE_MASK (0x1U << GRF_SOC_CON3_GRF_RPC_INITIAL_STATE_SHIFT) 5810 /* SOC_CON4 */ 5811 #define GRF_SOC_CON4_OFFSET (0x210U) 5812 #define GRF_SOC_CON4_ICACHE0_SPRA_MS_SHIFT (0U) 5813 #define GRF_SOC_CON4_ICACHE0_SPRA_MS_MASK (0xFU << GRF_SOC_CON4_ICACHE0_SPRA_MS_SHIFT) 5814 #define GRF_SOC_CON4_ICACHE0_SPRA_MSE_SHIFT (4U) 5815 #define GRF_SOC_CON4_ICACHE0_SPRA_MSE_MASK (0x1U << GRF_SOC_CON4_ICACHE0_SPRA_MSE_SHIFT) 5816 #define GRF_SOC_CON4_ICACHE0_SPRA_PD_SHIFT (5U) 5817 #define GRF_SOC_CON4_ICACHE0_SPRA_PD_MASK (0x1U << GRF_SOC_CON4_ICACHE0_SPRA_PD_SHIFT) 5818 #define GRF_SOC_CON4_ICACHE0_SPRA_NAP_SHIFT (6U) 5819 #define GRF_SOC_CON4_ICACHE0_SPRA_NAP_MASK (0x1U << GRF_SOC_CON4_ICACHE0_SPRA_NAP_SHIFT) 5820 #define GRF_SOC_CON4_ICACHE0_SPRA_RET_SHIFT (7U) 5821 #define GRF_SOC_CON4_ICACHE0_SPRA_RET_MASK (0x1U << GRF_SOC_CON4_ICACHE0_SPRA_RET_SHIFT) 5822 #define GRF_SOC_CON4_DCACHE0_SPRA_MS_SHIFT (8U) 5823 #define GRF_SOC_CON4_DCACHE0_SPRA_MS_MASK (0xFU << GRF_SOC_CON4_DCACHE0_SPRA_MS_SHIFT) 5824 #define GRF_SOC_CON4_DCACHE0_SPRA_MSE_SHIFT (12U) 5825 #define GRF_SOC_CON4_DCACHE0_SPRA_MSE_MASK (0x1U << GRF_SOC_CON4_DCACHE0_SPRA_MSE_SHIFT) 5826 #define GRF_SOC_CON4_DCACHE0_SPRA_PD_SHIFT (13U) 5827 #define GRF_SOC_CON4_DCACHE0_SPRA_PD_MASK (0x1U << GRF_SOC_CON4_DCACHE0_SPRA_PD_SHIFT) 5828 #define GRF_SOC_CON4_DCACHE0_SPRA_NAP_SHIFT (14U) 5829 #define GRF_SOC_CON4_DCACHE0_SPRA_NAP_MASK (0x1U << GRF_SOC_CON4_DCACHE0_SPRA_NAP_SHIFT) 5830 #define GRF_SOC_CON4_DCACHE0_SPRA_RET_SHIFT (15U) 5831 #define GRF_SOC_CON4_DCACHE0_SPRA_RET_MASK (0x1U << GRF_SOC_CON4_DCACHE0_SPRA_RET_SHIFT) 5832 /* SOC_CON5 */ 5833 #define GRF_SOC_CON5_OFFSET (0x214U) 5834 #define GRF_SOC_CON5_CACHE1_SPRA_MS_SHIFT (0U) 5835 #define GRF_SOC_CON5_CACHE1_SPRA_MS_MASK (0xFU << GRF_SOC_CON5_CACHE1_SPRA_MS_SHIFT) 5836 #define GRF_SOC_CON5_CACHE1_SPRA_MSE_SHIFT (4U) 5837 #define GRF_SOC_CON5_CACHE1_SPRA_MSE_MASK (0x1U << GRF_SOC_CON5_CACHE1_SPRA_MSE_SHIFT) 5838 #define GRF_SOC_CON5_CACHE1_SPRA_PD_SHIFT (5U) 5839 #define GRF_SOC_CON5_CACHE1_SPRA_PD_MASK (0x1U << GRF_SOC_CON5_CACHE1_SPRA_PD_SHIFT) 5840 #define GRF_SOC_CON5_CACHE1_SPRA_NAP_SHIFT (6U) 5841 #define GRF_SOC_CON5_CACHE1_SPRA_NAP_MASK (0x1U << GRF_SOC_CON5_CACHE1_SPRA_NAP_SHIFT) 5842 #define GRF_SOC_CON5_CACHE1_SPRA_RET_SHIFT (7U) 5843 #define GRF_SOC_CON5_CACHE1_SPRA_RET_MASK (0x1U << GRF_SOC_CON5_CACHE1_SPRA_RET_SHIFT) 5844 #define GRF_SOC_CON5_VOP_SPRF_PD_SHIFT (8U) 5845 #define GRF_SOC_CON5_VOP_SPRF_PD_MASK (0x1U << GRF_SOC_CON5_VOP_SPRF_PD_SHIFT) 5846 #define GRF_SOC_CON5_VOP_SPRF_RTSEL_SHIFT (9U) 5847 #define GRF_SOC_CON5_VOP_SPRF_RTSEL_MASK (0x1U << GRF_SOC_CON5_VOP_SPRF_RTSEL_SHIFT) 5848 #define GRF_SOC_CON5_VOP_SPRF_TURBO_SHIFT (10U) 5849 #define GRF_SOC_CON5_VOP_SPRF_TURBO_MASK (0x1U << GRF_SOC_CON5_VOP_SPRF_TURBO_SHIFT) 5850 #define GRF_SOC_CON5_VOP_SPRF_TSEL_SHIFT (11U) 5851 #define GRF_SOC_CON5_VOP_SPRF_TSEL_MASK (0x3U << GRF_SOC_CON5_VOP_SPRF_TSEL_SHIFT) 5852 #define GRF_SOC_CON5_VOP_DPRF_PD_SHIFT (13U) 5853 #define GRF_SOC_CON5_VOP_DPRF_PD_MASK (0x1U << GRF_SOC_CON5_VOP_DPRF_PD_SHIFT) 5854 /* SOC_CON6 */ 5855 #define GRF_SOC_CON6_OFFSET (0x218U) 5856 #define GRF_SOC_CON6_DSP_SPRF_PD_SHIFT (0U) 5857 #define GRF_SOC_CON6_DSP_SPRF_PD_MASK (0x1U << GRF_SOC_CON6_DSP_SPRF_PD_SHIFT) 5858 #define GRF_SOC_CON6_DSP_SPRF_RTSEL_SHIFT (1U) 5859 #define GRF_SOC_CON6_DSP_SPRF_RTSEL_MASK (0x1U << GRF_SOC_CON6_DSP_SPRF_RTSEL_SHIFT) 5860 #define GRF_SOC_CON6_DSP_SPRF_TURBO_SHIFT (2U) 5861 #define GRF_SOC_CON6_DSP_SPRF_TURBO_MASK (0x1U << GRF_SOC_CON6_DSP_SPRF_TURBO_SHIFT) 5862 #define GRF_SOC_CON6_DSP_SPRF_TSEL_SHIFT (3U) 5863 #define GRF_SOC_CON6_DSP_SPRF_TSEL_MASK (0x3U << GRF_SOC_CON6_DSP_SPRF_TSEL_SHIFT) 5864 #define GRF_SOC_CON6_DSP_CORE_SPRA_NAP_SHIFT (5U) 5865 #define GRF_SOC_CON6_DSP_CORE_SPRA_NAP_MASK (0x1U << GRF_SOC_CON6_DSP_CORE_SPRA_NAP_SHIFT) 5866 #define GRF_SOC_CON6_DSP_CORE_SPRA_RET_SHIFT (6U) 5867 #define GRF_SOC_CON6_DSP_CORE_SPRA_RET_MASK (0x1U << GRF_SOC_CON6_DSP_CORE_SPRA_RET_SHIFT) 5868 #define GRF_SOC_CON6_DSP_CORE_SPRA_PD_SHIFT (7U) 5869 #define GRF_SOC_CON6_DSP_CORE_SPRA_PD_MASK (0x1U << GRF_SOC_CON6_DSP_CORE_SPRA_PD_SHIFT) 5870 #define GRF_SOC_CON6_DSP_CORE_SPRA_MS_SHIFT (8U) 5871 #define GRF_SOC_CON6_DSP_CORE_SPRA_MS_MASK (0xFU << GRF_SOC_CON6_DSP_CORE_SPRA_MS_SHIFT) 5872 #define GRF_SOC_CON6_DSP_CORE_SPRA_MSE_SHIFT (12U) 5873 #define GRF_SOC_CON6_DSP_CORE_SPRA_MSE_MASK (0x1U << GRF_SOC_CON6_DSP_CORE_SPRA_MSE_SHIFT) 5874 #define GRF_SOC_CON6_BOOTROM_ROM_PD_SHIFT (13U) 5875 #define GRF_SOC_CON6_BOOTROM_ROM_PD_MASK (0x1U << GRF_SOC_CON6_BOOTROM_ROM_PD_SHIFT) 5876 /* SOC_CON7 */ 5877 #define GRF_SOC_CON7_OFFSET (0x21CU) 5878 #define GRF_SOC_CON7_USB_SPRA_MS_SHIFT (0U) 5879 #define GRF_SOC_CON7_USB_SPRA_MS_MASK (0xFU << GRF_SOC_CON7_USB_SPRA_MS_SHIFT) 5880 #define GRF_SOC_CON7_USB_SPRA_MSE_SHIFT (4U) 5881 #define GRF_SOC_CON7_USB_SPRA_MSE_MASK (0x1U << GRF_SOC_CON7_USB_SPRA_MSE_SHIFT) 5882 #define GRF_SOC_CON7_USB_SPRA_PD_SHIFT (5U) 5883 #define GRF_SOC_CON7_USB_SPRA_PD_MASK (0x1U << GRF_SOC_CON7_USB_SPRA_PD_SHIFT) 5884 #define GRF_SOC_CON7_USB_SPRA_NAP_SHIFT (6U) 5885 #define GRF_SOC_CON7_USB_SPRA_NAP_MASK (0x1U << GRF_SOC_CON7_USB_SPRA_NAP_SHIFT) 5886 #define GRF_SOC_CON7_USB_SPRA_RET_SHIFT (7U) 5887 #define GRF_SOC_CON7_USB_SPRA_RET_MASK (0x1U << GRF_SOC_CON7_USB_SPRA_RET_SHIFT) 5888 #define GRF_SOC_CON7_CRYPTO_SPRA_MS_SHIFT (8U) 5889 #define GRF_SOC_CON7_CRYPTO_SPRA_MS_MASK (0xFU << GRF_SOC_CON7_CRYPTO_SPRA_MS_SHIFT) 5890 #define GRF_SOC_CON7_CRYPTO_SPRA_MSE_SHIFT (12U) 5891 #define GRF_SOC_CON7_CRYPTO_SPRA_MSE_MASK (0x1U << GRF_SOC_CON7_CRYPTO_SPRA_MSE_SHIFT) 5892 #define GRF_SOC_CON7_CRYPTO_SPRA_PD_SHIFT (13U) 5893 #define GRF_SOC_CON7_CRYPTO_SPRA_PD_MASK (0x1U << GRF_SOC_CON7_CRYPTO_SPRA_PD_SHIFT) 5894 #define GRF_SOC_CON7_CRYPTO_SPRA_NAP_SHIFT (14U) 5895 #define GRF_SOC_CON7_CRYPTO_SPRA_NAP_MASK (0x1U << GRF_SOC_CON7_CRYPTO_SPRA_NAP_SHIFT) 5896 #define GRF_SOC_CON7_CRYPTO_SPRA_RET_SHIFT (15U) 5897 #define GRF_SOC_CON7_CRYPTO_SPRA_RET_MASK (0x1U << GRF_SOC_CON7_CRYPTO_SPRA_RET_SHIFT) 5898 /* SOC_CON8 */ 5899 #define GRF_SOC_CON8_OFFSET (0x220U) 5900 #define GRF_SOC_CON8_CRYPTO_DPRF_PD_SHIFT (0U) 5901 #define GRF_SOC_CON8_CRYPTO_DPRF_PD_MASK (0x1U << GRF_SOC_CON8_CRYPTO_DPRF_PD_SHIFT) 5902 #define GRF_SOC_CON8_SDMMC_DPRF_PD_SHIFT (1U) 5903 #define GRF_SOC_CON8_SDMMC_DPRF_PD_MASK (0x1U << GRF_SOC_CON8_SDMMC_DPRF_PD_SHIFT) 5904 #define GRF_SOC_CON8_VIP_DPRF_PD_SHIFT (2U) 5905 #define GRF_SOC_CON8_VIP_DPRF_PD_MASK (0x1U << GRF_SOC_CON8_VIP_DPRF_PD_SHIFT) 5906 #define GRF_SOC_CON8_AHBBUFFER_SPRA_MS_SHIFT (8U) 5907 #define GRF_SOC_CON8_AHBBUFFER_SPRA_MS_MASK (0xFU << GRF_SOC_CON8_AHBBUFFER_SPRA_MS_SHIFT) 5908 #define GRF_SOC_CON8_AHBBUFFER_SPRA_MSE_SHIFT (12U) 5909 #define GRF_SOC_CON8_AHBBUFFER_SPRA_MSE_MASK (0x1U << GRF_SOC_CON8_AHBBUFFER_SPRA_MSE_SHIFT) 5910 #define GRF_SOC_CON8_AHBBUFFER_SPRA_PD_SHIFT (13U) 5911 #define GRF_SOC_CON8_AHBBUFFER_SPRA_PD_MASK (0x1U << GRF_SOC_CON8_AHBBUFFER_SPRA_PD_SHIFT) 5912 #define GRF_SOC_CON8_AHBBUFFER_SPRA_NAP_SHIFT (14U) 5913 #define GRF_SOC_CON8_AHBBUFFER_SPRA_NAP_MASK (0x1U << GRF_SOC_CON8_AHBBUFFER_SPRA_NAP_SHIFT) 5914 #define GRF_SOC_CON8_AHBBUFFER_SPRA_RET_SHIFT (15U) 5915 #define GRF_SOC_CON8_AHBBUFFER_SPRA_RET_MASK (0x1U << GRF_SOC_CON8_AHBBUFFER_SPRA_RET_SHIFT) 5916 /* SOC_CON9 */ 5917 #define GRF_SOC_CON9_OFFSET (0x224U) 5918 #define GRF_SOC_CON9_INTMEM0_SPRA_MS_SHIFT (0U) 5919 #define GRF_SOC_CON9_INTMEM0_SPRA_MS_MASK (0xFU << GRF_SOC_CON9_INTMEM0_SPRA_MS_SHIFT) 5920 #define GRF_SOC_CON9_INTMEM0_SPRA_MSE_SHIFT (4U) 5921 #define GRF_SOC_CON9_INTMEM0_SPRA_MSE_MASK (0x1U << GRF_SOC_CON9_INTMEM0_SPRA_MSE_SHIFT) 5922 #define GRF_SOC_CON9_INTMEM1_SPRA_MS_SHIFT (8U) 5923 #define GRF_SOC_CON9_INTMEM1_SPRA_MS_MASK (0xFU << GRF_SOC_CON9_INTMEM1_SPRA_MS_SHIFT) 5924 #define GRF_SOC_CON9_INTMEM1_SPRA_MSE_SHIFT (12U) 5925 #define GRF_SOC_CON9_INTMEM1_SPRA_MSE_MASK (0x1U << GRF_SOC_CON9_INTMEM1_SPRA_MSE_SHIFT) 5926 /* SOC_CON10 */ 5927 #define GRF_SOC_CON10_OFFSET (0x228U) 5928 #define GRF_SOC_CON10_VAD_SPRF_PD_SHIFT (0U) 5929 #define GRF_SOC_CON10_VAD_SPRF_PD_MASK (0x1U << GRF_SOC_CON10_VAD_SPRF_PD_SHIFT) 5930 #define GRF_SOC_CON10_VAD_SPRF_RTSEL_SHIFT (1U) 5931 #define GRF_SOC_CON10_VAD_SPRF_RTSEL_MASK (0x1U << GRF_SOC_CON10_VAD_SPRF_RTSEL_SHIFT) 5932 #define GRF_SOC_CON10_VAD_SPRF_TURBO_SHIFT (2U) 5933 #define GRF_SOC_CON10_VAD_SPRF_TURBO_MASK (0x1U << GRF_SOC_CON10_VAD_SPRF_TURBO_SHIFT) 5934 #define GRF_SOC_CON10_VAD_SPRF_TSEL_SHIFT (3U) 5935 #define GRF_SOC_CON10_VAD_SPRF_TSEL_MASK (0x3U << GRF_SOC_CON10_VAD_SPRF_TSEL_SHIFT) 5936 #define GRF_SOC_CON10_PDM_SPRF_PD_SHIFT (5U) 5937 #define GRF_SOC_CON10_PDM_SPRF_PD_MASK (0x1U << GRF_SOC_CON10_PDM_SPRF_PD_SHIFT) 5938 #define GRF_SOC_CON10_PDM_SPRF_RTSEL_SHIFT (6U) 5939 #define GRF_SOC_CON10_PDM_SPRF_RTSEL_MASK (0x1U << GRF_SOC_CON10_PDM_SPRF_RTSEL_SHIFT) 5940 #define GRF_SOC_CON10_PDM_SPRF_TURBO_SHIFT (7U) 5941 #define GRF_SOC_CON10_PDM_SPRF_TURBO_MASK (0x1U << GRF_SOC_CON10_PDM_SPRF_TURBO_SHIFT) 5942 #define GRF_SOC_CON10_PDM_SPRF_TSEL_SHIFT (8U) 5943 #define GRF_SOC_CON10_PDM_SPRF_TSEL_MASK (0x3U << GRF_SOC_CON10_PDM_SPRF_TSEL_SHIFT) 5944 #define GRF_SOC_CON10_CODEC_SPRF_PD_SHIFT (10U) 5945 #define GRF_SOC_CON10_CODEC_SPRF_PD_MASK (0x1U << GRF_SOC_CON10_CODEC_SPRF_PD_SHIFT) 5946 #define GRF_SOC_CON10_CODEC_SPRF_RTSEL_SHIFT (11U) 5947 #define GRF_SOC_CON10_CODEC_SPRF_RTSEL_MASK (0x1U << GRF_SOC_CON10_CODEC_SPRF_RTSEL_SHIFT) 5948 #define GRF_SOC_CON10_CODEC_SPRF_TURBO_SHIFT (12U) 5949 #define GRF_SOC_CON10_CODEC_SPRF_TURBO_MASK (0x1U << GRF_SOC_CON10_CODEC_SPRF_TURBO_SHIFT) 5950 #define GRF_SOC_CON10_CODEC_SPRF_TSEL_SHIFT (13U) 5951 #define GRF_SOC_CON10_CODEC_SPRF_TSEL_MASK (0x3U << GRF_SOC_CON10_CODEC_SPRF_TSEL_SHIFT) 5952 /* SOC_CON11 */ 5953 #define GRF_SOC_CON11_OFFSET (0x22CU) 5954 #define GRF_SOC_CON11_DSP_SPRA_MS_SHIFT (0U) 5955 #define GRF_SOC_CON11_DSP_SPRA_MS_MASK (0xFU << GRF_SOC_CON11_DSP_SPRA_MS_SHIFT) 5956 #define GRF_SOC_CON11_DSP_SPRA_MSE_SHIFT (4U) 5957 #define GRF_SOC_CON11_DSP_SPRA_MSE_MASK (0x1U << GRF_SOC_CON11_DSP_SPRA_MSE_SHIFT) 5958 /* SOC_CON12 */ 5959 #define GRF_SOC_CON12_OFFSET (0x230U) 5960 #define GRF_SOC_CON12_DSP_ITCM_SPRA_NAP_SHIFT (0U) 5961 #define GRF_SOC_CON12_DSP_ITCM_SPRA_NAP_MASK (0x3U << GRF_SOC_CON12_DSP_ITCM_SPRA_NAP_SHIFT) 5962 #define GRF_SOC_CON12_DSP_DTCM_SPRA_NAP_SHIFT (4U) 5963 #define GRF_SOC_CON12_DSP_DTCM_SPRA_NAP_MASK (0xFFFU << GRF_SOC_CON12_DSP_DTCM_SPRA_NAP_SHIFT) 5964 /* SOC_CON13 */ 5965 #define GRF_SOC_CON13_OFFSET (0x234U) 5966 #define GRF_SOC_CON13_DSP_ITCM_SPRA_RET_SHIFT (0U) 5967 #define GRF_SOC_CON13_DSP_ITCM_SPRA_RET_MASK (0x3U << GRF_SOC_CON13_DSP_ITCM_SPRA_RET_SHIFT) 5968 #define GRF_SOC_CON13_DSP_DTCM_SPRA_RET_SHIFT (4U) 5969 #define GRF_SOC_CON13_DSP_DTCM_SPRA_RET_MASK (0xFFFU << GRF_SOC_CON13_DSP_DTCM_SPRA_RET_SHIFT) 5970 /* SOC_CON14 */ 5971 #define GRF_SOC_CON14_OFFSET (0x238U) 5972 #define GRF_SOC_CON14_DSP_ITCM_SPRA_PD_SHIFT (0U) 5973 #define GRF_SOC_CON14_DSP_ITCM_SPRA_PD_MASK (0x3U << GRF_SOC_CON14_DSP_ITCM_SPRA_PD_SHIFT) 5974 #define GRF_SOC_CON14_DSP_DTCM_SPRA_PD_SHIFT (4U) 5975 #define GRF_SOC_CON14_DSP_DTCM_SPRA_PD_MASK (0xFFFU << GRF_SOC_CON14_DSP_DTCM_SPRA_PD_SHIFT) 5976 /* SOC_CON15 */ 5977 #define GRF_SOC_CON15_OFFSET (0x23CU) 5978 #define GRF_SOC_CON15_GRF_SARADC_IEN_SHIFT (0U) 5979 #define GRF_SOC_CON15_GRF_SARADC_IEN_MASK (0xFFU << GRF_SOC_CON15_GRF_SARADC_IEN_SHIFT) 5980 /* SOC_CON16 */ 5981 #define GRF_SOC_CON16_OFFSET (0x240U) 5982 #define GRF_SOC_CON16_GRF_UART0_MULTI_IOFUNC_SRC_SEL_SHIFT (0U) 5983 #define GRF_SOC_CON16_GRF_UART0_MULTI_IOFUNC_SRC_SEL_MASK \ 5984 (0x1U << GRF_SOC_CON16_GRF_UART0_MULTI_IOFUNC_SRC_SEL_SHIFT) 5985 #define GRF_SOC_CON16_GRF_UART1_MULTI_IOFUNC_SRC_SEL_SHIFT (1U) 5986 #define GRF_SOC_CON16_GRF_UART1_MULTI_IOFUNC_SRC_SEL_MASK \ 5987 (0x3U << GRF_SOC_CON16_GRF_UART1_MULTI_IOFUNC_SRC_SEL_SHIFT) 5988 #define GRF_SOC_CON16_GRF_UART2_MULTI_IOFUNC_SRC_SEL_SHIFT (3U) 5989 #define GRF_SOC_CON16_GRF_UART2_MULTI_IOFUNC_SRC_SEL_MASK \ 5990 (0x1U << GRF_SOC_CON16_GRF_UART2_MULTI_IOFUNC_SRC_SEL_SHIFT) 5991 #define GRF_SOC_CON16_GRF_I2S_MULTI_IOFUNC_SRC_SEL_SHIFT (4U) 5992 #define GRF_SOC_CON16_GRF_I2S_MULTI_IOFUNC_SRC_SEL_MASK \ 5993 (0x1U << GRF_SOC_CON16_GRF_I2S_MULTI_IOFUNC_SRC_SEL_SHIFT) 5994 #define GRF_SOC_CON16_GRF_TOUCHKEY0_MULTI_IOFUNC_SRC_SEL_SHIFT (5U) 5995 #define GRF_SOC_CON16_GRF_TOUCHKEY0_MULTI_IOFUNC_SRC_SEL_MASK \ 5996 (0x1U << GRF_SOC_CON16_GRF_TOUCHKEY0_MULTI_IOFUNC_SRC_SEL_SHIFT) 5997 #define GRF_SOC_CON16_GRF_TOUCHKEY1_MULTI_IOFUNC_SRC_SEL_SHIFT (6U) 5998 #define GRF_SOC_CON16_GRF_TOUCHKEY1_MULTI_IOFUNC_SRC_SEL_MASK \ 5999 (0x1U << GRF_SOC_CON16_GRF_TOUCHKEY1_MULTI_IOFUNC_SRC_SEL_SHIFT) 6000 #define GRF_SOC_CON16_GRF_TOUCHKEY2_MULTI_IOFUNC_SRC_SEL_SHIFT (7U) 6001 #define GRF_SOC_CON16_GRF_TOUCHKEY2_MULTI_IOFUNC_SRC_SEL_MASK \ 6002 (0x1U << GRF_SOC_CON16_GRF_TOUCHKEY2_MULTI_IOFUNC_SRC_SEL_SHIFT) 6003 #define GRF_SOC_CON16_GRF_TOUCHKEY3_MULTI_IOFUNC_SRC_SEL_SHIFT (8U) 6004 #define GRF_SOC_CON16_GRF_TOUCHKEY3_MULTI_IOFUNC_SRC_SEL_MASK \ 6005 (0x1U << GRF_SOC_CON16_GRF_TOUCHKEY3_MULTI_IOFUNC_SRC_SEL_SHIFT) 6006 #define GRF_SOC_CON16_GRF_TOUCHKEY4_MULTI_IOFUNC_SRC_SEL_SHIFT (9U) 6007 #define GRF_SOC_CON16_GRF_TOUCHKEY4_MULTI_IOFUNC_SRC_SEL_MASK \ 6008 (0x1U << GRF_SOC_CON16_GRF_TOUCHKEY4_MULTI_IOFUNC_SRC_SEL_SHIFT) 6009 #define GRF_SOC_CON16_GRF_TOUCHKEY5_MULTI_IOFUNC_SRC_SEL_SHIFT (10U) 6010 #define GRF_SOC_CON16_GRF_TOUCHKEY5_MULTI_IOFUNC_SRC_SEL_MASK \ 6011 (0x1U << GRF_SOC_CON16_GRF_TOUCHKEY5_MULTI_IOFUNC_SRC_SEL_SHIFT) 6012 #define GRF_SOC_CON16_GRF_TOUCHKEY6_MULTI_IOFUNC_SRC_SEL_SHIFT (11U) 6013 #define GRF_SOC_CON16_GRF_TOUCHKEY6_MULTI_IOFUNC_SRC_SEL_MASK \ 6014 (0x1U << GRF_SOC_CON16_GRF_TOUCHKEY6_MULTI_IOFUNC_SRC_SEL_SHIFT) 6015 #define GRF_SOC_CON16_GRF_I2C_TRANS_REQ_SHIFT (12U) 6016 #define GRF_SOC_CON16_GRF_I2C_TRANS_REQ_MASK (0x1U << GRF_SOC_CON16_GRF_I2C_TRANS_REQ_SHIFT) 6017 #define GRF_SOC_CON16_GRF_CODEC_PMIC_MULTI_IOFUNC_SRC_SEL_SHIFT (13U) 6018 #define GRF_SOC_CON16_GRF_CODEC_PMIC_MULTI_IOFUNC_SRC_SEL_MASK \ 6019 (0x1U << GRF_SOC_CON16_GRF_CODEC_PMIC_MULTI_IOFUNC_SRC_SEL_SHIFT) 6020 #define GRF_SOC_CON16_GRF_FORCE_SEL_I2C2_SHIFT (14U) 6021 #define GRF_SOC_CON16_GRF_FORCE_SEL_I2C2_MASK (0x1U << GRF_SOC_CON16_GRF_FORCE_SEL_I2C2_SHIFT) 6022 /* SOC_CON17 */ 6023 #define GRF_SOC_CON17_OFFSET (0x244U) 6024 #define GRF_SOC_CON17_GRF_CON_CH0_REQ_ACK_SEL_SHIFT (0U) 6025 #define GRF_SOC_CON17_GRF_CON_CH0_REQ_ACK_SEL_MASK (0x3U << GRF_SOC_CON17_GRF_CON_CH0_REQ_ACK_SEL_SHIFT) 6026 #define GRF_SOC_CON17_GRF_CON_CH1_REQ_ACK_SEL_SHIFT (2U) 6027 #define GRF_SOC_CON17_GRF_CON_CH1_REQ_ACK_SEL_MASK (0x3U << GRF_SOC_CON17_GRF_CON_CH1_REQ_ACK_SEL_SHIFT) 6028 #define GRF_SOC_CON17_GRF_CON_CH2_REQ_ACK_SEL_SHIFT (4U) 6029 #define GRF_SOC_CON17_GRF_CON_CH2_REQ_ACK_SEL_MASK (0x3U << GRF_SOC_CON17_GRF_CON_CH2_REQ_ACK_SEL_SHIFT) 6030 #define GRF_SOC_CON17_GRF_CON_CH3_REQ_ACK_SEL_SHIFT (6U) 6031 #define GRF_SOC_CON17_GRF_CON_CH3_REQ_ACK_SEL_MASK (0x3U << GRF_SOC_CON17_GRF_CON_CH3_REQ_ACK_SEL_SHIFT) 6032 #define GRF_SOC_CON17_GRF_CON_CH8_REQ_ACK_SEL_SHIFT (8U) 6033 #define GRF_SOC_CON17_GRF_CON_CH8_REQ_ACK_SEL_MASK (0x3U << GRF_SOC_CON17_GRF_CON_CH8_REQ_ACK_SEL_SHIFT) 6034 /* SOC_CON18 */ 6035 #define GRF_SOC_CON18_OFFSET (0x248U) 6036 #define GRF_SOC_CON18_EFUSE_RD_MASK0_SHIFT (0U) 6037 #define GRF_SOC_CON18_EFUSE_RD_MASK0_MASK (0xFFFFFFFFU << GRF_SOC_CON18_EFUSE_RD_MASK0_SHIFT) 6038 /* SOC_CON19 */ 6039 #define GRF_SOC_CON19_OFFSET (0x24CU) 6040 #define GRF_SOC_CON19_EFUSE_RD_MASK1_SHIFT (0U) 6041 #define GRF_SOC_CON19_EFUSE_RD_MASK1_MASK (0xFFFFFFFFU << GRF_SOC_CON19_EFUSE_RD_MASK1_SHIFT) 6042 /* SOC_CON20 */ 6043 #define GRF_SOC_CON20_OFFSET (0x250U) 6044 #define GRF_SOC_CON20_EFUSE_RD_MASK2_SHIFT (0U) 6045 #define GRF_SOC_CON20_EFUSE_RD_MASK2_MASK (0xFFFFFFFFU << GRF_SOC_CON20_EFUSE_RD_MASK2_SHIFT) 6046 /* SOC_CON21 */ 6047 #define GRF_SOC_CON21_OFFSET (0x254U) 6048 #define GRF_SOC_CON21_EFUSE_RD_MASK3_SHIFT (0U) 6049 #define GRF_SOC_CON21_EFUSE_RD_MASK3_MASK (0xFFFFFFFFU << GRF_SOC_CON21_EFUSE_RD_MASK3_SHIFT) 6050 /* SOC_CON22 */ 6051 #define GRF_SOC_CON22_OFFSET (0x258U) 6052 #define GRF_SOC_CON22_EFUSE_PG_MASK0_SHIFT (0U) 6053 #define GRF_SOC_CON22_EFUSE_PG_MASK0_MASK (0xFFFFFFFFU << GRF_SOC_CON22_EFUSE_PG_MASK0_SHIFT) 6054 /* SOC_CON23 */ 6055 #define GRF_SOC_CON23_OFFSET (0x25CU) 6056 #define GRF_SOC_CON23_EFUSE_PG_MASK1_SHIFT (0U) 6057 #define GRF_SOC_CON23_EFUSE_PG_MASK1_MASK (0xFFFFFFFFU << GRF_SOC_CON23_EFUSE_PG_MASK1_SHIFT) 6058 /* SOC_CON24 */ 6059 #define GRF_SOC_CON24_OFFSET (0x260U) 6060 #define GRF_SOC_CON24_EFUSE_PG_MASK2_SHIFT (0U) 6061 #define GRF_SOC_CON24_EFUSE_PG_MASK2_MASK (0xFFFFFFFFU << GRF_SOC_CON24_EFUSE_PG_MASK2_SHIFT) 6062 /* SOC_CON25 */ 6063 #define GRF_SOC_CON25_OFFSET (0x264U) 6064 #define GRF_SOC_CON25_EFUSE_PG_MASK3_SHIFT (0U) 6065 #define GRF_SOC_CON25_EFUSE_PG_MASK3_MASK (0xFFFFFFFFU << GRF_SOC_CON25_EFUSE_PG_MASK3_SHIFT) 6066 /* SOC_CON26 */ 6067 #define GRF_SOC_CON26_OFFSET (0x268U) 6068 #define GRF_SOC_CON26_SPI2APB_ADDR_RANGE_LOW_SHIFT (0U) 6069 #define GRF_SOC_CON26_SPI2APB_ADDR_RANGE_LOW_MASK \ 6070 (0xFFFFFFFFU << GRF_SOC_CON26_SPI2APB_ADDR_RANGE_LOW_SHIFT) 6071 /* SOC_CON27 */ 6072 #define GRF_SOC_CON27_OFFSET (0x26CU) 6073 #define GRF_SOC_CON27_SPI2APB_ADDR_RANGE_HIGH_SHIFT (0U) 6074 #define GRF_SOC_CON27_SPI2APB_ADDR_RANGE_HIGH_MASK \ 6075 (0xFFFFFFFFU << GRF_SOC_CON27_SPI2APB_ADDR_RANGE_HIGH_SHIFT) 6076 /* SOC_CON28 */ 6077 #define GRF_SOC_CON28_OFFSET (0x270U) 6078 #define GRF_SOC_CON28_DMASSWFWD_PERISLVSWFWD_PWRSTALL_SHIFT (0U) 6079 #define GRF_SOC_CON28_DMASSWFWD_PERISLVSWFWD_PWRSTALL_MASK \ 6080 (0x1U << GRF_SOC_CON28_DMASSWFWD_PERISLVSWFWD_PWRSTALL_SHIFT) 6081 #define GRF_SOC_CON28_DMASSWFWD_PMUSLVSWFWD_PWRSTALL_SHIFT (1U) 6082 #define GRF_SOC_CON28_DMASSWFWD_PMUSLVSWFWD_PWRSTALL_MASK \ 6083 (0x1U << GRF_SOC_CON28_DMASSWFWD_PMUSLVSWFWD_PWRSTALL_SHIFT) 6084 #define GRF_SOC_CON28_DMASSWFWD_WIFISLVSWFWD_PWRSTALL_SHIFT (2U) 6085 #define GRF_SOC_CON28_DMASSWFWD_WIFISLVSWFWD_PWRSTALL_MASK \ 6086 (0x1U << GRF_SOC_CON28_DMASSWFWD_WIFISLVSWFWD_PWRSTALL_SHIFT) 6087 #define GRF_SOC_CON28_VADMSTSWFWD_PWRSTALL_SHIFT (3U) 6088 #define GRF_SOC_CON28_VADMSTSWFWD_PWRSTALL_MASK (0x1U << GRF_SOC_CON28_VADMSTSWFWD_PWRSTALL_SHIFT) 6089 #define GRF_SOC_CON28_WLANSRAMSWLINKFWD_PWRSTALL_SHIFT (4U) 6090 #define GRF_SOC_CON28_WLANSRAMSWLINKFWD_PWRSTALL_MASK (0x1U << GRF_SOC_CON28_WLANSRAMSWLINKFWD_PWRSTALL_SHIFT) 6091 #define GRF_SOC_CON28_PERIMSTSWLINKFWD_PWRSALL_SHIFT (5U) 6092 #define GRF_SOC_CON28_PERIMSTSWLINKFWD_PWRSALL_MASK (0x1U << GRF_SOC_CON28_PERIMSTSWLINKFWD_PWRSALL_SHIFT) 6093 /* SOC_CON29 */ 6094 #define GRF_SOC_CON29_OFFSET (0x274U) 6095 #define GRF_SOC_CON29_GRF_SARADC_ANA_REG_LOW_SHIFT (0U) 6096 #define GRF_SOC_CON29_GRF_SARADC_ANA_REG_LOW_MASK (0xFU << GRF_SOC_CON29_GRF_SARADC_ANA_REG_LOW_SHIFT) 6097 #define GRF_SOC_CON29_GRF_SARADC_VOL_SEL_SHIFT (4U) 6098 #define GRF_SOC_CON29_GRF_SARADC_VOL_SEL_MASK (0x1U << GRF_SOC_CON29_GRF_SARADC_VOL_SEL_SHIFT) 6099 #define GRF_SOC_CON29_GRF_SARADC_ANA_REG_HIGH_SHIFT (5U) 6100 #define GRF_SOC_CON29_GRF_SARADC_ANA_REG_HIGH_MASK (0x7FFU << GRF_SOC_CON29_GRF_SARADC_ANA_REG_HIGH_SHIFT) 6101 /* SOC_CON30 */ 6102 #define GRF_SOC_CON30_OFFSET (0x278U) 6103 #define GRF_SOC_CON30_GRF_TSADC_CLK_SEL_SHIFT (0U) 6104 #define GRF_SOC_CON30_GRF_TSADC_CLK_SEL_MASK (0x1U << GRF_SOC_CON30_GRF_TSADC_CLK_SEL_SHIFT) 6105 #define GRF_SOC_CON30_GRF_TSADC_DIG_BYPASS_SHIFT (1U) 6106 #define GRF_SOC_CON30_GRF_TSADC_DIG_BYPASS_MASK (0x1U << GRF_SOC_CON30_GRF_TSADC_DIG_BYPASS_SHIFT) 6107 #define GRF_SOC_CON30_GRF_TSADC_TSEN_PD_SHIFT (2U) 6108 #define GRF_SOC_CON30_GRF_TSADC_TSEN_PD_MASK (0x1U << GRF_SOC_CON30_GRF_TSADC_TSEN_PD_SHIFT) 6109 /* SOC_CON31 */ 6110 #define GRF_SOC_CON31_OFFSET (0x27CU) 6111 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG0_SHIFT (0U) 6112 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG0_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG0_SHIFT) 6113 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG1_SHIFT (1U) 6114 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG1_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG1_SHIFT) 6115 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG2_SHIFT (2U) 6116 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG2_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG2_SHIFT) 6117 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG3_SHIFT (3U) 6118 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG3_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG3_SHIFT) 6119 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG4_SHIFT (4U) 6120 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG4_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG4_SHIFT) 6121 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG5_SHIFT (5U) 6122 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG5_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG5_SHIFT) 6123 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG6_SHIFT (6U) 6124 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG6_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG6_SHIFT) 6125 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG7_SHIFT (7U) 6126 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG7_MASK (0x1U << GRF_SOC_CON31_GRF_TSADC_ANA_REG7_SHIFT) 6127 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG_SHIFT (8U) 6128 #define GRF_SOC_CON31_GRF_TSADC_ANA_REG_MASK (0xFFU << GRF_SOC_CON31_GRF_TSADC_ANA_REG_SHIFT) 6129 /* SOC_STATUS */ 6130 #define GRF_SOC_STATUS_OFFSET (0x280U) 6131 #define GRF_SOC_STATUS (0x0U) 6132 #define GRF_SOC_STATUS_GRF_ST_GPLL_LOCK_SHIFT (0U) 6133 #define GRF_SOC_STATUS_GRF_ST_GPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_GPLL_LOCK_SHIFT) 6134 #define GRF_SOC_STATUS_GRF_ST_TIMER0_EN_SHIFT (1U) 6135 #define GRF_SOC_STATUS_GRF_ST_TIMER0_EN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_TIMER0_EN_SHIFT) 6136 #define GRF_SOC_STATUS_GRF_ST_TIMER1_EN_SHIFT (2U) 6137 #define GRF_SOC_STATUS_GRF_ST_TIMER1_EN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_TIMER1_EN_SHIFT) 6138 #define GRF_SOC_STATUS_GRF_ST_TIMER2_EN_SHIFT (3U) 6139 #define GRF_SOC_STATUS_GRF_ST_TIMER2_EN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_TIMER2_EN_SHIFT) 6140 #define GRF_SOC_STATUS_GRF_ST_TIMER3_EN_SHIFT (4U) 6141 #define GRF_SOC_STATUS_GRF_ST_TIMER3_EN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_TIMER3_EN_SHIFT) 6142 #define GRF_SOC_STATUS_GRF_ST_TIMER4_EN_SHIFT (5U) 6143 #define GRF_SOC_STATUS_GRF_ST_TIMER4_EN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_TIMER4_EN_SHIFT) 6144 #define GRF_SOC_STATUS_GRF_ST_TIMER5_EN_SHIFT (6U) 6145 #define GRF_SOC_STATUS_GRF_ST_TIMER5_EN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_TIMER5_EN_SHIFT) 6146 #define GRF_SOC_STATUS_GRF_ST_VPLL_LOCK_SHIFT (7U) 6147 #define GRF_SOC_STATUS_GRF_ST_VPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_VPLL_LOCK_SHIFT) 6148 #define GRF_SOC_STATUS_GRF_ST_NPOR_BYPASSN_SHIFT (8U) 6149 #define GRF_SOC_STATUS_GRF_ST_NPOR_BYPASSN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_NPOR_BYPASSN_SHIFT) 6150 #define GRF_SOC_STATUS_GRF_ST_RTC_BYPASS_SHIFT (9U) 6151 #define GRF_SOC_STATUS_GRF_ST_RTC_BYPASS_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_RTC_BYPASS_SHIFT) 6152 #define GRF_SOC_STATUS_DCACHE0_FLUSH_ACK_SHIFT (10U) 6153 #define GRF_SOC_STATUS_DCACHE0_FLUSH_ACK_MASK (0x1U << GRF_SOC_STATUS_DCACHE0_FLUSH_ACK_SHIFT) 6154 #define GRF_SOC_STATUS_ICACHE0_FLUSH_ACK_SHIFT (11U) 6155 #define GRF_SOC_STATUS_ICACHE0_FLUSH_ACK_MASK (0x1U << GRF_SOC_STATUS_ICACHE0_FLUSH_ACK_SHIFT) 6156 #define GRF_SOC_STATUS_USB2OTG_UTMI_IDDIG_SHIFT (12U) 6157 #define GRF_SOC_STATUS_USB2OTG_UTMI_IDDIG_MASK (0x1U << GRF_SOC_STATUS_USB2OTG_UTMI_IDDIG_SHIFT) 6158 #define GRF_SOC_STATUS_USB2OTG_UTMI_BVALID_SHIFT (13U) 6159 #define GRF_SOC_STATUS_USB2OTG_UTMI_BVALID_MASK (0x1U << GRF_SOC_STATUS_USB2OTG_UTMI_BVALID_SHIFT) 6160 #define GRF_SOC_STATUS_USB2OTG_UTMI_LINESTATE_SHIFT (14U) 6161 #define GRF_SOC_STATUS_USB2OTG_UTMI_LINESTATE_MASK (0x3U << GRF_SOC_STATUS_USB2OTG_UTMI_LINESTATE_SHIFT) 6162 #define GRF_SOC_STATUS_USB2OTG_UTMI_VBUSVALID_SHIFT (16U) 6163 #define GRF_SOC_STATUS_USB2OTG_UTMI_VBUSVALID_MASK (0x1U << GRF_SOC_STATUS_USB2OTG_UTMI_VBUSVALID_SHIFT) 6164 #define GRF_SOC_STATUS_CACHE1_FLUSH_ACK_SHIFT (17U) 6165 #define GRF_SOC_STATUS_CACHE1_FLUSH_ACK_MASK (0x1U << GRF_SOC_STATUS_CACHE1_FLUSH_ACK_SHIFT) 6166 #define GRF_SOC_STATUS_GRF_ST_TIMER_1CH_EN_SHIFT (18U) 6167 #define GRF_SOC_STATUS_GRF_ST_TIMER_1CH_EN_MASK (0x1U << GRF_SOC_STATUS_GRF_ST_TIMER_1CH_EN_SHIFT) 6168 #define GRF_SOC_STATUS_GRF_CODEC_I2C_TRANS_ACK_SHIFT (19U) 6169 #define GRF_SOC_STATUS_GRF_CODEC_I2C_TRANS_ACK_MASK (0x1U << GRF_SOC_STATUS_GRF_CODEC_I2C_TRANS_ACK_SHIFT) 6170 #define GRF_SOC_STATUS_DMASSWFWD_PERISLVSWFWD_PWRACTIVE_SHIFT (20U) 6171 #define GRF_SOC_STATUS_DMASSWFWD_PERISLVSWFWD_PWRACTIVE_MASK \ 6172 (0x1U << GRF_SOC_STATUS_DMASSWFWD_PERISLVSWFWD_PWRACTIVE_SHIFT) 6173 #define GRF_SOC_STATUS_DMASSWFWD_PMUSLVSWFWD_PWRACTIVE_SHIFT (21U) 6174 #define GRF_SOC_STATUS_DMASSWFWD_PMUSLVSWFWD_PWRACTIVE_MASK \ 6175 (0x1U << GRF_SOC_STATUS_DMASSWFWD_PMUSLVSWFWD_PWRACTIVE_SHIFT) 6176 #define GRF_SOC_STATUS_DMASSWFWD_WIFISLVSWFWD_PWRACTIVE_SHIFT (22U) 6177 #define GRF_SOC_STATUS_DMASSWFWD_WIFISLVSWFWD_PWRACTIVE_MASK \ 6178 (0x1U << GRF_SOC_STATUS_DMASSWFWD_WIFISLVSWFWD_PWRACTIVE_SHIFT) 6179 #define GRF_SOC_STATUS_VADMSTSWFWD_PWRACTIVE_SHIFT (23U) 6180 #define GRF_SOC_STATUS_VADMSTSWFWD_PWRACTIVE_MASK (0x1U << GRF_SOC_STATUS_VADMSTSWFWD_PWRACTIVE_SHIFT) 6181 #define GRF_SOC_STATUS_WLANSRAMSWLINKFWD_PWRACTIVE_SHIFT (24U) 6182 #define GRF_SOC_STATUS_WLANSRAMSWLINKFWD_PWRACTIVE_MASK (0x1U << GRF_SOC_STATUS_WLANSRAMSWLINKFWD_PWRACTIVE_SHIFT) 6183 #define GRF_SOC_STATUS_PERIMSTSWLINKFWD_PWRACTIVE_SHIFT (25U) 6184 #define GRF_SOC_STATUS_PERIMSTSWLINKFWD_PWRACTIVE_MASK (0x1U << GRF_SOC_STATUS_PERIMSTSWLINKFWD_PWRACTIVE_SHIFT) 6185 /* MCU0_CON0 */ 6186 #define GRF_MCU0_CON0_OFFSET (0x300U) 6187 #define GRF_MCU0_CON0_M4_TENMS_SHIFT (0U) 6188 #define GRF_MCU0_CON0_M4_TENMS_MASK (0xFFFFFFU << GRF_MCU0_CON0_M4_TENMS_SHIFT) 6189 #define GRF_MCU0_CON0_M4_SKEW_SHIFT (24U) 6190 #define GRF_MCU0_CON0_M4_SKEW_MASK (0x1U << GRF_MCU0_CON0_M4_SKEW_SHIFT) 6191 /* MCU0_CON1 */ 6192 #define GRF_MCU0_CON1_OFFSET (0x304U) 6193 #define GRF_MCU0_CON1_GRF_CON_M4F_RXEV_SHIFT (0U) 6194 #define GRF_MCU0_CON1_GRF_CON_M4F_RXEV_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_RXEV_SHIFT) 6195 #define GRF_MCU0_CON1_GRF_CON_M4F_NMI_SHIFT (1U) 6196 #define GRF_MCU0_CON1_GRF_CON_M4F_NMI_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_NMI_SHIFT) 6197 #define GRF_MCU0_CON1_GRF_CON_M4F_EDBGRP_SHIFT (2U) 6198 #define GRF_MCU0_CON1_GRF_CON_M4F_EDBGRP_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_EDBGRP_SHIFT) 6199 #define GRF_MCU0_CON1_GRF_CON_M4F_DBGRESTART_SHIFT (3U) 6200 #define GRF_MCU0_CON1_GRF_CON_M4F_DBGRESTART_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_DBGRESTART_SHIFT) 6201 #define GRF_MCU0_CON1_GRF_CON_M4F_DBGEN_SHIFT (4U) 6202 #define GRF_MCU0_CON1_GRF_CON_M4F_DBGEN_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_DBGEN_SHIFT) 6203 #define GRF_MCU0_CON1_GRF_CON_M4F_PMU_ENABLE_SHIFT (5U) 6204 #define GRF_MCU0_CON1_GRF_CON_M4F_PMU_ENABLE_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_PMU_ENABLE_SHIFT) 6205 #define GRF_MCU0_CON1_GRF_CON_M4F_MPU_DISABLE_SHIFT (6U) 6206 #define GRF_MCU0_CON1_GRF_CON_M4F_MPU_DISABLE_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_MPU_DISABLE_SHIFT) 6207 #define GRF_MCU0_CON1_GRF_CON_M4F_FPU_DISABLE_SHIFT (7U) 6208 #define GRF_MCU0_CON1_GRF_CON_M4F_FPU_DISABLE_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4F_FPU_DISABLE_SHIFT) 6209 #define GRF_MCU0_CON1_GRF_CON_M4_DAP_FIXMASTER_SHIFT (8U) 6210 #define GRF_MCU0_CON1_GRF_CON_M4_DAP_FIXMASTER_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4_DAP_FIXMASTER_SHIFT) 6211 #define GRF_MCU0_CON1_GRF_CON_M4_DAP_DCACHE_SHIFT (9U) 6212 #define GRF_MCU0_CON1_GRF_CON_M4_DAP_DCACHE_MASK (0x1U << GRF_MCU0_CON1_GRF_CON_M4_DAP_DCACHE_SHIFT) 6213 /* MCU1_CON0 */ 6214 #define GRF_MCU1_CON0_OFFSET (0x308U) 6215 #define GRF_MCU1_CON0_GRF_CON_M0_STALIB_SHIFT (0U) 6216 #define GRF_MCU1_CON0_GRF_CON_M0_STALIB_MASK (0x3FFFFFFU << GRF_MCU1_CON0_GRF_CON_M0_STALIB_SHIFT) 6217 /* MCU1_CON1 */ 6218 #define GRF_MCU1_CON1_OFFSET (0x30CU) 6219 #define GRF_MCU1_CON1_GRF_CON_M0_RXEV_SHIFT (0U) 6220 #define GRF_MCU1_CON1_GRF_CON_M0_RXEV_MASK (0x1U << GRF_MCU1_CON1_GRF_CON_M0_RXEV_SHIFT) 6221 #define GRF_MCU1_CON1_GRF_CON_M0_NMI_SHIFT (1U) 6222 #define GRF_MCU1_CON1_GRF_CON_M0_NMI_MASK (0x1U << GRF_MCU1_CON1_GRF_CON_M0_NMI_SHIFT) 6223 #define GRF_MCU1_CON1_GRF_CON_M0_EDBGRP_SHIFT (2U) 6224 #define GRF_MCU1_CON1_GRF_CON_M0_EDBGRP_MASK (0x1U << GRF_MCU1_CON1_GRF_CON_M0_EDBGRP_SHIFT) 6225 #define GRF_MCU1_CON1_GRF_CON_M0_DBGRESTART_SHIFT (3U) 6226 #define GRF_MCU1_CON1_GRF_CON_M0_DBGRESTART_MASK (0x1U << GRF_MCU1_CON1_GRF_CON_M0_DBGRESTART_SHIFT) 6227 #define GRF_MCU1_CON1_GRF_CON_M0_DBGEN_SHIFT (4U) 6228 #define GRF_MCU1_CON1_GRF_CON_M0_DBGEN_MASK (0x1U << GRF_MCU1_CON1_GRF_CON_M0_DBGEN_SHIFT) 6229 #define GRF_MCU1_CON1_GRF_CON_M0_PMU_ENABLE_SHIFT (5U) 6230 #define GRF_MCU1_CON1_GRF_CON_M0_PMU_ENABLE_MASK (0x1U << GRF_MCU1_CON1_GRF_CON_M0_PMU_ENABLE_SHIFT) 6231 #define GRF_MCU1_CON1_GRF_CON_M0_MPU_DISABLE_SHIFT (6U) 6232 #define GRF_MCU1_CON1_GRF_CON_M0_MPU_DISABLE_MASK (0xFFU << GRF_MCU1_CON1_GRF_CON_M0_MPU_DISABLE_SHIFT) 6233 /* DSP_CON0 */ 6234 #define GRF_DSP_CON0_OFFSET (0x320U) 6235 #define GRF_DSP_CON0_OCDHALTONRESET_SHIFT (0U) 6236 #define GRF_DSP_CON0_OCDHALTONRESET_MASK (0x1U << GRF_DSP_CON0_OCDHALTONRESET_SHIFT) 6237 #define GRF_DSP_CON0_BREAKIN_SHIFT (1U) 6238 #define GRF_DSP_CON0_BREAKIN_MASK (0x1U << GRF_DSP_CON0_BREAKIN_SHIFT) 6239 #define GRF_DSP_CON0_BREAKOUTACK_SHIFT (2U) 6240 #define GRF_DSP_CON0_BREAKOUTACK_MASK (0x1U << GRF_DSP_CON0_BREAKOUTACK_SHIFT) 6241 #define GRF_DSP_CON0_STATVECTORSEL_SHIFT (4U) 6242 #define GRF_DSP_CON0_STATVECTORSEL_MASK (0x1U << GRF_DSP_CON0_STATVECTORSEL_SHIFT) 6243 #define GRF_DSP_CON0_RUNSTALL_SHIFT (5U) 6244 #define GRF_DSP_CON0_RUNSTALL_MASK (0x1U << GRF_DSP_CON0_RUNSTALL_SHIFT) 6245 /* DSP_CON1 */ 6246 #define GRF_DSP_CON1_OFFSET (0x324U) 6247 #define GRF_DSP_CON1_ALTRESETVEC_SHIFT (0U) 6248 #define GRF_DSP_CON1_ALTRESETVEC_MASK (0xFFFFFFFFU << GRF_DSP_CON1_ALTRESETVEC_SHIFT) 6249 /* DSP_CON2 */ 6250 #define GRF_DSP_CON2_OFFSET (0x328U) 6251 #define GRF_DSP_CON2_ICACHE_MEM_AUTO_GATING_EN_SHIFT (0U) 6252 #define GRF_DSP_CON2_ICACHE_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_ICACHE_MEM_AUTO_GATING_EN_SHIFT) 6253 #define GRF_DSP_CON2_ITAG_MEM_AUTO_GATING_EN_SHIFT (1U) 6254 #define GRF_DSP_CON2_ITAG_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_ITAG_MEM_AUTO_GATING_EN_SHIFT) 6255 #define GRF_DSP_CON2_DCACHE_MEM_AUTO_GATING_EN_SHIFT (2U) 6256 #define GRF_DSP_CON2_DCACHE_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_DCACHE_MEM_AUTO_GATING_EN_SHIFT) 6257 #define GRF_DSP_CON2_DTAG_MEM_AUTO_GATING_EN_SHIFT (3U) 6258 #define GRF_DSP_CON2_DTAG_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_DTAG_MEM_AUTO_GATING_EN_SHIFT) 6259 #define GRF_DSP_CON2_PREFETCH_RAM_AUTO_GATING_EN_SHIFT (4U) 6260 #define GRF_DSP_CON2_PREFETCH_RAM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_PREFETCH_RAM_AUTO_GATING_EN_SHIFT) 6261 #define GRF_DSP_CON2_DTCM_MEM_AUTO_GATING_EN_SHIFT (5U) 6262 #define GRF_DSP_CON2_DTCM_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_DTCM_MEM_AUTO_GATING_EN_SHIFT) 6263 #define GRF_DSP_CON2_ITCM_MEM_AUTO_GATING_EN_SHIFT (6U) 6264 #define GRF_DSP_CON2_ITCM_MEM_AUTO_GATING_EN_MASK (0x1U << GRF_DSP_CON2_ITCM_MEM_AUTO_GATING_EN_SHIFT) 6265 /* SOC_UOC0 */ 6266 #define GRF_SOC_UOC0_OFFSET (0x340U) 6267 #define GRF_SOC_UOC0_OTGPHY_COMMON_ON_N_SHIFT (0U) 6268 #define GRF_SOC_UOC0_OTGPHY_COMMON_ON_N_MASK (0x1U << GRF_SOC_UOC0_OTGPHY_COMMON_ON_N_SHIFT) 6269 #define GRF_SOC_UOC0_OTGPHY_COMPDISTUNE_SHIFT (1U) 6270 #define GRF_SOC_UOC0_OTGPHY_COMPDISTUNE_MASK (0x7U << GRF_SOC_UOC0_OTGPHY_COMPDISTUNE_SHIFT) 6271 #define GRF_SOC_UOC0_OTGPHY_DISABLE_SHIFT (4U) 6272 #define GRF_SOC_UOC0_OTGPHY_DISABLE_MASK (0x1U << GRF_SOC_UOC0_OTGPHY_DISABLE_SHIFT) 6273 #define GRF_SOC_UOC0_OTGPHY_TUNE_SHIFT (5U) 6274 #define GRF_SOC_UOC0_OTGPHY_TUNE_MASK (0x7U << GRF_SOC_UOC0_OTGPHY_TUNE_SHIFT) 6275 #define GRF_SOC_UOC0_OTGPHY_REFCLKDIV_SHIFT (8U) 6276 #define GRF_SOC_UOC0_OTGPHY_REFCLKDIV_MASK (0x3U << GRF_SOC_UOC0_OTGPHY_REFCLKDIV_SHIFT) 6277 #define GRF_SOC_UOC0_OTGPHY_REFCLKSEL_SHIFT (10U) 6278 #define GRF_SOC_UOC0_OTGPHY_REFCLKSEL_MASK (0x3U << GRF_SOC_UOC0_OTGPHY_REFCLKSEL_SHIFT) 6279 #define GRF_SOC_UOC0_OTGPHY_PORT_RESET_SHIFT (12U) 6280 #define GRF_SOC_UOC0_OTGPHY_PORT_RESET_MASK (0x1U << GRF_SOC_UOC0_OTGPHY_PORT_RESET_SHIFT) 6281 #define GRF_SOC_UOC0_OTGPHY_SIDDQ_SHIFT (13U) 6282 #define GRF_SOC_UOC0_OTGPHY_SIDDQ_MASK (0x1U << GRF_SOC_UOC0_OTGPHY_SIDDQ_SHIFT) 6283 #define GRF_SOC_UOC0_OTGPHY_TXBITSTUFFEN_SHIFT (14U) 6284 #define GRF_SOC_UOC0_OTGPHY_TXBITSTUFFEN_MASK (0x1U << GRF_SOC_UOC0_OTGPHY_TXBITSTUFFEN_SHIFT) 6285 #define GRF_SOC_UOC0_OTGPHY_TXBITSTUFFENH_SHIFT (15U) 6286 #define GRF_SOC_UOC0_OTGPHY_TXBITSTUFFENH_MASK (0x1U << GRF_SOC_UOC0_OTGPHY_TXBITSTUFFENH_SHIFT) 6287 /* SOC_UOC1 */ 6288 #define GRF_SOC_UOC1_OFFSET (0x344U) 6289 #define GRF_SOC_UOC1_OTGPHY_SQRXTUNE_SHIFT (0U) 6290 #define GRF_SOC_UOC1_OTGPHY_SQRXTUNE_MASK (0x7U << GRF_SOC_UOC1_OTGPHY_SQRXTUNE_SHIFT) 6291 #define GRF_SOC_UOC1_OTGPHY_TXPREEMPHASISTUNE_SHIFT (3U) 6292 #define GRF_SOC_UOC1_OTGPHY_TXPREEMPHASISTUNE_MASK (0x1U << GRF_SOC_UOC1_OTGPHY_TXPREEMPHASISTUNE_SHIFT) 6293 #define GRF_SOC_UOC1_OTGPHY_TXFSLSTUNE_SHIFT (4U) 6294 #define GRF_SOC_UOC1_OTGPHY_TXFSLSTUNE_MASK (0xFU << GRF_SOC_UOC1_OTGPHY_TXFSLSTUNE_SHIFT) 6295 #define GRF_SOC_UOC1_TOGPHY_TXVREFTUNE_SHIFT (8U) 6296 #define GRF_SOC_UOC1_TOGPHY_TXVREFTUNE_MASK (0xFU << GRF_SOC_UOC1_TOGPHY_TXVREFTUNE_SHIFT) 6297 #define GRF_SOC_UOC1_OTGPHY_TXHSXVTUNE_SHIFT (12U) 6298 #define GRF_SOC_UOC1_OTGPHY_TXHSXVTUNE_MASK (0x3U << GRF_SOC_UOC1_OTGPHY_TXHSXVTUNE_SHIFT) 6299 #define GRF_SOC_UOC1_OTGPHY_TXRISETUNE_SHIFT (14U) 6300 #define GRF_SOC_UOC1_OTGPHY_TXRISETUNE_MASK (0x1U << GRF_SOC_UOC1_OTGPHY_TXRISETUNE_SHIFT) 6301 /* SOC_UOC2 */ 6302 #define GRF_SOC_UOC2_OFFSET (0x348U) 6303 #define GRF_SOC_UOC2_OTGPHY_VBUSVLDEXT_SHIFT (0U) 6304 #define GRF_SOC_UOC2_OTGPHY_VBUSVLDEXT_MASK (0x1U << GRF_SOC_UOC2_OTGPHY_VBUSVLDEXT_SHIFT) 6305 #define GRF_SOC_UOC2_OTGPHY_VBUSVLDEXTSEL_SHIFT (1U) 6306 #define GRF_SOC_UOC2_OTGPHY_VBUSVLDEXTSEL_MASK (0x1U << GRF_SOC_UOC2_OTGPHY_VBUSVLDEXTSEL_SHIFT) 6307 #define GRF_SOC_UOC2_OTGPHY_SOFT_CON_SEL_SHIFT (2U) 6308 #define GRF_SOC_UOC2_OTGPHY_SOFT_CON_SEL_MASK (0x1U << GRF_SOC_UOC2_OTGPHY_SOFT_CON_SEL_SHIFT) 6309 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_SUSPEND_N_SHIFT (3U) 6310 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_SUSPEND_N_MASK (0x1U << GRF_SOC_UOC2_GRF_CON_OTG_UTMI_SUSPEND_N_SHIFT) 6311 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_OPMODE_SHIFT (4U) 6312 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_OPMODE_MASK (0x3U << GRF_SOC_UOC2_GRF_CON_OTG_UTMI_OPMODE_SHIFT) 6313 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_XCVRSELECT_SHIFT (6U) 6314 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_XCVRSELECT_MASK (0x3U << GRF_SOC_UOC2_GRF_CON_OTG_UTMI_XCVRSELECT_SHIFT) 6315 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_TERMSELECT_SHIFT (8U) 6316 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_TERMSELECT_MASK (0x1U << GRF_SOC_UOC2_GRF_CON_OTG_UTMI_TERMSELECT_SHIFT) 6317 #define GRF_SOC_UOC2_OTGPHY_VREGTUNE_SHIFT (9U) 6318 #define GRF_SOC_UOC2_OTGPHY_VREGTUNE_MASK (0x1U << GRF_SOC_UOC2_OTGPHY_VREGTUNE_SHIFT) 6319 #define GRF_SOC_UOC2_OTGPHY_SLEEPM_SHIFT (10U) 6320 #define GRF_SOC_UOC2_OTGPHY_SLEEPM_MASK (0x1U << GRF_SOC_UOC2_OTGPHY_SLEEPM_SHIFT) 6321 #define GRF_SOC_UOC2_GRF_CON_OTG_SCALEDOWN_MODE_SHIFT (11U) 6322 #define GRF_SOC_UOC2_GRF_CON_OTG_SCALEDOWN_MODE_MASK (0x3U << GRF_SOC_UOC2_GRF_CON_OTG_SCALEDOWN_MODE_SHIFT) 6323 #define GRF_SOC_UOC2_GRF_CON_OTG_DBNCE_FLTR_BYPASS_SHIFT (13U) 6324 #define GRF_SOC_UOC2_GRF_CON_OTG_DBNCE_FLTR_BYPASS_MASK (0x1U << GRF_SOC_UOC2_GRF_CON_OTG_DBNCE_FLTR_BYPASS_SHIFT) 6325 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_IDDIG_PMU_SHIFT (14U) 6326 #define GRF_SOC_UOC2_GRF_CON_OTG_UTMI_IDDIG_PMU_MASK (0x1U << GRF_SOC_UOC2_GRF_CON_OTG_UTMI_IDDIG_PMU_SHIFT) 6327 /* MCU0_STATUS */ 6328 #define GRF_MCU0_STATUS_OFFSET (0x380U) 6329 #define GRF_MCU0_STATUS (0x0U) 6330 #define GRF_MCU0_STATUS_GRF_ST_M4F_SLEEPING_SHIFT (0U) 6331 #define GRF_MCU0_STATUS_GRF_ST_M4F_SLEEPING_MASK (0x1U << GRF_MCU0_STATUS_GRF_ST_M4F_SLEEPING_SHIFT) 6332 #define GRF_MCU0_STATUS_GRF_ST_M4F_SLEEPDEEP_SHIFT (1U) 6333 #define GRF_MCU0_STATUS_GRF_ST_M4F_SLEEPDEEP_MASK (0x1U << GRF_MCU0_STATUS_GRF_ST_M4F_SLEEPDEEP_SHIFT) 6334 #define GRF_MCU0_STATUS_GRF_ST_M4F_HALTED_SHIFT (2U) 6335 #define GRF_MCU0_STATUS_GRF_ST_M4F_HALTED_MASK (0x1U << GRF_MCU0_STATUS_GRF_ST_M4F_HALTED_SHIFT) 6336 #define GRF_MCU0_STATUS_GRF_ST_M4F_DEGRESTARTED_SHIFT (3U) 6337 #define GRF_MCU0_STATUS_GRF_ST_M4F_DEGRESTARTED_MASK (0x1U << GRF_MCU0_STATUS_GRF_ST_M4F_DEGRESTARTED_SHIFT) 6338 #define GRF_MCU0_STATUS_GRF_ST_M4F_GATEHCLK_SHIFT (4U) 6339 #define GRF_MCU0_STATUS_GRF_ST_M4F_GATEHCLK_MASK (0x1U << GRF_MCU0_STATUS_GRF_ST_M4F_GATEHCLK_SHIFT) 6340 #define GRF_MCU0_STATUS_GRF_ST_M4F_LOCKUP_SHIFT (5U) 6341 #define GRF_MCU0_STATUS_GRF_ST_M4F_LOCKUP_MASK (0x1U << GRF_MCU0_STATUS_GRF_ST_M4F_LOCKUP_SHIFT) 6342 #define GRF_MCU0_STATUS_GRF_ST_M4F_CURRPRI_SHIFT (8U) 6343 #define GRF_MCU0_STATUS_GRF_ST_M4F_CURRPRI_MASK (0xFFU << GRF_MCU0_STATUS_GRF_ST_M4F_CURRPRI_SHIFT) 6344 #define GRF_MCU0_STATUS_M4_FPIXC_SHIFT (16U) 6345 #define GRF_MCU0_STATUS_M4_FPIXC_MASK (0x1U << GRF_MCU0_STATUS_M4_FPIXC_SHIFT) 6346 #define GRF_MCU0_STATUS_M4_FPOFC_SHIFT (17U) 6347 #define GRF_MCU0_STATUS_M4_FPOFC_MASK (0x1U << GRF_MCU0_STATUS_M4_FPOFC_SHIFT) 6348 #define GRF_MCU0_STATUS_M4_FPUFC_SHIFT (18U) 6349 #define GRF_MCU0_STATUS_M4_FPUFC_MASK (0x1U << GRF_MCU0_STATUS_M4_FPUFC_SHIFT) 6350 #define GRF_MCU0_STATUS_M4_FPIOC_SHIFT (19U) 6351 #define GRF_MCU0_STATUS_M4_FPIOC_MASK (0x1U << GRF_MCU0_STATUS_M4_FPIOC_SHIFT) 6352 #define GRF_MCU0_STATUS_M4_FPDZC_SHIFT (20U) 6353 #define GRF_MCU0_STATUS_M4_FPDZC_MASK (0x1U << GRF_MCU0_STATUS_M4_FPDZC_SHIFT) 6354 #define GRF_MCU0_STATUS_M4_FPIDC_SHIFT (21U) 6355 #define GRF_MCU0_STATUS_M4_FPIDC_MASK (0x1U << GRF_MCU0_STATUS_M4_FPIDC_SHIFT) 6356 /* MCU1_STATUS */ 6357 #define GRF_MCU1_STATUS_OFFSET (0x384U) 6358 #define GRF_MCU1_STATUS_GRF_ST_M0_DBGRESTARTED_SHIFT (0U) 6359 #define GRF_MCU1_STATUS_GRF_ST_M0_DBGRESTARTED_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_DBGRESTARTED_SHIFT) 6360 #define GRF_MCU1_STATUS_GRF_ST_M0_HALTED_SHIFT (1U) 6361 #define GRF_MCU1_STATUS_GRF_ST_M0_HALTED_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_HALTED_SHIFT) 6362 #define GRF_MCU1_STATUS_GRF_ST_M0_TXEV_SHIFT (2U) 6363 #define GRF_MCU1_STATUS_GRF_ST_M0_TXEV_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_TXEV_SHIFT) 6364 #define GRF_MCU1_STATUS_GRF_ST_M0_LOCKUP_SHIFT (3U) 6365 #define GRF_MCU1_STATUS_GRF_ST_M0_LOCKUP_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_LOCKUP_SHIFT) 6366 #define GRF_MCU1_STATUS_GRF_ST_M0_HCLK_GATE_SHIFT (4U) 6367 #define GRF_MCU1_STATUS_GRF_ST_M0_HCLK_GATE_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_HCLK_GATE_SHIFT) 6368 #define GRF_MCU1_STATUS_GRF_ST_M0_WAKEUP_SHIFT (5U) 6369 #define GRF_MCU1_STATUS_GRF_ST_M0_WAKEUP_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_WAKEUP_SHIFT) 6370 #define GRF_MCU1_STATUS_GRF_ST_M0_SLEEPDEEP_SHIFT (6U) 6371 #define GRF_MCU1_STATUS_GRF_ST_M0_SLEEPDEEP_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_SLEEPDEEP_SHIFT) 6372 #define GRF_MCU1_STATUS_GRF_ST_M0_SLEEPING_SHIFT (7U) 6373 #define GRF_MCU1_STATUS_GRF_ST_M0_SLEEPING_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_SLEEPING_SHIFT) 6374 #define GRF_MCU1_STATUS_GRF_ST_M0_SLEEPHOLDACKN_SHIFT (8U) 6375 #define GRF_MCU1_STATUS_GRF_ST_M0_SLEEPHOLDACKN_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_SLEEPHOLDACKN_SHIFT) 6376 #define GRF_MCU1_STATUS_GRF_ST_M0_WICENACK_SHIFT (9U) 6377 #define GRF_MCU1_STATUS_GRF_ST_M0_WICENACK_MASK (0x1U << GRF_MCU1_STATUS_GRF_ST_M0_WICENACK_SHIFT) 6378 /* DSP_STAT0 */ 6379 #define GRF_DSP_STAT0_OFFSET (0x388U) 6380 #define GRF_DSP_STAT0 (0x0U) 6381 #define GRF_DSP_STAT0_XOCDMODE_SHIFT (0U) 6382 #define GRF_DSP_STAT0_XOCDMODE_MASK (0x1U << GRF_DSP_STAT0_XOCDMODE_SHIFT) 6383 #define GRF_DSP_STAT0_DEBUGMODE_SHIFT (1U) 6384 #define GRF_DSP_STAT0_DEBUGMODE_MASK (0x1U << GRF_DSP_STAT0_DEBUGMODE_SHIFT) 6385 #define GRF_DSP_STAT0_BREAKINACK_SHIFT (2U) 6386 #define GRF_DSP_STAT0_BREAKINACK_MASK (0x1U << GRF_DSP_STAT0_BREAKINACK_SHIFT) 6387 #define GRF_DSP_STAT0_BREAKOUT_SHIFT (3U) 6388 #define GRF_DSP_STAT0_BREAKOUT_MASK (0x1U << GRF_DSP_STAT0_BREAKOUT_SHIFT) 6389 #define GRF_DSP_STAT0_DOUBLEEXCEPTIONERROR_SHIFT (4U) 6390 #define GRF_DSP_STAT0_DOUBLEEXCEPTIONERROR_MASK (0x1U << GRF_DSP_STAT0_DOUBLEEXCEPTIONERROR_SHIFT) 6391 #define GRF_DSP_STAT0_PFATALERROR_SHIFT (5U) 6392 #define GRF_DSP_STAT0_PFATALERROR_MASK (0x1U << GRF_DSP_STAT0_PFATALERROR_SHIFT) 6393 #define GRF_DSP_STAT0_PFAULTINFOVALID_SHIFT (6U) 6394 #define GRF_DSP_STAT0_PFAULTINFOVALID_MASK (0x1U << GRF_DSP_STAT0_PFAULTINFOVALID_SHIFT) 6395 #define GRF_DSP_STAT0_PWAITMODE_SHIFT (7U) 6396 #define GRF_DSP_STAT0_PWAITMODE_MASK (0x1U << GRF_DSP_STAT0_PWAITMODE_SHIFT) 6397 #define GRF_DSP_STAT0_IRAM0LADSTORE_SHIFT (8U) 6398 #define GRF_DSP_STAT0_IRAM0LADSTORE_MASK (0x1U << GRF_DSP_STAT0_IRAM0LADSTORE_SHIFT) 6399 /* DSP_STAT1 */ 6400 #define GRF_DSP_STAT1_OFFSET (0x38CU) 6401 #define GRF_DSP_STAT1 (0x0U) 6402 #define GRF_DSP_STAT1_PFAULTINFO_SHIFT (0U) 6403 #define GRF_DSP_STAT1_PFAULTINFO_MASK (0xFFFFFFFFU << GRF_DSP_STAT1_PFAULTINFO_SHIFT) 6404 /* GRF_FAST_BOOT */ 6405 #define GRF_GRF_FAST_BOOT_OFFSET (0x400U) 6406 #define GRF_GRF_FAST_BOOT_GRF_FAST_BOOT_SHIFT (0U) 6407 #define GRF_GRF_FAST_BOOT_GRF_FAST_BOOT_MASK (0x1U << GRF_GRF_FAST_BOOT_GRF_FAST_BOOT_SHIFT) 6408 /* GRF_FAST_BOOT_ADDR */ 6409 #define GRF_GRF_FAST_BOOT_ADDR_OFFSET (0x404U) 6410 #define GRF_GRF_FAST_BOOT_ADDR_GRF_FAST_BOOT_ADDR_SHIFT (0U) 6411 #define GRF_GRF_FAST_BOOT_ADDR_GRF_FAST_BOOT_ADDR_MASK \ 6412 (0xFFFFFFFFU << GRF_GRF_FAST_BOOT_ADDR_GRF_FAST_BOOT_ADDR_SHIFT) 6413 /* WLAN_CON */ 6414 #define GRF_WLAN_CON_OFFSET (0x500U) 6415 #define GRF_WLAN_CON_XTALMOD_0_SHIFT (0U) 6416 #define GRF_WLAN_CON_XTALMOD_0_MASK (0x1U << GRF_WLAN_CON_XTALMOD_0_SHIFT) 6417 #define GRF_WLAN_CON_XTALMOD_1_SHIFT (1U) 6418 #define GRF_WLAN_CON_XTALMOD_1_MASK (0x1U << GRF_WLAN_CON_XTALMOD_1_SHIFT) 6419 #define GRF_WLAN_CON_XTALMOD_2_SHIFT (2U) 6420 #define GRF_WLAN_CON_XTALMOD_2_MASK (0x1U << GRF_WLAN_CON_XTALMOD_2_SHIFT) 6421 #define GRF_WLAN_CON_WLAN_WRITE_INT_EN_SHIFT (3U) 6422 #define GRF_WLAN_CON_WLAN_WRITE_INT_EN_MASK (0x1U << GRF_WLAN_CON_WLAN_WRITE_INT_EN_SHIFT) 6423 #define GRF_WLAN_CON_RPU_SLEEP_IRQ_EN_SHIFT (4U) 6424 #define GRF_WLAN_CON_RPU_SLEEP_IRQ_EN_MASK (0x1U << GRF_WLAN_CON_RPU_SLEEP_IRQ_EN_SHIFT) 6425 #define GRF_WLAN_CON_RPU_WAKEUP_IRQ_EN_SHIFT (5U) 6426 #define GRF_WLAN_CON_RPU_WAKEUP_IRQ_EN_MASK (0x1U << GRF_WLAN_CON_RPU_WAKEUP_IRQ_EN_SHIFT) 6427 #define GRF_WLAN_CON_RPU_READY_IRQ_EN_SHIFT (6U) 6428 #define GRF_WLAN_CON_RPU_READY_IRQ_EN_MASK (0x1U << GRF_WLAN_CON_RPU_READY_IRQ_EN_SHIFT) 6429 #define GRF_WLAN_CON_WLAN_EXT_IRQ_SHIFT (7U) 6430 #define GRF_WLAN_CON_WLAN_EXT_IRQ_MASK (0x1U << GRF_WLAN_CON_WLAN_EXT_IRQ_SHIFT) 6431 #define GRF_WLAN_CON_WLAN_REV_SHIFT (8U) 6432 #define GRF_WLAN_CON_WLAN_REV_MASK (0xFFU << GRF_WLAN_CON_WLAN_REV_SHIFT) 6433 /* WLANCLK_CON */ 6434 #define GRF_WLANCLK_CON_OFFSET (0x504U) 6435 #define GRF_WLANCLK_CON_WLAN_SYS_CLK_GATE_SHIFT (0U) 6436 #define GRF_WLANCLK_CON_WLAN_SYS_CLK_GATE_MASK (0x1U << GRF_WLANCLK_CON_WLAN_SYS_CLK_GATE_SHIFT) 6437 #define GRF_WLANCLK_CON_RPU_CLK_FLEVEL_SHIFT (1U) 6438 #define GRF_WLANCLK_CON_RPU_CLK_FLEVEL_MASK (0x1U << GRF_WLANCLK_CON_RPU_CLK_FLEVEL_SHIFT) 6439 #define GRF_WLANCLK_CON_RPU_CLK_FORCE_SHIFT (2U) 6440 #define GRF_WLANCLK_CON_RPU_CLK_FORCE_MASK (0x1U << GRF_WLANCLK_CON_RPU_CLK_FORCE_SHIFT) 6441 #define GRF_WLANCLK_CON_MCU_CLK_FLEVEL_SHIFT (3U) 6442 #define GRF_WLANCLK_CON_MCU_CLK_FLEVEL_MASK (0x1U << GRF_WLANCLK_CON_MCU_CLK_FLEVEL_SHIFT) 6443 #define GRF_WLANCLK_CON_MCU_CLK_FORCE_SHIFT (4U) 6444 #define GRF_WLANCLK_CON_MCU_CLK_FORCE_MASK (0x1U << GRF_WLANCLK_CON_MCU_CLK_FORCE_SHIFT) 6445 #define GRF_WLANCLK_CON_WLAN_AON_WAKEUP_SHIFT (5U) 6446 #define GRF_WLANCLK_CON_WLAN_AON_WAKEUP_MASK (0x1U << GRF_WLANCLK_CON_WLAN_AON_WAKEUP_SHIFT) 6447 #define GRF_WLANCLK_CON_BT_PTI1_SHIFT (6U) 6448 #define GRF_WLANCLK_CON_BT_PTI1_MASK (0x1U << GRF_WLANCLK_CON_BT_PTI1_SHIFT) 6449 /* WLAN_GPIO_IN */ 6450 #define GRF_WLAN_GPIO_IN_OFFSET (0x508U) 6451 #define GRF_WLAN_GPIO_IN_WLAN_GPIO_IN_SHIFT (0U) 6452 #define GRF_WLAN_GPIO_IN_WLAN_GPIO_IN_MASK (0xFFFFFFFFU << GRF_WLAN_GPIO_IN_WLAN_GPIO_IN_SHIFT) 6453 /* WLAN_GPIO_OUT */ 6454 #define GRF_WLAN_GPIO_OUT_OFFSET (0x50CU) 6455 #define GRF_WLAN_GPIO_OUT_WLAN_GPIO_OUT_SHIFT (0U) 6456 #define GRF_WLAN_GPIO_OUT_WLAN_GPIO_OUT_MASK (0xFFFFFFFFU << GRF_WLAN_GPIO_OUT_WLAN_GPIO_OUT_SHIFT) 6457 /* WLAN_STATUS */ 6458 #define GRF_WLAN_STATUS_OFFSET (0x580U) 6459 #define GRF_WLAN_STATUS_RPU_SLEEP_SHIFT (0U) 6460 #define GRF_WLAN_STATUS_RPU_SLEEP_MASK (0x1U << GRF_WLAN_STATUS_RPU_SLEEP_SHIFT) 6461 #define GRF_WLAN_STATUS_RPU_WAKEUP_SHIFT (1U) 6462 #define GRF_WLAN_STATUS_RPU_WAKEUP_MASK (0x1U << GRF_WLAN_STATUS_RPU_WAKEUP_SHIFT) 6463 #define GRF_WLAN_STATUS_RPU_READY_STATUS_SHIFT (2U) 6464 #define GRF_WLAN_STATUS_RPU_READY_STATUS_MASK (0x1U << GRF_WLAN_STATUS_RPU_READY_STATUS_SHIFT) 6465 #define GRF_WLAN_STATUS_WLAN_WRITE_DATA_INT_STATUS_SHIFT (3U) 6466 #define GRF_WLAN_STATUS_WLAN_WRITE_DATA_INT_STATUS_MASK (0x1U << GRF_WLAN_STATUS_WLAN_WRITE_DATA_INT_STATUS_SHIFT) 6467 #define GRF_WLAN_STATUS_WLAN_MAC_PHY_DEBUG_BUS_SHIFT (4U) 6468 #define GRF_WLAN_STATUS_WLAN_MAC_PHY_DEBUG_BUS_MASK (0xFFFU << GRF_WLAN_STATUS_WLAN_MAC_PHY_DEBUG_BUS_SHIFT) 6469 /* USB2_DISCONNECT_CON */ 6470 #define GRF_USB2_DISCONNECT_CON_OFFSET (0x680U) 6471 #define GRF_USB2_DISCONNECT_CON_DISCONNECT_FILTER_CON_SHIFT (0U) 6472 #define GRF_USB2_DISCONNECT_CON_DISCONNECT_FILTER_CON_MASK \ 6473 (0xFFFFFFFFU << GRF_USB2_DISCONNECT_CON_DISCONNECT_FILTER_CON_SHIFT) 6474 /* USB2_LINESTATE_CON */ 6475 #define GRF_USB2_LINESTATE_CON_OFFSET (0x684U) 6476 #define GRF_USB2_LINESTATE_CON_LINESTATE_FILTER_CON_SHIFT (0U) 6477 #define GRF_USB2_LINESTATE_CON_LINESTATE_FILTER_CON_MASK \ 6478 (0xFFFFFFFFU << GRF_USB2_LINESTATE_CON_LINESTATE_FILTER_CON_SHIFT) 6479 /* USB2_BVALID_CON */ 6480 #define GRF_USB2_BVALID_CON_OFFSET (0x688U) 6481 #define GRF_USB2_BVALID_CON_BVALID_FILTER_CON_SHIFT (0U) 6482 #define GRF_USB2_BVALID_CON_BVALID_FILTER_CON_MASK \ 6483 (0xFFFFFFFFU << GRF_USB2_BVALID_CON_BVALID_FILTER_CON_SHIFT) 6484 /* USB2_ID_CON */ 6485 #define GRF_USB2_ID_CON_OFFSET (0x68CU) 6486 #define GRF_USB2_ID_CON_ID_FILTER_CON_SHIFT (0U) 6487 #define GRF_USB2_ID_CON_ID_FILTER_CON_MASK (0xFFFFFFFFU << GRF_USB2_ID_CON_ID_FILTER_CON_SHIFT) 6488 /* USB2_DETECT_IRQ_ENABLE */ 6489 #define GRF_USB2_DETECT_IRQ_ENABLE_OFFSET (0x690U) 6490 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_LINESTATE_IRQ_EN_SHIFT (0U) 6491 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_LINESTATE_IRQ_EN_MASK \ 6492 (0x1U << GRF_USB2_DETECT_IRQ_ENABLE_OTG0_LINESTATE_IRQ_EN_SHIFT) 6493 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_BVALID_POS_IRQ_EN_SHIFT (1U) 6494 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_BVALID_POS_IRQ_EN_MASK \ 6495 (0x1U << GRF_USB2_DETECT_IRQ_ENABLE_OTG0_BVALID_POS_IRQ_EN_SHIFT) 6496 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_BVALID_NEG_IRQ_EN_SHIFT (2U) 6497 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_BVALID_NEG_IRQ_EN_MASK \ 6498 (0x1U << GRF_USB2_DETECT_IRQ_ENABLE_OTG0_BVALID_NEG_IRQ_EN_SHIFT) 6499 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_ID_POS_IRQ_EN_SHIFT (3U) 6500 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_ID_POS_IRQ_EN_MASK \ 6501 (0x1U << GRF_USB2_DETECT_IRQ_ENABLE_OTG0_ID_POS_IRQ_EN_SHIFT) 6502 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_ID_NEG_IRQ_EN_SHIFT (4U) 6503 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_ID_NEG_IRQ_EN_MASK \ 6504 (0x1U << GRF_USB2_DETECT_IRQ_ENABLE_OTG0_ID_NEG_IRQ_EN_SHIFT) 6505 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_DISCONNECT_POS_IRQ_EN_SHIFT (5U) 6506 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_DISCONNECT_POS_IRQ_EN_MASK \ 6507 (0x1U << GRF_USB2_DETECT_IRQ_ENABLE_OTG0_DISCONNECT_POS_IRQ_EN_SHIFT) 6508 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_DISCONNECT_NEG_IRQ_EN_SHIFT (6U) 6509 #define GRF_USB2_DETECT_IRQ_ENABLE_OTG0_DISCONNECT_NEG_IRQ_EN_MASK \ 6510 (0x1U << GRF_USB2_DETECT_IRQ_ENABLE_OTG0_DISCONNECT_NEG_IRQ_EN_SHIFT) 6511 /* USB2_DETECT_IRQ_STATUS */ 6512 #define GRF_USB2_DETECT_IRQ_STATUS_OFFSET (0x694U) 6513 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_LINESTATE_IRQ_SHIFT (0U) 6514 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_LINESTATE_IRQ_MASK \ 6515 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_OTG0_LINESTATE_IRQ_SHIFT) 6516 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_BVALID_POS_IRQ_SHIFT (1U) 6517 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_BVALID_POS_IRQ_MASK \ 6518 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_OTG0_BVALID_POS_IRQ_SHIFT) 6519 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_BVALID_NEG_IRQ_SHIFT (2U) 6520 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_BVALID_NEG_IRQ_MASK \ 6521 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_OTG0_BVALID_NEG_IRQ_SHIFT) 6522 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_ID_POS_IRQ_SHIFT (3U) 6523 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_ID_POS_IRQ_MASK \ 6524 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_OTG0_ID_POS_IRQ_SHIFT) 6525 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_ID_NEG_IRQ_SHIFT (4U) 6526 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_ID_NEG_IRQ_MASK \ 6527 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_OTG0_ID_NEG_IRQ_SHIFT) 6528 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_DISCONNECT_POS_IRQ_SHIFT (5U) 6529 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_DISCONNECT_POS_IRQ_MASK \ 6530 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_OTG0_DISCONNECT_POS_IRQ_SHIFT) 6531 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_DISCONNECT_NEG_IRQ_SHIFT (6U) 6532 #define GRF_USB2_DETECT_IRQ_STATUS_OTG0_DISCONNECT_NEG_IRQ_MASK \ 6533 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_OTG0_DISCONNECT_NEG_IRQ_SHIFT) 6534 /* USB2_DETECT_IRQ_STATUS_CLR */ 6535 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OFFSET (0x698U) 6536 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_LINESTATE_IRQ_CLR_SHIFT (0U) 6537 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_LINESTATE_IRQ_CLR_MASK \ 6538 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_LINESTATE_IRQ_CLR_SHIFT) 6539 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_BVALID_POS_IRQ_CLR_SHIFT (1U) 6540 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_BVALID_POS_IRQ_CLR_MASK \ 6541 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_BVALID_POS_IRQ_CLR_SHIFT) 6542 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_BVALID_NEG_IRQ_CLR_SHIFT (2U) 6543 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_BVALID_NEG_IRQ_CLR_MASK \ 6544 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_BVALID_NEG_IRQ_CLR_SHIFT) 6545 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_ID_POS_IRQ_CLR_SHIFT (3U) 6546 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_ID_POS_IRQ_CLR_MASK \ 6547 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_ID_POS_IRQ_CLR_SHIFT) 6548 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_ID_NEG_IRQ_CLR_SHIFT (4U) 6549 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_ID_NEG_IRQ_CLR_MASK \ 6550 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_ID_NEG_IRQ_CLR_SHIFT) 6551 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_DISCONNECT_POS_IRQ_CLR_SHIFT (5U) 6552 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_DISCONNECT_POS_IRQ_CLR_MASK \ 6553 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_DISCONNECT_POS_IRQ_CLR_SHIFT) 6554 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_DISCONNECT_NEG_IRQ_CLR_SHIFT (6U) 6555 #define GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_DISCONNECT_NEG_IRQ_CLR_MASK \ 6556 (0x1U << GRF_USB2_DETECT_IRQ_STATUS_CLR_OTG0_DISCONNECT_NEG_IRQ_CLR_SHIFT) 6557 /* HW_SPINLOCK00 */ 6558 #define GRF_HW_SPINLOCK00_OFFSET (0x700U) 6559 #define GRF_HW_SPINLOCK00_SPINLOCK_REG_X_SHIFT (0U) 6560 #define GRF_HW_SPINLOCK00_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK00_SPINLOCK_REG_X_SHIFT) 6561 /* HW_SPINLOCK01 */ 6562 #define GRF_HW_SPINLOCK01_OFFSET (0x704U) 6563 #define GRF_HW_SPINLOCK01_SPINLOCK_REG_X_SHIFT (0U) 6564 #define GRF_HW_SPINLOCK01_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK01_SPINLOCK_REG_X_SHIFT) 6565 /* HW_SPINLOCK02 */ 6566 #define GRF_HW_SPINLOCK02_OFFSET (0x708U) 6567 #define GRF_HW_SPINLOCK02_SPINLOCK_REG_X_SHIFT (0U) 6568 #define GRF_HW_SPINLOCK02_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK02_SPINLOCK_REG_X_SHIFT) 6569 /* HW_SPINLOCK03 */ 6570 #define GRF_HW_SPINLOCK03_OFFSET (0x70CU) 6571 #define GRF_HW_SPINLOCK03_SPINLOCK_REG_X_SHIFT (0U) 6572 #define GRF_HW_SPINLOCK03_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK03_SPINLOCK_REG_X_SHIFT) 6573 /* HW_SPINLOCK04 */ 6574 #define GRF_HW_SPINLOCK04_OFFSET (0x710U) 6575 #define GRF_HW_SPINLOCK04_SPINLOCK_REG_X_SHIFT (0U) 6576 #define GRF_HW_SPINLOCK04_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK04_SPINLOCK_REG_X_SHIFT) 6577 /* HW_SPINLOCK05 */ 6578 #define GRF_HW_SPINLOCK05_OFFSET (0x714U) 6579 #define GRF_HW_SPINLOCK05_SPINLOCK_REG_X_SHIFT (0U) 6580 #define GRF_HW_SPINLOCK05_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK05_SPINLOCK_REG_X_SHIFT) 6581 /* HW_SPINLOCK06 */ 6582 #define GRF_HW_SPINLOCK06_OFFSET (0x718U) 6583 #define GRF_HW_SPINLOCK06_SPINLOCK_REG_X_SHIFT (0U) 6584 #define GRF_HW_SPINLOCK06_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK06_SPINLOCK_REG_X_SHIFT) 6585 /* HW_SPINLOCK07 */ 6586 #define GRF_HW_SPINLOCK07_OFFSET (0x71CU) 6587 #define GRF_HW_SPINLOCK07_SPINLOCK_REG_X_SHIFT (0U) 6588 #define GRF_HW_SPINLOCK07_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK07_SPINLOCK_REG_X_SHIFT) 6589 /* HW_SPINLOCK08 */ 6590 #define GRF_HW_SPINLOCK08_OFFSET (0x720U) 6591 #define GRF_HW_SPINLOCK08_SPINLOCK_REG_X_SHIFT (0U) 6592 #define GRF_HW_SPINLOCK08_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK08_SPINLOCK_REG_X_SHIFT) 6593 /* HW_SPINLOCK09 */ 6594 #define GRF_HW_SPINLOCK09_OFFSET (0x724U) 6595 #define GRF_HW_SPINLOCK09_SPINLOCK_REG_X_SHIFT (0U) 6596 #define GRF_HW_SPINLOCK09_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK09_SPINLOCK_REG_X_SHIFT) 6597 /* HW_SPINLOCK10 */ 6598 #define GRF_HW_SPINLOCK10_OFFSET (0x728U) 6599 #define GRF_HW_SPINLOCK10_SPINLOCK_REG_X_SHIFT (0U) 6600 #define GRF_HW_SPINLOCK10_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK10_SPINLOCK_REG_X_SHIFT) 6601 /* HW_SPINLOCK11 */ 6602 #define GRF_HW_SPINLOCK11_OFFSET (0x72CU) 6603 #define GRF_HW_SPINLOCK11_SPINLOCK_REG_X_SHIFT (0U) 6604 #define GRF_HW_SPINLOCK11_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK11_SPINLOCK_REG_X_SHIFT) 6605 /* HW_SPINLOCK12 */ 6606 #define GRF_HW_SPINLOCK12_OFFSET (0x730U) 6607 #define GRF_HW_SPINLOCK12_SPINLOCK_REG_X_SHIFT (0U) 6608 #define GRF_HW_SPINLOCK12_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK12_SPINLOCK_REG_X_SHIFT) 6609 /* HW_SPINLOCK13 */ 6610 #define GRF_HW_SPINLOCK13_OFFSET (0x734U) 6611 #define GRF_HW_SPINLOCK13_SPINLOCK_REG_X_SHIFT (0U) 6612 #define GRF_HW_SPINLOCK13_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK13_SPINLOCK_REG_X_SHIFT) 6613 /* HW_SPINLOCK14 */ 6614 #define GRF_HW_SPINLOCK14_OFFSET (0x738U) 6615 #define GRF_HW_SPINLOCK14_SPINLOCK_REG_X_SHIFT (0U) 6616 #define GRF_HW_SPINLOCK14_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK14_SPINLOCK_REG_X_SHIFT) 6617 /* HW_SPINLOCK15 */ 6618 #define GRF_HW_SPINLOCK15_OFFSET (0x73CU) 6619 #define GRF_HW_SPINLOCK15_SPINLOCK_REG_X_SHIFT (0U) 6620 #define GRF_HW_SPINLOCK15_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK15_SPINLOCK_REG_X_SHIFT) 6621 /* HW_SPINLOCK16 */ 6622 #define GRF_HW_SPINLOCK16_OFFSET (0x740U) 6623 #define GRF_HW_SPINLOCK16_SPINLOCK_REG_X_SHIFT (0U) 6624 #define GRF_HW_SPINLOCK16_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK16_SPINLOCK_REG_X_SHIFT) 6625 /* HW_SPINLOCK17 */ 6626 #define GRF_HW_SPINLOCK17_OFFSET (0x744U) 6627 #define GRF_HW_SPINLOCK17_SPINLOCK_REG_X_SHIFT (0U) 6628 #define GRF_HW_SPINLOCK17_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK17_SPINLOCK_REG_X_SHIFT) 6629 /* HW_SPINLOCK18 */ 6630 #define GRF_HW_SPINLOCK18_OFFSET (0x748U) 6631 #define GRF_HW_SPINLOCK18_SPINLOCK_REG_X_SHIFT (0U) 6632 #define GRF_HW_SPINLOCK18_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK18_SPINLOCK_REG_X_SHIFT) 6633 /* HW_SPINLOCK19 */ 6634 #define GRF_HW_SPINLOCK19_OFFSET (0x74CU) 6635 #define GRF_HW_SPINLOCK19_SPINLOCK_REG_X_SHIFT (0U) 6636 #define GRF_HW_SPINLOCK19_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK19_SPINLOCK_REG_X_SHIFT) 6637 /* HW_SPINLOCK20 */ 6638 #define GRF_HW_SPINLOCK20_OFFSET (0x750U) 6639 #define GRF_HW_SPINLOCK20_SPINLOCK_REG_X_SHIFT (0U) 6640 #define GRF_HW_SPINLOCK20_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK20_SPINLOCK_REG_X_SHIFT) 6641 /* HW_SPINLOCK21 */ 6642 #define GRF_HW_SPINLOCK21_OFFSET (0x754U) 6643 #define GRF_HW_SPINLOCK21_SPINLOCK_REG_X_SHIFT (0U) 6644 #define GRF_HW_SPINLOCK21_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK21_SPINLOCK_REG_X_SHIFT) 6645 /* HW_SPINLOCK22 */ 6646 #define GRF_HW_SPINLOCK22_OFFSET (0x758U) 6647 #define GRF_HW_SPINLOCK22_SPINLOCK_REG_X_SHIFT (0U) 6648 #define GRF_HW_SPINLOCK22_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK22_SPINLOCK_REG_X_SHIFT) 6649 /* HW_SPINLOCK23 */ 6650 #define GRF_HW_SPINLOCK23_OFFSET (0x75CU) 6651 #define GRF_HW_SPINLOCK23_SPINLOCK_REG_X_SHIFT (0U) 6652 #define GRF_HW_SPINLOCK23_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK23_SPINLOCK_REG_X_SHIFT) 6653 /* HW_SPINLOCK24 */ 6654 #define GRF_HW_SPINLOCK24_OFFSET (0x760U) 6655 #define GRF_HW_SPINLOCK24_SPINLOCK_REG_X_SHIFT (0U) 6656 #define GRF_HW_SPINLOCK24_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK24_SPINLOCK_REG_X_SHIFT) 6657 /* HW_SPINLOCK25 */ 6658 #define GRF_HW_SPINLOCK25_OFFSET (0x764U) 6659 #define GRF_HW_SPINLOCK25_SPINLOCK_REG_X_SHIFT (0U) 6660 #define GRF_HW_SPINLOCK25_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK25_SPINLOCK_REG_X_SHIFT) 6661 /* HW_SPINLOCK26 */ 6662 #define GRF_HW_SPINLOCK26_OFFSET (0x768U) 6663 #define GRF_HW_SPINLOCK26_SPINLOCK_REG_X_SHIFT (0U) 6664 #define GRF_HW_SPINLOCK26_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK26_SPINLOCK_REG_X_SHIFT) 6665 /* HW_SPINLOCK27 */ 6666 #define GRF_HW_SPINLOCK27_OFFSET (0x76CU) 6667 #define GRF_HW_SPINLOCK27_SPINLOCK_REG_X_SHIFT (0U) 6668 #define GRF_HW_SPINLOCK27_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK27_SPINLOCK_REG_X_SHIFT) 6669 /* HW_SPINLOCK28 */ 6670 #define GRF_HW_SPINLOCK28_OFFSET (0x770U) 6671 #define GRF_HW_SPINLOCK28_SPINLOCK_REG_X_SHIFT (0U) 6672 #define GRF_HW_SPINLOCK28_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK28_SPINLOCK_REG_X_SHIFT) 6673 /* HW_SPINLOCK29 */ 6674 #define GRF_HW_SPINLOCK29_OFFSET (0x774U) 6675 #define GRF_HW_SPINLOCK29_SPINLOCK_REG_X_SHIFT (0U) 6676 #define GRF_HW_SPINLOCK29_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK29_SPINLOCK_REG_X_SHIFT) 6677 /* HW_SPINLOCK30 */ 6678 #define GRF_HW_SPINLOCK30_OFFSET (0x778U) 6679 #define GRF_HW_SPINLOCK30_SPINLOCK_REG_X_SHIFT (0U) 6680 #define GRF_HW_SPINLOCK30_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK30_SPINLOCK_REG_X_SHIFT) 6681 /* HW_SPINLOCK31 */ 6682 #define GRF_HW_SPINLOCK31_OFFSET (0x77CU) 6683 #define GRF_HW_SPINLOCK31_SPINLOCK_REG_X_SHIFT (0U) 6684 #define GRF_HW_SPINLOCK31_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK31_SPINLOCK_REG_X_SHIFT) 6685 /* HW_SPINLOCK32 */ 6686 #define GRF_HW_SPINLOCK32_OFFSET (0x780U) 6687 #define GRF_HW_SPINLOCK32_SPINLOCK_REG_X_SHIFT (0U) 6688 #define GRF_HW_SPINLOCK32_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK32_SPINLOCK_REG_X_SHIFT) 6689 /* HW_SPINLOCK33 */ 6690 #define GRF_HW_SPINLOCK33_OFFSET (0x784U) 6691 #define GRF_HW_SPINLOCK33_SPINLOCK_REG_X_SHIFT (0U) 6692 #define GRF_HW_SPINLOCK33_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK33_SPINLOCK_REG_X_SHIFT) 6693 /* HW_SPINLOCK34 */ 6694 #define GRF_HW_SPINLOCK34_OFFSET (0x788U) 6695 #define GRF_HW_SPINLOCK34_SPINLOCK_REG_X_SHIFT (0U) 6696 #define GRF_HW_SPINLOCK34_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK34_SPINLOCK_REG_X_SHIFT) 6697 /* HW_SPINLOCK35 */ 6698 #define GRF_HW_SPINLOCK35_OFFSET (0x78CU) 6699 #define GRF_HW_SPINLOCK35_SPINLOCK_REG_X_SHIFT (0U) 6700 #define GRF_HW_SPINLOCK35_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK35_SPINLOCK_REG_X_SHIFT) 6701 /* HW_SPINLOCK36 */ 6702 #define GRF_HW_SPINLOCK36_OFFSET (0x790U) 6703 #define GRF_HW_SPINLOCK36_SPINLOCK_REG_X_SHIFT (0U) 6704 #define GRF_HW_SPINLOCK36_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK36_SPINLOCK_REG_X_SHIFT) 6705 /* HW_SPINLOCK37 */ 6706 #define GRF_HW_SPINLOCK37_OFFSET (0x794U) 6707 #define GRF_HW_SPINLOCK37_SPINLOCK_REG_X_SHIFT (0U) 6708 #define GRF_HW_SPINLOCK37_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK37_SPINLOCK_REG_X_SHIFT) 6709 /* HW_SPINLOCK38 */ 6710 #define GRF_HW_SPINLOCK38_OFFSET (0x798U) 6711 #define GRF_HW_SPINLOCK38_SPINLOCK_REG_X_SHIFT (0U) 6712 #define GRF_HW_SPINLOCK38_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK38_SPINLOCK_REG_X_SHIFT) 6713 /* HW_SPINLOCK39 */ 6714 #define GRF_HW_SPINLOCK39_OFFSET (0x79CU) 6715 #define GRF_HW_SPINLOCK39_SPINLOCK_REG_X_SHIFT (0U) 6716 #define GRF_HW_SPINLOCK39_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK39_SPINLOCK_REG_X_SHIFT) 6717 /* HW_SPINLOCK40 */ 6718 #define GRF_HW_SPINLOCK40_OFFSET (0x7A0U) 6719 #define GRF_HW_SPINLOCK40_SPINLOCK_REG_X_SHIFT (0U) 6720 #define GRF_HW_SPINLOCK40_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK40_SPINLOCK_REG_X_SHIFT) 6721 /* HW_SPINLOCK41 */ 6722 #define GRF_HW_SPINLOCK41_OFFSET (0x7A4U) 6723 #define GRF_HW_SPINLOCK41_SPINLOCK_REG_X_SHIFT (0U) 6724 #define GRF_HW_SPINLOCK41_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK41_SPINLOCK_REG_X_SHIFT) 6725 /* HW_SPINLOCK42 */ 6726 #define GRF_HW_SPINLOCK42_OFFSET (0x7A8U) 6727 #define GRF_HW_SPINLOCK42_SPINLOCK_REG_X_SHIFT (0U) 6728 #define GRF_HW_SPINLOCK42_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK42_SPINLOCK_REG_X_SHIFT) 6729 /* HW_SPINLOCK43 */ 6730 #define GRF_HW_SPINLOCK43_OFFSET (0x7ACU) 6731 #define GRF_HW_SPINLOCK43_SPINLOCK_REG_X_SHIFT (0U) 6732 #define GRF_HW_SPINLOCK43_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK43_SPINLOCK_REG_X_SHIFT) 6733 /* HW_SPINLOCK44 */ 6734 #define GRF_HW_SPINLOCK44_OFFSET (0x7B0U) 6735 #define GRF_HW_SPINLOCK44_SPINLOCK_REG_X_SHIFT (0U) 6736 #define GRF_HW_SPINLOCK44_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK44_SPINLOCK_REG_X_SHIFT) 6737 /* HW_SPINLOCK45 */ 6738 #define GRF_HW_SPINLOCK45_OFFSET (0x7B4U) 6739 #define GRF_HW_SPINLOCK45_SPINLOCK_REG_X_SHIFT (0U) 6740 #define GRF_HW_SPINLOCK45_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK45_SPINLOCK_REG_X_SHIFT) 6741 /* HW_SPINLOCK46 */ 6742 #define GRF_HW_SPINLOCK46_OFFSET (0x7B8U) 6743 #define GRF_HW_SPINLOCK46_SPINLOCK_REG_X_SHIFT (0U) 6744 #define GRF_HW_SPINLOCK46_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK46_SPINLOCK_REG_X_SHIFT) 6745 /* HW_SPINLOCK47 */ 6746 #define GRF_HW_SPINLOCK47_OFFSET (0x7BCU) 6747 #define GRF_HW_SPINLOCK47_SPINLOCK_REG_X_SHIFT (0U) 6748 #define GRF_HW_SPINLOCK47_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK47_SPINLOCK_REG_X_SHIFT) 6749 /* HW_SPINLOCK48 */ 6750 #define GRF_HW_SPINLOCK48_OFFSET (0x7C0U) 6751 #define GRF_HW_SPINLOCK48_SPINLOCK_REG_X_SHIFT (0U) 6752 #define GRF_HW_SPINLOCK48_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK48_SPINLOCK_REG_X_SHIFT) 6753 /* HW_SPINLOCK49 */ 6754 #define GRF_HW_SPINLOCK49_OFFSET (0x7C4U) 6755 #define GRF_HW_SPINLOCK49_SPINLOCK_REG_X_SHIFT (0U) 6756 #define GRF_HW_SPINLOCK49_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK49_SPINLOCK_REG_X_SHIFT) 6757 /* HW_SPINLOCK50 */ 6758 #define GRF_HW_SPINLOCK50_OFFSET (0x7C8U) 6759 #define GRF_HW_SPINLOCK50_SPINLOCK_REG_X_SHIFT (0U) 6760 #define GRF_HW_SPINLOCK50_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK50_SPINLOCK_REG_X_SHIFT) 6761 /* HW_SPINLOCK51 */ 6762 #define GRF_HW_SPINLOCK51_OFFSET (0x7CCU) 6763 #define GRF_HW_SPINLOCK51_SPINLOCK_REG_X_SHIFT (0U) 6764 #define GRF_HW_SPINLOCK51_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK51_SPINLOCK_REG_X_SHIFT) 6765 /* HW_SPINLOCK52 */ 6766 #define GRF_HW_SPINLOCK52_OFFSET (0x7D0U) 6767 #define GRF_HW_SPINLOCK52_SPINLOCK_REG_X_SHIFT (0U) 6768 #define GRF_HW_SPINLOCK52_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK52_SPINLOCK_REG_X_SHIFT) 6769 /* HW_SPINLOCK53 */ 6770 #define GRF_HW_SPINLOCK53_OFFSET (0x7D4U) 6771 #define GRF_HW_SPINLOCK53_SPINLOCK_REG_X_SHIFT (0U) 6772 #define GRF_HW_SPINLOCK53_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK53_SPINLOCK_REG_X_SHIFT) 6773 /* HW_SPINLOCK54 */ 6774 #define GRF_HW_SPINLOCK54_OFFSET (0x7D8U) 6775 #define GRF_HW_SPINLOCK54_SPINLOCK_REG_X_SHIFT (0U) 6776 #define GRF_HW_SPINLOCK54_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK54_SPINLOCK_REG_X_SHIFT) 6777 /* HW_SPINLOCK55 */ 6778 #define GRF_HW_SPINLOCK55_OFFSET (0x7DCU) 6779 #define GRF_HW_SPINLOCK55_SPINLOCK_REG_X_SHIFT (0U) 6780 #define GRF_HW_SPINLOCK55_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK55_SPINLOCK_REG_X_SHIFT) 6781 /* HW_SPINLOCK56 */ 6782 #define GRF_HW_SPINLOCK56_OFFSET (0x7E0U) 6783 #define GRF_HW_SPINLOCK56_SPINLOCK_REG_X_SHIFT (0U) 6784 #define GRF_HW_SPINLOCK56_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK56_SPINLOCK_REG_X_SHIFT) 6785 /* HW_SPINLOCK57 */ 6786 #define GRF_HW_SPINLOCK57_OFFSET (0x7E4U) 6787 #define GRF_HW_SPINLOCK57_SPINLOCK_REG_X_SHIFT (0U) 6788 #define GRF_HW_SPINLOCK57_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK57_SPINLOCK_REG_X_SHIFT) 6789 /* HW_SPINLOCK58 */ 6790 #define GRF_HW_SPINLOCK58_OFFSET (0x7E8U) 6791 #define GRF_HW_SPINLOCK58_SPINLOCK_REG_X_SHIFT (0U) 6792 #define GRF_HW_SPINLOCK58_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK58_SPINLOCK_REG_X_SHIFT) 6793 /* HW_SPINLOCK59 */ 6794 #define GRF_HW_SPINLOCK59_OFFSET (0x7ECU) 6795 #define GRF_HW_SPINLOCK59_SPINLOCK_REG_X_SHIFT (0U) 6796 #define GRF_HW_SPINLOCK59_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK59_SPINLOCK_REG_X_SHIFT) 6797 /* HW_SPINLOCK60 */ 6798 #define GRF_HW_SPINLOCK60_OFFSET (0x7F0U) 6799 #define GRF_HW_SPINLOCK60_SPINLOCK_REG_X_SHIFT (0U) 6800 #define GRF_HW_SPINLOCK60_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK60_SPINLOCK_REG_X_SHIFT) 6801 /* HW_SPINLOCK61 */ 6802 #define GRF_HW_SPINLOCK61_OFFSET (0x7F4U) 6803 #define GRF_HW_SPINLOCK61_SPINLOCK_REG_X_SHIFT (0U) 6804 #define GRF_HW_SPINLOCK61_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK61_SPINLOCK_REG_X_SHIFT) 6805 /* HW_SPINLOCK62 */ 6806 #define GRF_HW_SPINLOCK62_OFFSET (0x7F8U) 6807 #define GRF_HW_SPINLOCK62_SPINLOCK_REG_X_SHIFT (0U) 6808 #define GRF_HW_SPINLOCK62_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK62_SPINLOCK_REG_X_SHIFT) 6809 /* HW_SPINLOCK63 */ 6810 #define GRF_HW_SPINLOCK63_OFFSET (0x7FCU) 6811 #define GRF_HW_SPINLOCK63_SPINLOCK_REG_X_SHIFT (0U) 6812 #define GRF_HW_SPINLOCK63_SPINLOCK_REG_X_MASK (0xFU << GRF_HW_SPINLOCK63_SPINLOCK_REG_X_SHIFT) 6813 /* OS_REG0 */ 6814 #define GRF_OS_REG0_OFFSET (0x800U) 6815 #define GRF_OS_REG0_OS_REGISTER0_SHIFT (0U) 6816 #define GRF_OS_REG0_OS_REGISTER0_MASK (0xFFFFFFFFU << GRF_OS_REG0_OS_REGISTER0_SHIFT) 6817 /* OS_REG1 */ 6818 #define GRF_OS_REG1_OFFSET (0x804U) 6819 #define GRF_OS_REG1_OS_REGISTER1_SHIFT (0U) 6820 #define GRF_OS_REG1_OS_REGISTER1_MASK (0xFFFFFFFFU << GRF_OS_REG1_OS_REGISTER1_SHIFT) 6821 /* OS_REG2 */ 6822 #define GRF_OS_REG2_OFFSET (0x808U) 6823 #define GRF_OS_REG2_OS_REGISTER2_SHIFT (0U) 6824 #define GRF_OS_REG2_OS_REGISTER2_MASK (0xFFFFFFFFU << GRF_OS_REG2_OS_REGISTER2_SHIFT) 6825 /* OS_REG3 */ 6826 #define GRF_OS_REG3_OFFSET (0x80CU) 6827 #define GRF_OS_REG3_OS_REGISTER3_SHIFT (0U) 6828 #define GRF_OS_REG3_OS_REGISTER3_MASK (0xFFFFFFFFU << GRF_OS_REG3_OS_REGISTER3_SHIFT) 6829 /* OS_REG4 */ 6830 #define GRF_OS_REG4_OFFSET (0x810U) 6831 #define GRF_OS_REG4_OS_REGISTER4_SHIFT (0U) 6832 #define GRF_OS_REG4_OS_REGISTER4_MASK (0xFFFFFFFFU << GRF_OS_REG4_OS_REGISTER4_SHIFT) 6833 /* OS_REG5 */ 6834 #define GRF_OS_REG5_OFFSET (0x814U) 6835 #define GRF_OS_REG5_OS_REGISTER5_SHIFT (0U) 6836 #define GRF_OS_REG5_OS_REGISTER5_MASK (0xFFFFFFFFU << GRF_OS_REG5_OS_REGISTER5_SHIFT) 6837 /* OS_REG6 */ 6838 #define GRF_OS_REG6_OFFSET (0x818U) 6839 #define GRF_OS_REG6_OS_REGISTER6_SHIFT (0U) 6840 #define GRF_OS_REG6_OS_REGISTER6_MASK (0xFFFFFFFFU << GRF_OS_REG6_OS_REGISTER6_SHIFT) 6841 /* OS_REG7 */ 6842 #define GRF_OS_REG7_OFFSET (0x81CU) 6843 #define GRF_OS_REG7_OS_REGISTER7_SHIFT (0U) 6844 #define GRF_OS_REG7_OS_REGISTER7_MASK (0xFFFFFFFFU << GRF_OS_REG7_OS_REGISTER7_SHIFT) 6845 /* GRF_SOC_VERSION */ 6846 #define GRF_GRF_SOC_VERSION_OFFSET (0x820U) 6847 #define GRF_GRF_SOC_VERSION (0x2206U) 6848 #define GRF_GRF_SOC_VERSION_SOC_VERSION_SHIFT (0U) 6849 #define GRF_GRF_SOC_VERSION_SOC_VERSION_MASK (0xFFFFFFFFU << GRF_GRF_SOC_VERSION_SOC_VERSION_SHIFT) 6850 /******************************************CRU*******************************************/ 6851 /* GPLL_CON0 */ 6852 #define CRU_GPLL_CON0_OFFSET (0x0U) 6853 #define CRU_GPLL_CON0_FBDIV_SHIFT (0U) 6854 #define CRU_GPLL_CON0_FBDIV_MASK (0xFFFU << CRU_GPLL_CON0_FBDIV_SHIFT) 6855 #define CRU_GPLL_CON0_POSTDIV1_SHIFT (12U) 6856 #define CRU_GPLL_CON0_POSTDIV1_MASK (0x7U << CRU_GPLL_CON0_POSTDIV1_SHIFT) 6857 #define CRU_GPLL_CON0_BYPASS_SHIFT (15U) 6858 #define CRU_GPLL_CON0_BYPASS_MASK (0x1U << CRU_GPLL_CON0_BYPASS_SHIFT) 6859 /* GPLL_CON1 */ 6860 #define CRU_GPLL_CON1_OFFSET (0x4U) 6861 #define CRU_GPLL_CON1_REFDIV_SHIFT (0U) 6862 #define CRU_GPLL_CON1_REFDIV_MASK (0x3FU << CRU_GPLL_CON1_REFDIV_SHIFT) 6863 #define CRU_GPLL_CON1_POSTDIV2_SHIFT (6U) 6864 #define CRU_GPLL_CON1_POSTDIV2_MASK (0x7U << CRU_GPLL_CON1_POSTDIV2_SHIFT) 6865 #define CRU_GPLL_CON1_PLL_LOCK_SHIFT (10U) 6866 #define CRU_GPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_GPLL_CON1_PLL_LOCK_SHIFT) 6867 #define CRU_GPLL_CON1_DSMPD_SHIFT (12U) 6868 #define CRU_GPLL_CON1_DSMPD_MASK (0x1U << CRU_GPLL_CON1_DSMPD_SHIFT) 6869 #define CRU_GPLL_CON1_PLLPD_SHIFT (13U) 6870 #define CRU_GPLL_CON1_PLLPD_MASK (0x1U << CRU_GPLL_CON1_PLLPD_SHIFT) 6871 /* GPLL_CON2 */ 6872 #define CRU_GPLL_CON2_OFFSET (0x8U) 6873 #define CRU_GPLL_CON2_FRACDIV_SHIFT (0U) 6874 #define CRU_GPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_GPLL_CON2_FRACDIV_SHIFT) 6875 #define CRU_GPLL_CON2_DACPD_SHIFT (24U) 6876 #define CRU_GPLL_CON2_DACPD_MASK (0x1U << CRU_GPLL_CON2_DACPD_SHIFT) 6877 #define CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) 6878 #define CRU_GPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT) 6879 #define CRU_GPLL_CON2_FOUTVCOPD_SHIFT (26U) 6880 #define CRU_GPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_GPLL_CON2_FOUTVCOPD_SHIFT) 6881 #define CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT (27U) 6882 #define CRU_GPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT) 6883 /* GPLL_CON3 */ 6884 #define CRU_GPLL_CON3_OFFSET (0xCU) 6885 #define CRU_GPLL_CON3_SSMOD_BP_SHIFT (0U) 6886 #define CRU_GPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_GPLL_CON3_SSMOD_BP_SHIFT) 6887 #define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) 6888 #define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) 6889 #define CRU_GPLL_CON3_SSMOD_RESET_SHIFT (2U) 6890 #define CRU_GPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_GPLL_CON3_SSMOD_RESET_SHIFT) 6891 #define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) 6892 #define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) 6893 #define CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) 6894 #define CRU_GPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT) 6895 #define CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT (8U) 6896 #define CRU_GPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT) 6897 /* GPLL_CON4 */ 6898 #define CRU_GPLL_CON4_OFFSET (0x10U) 6899 #define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) 6900 #define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) 6901 #define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) 6902 #define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) 6903 /* VPLL_CON0 */ 6904 #define CRU_VPLL_CON0_OFFSET (0x20U) 6905 #define CRU_VPLL_CON0_FBDIV_SHIFT (0U) 6906 #define CRU_VPLL_CON0_FBDIV_MASK (0xFFFU << CRU_VPLL_CON0_FBDIV_SHIFT) 6907 #define CRU_VPLL_CON0_POSTDIV1_SHIFT (12U) 6908 #define CRU_VPLL_CON0_POSTDIV1_MASK (0x7U << CRU_VPLL_CON0_POSTDIV1_SHIFT) 6909 #define CRU_VPLL_CON0_BYPASS_SHIFT (15U) 6910 #define CRU_VPLL_CON0_BYPASS_MASK (0x1U << CRU_VPLL_CON0_BYPASS_SHIFT) 6911 /* VPLL_CON1 */ 6912 #define CRU_VPLL_CON1_OFFSET (0x24U) 6913 #define CRU_VPLL_CON1_REFDIV_SHIFT (0U) 6914 #define CRU_VPLL_CON1_REFDIV_MASK (0x3FU << CRU_VPLL_CON1_REFDIV_SHIFT) 6915 #define CRU_VPLL_CON1_POSTDIV2_SHIFT (6U) 6916 #define CRU_VPLL_CON1_POSTDIV2_MASK (0x7U << CRU_VPLL_CON1_POSTDIV2_SHIFT) 6917 #define CRU_VPLL_CON1_PLL_LOCK_SHIFT (10U) 6918 #define CRU_VPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_VPLL_CON1_PLL_LOCK_SHIFT) 6919 #define CRU_VPLL_CON1_DSMPD_SHIFT (12U) 6920 #define CRU_VPLL_CON1_DSMPD_MASK (0x1U << CRU_VPLL_CON1_DSMPD_SHIFT) 6921 #define CRU_VPLL_CON1_PLLPD_SHIFT (13U) 6922 #define CRU_VPLL_CON1_PLLPD_MASK (0x1U << CRU_VPLL_CON1_PLLPD_SHIFT) 6923 /* VPLL_CON2 */ 6924 #define CRU_VPLL_CON2_OFFSET (0x28U) 6925 #define CRU_VPLL_CON2_FRACDIV_SHIFT (0U) 6926 #define CRU_VPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_VPLL_CON2_FRACDIV_SHIFT) 6927 #define CRU_VPLL_CON2_DACPD_SHIFT (24U) 6928 #define CRU_VPLL_CON2_DACPD_MASK (0x1U << CRU_VPLL_CON2_DACPD_SHIFT) 6929 #define CRU_VPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) 6930 #define CRU_VPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_VPLL_CON2_FOUTPOSTDIVPD_SHIFT) 6931 #define CRU_VPLL_CON2_FOUTVCOPD_SHIFT (26U) 6932 #define CRU_VPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_VPLL_CON2_FOUTVCOPD_SHIFT) 6933 #define CRU_VPLL_CON2_FOUT4PHASEPD_SHIFT (27U) 6934 #define CRU_VPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_VPLL_CON2_FOUT4PHASEPD_SHIFT) 6935 /* VPLL_CON3 */ 6936 #define CRU_VPLL_CON3_OFFSET (0x2CU) 6937 #define CRU_VPLL_CON3_SSMOD_BP_SHIFT (0U) 6938 #define CRU_VPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_VPLL_CON3_SSMOD_BP_SHIFT) 6939 #define CRU_VPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) 6940 #define CRU_VPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_VPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) 6941 #define CRU_VPLL_CON3_SSMOD_RESET_SHIFT (2U) 6942 #define CRU_VPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_VPLL_CON3_SSMOD_RESET_SHIFT) 6943 #define CRU_VPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) 6944 #define CRU_VPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_VPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) 6945 #define CRU_VPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) 6946 #define CRU_VPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_VPLL_CON3_SSMOD_DIVVAL_SHIFT) 6947 #define CRU_VPLL_CON3_SSMOD_SPREAD_SHIFT (8U) 6948 #define CRU_VPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_VPLL_CON3_SSMOD_SPREAD_SHIFT) 6949 /* VPLL_CON4 */ 6950 #define CRU_VPLL_CON4_OFFSET (0x30U) 6951 #define CRU_VPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) 6952 #define CRU_VPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_VPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) 6953 #define CRU_VPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) 6954 #define CRU_VPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_VPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) 6955 /* MODE_CON00 */ 6956 #define CRU_MODE_CON00_OFFSET (0xA0U) 6957 #define CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT (0U) 6958 #define CRU_MODE_CON00_CLK_GPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT) 6959 #define CRU_MODE_CON00_CLK_USBPLL_MODE_SHIFT (2U) 6960 #define CRU_MODE_CON00_CLK_USBPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_USBPLL_MODE_SHIFT) 6961 #define CRU_MODE_CON00_CLK_VPLL_MODE_SHIFT (4U) 6962 #define CRU_MODE_CON00_CLK_VPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_VPLL_MODE_SHIFT) 6963 /* GLB_CNT_TH */ 6964 #define CRU_GLB_CNT_TH_OFFSET (0xB0U) 6965 #define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT (0U) 6966 #define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_MASK \ 6967 (0xFFFFFFFFU << CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT) 6968 /* GLB_RST_ST */ 6969 #define CRU_GLB_RST_ST_OFFSET (0xB4U) 6970 #define CRU_GLB_RST_ST_FST_GLB_RST_ST_SHIFT (0U) 6971 #define CRU_GLB_RST_ST_FST_GLB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_RST_ST_SHIFT) 6972 #define CRU_GLB_RST_ST_SND_GLB_RST_ST_SHIFT (1U) 6973 #define CRU_GLB_RST_ST_SND_GLB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_RST_ST_SHIFT) 6974 #define CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_SHIFT (2U) 6975 #define CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_SHIFT) 6976 #define CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_SHIFT (3U) 6977 #define CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_SHIFT) 6978 #define CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_SHIFT (4U) 6979 #define CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_SHIFT) 6980 #define CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_SHIFT (5U) 6981 #define CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_SHIFT) 6982 #define CRU_GLB_RST_ST_GLB_WDT0_RST_ST_SHIFT (6U) 6983 #define CRU_GLB_RST_ST_GLB_WDT0_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_WDT0_RST_ST_SHIFT) 6984 #define CRU_GLB_RST_ST_GLB_WDT1_RST_ST_SHIFT (7U) 6985 #define CRU_GLB_RST_ST_GLB_WDT1_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_WDT1_RST_ST_SHIFT) 6986 #define CRU_GLB_RST_ST_GLB_WDT2_RST_ST_SHIFT (8U) 6987 #define CRU_GLB_RST_ST_GLB_WDT2_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_WDT2_RST_ST_SHIFT) 6988 /* GLB_SRST_FST_VALUE */ 6989 #define CRU_GLB_SRST_FST_VALUE_OFFSET (0xB8U) 6990 #define CRU_GLB_SRST_FST_VALUE_GLB_SRST_FST_SHIFT (0U) 6991 #define CRU_GLB_SRST_FST_VALUE_GLB_SRST_FST_MASK (0xFFFFU << CRU_GLB_SRST_FST_VALUE_GLB_SRST_FST_SHIFT) 6992 /* GLB_SRST_SND_VALUE */ 6993 #define CRU_GLB_SRST_SND_VALUE_OFFSET (0xBCU) 6994 #define CRU_GLB_SRST_SND_VALUE_GLB_SRST_SND_SHIFT (0U) 6995 #define CRU_GLB_SRST_SND_VALUE_GLB_SRST_SND_MASK (0xFFFFU << CRU_GLB_SRST_SND_VALUE_GLB_SRST_SND_SHIFT) 6996 /* GLB_RST_CON */ 6997 #define CRU_GLB_RST_CON_OFFSET (0xC0U) 6998 #define CRU_GLB_RST_CON_TSADC_GLB_SRST_EN_SHIFT (0U) 6999 #define CRU_GLB_RST_CON_TSADC_GLB_SRST_EN_MASK (0x1U << CRU_GLB_RST_CON_TSADC_GLB_SRST_EN_SHIFT) 7000 #define CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_SHIFT (1U) 7001 #define CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_SHIFT) 7002 #define CRU_GLB_RST_CON_PMU_SRST_CTRL_SHIFT (2U) 7003 #define CRU_GLB_RST_CON_PMU_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_CTRL_SHIFT) 7004 #define CRU_GLB_RST_CON_PMU_SRST_GLB_RST_EN_SHIFT (3U) 7005 #define CRU_GLB_RST_CON_PMU_SRST_GLB_RST_EN_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_GLB_RST_EN_SHIFT) 7006 #define CRU_GLB_RST_CON_PMU_SRST_WDT_EN_SHIFT (4U) 7007 #define CRU_GLB_RST_CON_PMU_SRST_WDT_EN_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_WDT_EN_SHIFT) 7008 #define CRU_GLB_RST_CON_TSADC_RESET_EXT_EN_SHIFT (6U) 7009 #define CRU_GLB_RST_CON_TSADC_RESET_EXT_EN_MASK (0x1U << CRU_GLB_RST_CON_TSADC_RESET_EXT_EN_SHIFT) 7010 #define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT (7U) 7011 #define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT) 7012 #define CRU_GLB_RST_CON_WDT0_GLB_SRST_EN_SHIFT (8U) 7013 #define CRU_GLB_RST_CON_WDT0_GLB_SRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT0_GLB_SRST_EN_SHIFT) 7014 #define CRU_GLB_RST_CON_WDT1_GLB_SRST_EN_SHIFT (9U) 7015 #define CRU_GLB_RST_CON_WDT1_GLB_SRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT1_GLB_SRST_EN_SHIFT) 7016 #define CRU_GLB_RST_CON_WDT2_GLB_SRST_EN_SHIFT (10U) 7017 #define CRU_GLB_RST_CON_WDT2_GLB_SRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT2_GLB_SRST_EN_SHIFT) 7018 #define CRU_GLB_RST_CON_WDT0_GLB_SRST_CTRL_SHIFT (12U) 7019 #define CRU_GLB_RST_CON_WDT0_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_WDT0_GLB_SRST_CTRL_SHIFT) 7020 #define CRU_GLB_RST_CON_WDT1_GLB_SRST_CTRL_SHIFT (13U) 7021 #define CRU_GLB_RST_CON_WDT1_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_WDT1_GLB_SRST_CTRL_SHIFT) 7022 #define CRU_GLB_RST_CON_WDT2_GLB_SRST_CTRL_SHIFT (14U) 7023 #define CRU_GLB_RST_CON_WDT2_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_WDT2_GLB_SRST_CTRL_SHIFT) 7024 /* CLKSEL_CON00 */ 7025 #define CRU_CLKSEL_CON00_OFFSET (0x100U) 7026 #define CRU_CLKSEL_CON00_CLK_32K_SEL_SHIFT (5U) 7027 #define CRU_CLKSEL_CON00_CLK_32K_SEL_MASK (0x3U << CRU_CLKSEL_CON00_CLK_32K_SEL_SHIFT) 7028 #define CRU_CLKSEL_CON00_CLK_32K_FRAC_DIV_SEL_SHIFT (7U) 7029 #define CRU_CLKSEL_CON00_CLK_32K_FRAC_DIV_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_32K_FRAC_DIV_SEL_SHIFT) 7030 #define CRU_CLKSEL_CON00_CLK_GPLL_MUX_NP5_DIV_SHIFT (8U) 7031 #define CRU_CLKSEL_CON00_CLK_GPLL_MUX_NP5_DIV_MASK (0xFU << CRU_CLKSEL_CON00_CLK_GPLL_MUX_NP5_DIV_SHIFT) 7032 /* CLKSEL_CON01 */ 7033 #define CRU_CLKSEL_CON01_OFFSET (0x104U) 7034 #define CRU_CLKSEL_CON01_CLK_32K_FRAC_DIV_DIV_SHIFT (0U) 7035 #define CRU_CLKSEL_CON01_CLK_32K_FRAC_DIV_DIV_MASK \ 7036 (0xFFFFFFFFU << CRU_CLKSEL_CON01_CLK_32K_FRAC_DIV_DIV_SHIFT) 7037 /* CLKSEL_CON02 */ 7038 #define CRU_CLKSEL_CON02_OFFSET (0x108U) 7039 #define CRU_CLKSEL_CON02_HCLK_MCU_BUS_DIV_SHIFT (0U) 7040 #define CRU_CLKSEL_CON02_HCLK_MCU_BUS_DIV_MASK (0x1FU << CRU_CLKSEL_CON02_HCLK_MCU_BUS_DIV_SHIFT) 7041 #define CRU_CLKSEL_CON02_HCLK_MCU_BUS_SEL_SHIFT (6U) 7042 #define CRU_CLKSEL_CON02_HCLK_MCU_BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON02_HCLK_MCU_BUS_SEL_SHIFT) 7043 #define CRU_CLKSEL_CON02_PCLK_MCU_BUS_DIV_SHIFT (8U) 7044 #define CRU_CLKSEL_CON02_PCLK_MCU_BUS_DIV_MASK (0x1FU << CRU_CLKSEL_CON02_PCLK_MCU_BUS_DIV_SHIFT) 7045 /* CLKSEL_CON03 */ 7046 #define CRU_CLKSEL_CON03_OFFSET (0x10CU) 7047 #define CRU_CLKSEL_CON03_CLK_HIFI3_DIV_DIV_SHIFT (0U) 7048 #define CRU_CLKSEL_CON03_CLK_HIFI3_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_CLK_HIFI3_DIV_DIV_SHIFT) 7049 #define CRU_CLKSEL_CON03_CLK_HIFI3_SRC_SEL_SHIFT (6U) 7050 #define CRU_CLKSEL_CON03_CLK_HIFI3_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON03_CLK_HIFI3_SRC_SEL_SHIFT) 7051 #define CRU_CLKSEL_CON03_CLK_HIFI_NP5_DIV_DIV_SHIFT (8U) 7052 #define CRU_CLKSEL_CON03_CLK_HIFI_NP5_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_CLK_HIFI_NP5_DIV_DIV_SHIFT) 7053 #define CRU_CLKSEL_CON03_CLK_HIFI_SEL_SHIFT (15U) 7054 #define CRU_CLKSEL_CON03_CLK_HIFI_SEL_MASK (0x1U << CRU_CLKSEL_CON03_CLK_HIFI_SEL_SHIFT) 7055 /* CLKSEL_CON04 */ 7056 #define CRU_CLKSEL_CON04_OFFSET (0x110U) 7057 #define CRU_CLKSEL_CON04_CLK_UART0_DIV_DIV_SHIFT (0U) 7058 #define CRU_CLKSEL_CON04_CLK_UART0_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON04_CLK_UART0_DIV_DIV_SHIFT) 7059 #define CRU_CLKSEL_CON04_CLK_UART0_DIV_SEL_SHIFT (7U) 7060 #define CRU_CLKSEL_CON04_CLK_UART0_DIV_SEL_MASK (0x1U << CRU_CLKSEL_CON04_CLK_UART0_DIV_SEL_SHIFT) 7061 #define CRU_CLKSEL_CON04_SCLK_UART0_SEL_SHIFT (15U) 7062 #define CRU_CLKSEL_CON04_SCLK_UART0_SEL_MASK (0x1U << CRU_CLKSEL_CON04_SCLK_UART0_SEL_SHIFT) 7063 /* CLKSEL_CON05 */ 7064 #define CRU_CLKSEL_CON05_OFFSET (0x114U) 7065 #define CRU_CLKSEL_CON05_CLK_UART0_FRAC_DIV_DIV_SHIFT (0U) 7066 #define CRU_CLKSEL_CON05_CLK_UART0_FRAC_DIV_DIV_MASK \ 7067 (0xFFFFFFFFU << CRU_CLKSEL_CON05_CLK_UART0_FRAC_DIV_DIV_SHIFT) 7068 /* CLKSEL_CON06 */ 7069 #define CRU_CLKSEL_CON06_OFFSET (0x118U) 7070 #define CRU_CLKSEL_CON06_CLK_UART1_DIV_DIV_SHIFT (0U) 7071 #define CRU_CLKSEL_CON06_CLK_UART1_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON06_CLK_UART1_DIV_DIV_SHIFT) 7072 #define CRU_CLKSEL_CON06_CLK_UART1_DIV_SEL_SHIFT (7U) 7073 #define CRU_CLKSEL_CON06_CLK_UART1_DIV_SEL_MASK (0x1U << CRU_CLKSEL_CON06_CLK_UART1_DIV_SEL_SHIFT) 7074 #define CRU_CLKSEL_CON06_SCLK_UART1_SEL_SHIFT (15U) 7075 #define CRU_CLKSEL_CON06_SCLK_UART1_SEL_MASK (0x1U << CRU_CLKSEL_CON06_SCLK_UART1_SEL_SHIFT) 7076 /* CLKSEL_CON07 */ 7077 #define CRU_CLKSEL_CON07_OFFSET (0x11CU) 7078 #define CRU_CLKSEL_CON07_CLK_UART1_FRAC_DIV_DIV_SHIFT (0U) 7079 #define CRU_CLKSEL_CON07_CLK_UART1_FRAC_DIV_DIV_MASK \ 7080 (0xFFFFFFFFU << CRU_CLKSEL_CON07_CLK_UART1_FRAC_DIV_DIV_SHIFT) 7081 /* CLKSEL_CON08 */ 7082 #define CRU_CLKSEL_CON08_OFFSET (0x120U) 7083 #define CRU_CLKSEL_CON08_CLK_UART2_DIV_DIV_SHIFT (0U) 7084 #define CRU_CLKSEL_CON08_CLK_UART2_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON08_CLK_UART2_DIV_DIV_SHIFT) 7085 #define CRU_CLKSEL_CON08_CLK_UART2_DIV_SEL_SHIFT (7U) 7086 #define CRU_CLKSEL_CON08_CLK_UART2_DIV_SEL_MASK (0x1U << CRU_CLKSEL_CON08_CLK_UART2_DIV_SEL_SHIFT) 7087 #define CRU_CLKSEL_CON08_SCLK_UART2_SEL_SHIFT (15U) 7088 #define CRU_CLKSEL_CON08_SCLK_UART2_SEL_MASK (0x1U << CRU_CLKSEL_CON08_SCLK_UART2_SEL_SHIFT) 7089 /* CLKSEL_CON09 */ 7090 #define CRU_CLKSEL_CON09_OFFSET (0x124U) 7091 #define CRU_CLKSEL_CON09_CLK_UART2_FRAC_DIV_DIV_SHIFT (0U) 7092 #define CRU_CLKSEL_CON09_CLK_UART2_FRAC_DIV_DIV_MASK \ 7093 (0xFFFFFFFFU << CRU_CLKSEL_CON09_CLK_UART2_FRAC_DIV_DIV_SHIFT) 7094 /* CLKSEL_CON10 */ 7095 #define CRU_CLKSEL_CON10_OFFSET (0x128U) 7096 #define CRU_CLKSEL_CON10_CLK_I2C0_DIV_SHIFT (0U) 7097 #define CRU_CLKSEL_CON10_CLK_I2C0_DIV_MASK (0x3FU << CRU_CLKSEL_CON10_CLK_I2C0_DIV_SHIFT) 7098 #define CRU_CLKSEL_CON10_CLK_I2C0_SEL_SHIFT (6U) 7099 #define CRU_CLKSEL_CON10_CLK_I2C0_SEL_MASK (0x3U << CRU_CLKSEL_CON10_CLK_I2C0_SEL_SHIFT) 7100 #define CRU_CLKSEL_CON10_CLK_I2C1_DIV_SHIFT (8U) 7101 #define CRU_CLKSEL_CON10_CLK_I2C1_DIV_MASK (0x3FU << CRU_CLKSEL_CON10_CLK_I2C1_DIV_SHIFT) 7102 #define CRU_CLKSEL_CON10_CLK_I2C1_SEL_SHIFT (14U) 7103 #define CRU_CLKSEL_CON10_CLK_I2C1_SEL_MASK (0x3U << CRU_CLKSEL_CON10_CLK_I2C1_SEL_SHIFT) 7104 /* CLKSEL_CON11 */ 7105 #define CRU_CLKSEL_CON11_OFFSET (0x12CU) 7106 #define CRU_CLKSEL_CON11_CLK_I2C2_DIV_SHIFT (0U) 7107 #define CRU_CLKSEL_CON11_CLK_I2C2_DIV_MASK (0x3FU << CRU_CLKSEL_CON11_CLK_I2C2_DIV_SHIFT) 7108 #define CRU_CLKSEL_CON11_CLK_I2C2_SEL_SHIFT (6U) 7109 #define CRU_CLKSEL_CON11_CLK_I2C2_SEL_MASK (0x3U << CRU_CLKSEL_CON11_CLK_I2C2_SEL_SHIFT) 7110 #define CRU_CLKSEL_CON11_CLK_I2C_CODEC_DIV_SHIFT (8U) 7111 #define CRU_CLKSEL_CON11_CLK_I2C_CODEC_DIV_MASK (0x3FU << CRU_CLKSEL_CON11_CLK_I2C_CODEC_DIV_SHIFT) 7112 #define CRU_CLKSEL_CON11_CLK_I2C_CODEC_SEL_SHIFT (14U) 7113 #define CRU_CLKSEL_CON11_CLK_I2C_CODEC_SEL_MASK (0x3U << CRU_CLKSEL_CON11_CLK_I2C_CODEC_SEL_SHIFT) 7114 /* CLKSEL_CON12 */ 7115 #define CRU_CLKSEL_CON12_OFFSET (0x130U) 7116 #define CRU_CLKSEL_CON12_CLK_PWM0_DIV_SHIFT (0U) 7117 #define CRU_CLKSEL_CON12_CLK_PWM0_DIV_MASK (0x3FU << CRU_CLKSEL_CON12_CLK_PWM0_DIV_SHIFT) 7118 #define CRU_CLKSEL_CON12_CLK_PWM0_SEL_SHIFT (7U) 7119 #define CRU_CLKSEL_CON12_CLK_PWM0_SEL_MASK (0x1U << CRU_CLKSEL_CON12_CLK_PWM0_SEL_SHIFT) 7120 #define CRU_CLKSEL_CON12_CLK_PWM1_DIV_SHIFT (8U) 7121 #define CRU_CLKSEL_CON12_CLK_PWM1_DIV_MASK (0x3FU << CRU_CLKSEL_CON12_CLK_PWM1_DIV_SHIFT) 7122 #define CRU_CLKSEL_CON12_CLK_PWM1_SEL_SHIFT (15U) 7123 #define CRU_CLKSEL_CON12_CLK_PWM1_SEL_MASK (0x1U << CRU_CLKSEL_CON12_CLK_PWM1_SEL_SHIFT) 7124 /* CLKSEL_CON13 */ 7125 #define CRU_CLKSEL_CON13_OFFSET (0x134U) 7126 #define CRU_CLKSEL_CON13_CLK_PWM2_DIV_SHIFT (0U) 7127 #define CRU_CLKSEL_CON13_CLK_PWM2_DIV_MASK (0x3FU << CRU_CLKSEL_CON13_CLK_PWM2_DIV_SHIFT) 7128 #define CRU_CLKSEL_CON13_CLK_PWM2_SEL_SHIFT (7U) 7129 #define CRU_CLKSEL_CON13_CLK_PWM2_SEL_MASK (0x1U << CRU_CLKSEL_CON13_CLK_PWM2_SEL_SHIFT) 7130 #define CRU_CLKSEL_CON13_CLK_EFUSE_DIV_SHIFT (8U) 7131 #define CRU_CLKSEL_CON13_CLK_EFUSE_DIV_MASK (0x3FU << CRU_CLKSEL_CON13_CLK_EFUSE_DIV_SHIFT) 7132 /* CLKSEL_CON14 */ 7133 #define CRU_CLKSEL_CON14_OFFSET (0x138U) 7134 #define CRU_CLKSEL_CON14_CLK_SPI0_DIV_SHIFT (0U) 7135 #define CRU_CLKSEL_CON14_CLK_SPI0_DIV_MASK (0x3FU << CRU_CLKSEL_CON14_CLK_SPI0_DIV_SHIFT) 7136 #define CRU_CLKSEL_CON14_CLK_SPI0_SEL_SHIFT (7U) 7137 #define CRU_CLKSEL_CON14_CLK_SPI0_SEL_MASK (0x1U << CRU_CLKSEL_CON14_CLK_SPI0_SEL_SHIFT) 7138 #define CRU_CLKSEL_CON14_CLK_SPI1_DIV_SHIFT (8U) 7139 #define CRU_CLKSEL_CON14_CLK_SPI1_DIV_MASK (0x3FU << CRU_CLKSEL_CON14_CLK_SPI1_DIV_SHIFT) 7140 #define CRU_CLKSEL_CON14_CLK_SPI1_SEL_SHIFT (15U) 7141 #define CRU_CLKSEL_CON14_CLK_SPI1_SEL_MASK (0x1U << CRU_CLKSEL_CON14_CLK_SPI1_SEL_SHIFT) 7142 /* CLKSEL_CON15 */ 7143 #define CRU_CLKSEL_CON15_OFFSET (0x13CU) 7144 #define CRU_CLKSEL_CON15_CLK_TIMER_DIV_SHIFT (0U) 7145 #define CRU_CLKSEL_CON15_CLK_TIMER_DIV_MASK (0x3FU << CRU_CLKSEL_CON15_CLK_TIMER_DIV_SHIFT) 7146 #define CRU_CLKSEL_CON15_CLK_TIMER_SEL_SHIFT (7U) 7147 #define CRU_CLKSEL_CON15_CLK_TIMER_SEL_MASK (0x1U << CRU_CLKSEL_CON15_CLK_TIMER_SEL_SHIFT) 7148 #define CRU_CLKSEL_CON15_CLK_TOP_TIMER_DIV_SHIFT (8U) 7149 #define CRU_CLKSEL_CON15_CLK_TOP_TIMER_DIV_MASK (0x3FU << CRU_CLKSEL_CON15_CLK_TOP_TIMER_DIV_SHIFT) 7150 #define CRU_CLKSEL_CON15_CLK_TOP_TIMER_SEL_SHIFT (14U) 7151 #define CRU_CLKSEL_CON15_CLK_TOP_TIMER_SEL_MASK (0x3U << CRU_CLKSEL_CON15_CLK_TOP_TIMER_SEL_SHIFT) 7152 /* CLKSEL_CON16 */ 7153 #define CRU_CLKSEL_CON16_OFFSET (0x140U) 7154 #define CRU_CLKSEL_CON16_CLK_XIP_SFC0_DIV_SHIFT (0U) 7155 #define CRU_CLKSEL_CON16_CLK_XIP_SFC0_DIV_MASK (0x3FU << CRU_CLKSEL_CON16_CLK_XIP_SFC0_DIV_SHIFT) 7156 #define CRU_CLKSEL_CON16_CLK_XIP_SFC0_SEL_SHIFT (6U) 7157 #define CRU_CLKSEL_CON16_CLK_XIP_SFC0_SEL_MASK (0x3U << CRU_CLKSEL_CON16_CLK_XIP_SFC0_SEL_SHIFT) 7158 #define CRU_CLKSEL_CON16_CLK_XIP_SFC1_DIV_SHIFT (8U) 7159 #define CRU_CLKSEL_CON16_CLK_XIP_SFC1_DIV_MASK (0x3FU << CRU_CLKSEL_CON16_CLK_XIP_SFC1_DIV_SHIFT) 7160 #define CRU_CLKSEL_CON16_CLK_XIP_SFC1_SEL_SHIFT (14U) 7161 #define CRU_CLKSEL_CON16_CLK_XIP_SFC1_SEL_MASK (0x3U << CRU_CLKSEL_CON16_CLK_XIP_SFC1_SEL_SHIFT) 7162 /* CLKSEL_CON17 */ 7163 #define CRU_CLKSEL_CON17_OFFSET (0x144U) 7164 #define CRU_CLKSEL_CON17_CLK_XIP_HYPERX8_DIV_SHIFT (0U) 7165 #define CRU_CLKSEL_CON17_CLK_XIP_HYPERX8_DIV_MASK (0x3FU << CRU_CLKSEL_CON17_CLK_XIP_HYPERX8_DIV_SHIFT) 7166 #define CRU_CLKSEL_CON17_CLK_XIP_HYPERX8_SEL_SHIFT (6U) 7167 #define CRU_CLKSEL_CON17_CLK_XIP_HYPERX8_SEL_MASK (0x3U << CRU_CLKSEL_CON17_CLK_XIP_HYPERX8_SEL_SHIFT) 7168 /* CLKSEL_CON18 */ 7169 #define CRU_CLKSEL_CON18_OFFSET (0x148U) 7170 #define CRU_CLKSEL_CON18_CLK_AUDIOPWM_DIV_DIV_SHIFT (0U) 7171 #define CRU_CLKSEL_CON18_CLK_AUDIOPWM_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON18_CLK_AUDIOPWM_DIV_DIV_SHIFT) 7172 #define CRU_CLKSEL_CON18_CLK_AUDIOPWM_DIV_SEL_SHIFT (6U) 7173 #define CRU_CLKSEL_CON18_CLK_AUDIOPWM_DIV_SEL_MASK (0x3U << CRU_CLKSEL_CON18_CLK_AUDIOPWM_DIV_SEL_SHIFT) 7174 #define CRU_CLKSEL_CON18_SCLK_AUDIOPWM_SEL_SHIFT (15U) 7175 #define CRU_CLKSEL_CON18_SCLK_AUDIOPWM_SEL_MASK (0x1U << CRU_CLKSEL_CON18_SCLK_AUDIOPWM_SEL_SHIFT) 7176 /* CLKSEL_CON19 */ 7177 #define CRU_CLKSEL_CON19_OFFSET (0x14CU) 7178 #define CRU_CLKSEL_CON19_CLK_AUDIOPWM_FRAC_DIV_DIV_SHIFT (0U) 7179 #define CRU_CLKSEL_CON19_CLK_AUDIOPWM_FRAC_DIV_DIV_MASK \ 7180 (0xFFFFFFFFU << CRU_CLKSEL_CON19_CLK_AUDIOPWM_FRAC_DIV_DIV_SHIFT) 7181 /* CLKSEL_CON20 */ 7182 #define CRU_CLKSEL_CON20_OFFSET (0x150U) 7183 #define CRU_CLKSEL_CON20_ACLK_PERI_BUS_DIV_SHIFT (0U) 7184 #define CRU_CLKSEL_CON20_ACLK_PERI_BUS_DIV_MASK (0x1FU << CRU_CLKSEL_CON20_ACLK_PERI_BUS_DIV_SHIFT) 7185 #define CRU_CLKSEL_CON20_ACLK_PERI_BUS_SEL_SHIFT (7U) 7186 #define CRU_CLKSEL_CON20_ACLK_PERI_BUS_SEL_MASK (0x1U << CRU_CLKSEL_CON20_ACLK_PERI_BUS_SEL_SHIFT) 7187 #define CRU_CLKSEL_CON20_HCLK_PERI_BUS_DIV_SHIFT (8U) 7188 #define CRU_CLKSEL_CON20_HCLK_PERI_BUS_DIV_MASK (0x1FU << CRU_CLKSEL_CON20_HCLK_PERI_BUS_DIV_SHIFT) 7189 /* CLKSEL_CON21 */ 7190 #define CRU_CLKSEL_CON21_OFFSET (0x154U) 7191 #define CRU_CLKSEL_CON21_CLK_VIP_OUT_DIV_SHIFT (0U) 7192 #define CRU_CLKSEL_CON21_CLK_VIP_OUT_DIV_MASK (0x3FU << CRU_CLKSEL_CON21_CLK_VIP_OUT_DIV_SHIFT) 7193 #define CRU_CLKSEL_CON21_CLK_VIP_OUT_SEL_SHIFT (6U) 7194 #define CRU_CLKSEL_CON21_CLK_VIP_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON21_CLK_VIP_OUT_SEL_SHIFT) 7195 #define CRU_CLKSEL_CON21_CLK_SDMMC_DIV_SHIFT (8U) 7196 #define CRU_CLKSEL_CON21_CLK_SDMMC_DIV_MASK (0x7FU << CRU_CLKSEL_CON21_CLK_SDMMC_DIV_SHIFT) 7197 #define CRU_CLKSEL_CON21_CLK_SDMMC_SEL_SHIFT (15U) 7198 #define CRU_CLKSEL_CON21_CLK_SDMMC_SEL_MASK (0x1U << CRU_CLKSEL_CON21_CLK_SDMMC_SEL_SHIFT) 7199 /* CLKSEL_CON22 */ 7200 #define CRU_CLKSEL_CON22_OFFSET (0x158U) 7201 #define CRU_CLKSEL_CON22_CLK_CRYPTO_DIV_DIV_SHIFT (0U) 7202 #define CRU_CLKSEL_CON22_CLK_CRYPTO_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON22_CLK_CRYPTO_DIV_DIV_SHIFT) 7203 #define CRU_CLKSEL_CON22_CLK_CRYPTO_SRC_SEL_SHIFT (7U) 7204 #define CRU_CLKSEL_CON22_CLK_CRYPTO_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON22_CLK_CRYPTO_SRC_SEL_SHIFT) 7205 #define CRU_CLKSEL_CON22_CLK_CRYPTO_NP5_DIV_DIV_SHIFT (8U) 7206 #define CRU_CLKSEL_CON22_CLK_CRYPTO_NP5_DIV_DIV_MASK (0x1FU << CRU_CLKSEL_CON22_CLK_CRYPTO_NP5_DIV_DIV_SHIFT) 7207 #define CRU_CLKSEL_CON22_CLK_CRYPTO_PKA_SEL_SHIFT (14U) 7208 #define CRU_CLKSEL_CON22_CLK_CRYPTO_PKA_SEL_MASK (0x1U << CRU_CLKSEL_CON22_CLK_CRYPTO_PKA_SEL_SHIFT) 7209 #define CRU_CLKSEL_CON22_CLK_CRYPTO_SEL_SHIFT (15U) 7210 #define CRU_CLKSEL_CON22_CLK_CRYPTO_SEL_MASK (0x1U << CRU_CLKSEL_CON22_CLK_CRYPTO_SEL_SHIFT) 7211 /* CLKSEL_CON23 */ 7212 #define CRU_CLKSEL_CON23_OFFSET (0x15CU) 7213 #define CRU_CLKSEL_CON23_CLK_SARADC_DIV_SHIFT (0U) 7214 #define CRU_CLKSEL_CON23_CLK_SARADC_DIV_MASK (0xFFU << CRU_CLKSEL_CON23_CLK_SARADC_DIV_SHIFT) 7215 #define CRU_CLKSEL_CON23_CLK_TSADC_DIV_SHIFT (8U) 7216 #define CRU_CLKSEL_CON23_CLK_TSADC_DIV_MASK (0xFFU << CRU_CLKSEL_CON23_CLK_TSADC_DIV_SHIFT) 7217 /* CLKSEL_CON24 */ 7218 #define CRU_CLKSEL_CON24_OFFSET (0x160U) 7219 #define CRU_CLKSEL_CON24_HCLK_TOP_BUS_DIV_SHIFT (0U) 7220 #define CRU_CLKSEL_CON24_HCLK_TOP_BUS_DIV_MASK (0x3FU << CRU_CLKSEL_CON24_HCLK_TOP_BUS_DIV_SHIFT) 7221 #define CRU_CLKSEL_CON24_HCLK_TOP_BUS_SEL_SHIFT (6U) 7222 #define CRU_CLKSEL_CON24_HCLK_TOP_BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON24_HCLK_TOP_BUS_SEL_SHIFT) 7223 #define CRU_CLKSEL_CON24_PCLK_TOP_BUS_DIV_SHIFT (8U) 7224 #define CRU_CLKSEL_CON24_PCLK_TOP_BUS_DIV_MASK (0x3FU << CRU_CLKSEL_CON24_PCLK_TOP_BUS_DIV_SHIFT) 7225 #define CRU_CLKSEL_CON24_PCLK_TOP_BUS_SEL_SHIFT (14U) 7226 #define CRU_CLKSEL_CON24_PCLK_TOP_BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON24_PCLK_TOP_BUS_SEL_SHIFT) 7227 /* CLKSEL_CON25 */ 7228 #define CRU_CLKSEL_CON25_OFFSET (0x164U) 7229 #define CRU_CLKSEL_CON25_MCLK_PDM_DIV_SHIFT (0U) 7230 #define CRU_CLKSEL_CON25_MCLK_PDM_DIV_MASK (0x3FU << CRU_CLKSEL_CON25_MCLK_PDM_DIV_SHIFT) 7231 #define CRU_CLKSEL_CON25_MCLK_PDM_SEL_SHIFT (6U) 7232 #define CRU_CLKSEL_CON25_MCLK_PDM_SEL_MASK (0x3U << CRU_CLKSEL_CON25_MCLK_PDM_SEL_SHIFT) 7233 /* CLKSEL_CON26 */ 7234 #define CRU_CLKSEL_CON26_OFFSET (0x168U) 7235 #define CRU_CLKSEL_CON26_CLK_I2S8CH_0_TX_DIV_DIV_SHIFT (0U) 7236 #define CRU_CLKSEL_CON26_CLK_I2S8CH_0_TX_DIV_DIV_MASK (0x7FU << CRU_CLKSEL_CON26_CLK_I2S8CH_0_TX_DIV_DIV_SHIFT) 7237 #define CRU_CLKSEL_CON26_CLK_I2S8CH_0_TX_DIV_SEL_SHIFT (8U) 7238 #define CRU_CLKSEL_CON26_CLK_I2S8CH_0_TX_DIV_SEL_MASK (0x3U << CRU_CLKSEL_CON26_CLK_I2S8CH_0_TX_DIV_SEL_SHIFT) 7239 #define CRU_CLKSEL_CON26_MCLK_I2S8CH_0_TX_MUX_SEL_SHIFT (10U) 7240 #define CRU_CLKSEL_CON26_MCLK_I2S8CH_0_TX_MUX_SEL_MASK (0x3U << CRU_CLKSEL_CON26_MCLK_I2S8CH_0_TX_MUX_SEL_SHIFT) 7241 #define CRU_CLKSEL_CON26_MCLKOUT_I2S8CH_0_SEL_SHIFT (14U) 7242 #define CRU_CLKSEL_CON26_MCLKOUT_I2S8CH_0_SEL_MASK (0x3U << CRU_CLKSEL_CON26_MCLKOUT_I2S8CH_0_SEL_SHIFT) 7243 /* CLKSEL_CON27 */ 7244 #define CRU_CLKSEL_CON27_OFFSET (0x16CU) 7245 #define CRU_CLKSEL_CON27_CLK_I2S8CH_0_TX_FRAC_DIV_DIV_SHIFT (0U) 7246 #define CRU_CLKSEL_CON27_CLK_I2S8CH_0_TX_FRAC_DIV_DIV_MASK \ 7247 (0xFFFFFFFFU << CRU_CLKSEL_CON27_CLK_I2S8CH_0_TX_FRAC_DIV_DIV_SHIFT) 7248 /* CLKSEL_CON28 */ 7249 #define CRU_CLKSEL_CON28_OFFSET (0x170U) 7250 #define CRU_CLKSEL_CON28_CLK_I2S8CH_0_RX_DIV_DIV_SHIFT (0U) 7251 #define CRU_CLKSEL_CON28_CLK_I2S8CH_0_RX_DIV_DIV_MASK (0x7FU << CRU_CLKSEL_CON28_CLK_I2S8CH_0_RX_DIV_DIV_SHIFT) 7252 #define CRU_CLKSEL_CON28_CLK_I2S8CH_0_RX_DIV_SEL_SHIFT (8U) 7253 #define CRU_CLKSEL_CON28_CLK_I2S8CH_0_RX_DIV_SEL_MASK (0x3U << CRU_CLKSEL_CON28_CLK_I2S8CH_0_RX_DIV_SEL_SHIFT) 7254 #define CRU_CLKSEL_CON28_MCLK_I2S8CH_0_RX_MUX_SEL_SHIFT (10U) 7255 #define CRU_CLKSEL_CON28_MCLK_I2S8CH_0_RX_MUX_SEL_MASK (0x3U << CRU_CLKSEL_CON28_MCLK_I2S8CH_0_RX_MUX_SEL_SHIFT) 7256 /* CLKSEL_CON29 */ 7257 #define CRU_CLKSEL_CON29_OFFSET (0x174U) 7258 #define CRU_CLKSEL_CON29_CLK_I2S8CH_0_RX_FRAC_DIV_DIV_SHIFT (0U) 7259 #define CRU_CLKSEL_CON29_CLK_I2S8CH_0_RX_FRAC_DIV_DIV_MASK \ 7260 (0xFFFFFFFFU << CRU_CLKSEL_CON29_CLK_I2S8CH_0_RX_FRAC_DIV_DIV_SHIFT) 7261 /* CLKSEL_CON30 */ 7262 #define CRU_CLKSEL_CON30_OFFSET (0x178U) 7263 #define CRU_CLKSEL_CON30_CLK_I2S8CH_1_TX_DIV_DIV_SHIFT (0U) 7264 #define CRU_CLKSEL_CON30_CLK_I2S8CH_1_TX_DIV_DIV_MASK (0x7FU << CRU_CLKSEL_CON30_CLK_I2S8CH_1_TX_DIV_DIV_SHIFT) 7265 #define CRU_CLKSEL_CON30_CLK_I2S8CH_1_TX_DIV_SEL_SHIFT (8U) 7266 #define CRU_CLKSEL_CON30_CLK_I2S8CH_1_TX_DIV_SEL_MASK (0x3U << CRU_CLKSEL_CON30_CLK_I2S8CH_1_TX_DIV_SEL_SHIFT) 7267 #define CRU_CLKSEL_CON30_MCLK_I2S8CH_1_TX_MUX_SEL_SHIFT (10U) 7268 #define CRU_CLKSEL_CON30_MCLK_I2S8CH_1_TX_MUX_SEL_MASK (0x3U << CRU_CLKSEL_CON30_MCLK_I2S8CH_1_TX_MUX_SEL_SHIFT) 7269 #define CRU_CLKSEL_CON30_CLK_CODEC_SEL_SHIFT (15U) 7270 #define CRU_CLKSEL_CON30_CLK_CODEC_SEL_MASK (0x1U << CRU_CLKSEL_CON30_CLK_CODEC_SEL_SHIFT) 7271 /* CLKSEL_CON31 */ 7272 #define CRU_CLKSEL_CON31_OFFSET (0x17CU) 7273 #define CRU_CLKSEL_CON31_CLK_I2S8CH_1_TX_FRAC_DIV_DIV_SHIFT (0U) 7274 #define CRU_CLKSEL_CON31_CLK_I2S8CH_1_TX_FRAC_DIV_DIV_MASK \ 7275 (0xFFFFFFFFU << CRU_CLKSEL_CON31_CLK_I2S8CH_1_TX_FRAC_DIV_DIV_SHIFT) 7276 /* CLKSEL_CON32 */ 7277 #define CRU_CLKSEL_CON32_OFFSET (0x180U) 7278 #define CRU_CLKSEL_CON32_CLK_I2S8CH_1_RX_DIV_DIV_SHIFT (0U) 7279 #define CRU_CLKSEL_CON32_CLK_I2S8CH_1_RX_DIV_DIV_MASK (0x7FU << CRU_CLKSEL_CON32_CLK_I2S8CH_1_RX_DIV_DIV_SHIFT) 7280 #define CRU_CLKSEL_CON32_CLK_I2S8CH_1_RX_DIV_SEL_SHIFT (8U) 7281 #define CRU_CLKSEL_CON32_CLK_I2S8CH_1_RX_DIV_SEL_MASK (0x3U << CRU_CLKSEL_CON32_CLK_I2S8CH_1_RX_DIV_SEL_SHIFT) 7282 #define CRU_CLKSEL_CON32_MCLK_I2S8CH_1_RX_MUX_SEL_SHIFT (10U) 7283 #define CRU_CLKSEL_CON32_MCLK_I2S8CH_1_RX_MUX_SEL_MASK (0x3U << CRU_CLKSEL_CON32_MCLK_I2S8CH_1_RX_MUX_SEL_SHIFT) 7284 /* CLKSEL_CON33 */ 7285 #define CRU_CLKSEL_CON33_OFFSET (0x184U) 7286 #define CRU_CLKSEL_CON33_CLK_I2S8CH_1_RX_FRAC_DIV_DIV_SHIFT (0U) 7287 #define CRU_CLKSEL_CON33_CLK_I2S8CH_1_RX_FRAC_DIV_DIV_MASK \ 7288 (0xFFFFFFFFU << CRU_CLKSEL_CON33_CLK_I2S8CH_1_RX_FRAC_DIV_DIV_SHIFT) 7289 /* CLKSEL_CON34 */ 7290 #define CRU_CLKSEL_CON34_OFFSET (0x188U) 7291 #define CRU_CLKSEL_CON34_CLK_OTG_USBPHY_DIV_SHIFT (0U) 7292 #define CRU_CLKSEL_CON34_CLK_OTG_USBPHY_DIV_MASK (0x1FU << CRU_CLKSEL_CON34_CLK_OTG_USBPHY_DIV_SHIFT) 7293 /* CLKSEL_CON35 */ 7294 #define CRU_CLKSEL_CON35_OFFSET (0x18CU) 7295 #define CRU_CLKSEL_CON35_OUTCLOCK_TEST_DIV_SHIFT (0U) 7296 #define CRU_CLKSEL_CON35_OUTCLOCK_TEST_DIV_MASK (0xFU << CRU_CLKSEL_CON35_OUTCLOCK_TEST_DIV_SHIFT) 7297 #define CRU_CLKSEL_CON35_OUTCLOCK_TEST_SEL_SHIFT (4U) 7298 #define CRU_CLKSEL_CON35_OUTCLOCK_TEST_SEL_MASK (0x1FU << CRU_CLKSEL_CON35_OUTCLOCK_TEST_SEL_SHIFT) 7299 /* CLKSEL_CON36 */ 7300 #define CRU_CLKSEL_CON36_OFFSET (0x190U) 7301 #define CRU_CLKSEL_CON36_STCLK_M4F0_DIV_SHIFT (0U) 7302 #define CRU_CLKSEL_CON36_STCLK_M4F0_DIV_MASK (0x3FU << CRU_CLKSEL_CON36_STCLK_M4F0_DIV_SHIFT) 7303 #define CRU_CLKSEL_CON36_STCLK_M0_DIV_SHIFT (8U) 7304 #define CRU_CLKSEL_CON36_STCLK_M0_DIV_MASK (0x3FU << CRU_CLKSEL_CON36_STCLK_M0_DIV_SHIFT) 7305 /* CLKGATE_CON00 */ 7306 #define CRU_CLKGATE_CON00_OFFSET (0x300U) 7307 #define CRU_CLKGATE_CON00_CLK_32K_FRAC_DIV_EN_SHIFT (1U) 7308 #define CRU_CLKGATE_CON00_CLK_32K_FRAC_DIV_EN_MASK (0x1U << CRU_CLKGATE_CON00_CLK_32K_FRAC_DIV_EN_SHIFT) 7309 #define CRU_CLKGATE_CON00_CLK_32K_EN_SHIFT (2U) 7310 #define CRU_CLKGATE_CON00_CLK_32K_EN_MASK (0x1U << CRU_CLKGATE_CON00_CLK_32K_EN_SHIFT) 7311 #define CRU_CLKGATE_CON00_CLK_GPLL_MUX_DIV_NP5_EN_SHIFT (4U) 7312 #define CRU_CLKGATE_CON00_CLK_GPLL_MUX_DIV_NP5_EN_MASK (0x1U << CRU_CLKGATE_CON00_CLK_GPLL_MUX_DIV_NP5_EN_SHIFT) 7313 /* CLKGATE_CON01 */ 7314 #define CRU_CLKGATE_CON01_OFFSET (0x304U) 7315 #define CRU_CLKGATE_CON01_HCLK_MCU_BUS_PLL_EN_SHIFT (0U) 7316 #define CRU_CLKGATE_CON01_HCLK_MCU_BUS_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_MCU_BUS_PLL_EN_SHIFT) 7317 #define CRU_CLKGATE_CON01_HCLK_MCU_BUS_NIU_EN_SHIFT (1U) 7318 #define CRU_CLKGATE_CON01_HCLK_MCU_BUS_NIU_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_MCU_BUS_NIU_EN_SHIFT) 7319 #define CRU_CLKGATE_CON01_FCLK_M4F0_EN_SHIFT (2U) 7320 #define CRU_CLKGATE_CON01_FCLK_M4F0_EN_MASK (0x1U << CRU_CLKGATE_CON01_FCLK_M4F0_EN_SHIFT) 7321 #define CRU_CLKGATE_CON01_FCLK_M0_EN_SHIFT (4U) 7322 #define CRU_CLKGATE_CON01_FCLK_M0_EN_MASK (0x1U << CRU_CLKGATE_CON01_FCLK_M0_EN_SHIFT) 7323 #define CRU_CLKGATE_CON01_DCLK_M0_EN_SHIFT (6U) 7324 #define CRU_CLKGATE_CON01_DCLK_M0_EN_MASK (0x1U << CRU_CLKGATE_CON01_DCLK_M0_EN_SHIFT) 7325 #define CRU_CLKGATE_CON01_SCLK_M0_EN_SHIFT (7U) 7326 #define CRU_CLKGATE_CON01_SCLK_M0_EN_MASK (0x1U << CRU_CLKGATE_CON01_SCLK_M0_EN_SHIFT) 7327 #define CRU_CLKGATE_CON01_HCLK_INTMEM0_MCU_EN_SHIFT (9U) 7328 #define CRU_CLKGATE_CON01_HCLK_INTMEM0_MCU_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_INTMEM0_MCU_EN_SHIFT) 7329 #define CRU_CLKGATE_CON01_HCLK_INTMEM1_MCU_EN_SHIFT (10U) 7330 #define CRU_CLKGATE_CON01_HCLK_INTMEM1_MCU_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_INTMEM1_MCU_EN_SHIFT) 7331 #define CRU_CLKGATE_CON01_HCLK_DMAC_EN_SHIFT (11U) 7332 #define CRU_CLKGATE_CON01_HCLK_DMAC_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_DMAC_EN_SHIFT) 7333 #define CRU_CLKGATE_CON01_HCLK_ROM_EN_SHIFT (12U) 7334 #define CRU_CLKGATE_CON01_HCLK_ROM_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_ROM_EN_SHIFT) 7335 #define CRU_CLKGATE_CON01_HCLK_HIFI3_TCM_EN_SHIFT (13U) 7336 #define CRU_CLKGATE_CON01_HCLK_HIFI3_TCM_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_HIFI3_TCM_EN_SHIFT) 7337 #define CRU_CLKGATE_CON01_HCLK_VOP_EN_SHIFT (14U) 7338 #define CRU_CLKGATE_CON01_HCLK_VOP_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_VOP_EN_SHIFT) 7339 #define CRU_CLKGATE_CON01_HCLK_SFC0_EN_SHIFT (15U) 7340 #define CRU_CLKGATE_CON01_HCLK_SFC0_EN_MASK (0x1U << CRU_CLKGATE_CON01_HCLK_SFC0_EN_SHIFT) 7341 /* CLKGATE_CON02 */ 7342 #define CRU_CLKGATE_CON02_OFFSET (0x308U) 7343 #define CRU_CLKGATE_CON02_HCLK_SFC0_XIP_EN_SHIFT (0U) 7344 #define CRU_CLKGATE_CON02_HCLK_SFC0_XIP_EN_MASK (0x1U << CRU_CLKGATE_CON02_HCLK_SFC0_XIP_EN_SHIFT) 7345 #define CRU_CLKGATE_CON02_HCLK_SFC1_EN_SHIFT (1U) 7346 #define CRU_CLKGATE_CON02_HCLK_SFC1_EN_MASK (0x1U << CRU_CLKGATE_CON02_HCLK_SFC1_EN_SHIFT) 7347 #define CRU_CLKGATE_CON02_HCLK_SFC1_XIP_EN_SHIFT (2U) 7348 #define CRU_CLKGATE_CON02_HCLK_SFC1_XIP_EN_MASK (0x1U << CRU_CLKGATE_CON02_HCLK_SFC1_XIP_EN_SHIFT) 7349 #define CRU_CLKGATE_CON02_ACLK_XIP_HYPERX8_EN_SHIFT (3U) 7350 #define CRU_CLKGATE_CON02_ACLK_XIP_HYPERX8_EN_MASK (0x1U << CRU_CLKGATE_CON02_ACLK_XIP_HYPERX8_EN_SHIFT) 7351 #define CRU_CLKGATE_CON02_HCLK_AUDIOPWM_EN_SHIFT (4U) 7352 #define CRU_CLKGATE_CON02_HCLK_AUDIOPWM_EN_MASK (0x1U << CRU_CLKGATE_CON02_HCLK_AUDIOPWM_EN_SHIFT) 7353 #define CRU_CLKGATE_CON02_PCLK_MCU_BUS_PLL_EN_SHIFT (8U) 7354 #define CRU_CLKGATE_CON02_PCLK_MCU_BUS_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON02_PCLK_MCU_BUS_PLL_EN_SHIFT) 7355 #define CRU_CLKGATE_CON02_HCLK_AHB2APB_EN_SHIFT (9U) 7356 #define CRU_CLKGATE_CON02_HCLK_AHB2APB_EN_MASK (0x1U << CRU_CLKGATE_CON02_HCLK_AHB2APB_EN_SHIFT) 7357 #define CRU_CLKGATE_CON02_PCLK_UART0_EN_SHIFT (10U) 7358 #define CRU_CLKGATE_CON02_PCLK_UART0_EN_MASK (0x1U << CRU_CLKGATE_CON02_PCLK_UART0_EN_SHIFT) 7359 #define CRU_CLKGATE_CON02_PCLK_UART1_EN_SHIFT (11U) 7360 #define CRU_CLKGATE_CON02_PCLK_UART1_EN_MASK (0x1U << CRU_CLKGATE_CON02_PCLK_UART1_EN_SHIFT) 7361 #define CRU_CLKGATE_CON02_PCLK_UART2_EN_SHIFT (12U) 7362 #define CRU_CLKGATE_CON02_PCLK_UART2_EN_MASK (0x1U << CRU_CLKGATE_CON02_PCLK_UART2_EN_SHIFT) 7363 #define CRU_CLKGATE_CON02_PCLK_I2C0_EN_SHIFT (13U) 7364 #define CRU_CLKGATE_CON02_PCLK_I2C0_EN_MASK (0x1U << CRU_CLKGATE_CON02_PCLK_I2C0_EN_SHIFT) 7365 #define CRU_CLKGATE_CON02_PCLK_I2C1_EN_SHIFT (14U) 7366 #define CRU_CLKGATE_CON02_PCLK_I2C1_EN_MASK (0x1U << CRU_CLKGATE_CON02_PCLK_I2C1_EN_SHIFT) 7367 #define CRU_CLKGATE_CON02_PCLK_I2C2_EN_SHIFT (15U) 7368 #define CRU_CLKGATE_CON02_PCLK_I2C2_EN_MASK (0x1U << CRU_CLKGATE_CON02_PCLK_I2C2_EN_SHIFT) 7369 /* CLKGATE_CON03 */ 7370 #define CRU_CLKGATE_CON03_OFFSET (0x30CU) 7371 #define CRU_CLKGATE_CON03_PCLK_PWM0_EN_SHIFT (0U) 7372 #define CRU_CLKGATE_CON03_PCLK_PWM0_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_PWM0_EN_SHIFT) 7373 #define CRU_CLKGATE_CON03_PCLK_PWM1_EN_SHIFT (1U) 7374 #define CRU_CLKGATE_CON03_PCLK_PWM1_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_PWM1_EN_SHIFT) 7375 #define CRU_CLKGATE_CON03_PCLK_PWM2_EN_SHIFT (2U) 7376 #define CRU_CLKGATE_CON03_PCLK_PWM2_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_PWM2_EN_SHIFT) 7377 #define CRU_CLKGATE_CON03_PCLK_SPI0_EN_SHIFT (3U) 7378 #define CRU_CLKGATE_CON03_PCLK_SPI0_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_SPI0_EN_SHIFT) 7379 #define CRU_CLKGATE_CON03_PCLK_SPI1_EN_SHIFT (4U) 7380 #define CRU_CLKGATE_CON03_PCLK_SPI1_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_SPI1_EN_SHIFT) 7381 #define CRU_CLKGATE_CON03_PCLK_SARADC_CONTROL_EN_SHIFT (5U) 7382 #define CRU_CLKGATE_CON03_PCLK_SARADC_CONTROL_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_SARADC_CONTROL_EN_SHIFT) 7383 #define CRU_CLKGATE_CON03_PCLK_EFUSE_EN_SHIFT (6U) 7384 #define CRU_CLKGATE_CON03_PCLK_EFUSE_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_EFUSE_EN_SHIFT) 7385 #define CRU_CLKGATE_CON03_PCLK_TIMER_EN_SHIFT (7U) 7386 #define CRU_CLKGATE_CON03_PCLK_TIMER_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_TIMER_EN_SHIFT) 7387 #define CRU_CLKGATE_CON03_PCLK_WDT0_EN_SHIFT (8U) 7388 #define CRU_CLKGATE_CON03_PCLK_WDT0_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_WDT0_EN_SHIFT) 7389 #define CRU_CLKGATE_CON03_PCLK_WDT1_EN_SHIFT (9U) 7390 #define CRU_CLKGATE_CON03_PCLK_WDT1_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_WDT1_EN_SHIFT) 7391 #define CRU_CLKGATE_CON03_PCLK_WDT2_EN_SHIFT (10U) 7392 #define CRU_CLKGATE_CON03_PCLK_WDT2_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_WDT2_EN_SHIFT) 7393 #define CRU_CLKGATE_CON03_PCLK_MAILBOX0_EN_SHIFT (11U) 7394 #define CRU_CLKGATE_CON03_PCLK_MAILBOX0_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_MAILBOX0_EN_SHIFT) 7395 #define CRU_CLKGATE_CON03_PCLK_MAILBOX1_EN_SHIFT (12U) 7396 #define CRU_CLKGATE_CON03_PCLK_MAILBOX1_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_MAILBOX1_EN_SHIFT) 7397 #define CRU_CLKGATE_CON03_PCLK_INT_CTRL_EN_SHIFT (13U) 7398 #define CRU_CLKGATE_CON03_PCLK_INT_CTRL_EN_MASK (0x1U << CRU_CLKGATE_CON03_PCLK_INT_CTRL_EN_SHIFT) 7399 /* CLKGATE_CON04 */ 7400 #define CRU_CLKGATE_CON04_OFFSET (0x310U) 7401 #define CRU_CLKGATE_CON04_CLK_HIFI3_DIV_EN_SHIFT (0U) 7402 #define CRU_CLKGATE_CON04_CLK_HIFI3_DIV_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_HIFI3_DIV_EN_SHIFT) 7403 #define CRU_CLKGATE_CON04_CLK_HIFI3_NP5_DIV_EN_SHIFT (1U) 7404 #define CRU_CLKGATE_CON04_CLK_HIFI3_NP5_DIV_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_HIFI3_NP5_DIV_EN_SHIFT) 7405 #define CRU_CLKGATE_CON04_CLK_HIFI3_EN_SHIFT (2U) 7406 #define CRU_CLKGATE_CON04_CLK_HIFI3_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_HIFI3_EN_SHIFT) 7407 #define CRU_CLKGATE_CON04_ACLK_HIFI3_NIU_EN_SHIFT (3U) 7408 #define CRU_CLKGATE_CON04_ACLK_HIFI3_NIU_EN_MASK (0x1U << CRU_CLKGATE_CON04_ACLK_HIFI3_NIU_EN_SHIFT) 7409 #define CRU_CLKGATE_CON04_CLK_UART0_PLL_EN_SHIFT (4U) 7410 #define CRU_CLKGATE_CON04_CLK_UART0_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_UART0_PLL_EN_SHIFT) 7411 #define CRU_CLKGATE_CON04_CLK_UART0_FRAC_EN_SHIFT (5U) 7412 #define CRU_CLKGATE_CON04_CLK_UART0_FRAC_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_UART0_FRAC_EN_SHIFT) 7413 #define CRU_CLKGATE_CON04_SCLK_UART0_EN_SHIFT (6U) 7414 #define CRU_CLKGATE_CON04_SCLK_UART0_EN_MASK (0x1U << CRU_CLKGATE_CON04_SCLK_UART0_EN_SHIFT) 7415 #define CRU_CLKGATE_CON04_CLK_UART1_EN_SHIFT (7U) 7416 #define CRU_CLKGATE_CON04_CLK_UART1_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_UART1_EN_SHIFT) 7417 #define CRU_CLKGATE_CON04_CLK_UART1_FRAC_EN_SHIFT (8U) 7418 #define CRU_CLKGATE_CON04_CLK_UART1_FRAC_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_UART1_FRAC_EN_SHIFT) 7419 #define CRU_CLKGATE_CON04_SCLK_UART1_EN_SHIFT (9U) 7420 #define CRU_CLKGATE_CON04_SCLK_UART1_EN_MASK (0x1U << CRU_CLKGATE_CON04_SCLK_UART1_EN_SHIFT) 7421 #define CRU_CLKGATE_CON04_CLK_UART2_PLL_EN_SHIFT (10U) 7422 #define CRU_CLKGATE_CON04_CLK_UART2_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_UART2_PLL_EN_SHIFT) 7423 #define CRU_CLKGATE_CON04_CLK_UART2_FRAC_EN_SHIFT (11U) 7424 #define CRU_CLKGATE_CON04_CLK_UART2_FRAC_EN_MASK (0x1U << CRU_CLKGATE_CON04_CLK_UART2_FRAC_EN_SHIFT) 7425 #define CRU_CLKGATE_CON04_SCLK_UART2_EN_SHIFT (12U) 7426 #define CRU_CLKGATE_CON04_SCLK_UART2_EN_MASK (0x1U << CRU_CLKGATE_CON04_SCLK_UART2_EN_SHIFT) 7427 /* CLKGATE_CON05 */ 7428 #define CRU_CLKGATE_CON05_OFFSET (0x314U) 7429 #define CRU_CLKGATE_CON05_CLK_I2C0_PLL_EN_SHIFT (0U) 7430 #define CRU_CLKGATE_CON05_CLK_I2C0_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_I2C0_PLL_EN_SHIFT) 7431 #define CRU_CLKGATE_CON05_CLK_I2C1_PLL_EN_SHIFT (1U) 7432 #define CRU_CLKGATE_CON05_CLK_I2C1_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_I2C1_PLL_EN_SHIFT) 7433 #define CRU_CLKGATE_CON05_CLK_I2C2_PLL_EN_SHIFT (2U) 7434 #define CRU_CLKGATE_CON05_CLK_I2C2_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_I2C2_PLL_EN_SHIFT) 7435 #define CRU_CLKGATE_CON05_CLK_PWM0_PLL_EN_SHIFT (3U) 7436 #define CRU_CLKGATE_CON05_CLK_PWM0_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_PWM0_PLL_EN_SHIFT) 7437 #define CRU_CLKGATE_CON05_CLK_PWM1_PLL_EN_SHIFT (4U) 7438 #define CRU_CLKGATE_CON05_CLK_PWM1_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_PWM1_PLL_EN_SHIFT) 7439 #define CRU_CLKGATE_CON05_CLK_PWM2_PLL_EN_SHIFT (5U) 7440 #define CRU_CLKGATE_CON05_CLK_PWM2_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_PWM2_PLL_EN_SHIFT) 7441 #define CRU_CLKGATE_CON05_CLK_SPI0_PLL_EN_SHIFT (6U) 7442 #define CRU_CLKGATE_CON05_CLK_SPI0_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_SPI0_PLL_EN_SHIFT) 7443 #define CRU_CLKGATE_CON05_CLK_SPI1_PLL_EN_SHIFT (7U) 7444 #define CRU_CLKGATE_CON05_CLK_SPI1_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_SPI1_PLL_EN_SHIFT) 7445 #define CRU_CLKGATE_CON05_CLK_TIMER_PLL_EN_SHIFT (8U) 7446 #define CRU_CLKGATE_CON05_CLK_TIMER_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_TIMER_PLL_EN_SHIFT) 7447 #define CRU_CLKGATE_CON05_CLK_TIMER0_EN_SHIFT (9U) 7448 #define CRU_CLKGATE_CON05_CLK_TIMER0_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_TIMER0_EN_SHIFT) 7449 #define CRU_CLKGATE_CON05_CLK_TIMER1_EN_SHIFT (10U) 7450 #define CRU_CLKGATE_CON05_CLK_TIMER1_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_TIMER1_EN_SHIFT) 7451 #define CRU_CLKGATE_CON05_CLK_TIMER2_EN_SHIFT (11U) 7452 #define CRU_CLKGATE_CON05_CLK_TIMER2_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_TIMER2_EN_SHIFT) 7453 #define CRU_CLKGATE_CON05_CLK_TIMER3_EN_SHIFT (12U) 7454 #define CRU_CLKGATE_CON05_CLK_TIMER3_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_TIMER3_EN_SHIFT) 7455 #define CRU_CLKGATE_CON05_CLK_TIMER4_EN_SHIFT (13U) 7456 #define CRU_CLKGATE_CON05_CLK_TIMER4_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_TIMER4_EN_SHIFT) 7457 #define CRU_CLKGATE_CON05_CLK_TIMER5_EN_SHIFT (14U) 7458 #define CRU_CLKGATE_CON05_CLK_TIMER5_EN_MASK (0x1U << CRU_CLKGATE_CON05_CLK_TIMER5_EN_SHIFT) 7459 /* CLKGATE_CON06 */ 7460 #define CRU_CLKGATE_CON06_OFFSET (0x318U) 7461 #define CRU_CLKGATE_CON06_CLK_EFUSE_EN_SHIFT (2U) 7462 #define CRU_CLKGATE_CON06_CLK_EFUSE_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_EFUSE_EN_SHIFT) 7463 #define CRU_CLKGATE_CON06_CLK_XIP_SFC0_DT50_EN_SHIFT (3U) 7464 #define CRU_CLKGATE_CON06_CLK_XIP_SFC0_DT50_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_XIP_SFC0_DT50_EN_SHIFT) 7465 #define CRU_CLKGATE_CON06_CLK_XIP_SFC1_DT50_EN_SHIFT (4U) 7466 #define CRU_CLKGATE_CON06_CLK_XIP_SFC1_DT50_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_XIP_SFC1_DT50_EN_SHIFT) 7467 #define CRU_CLKGATE_CON06_CLK_XIP_HYPERX8_DT50_EN_SHIFT (5U) 7468 #define CRU_CLKGATE_CON06_CLK_XIP_HYPERX8_DT50_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_XIP_HYPERX8_DT50_EN_SHIFT) 7469 #define CRU_CLKGATE_CON06_STCLK_M4F0_EN_SHIFT (6U) 7470 #define CRU_CLKGATE_CON06_STCLK_M4F0_EN_MASK (0x1U << CRU_CLKGATE_CON06_STCLK_M4F0_EN_SHIFT) 7471 #define CRU_CLKGATE_CON06_CLK_AUDIOPWM_PLL_EN_SHIFT (7U) 7472 #define CRU_CLKGATE_CON06_CLK_AUDIOPWM_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_AUDIOPWM_PLL_EN_SHIFT) 7473 #define CRU_CLKGATE_CON06_CLK_AUDIOPWM_FRAC_EN_SHIFT (8U) 7474 #define CRU_CLKGATE_CON06_CLK_AUDIOPWM_FRAC_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_AUDIOPWM_FRAC_EN_SHIFT) 7475 #define CRU_CLKGATE_CON06_SCLK_AUDIOPWM_EN_SHIFT (9U) 7476 #define CRU_CLKGATE_CON06_SCLK_AUDIOPWM_EN_MASK (0x1U << CRU_CLKGATE_CON06_SCLK_AUDIOPWM_EN_SHIFT) 7477 #define CRU_CLKGATE_CON06_CLK_PWM_CAPTURE0_PLL_EN_SHIFT (10U) 7478 #define CRU_CLKGATE_CON06_CLK_PWM_CAPTURE0_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_PWM_CAPTURE0_PLL_EN_SHIFT) 7479 #define CRU_CLKGATE_CON06_CLK_PWM_CAPTURE1_PLL_EN_SHIFT (11U) 7480 #define CRU_CLKGATE_CON06_CLK_PWM_CAPTURE1_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_PWM_CAPTURE1_PLL_EN_SHIFT) 7481 #define CRU_CLKGATE_CON06_CLK_PWM_CAPTURE2_PLL_EN_SHIFT (12U) 7482 #define CRU_CLKGATE_CON06_CLK_PWM_CAPTURE2_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON06_CLK_PWM_CAPTURE2_PLL_EN_SHIFT) 7483 #define CRU_CLKGATE_CON06_STCLK_M0_EN_SHIFT (13U) 7484 #define CRU_CLKGATE_CON06_STCLK_M0_EN_MASK (0x1U << CRU_CLKGATE_CON06_STCLK_M0_EN_SHIFT) 7485 /* CLKGATE_CON07 */ 7486 #define CRU_CLKGATE_CON07_OFFSET (0x31CU) 7487 #define CRU_CLKGATE_CON07_ACLK_PERI_BUS_PLL_EN_SHIFT (0U) 7488 #define CRU_CLKGATE_CON07_ACLK_PERI_BUS_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON07_ACLK_PERI_BUS_PLL_EN_SHIFT) 7489 #define CRU_CLKGATE_CON07_HCLK_PERI_BUS_PLL_EN_SHIFT (1U) 7490 #define CRU_CLKGATE_CON07_HCLK_PERI_BUS_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON07_HCLK_PERI_BUS_PLL_EN_SHIFT) 7491 #define CRU_CLKGATE_CON07_ACLK_PERI_BUS_NIU_EN_SHIFT (2U) 7492 #define CRU_CLKGATE_CON07_ACLK_PERI_BUS_NIU_EN_MASK (0x1U << CRU_CLKGATE_CON07_ACLK_PERI_BUS_NIU_EN_SHIFT) 7493 #define CRU_CLKGATE_CON07_HCLK_PERI_BUS_NIU_EN_SHIFT (3U) 7494 #define CRU_CLKGATE_CON07_HCLK_PERI_BUS_NIU_EN_MASK (0x1U << CRU_CLKGATE_CON07_HCLK_PERI_BUS_NIU_EN_SHIFT) 7495 #define CRU_CLKGATE_CON07_ACLK_VIP_EN_SHIFT (4U) 7496 #define CRU_CLKGATE_CON07_ACLK_VIP_EN_MASK (0x1U << CRU_CLKGATE_CON07_ACLK_VIP_EN_SHIFT) 7497 #define CRU_CLKGATE_CON07_ACLK_CRYPTO_EN_SHIFT (5U) 7498 #define CRU_CLKGATE_CON07_ACLK_CRYPTO_EN_MASK (0x1U << CRU_CLKGATE_CON07_ACLK_CRYPTO_EN_SHIFT) 7499 #define CRU_CLKGATE_CON07_HCLK_VIP_EN_SHIFT (6U) 7500 #define CRU_CLKGATE_CON07_HCLK_VIP_EN_MASK (0x1U << CRU_CLKGATE_CON07_HCLK_VIP_EN_SHIFT) 7501 #define CRU_CLKGATE_CON07_HCLK_CRYPTO_EN_SHIFT (7U) 7502 #define CRU_CLKGATE_CON07_HCLK_CRYPTO_EN_MASK (0x1U << CRU_CLKGATE_CON07_HCLK_CRYPTO_EN_SHIFT) 7503 #define CRU_CLKGATE_CON07_HCLK_SDMMC_EN_SHIFT (8U) 7504 #define CRU_CLKGATE_CON07_HCLK_SDMMC_EN_MASK (0x1U << CRU_CLKGATE_CON07_HCLK_SDMMC_EN_SHIFT) 7505 #define CRU_CLKGATE_CON07_HCLK_USBOTG_EN_SHIFT (9U) 7506 #define CRU_CLKGATE_CON07_HCLK_USBOTG_EN_MASK (0x1U << CRU_CLKGATE_CON07_HCLK_USBOTG_EN_SHIFT) 7507 #define CRU_CLKGATE_CON07_HCLK_USBOTG_PMU_EN_SHIFT (10U) 7508 #define CRU_CLKGATE_CON07_HCLK_USBOTG_PMU_EN_MASK (0x1U << CRU_CLKGATE_CON07_HCLK_USBOTG_PMU_EN_SHIFT) 7509 #define CRU_CLKGATE_CON07_PCLK_SPI2APB_EN_SHIFT (13U) 7510 #define CRU_CLKGATE_CON07_PCLK_SPI2APB_EN_MASK (0x1U << CRU_CLKGATE_CON07_PCLK_SPI2APB_EN_SHIFT) 7511 #define CRU_CLKGATE_CON07_CLK_VIP_PLL_EN_SHIFT (14U) 7512 #define CRU_CLKGATE_CON07_CLK_VIP_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON07_CLK_VIP_PLL_EN_SHIFT) 7513 /* CLKGATE_CON08 */ 7514 #define CRU_CLKGATE_CON08_OFFSET (0x320U) 7515 #define CRU_CLKGATE_CON08_CLK_OTG_ADP_EN_SHIFT (1U) 7516 #define CRU_CLKGATE_CON08_CLK_OTG_ADP_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK_OTG_ADP_EN_SHIFT) 7517 #define CRU_CLKGATE_CON08_CLK_SDMMC_DT50_EN_SHIFT (2U) 7518 #define CRU_CLKGATE_CON08_CLK_SDMMC_DT50_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK_SDMMC_DT50_EN_SHIFT) 7519 #define CRU_CLKGATE_CON08_CLK_CRYPTO_DIV_EN_SHIFT (3U) 7520 #define CRU_CLKGATE_CON08_CLK_CRYPTO_DIV_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK_CRYPTO_DIV_EN_SHIFT) 7521 #define CRU_CLKGATE_CON08_CLK_CRYPTO_NP5_DIV_EN_SHIFT (4U) 7522 #define CRU_CLKGATE_CON08_CLK_CRYPTO_NP5_DIV_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK_CRYPTO_NP5_DIV_EN_SHIFT) 7523 #define CRU_CLKGATE_CON08_CLK_CRYPTO_EN_SHIFT (5U) 7524 #define CRU_CLKGATE_CON08_CLK_CRYPTO_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK_CRYPTO_EN_SHIFT) 7525 #define CRU_CLKGATE_CON08_CLK_CRYPTO_PKA_EN_SHIFT (6U) 7526 #define CRU_CLKGATE_CON08_CLK_CRYPTO_PKA_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK_CRYPTO_PKA_EN_SHIFT) 7527 #define CRU_CLKGATE_CON08_ACLK_WIFI_BUS_EN_SHIFT (8U) 7528 #define CRU_CLKGATE_CON08_ACLK_WIFI_BUS_EN_MASK (0x1U << CRU_CLKGATE_CON08_ACLK_WIFI_BUS_EN_SHIFT) 7529 #define CRU_CLKGATE_CON08_ACLK_WIFI_BUS_NIU_EN_SHIFT (9U) 7530 #define CRU_CLKGATE_CON08_ACLK_WIFI_BUS_NIU_EN_MASK (0x1U << CRU_CLKGATE_CON08_ACLK_WIFI_BUS_NIU_EN_SHIFT) 7531 #define CRU_CLKGATE_CON08_HCLK_BUFFER_EN_SHIFT (11U) 7532 #define CRU_CLKGATE_CON08_HCLK_BUFFER_EN_MASK (0x1U << CRU_CLKGATE_CON08_HCLK_BUFFER_EN_SHIFT) 7533 #define CRU_CLKGATE_CON08_CLK80_LPW_EN_SHIFT (12U) 7534 #define CRU_CLKGATE_CON08_CLK80_LPW_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK80_LPW_EN_SHIFT) 7535 #define CRU_CLKGATE_CON08_CLK40_LPW_EN_SHIFT (13U) 7536 #define CRU_CLKGATE_CON08_CLK40_LPW_EN_MASK (0x1U << CRU_CLKGATE_CON08_CLK40_LPW_EN_SHIFT) 7537 /* CLKGATE_CON09 */ 7538 #define CRU_CLKGATE_CON09_OFFSET (0x324U) 7539 #define CRU_CLKGATE_CON09_HCLK_TOP_BUS_PLL_EN_SHIFT (0U) 7540 #define CRU_CLKGATE_CON09_HCLK_TOP_BUS_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON09_HCLK_TOP_BUS_PLL_EN_SHIFT) 7541 #define CRU_CLKGATE_CON09_HCLK_TOP_BUS_NIU_EN_SHIFT (1U) 7542 #define CRU_CLKGATE_CON09_HCLK_TOP_BUS_NIU_EN_MASK (0x1U << CRU_CLKGATE_CON09_HCLK_TOP_BUS_NIU_EN_SHIFT) 7543 #define CRU_CLKGATE_CON09_HCLK_PDM_EN_SHIFT (2U) 7544 #define CRU_CLKGATE_CON09_HCLK_PDM_EN_MASK (0x1U << CRU_CLKGATE_CON09_HCLK_PDM_EN_SHIFT) 7545 #define CRU_CLKGATE_CON09_HCLK_I2S0_EN_SHIFT (3U) 7546 #define CRU_CLKGATE_CON09_HCLK_I2S0_EN_MASK (0x1U << CRU_CLKGATE_CON09_HCLK_I2S0_EN_SHIFT) 7547 #define CRU_CLKGATE_CON09_HCLK_I2S1_EN_SHIFT (4U) 7548 #define CRU_CLKGATE_CON09_HCLK_I2S1_EN_MASK (0x1U << CRU_CLKGATE_CON09_HCLK_I2S1_EN_SHIFT) 7549 #define CRU_CLKGATE_CON09_HCLK_VAD_EN_SHIFT (5U) 7550 #define CRU_CLKGATE_CON09_HCLK_VAD_EN_MASK (0x1U << CRU_CLKGATE_CON09_HCLK_VAD_EN_SHIFT) 7551 #define CRU_CLKGATE_CON09_PCLK_TOP_BUS_PLL_EN_SHIFT (6U) 7552 #define CRU_CLKGATE_CON09_PCLK_TOP_BUS_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_TOP_BUS_PLL_EN_SHIFT) 7553 #define CRU_CLKGATE_CON09_PCLK_TOP_BUS_NIU_EN_SHIFT (7U) 7554 #define CRU_CLKGATE_CON09_PCLK_TOP_BUS_NIU_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_TOP_BUS_NIU_EN_SHIFT) 7555 #define CRU_CLKGATE_CON09_PCLK_GPIO0_EN_SHIFT (8U) 7556 #define CRU_CLKGATE_CON09_PCLK_GPIO0_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_GPIO0_EN_SHIFT) 7557 #define CRU_CLKGATE_CON09_PCLK_GPIO1_EN_SHIFT (9U) 7558 #define CRU_CLKGATE_CON09_PCLK_GPIO1_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_GPIO1_EN_SHIFT) 7559 #define CRU_CLKGATE_CON09_PCLK_PMU_EN_SHIFT (10U) 7560 #define CRU_CLKGATE_CON09_PCLK_PMU_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_PMU_EN_SHIFT) 7561 #define CRU_CLKGATE_CON09_PCLK_CRU_EN_SHIFT (11U) 7562 #define CRU_CLKGATE_CON09_PCLK_CRU_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_CRU_EN_SHIFT) 7563 #define CRU_CLKGATE_CON09_PCLK_GRF_EN_SHIFT (12U) 7564 #define CRU_CLKGATE_CON09_PCLK_GRF_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_GRF_EN_SHIFT) 7565 #define CRU_CLKGATE_CON09_PCLK_ACODEC_EN_SHIFT (13U) 7566 #define CRU_CLKGATE_CON09_PCLK_ACODEC_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_ACODEC_EN_SHIFT) 7567 #define CRU_CLKGATE_CON09_PCLK_32KTRIM_EN_SHIFT (14U) 7568 #define CRU_CLKGATE_CON09_PCLK_32KTRIM_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_32KTRIM_EN_SHIFT) 7569 #define CRU_CLKGATE_CON09_PCLK_TOP_TIMER_EN_SHIFT (15U) 7570 #define CRU_CLKGATE_CON09_PCLK_TOP_TIMER_EN_MASK (0x1U << CRU_CLKGATE_CON09_PCLK_TOP_TIMER_EN_SHIFT) 7571 /* CLKGATE_CON10 */ 7572 #define CRU_CLKGATE_CON10_OFFSET (0x328U) 7573 #define CRU_CLKGATE_CON10_PCLK_PVTM_EN_SHIFT (0U) 7574 #define CRU_CLKGATE_CON10_PCLK_PVTM_EN_MASK (0x1U << CRU_CLKGATE_CON10_PCLK_PVTM_EN_SHIFT) 7575 #define CRU_CLKGATE_CON10_PCLK_TOUCH_DETECT_EN_SHIFT (1U) 7576 #define CRU_CLKGATE_CON10_PCLK_TOUCH_DETECT_EN_MASK (0x1U << CRU_CLKGATE_CON10_PCLK_TOUCH_DETECT_EN_SHIFT) 7577 #define CRU_CLKGATE_CON10_PCLK_TSADC_EN_SHIFT (2U) 7578 #define CRU_CLKGATE_CON10_PCLK_TSADC_EN_MASK (0x1U << CRU_CLKGATE_CON10_PCLK_TSADC_EN_SHIFT) 7579 #define CRU_CLKGATE_CON10_AON_SLEEP_CLK_EN_SHIFT (5U) 7580 #define CRU_CLKGATE_CON10_AON_SLEEP_CLK_EN_MASK (0x1U << CRU_CLKGATE_CON10_AON_SLEEP_CLK_EN_SHIFT) 7581 #define CRU_CLKGATE_CON10_CLK_32K_TOP_EN_SHIFT (6U) 7582 #define CRU_CLKGATE_CON10_CLK_32K_TOP_EN_MASK (0x1U << CRU_CLKGATE_CON10_CLK_32K_TOP_EN_SHIFT) 7583 #define CRU_CLKGATE_CON10_CLK_PMU_EN_SHIFT (7U) 7584 #define CRU_CLKGATE_CON10_CLK_PMU_EN_MASK (0x1U << CRU_CLKGATE_CON10_CLK_PMU_EN_SHIFT) 7585 #define CRU_CLKGATE_CON10_DBCLK_GPIO0_EN_SHIFT (8U) 7586 #define CRU_CLKGATE_CON10_DBCLK_GPIO0_EN_MASK (0x1U << CRU_CLKGATE_CON10_DBCLK_GPIO0_EN_SHIFT) 7587 #define CRU_CLKGATE_CON10_DBCLK_GPIO1_EN_SHIFT (9U) 7588 #define CRU_CLKGATE_CON10_DBCLK_GPIO1_EN_MASK (0x1U << CRU_CLKGATE_CON10_DBCLK_GPIO1_EN_SHIFT) 7589 #define CRU_CLKGATE_CON10_CLK_PMU_OSC_EN_SHIFT (10U) 7590 #define CRU_CLKGATE_CON10_CLK_PMU_OSC_EN_MASK (0x1U << CRU_CLKGATE_CON10_CLK_PMU_OSC_EN_SHIFT) 7591 #define CRU_CLKGATE_CON10_MCLK_PDM_PLL_EN_SHIFT (12U) 7592 #define CRU_CLKGATE_CON10_MCLK_PDM_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON10_MCLK_PDM_PLL_EN_SHIFT) 7593 #define CRU_CLKGATE_CON10_CLK_I2S8CH_0_TX_PLL_EN_SHIFT (13U) 7594 #define CRU_CLKGATE_CON10_CLK_I2S8CH_0_TX_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON10_CLK_I2S8CH_0_TX_PLL_EN_SHIFT) 7595 #define CRU_CLKGATE_CON10_CLK_I2S8CH_0_TX_FRAC_DIV_EN_SHIFT (14U) 7596 #define CRU_CLKGATE_CON10_CLK_I2S8CH_0_TX_FRAC_DIV_EN_MASK \ 7597 (0x1U << CRU_CLKGATE_CON10_CLK_I2S8CH_0_TX_FRAC_DIV_EN_SHIFT) 7598 #define CRU_CLKGATE_CON10_MCLK_I2S8CH_0_TX_EN_SHIFT (15U) 7599 #define CRU_CLKGATE_CON10_MCLK_I2S8CH_0_TX_EN_MASK (0x1U << CRU_CLKGATE_CON10_MCLK_I2S8CH_0_TX_EN_SHIFT) 7600 /* CLKGATE_CON11 */ 7601 #define CRU_CLKGATE_CON11_OFFSET (0x32CU) 7602 #define CRU_CLKGATE_CON11_CLK_I2S8CH_0_RX_PLL_EN_SHIFT (0U) 7603 #define CRU_CLKGATE_CON11_CLK_I2S8CH_0_RX_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON11_CLK_I2S8CH_0_RX_PLL_EN_SHIFT) 7604 #define CRU_CLKGATE_CON11_CLK_I2S8CH_0_RX_FRAC_DIV_EN_SHIFT (1U) 7605 #define CRU_CLKGATE_CON11_CLK_I2S8CH_0_RX_FRAC_DIV_EN_MASK \ 7606 (0x1U << CRU_CLKGATE_CON11_CLK_I2S8CH_0_RX_FRAC_DIV_EN_SHIFT) 7607 #define CRU_CLKGATE_CON11_MCLK_I2S8CH_0_RX_EN_SHIFT (2U) 7608 #define CRU_CLKGATE_CON11_MCLK_I2S8CH_0_RX_EN_MASK (0x1U << CRU_CLKGATE_CON11_MCLK_I2S8CH_0_RX_EN_SHIFT) 7609 #define CRU_CLKGATE_CON11_MCLKOUT_I2S8CH_0_EN_SHIFT (3U) 7610 #define CRU_CLKGATE_CON11_MCLKOUT_I2S8CH_0_EN_MASK (0x1U << CRU_CLKGATE_CON11_MCLKOUT_I2S8CH_0_EN_SHIFT) 7611 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_TX_PLL_EN_SHIFT (4U) 7612 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_TX_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON11_CLK_I2S8CH_1_TX_PLL_EN_SHIFT) 7613 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_TX_FRAC_DIV_EN_SHIFT (5U) 7614 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_TX_FRAC_DIV_EN_MASK \ 7615 (0x1U << CRU_CLKGATE_CON11_CLK_I2S8CH_1_TX_FRAC_DIV_EN_SHIFT) 7616 #define CRU_CLKGATE_CON11_MCLK_I2S8CH_1_TX_EN_SHIFT (6U) 7617 #define CRU_CLKGATE_CON11_MCLK_I2S8CH_1_TX_EN_MASK (0x1U << CRU_CLKGATE_CON11_MCLK_I2S8CH_1_TX_EN_SHIFT) 7618 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_RX_PLL_EN_SHIFT (7U) 7619 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_RX_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON11_CLK_I2S8CH_1_RX_PLL_EN_SHIFT) 7620 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_RX_FRAC_DIV_EN_SHIFT (8U) 7621 #define CRU_CLKGATE_CON11_CLK_I2S8CH_1_RX_FRAC_DIV_EN_MASK \ 7622 (0x1U << CRU_CLKGATE_CON11_CLK_I2S8CH_1_RX_FRAC_DIV_EN_SHIFT) 7623 #define CRU_CLKGATE_CON11_MCLK_I2S8CH_1_RX_EN_SHIFT (9U) 7624 #define CRU_CLKGATE_CON11_MCLK_I2S8CH_1_RX_EN_MASK (0x1U << CRU_CLKGATE_CON11_MCLK_I2S8CH_1_RX_EN_SHIFT) 7625 #define CRU_CLKGATE_CON11_SCLK_CODEC_EN_SHIFT (10U) 7626 #define CRU_CLKGATE_CON11_SCLK_CODEC_EN_MASK (0x1U << CRU_CLKGATE_CON11_SCLK_CODEC_EN_SHIFT) 7627 #define CRU_CLKGATE_CON11_CLK_I2C_CODEC_PLL_EN_SHIFT (11U) 7628 #define CRU_CLKGATE_CON11_CLK_I2C_CODEC_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON11_CLK_I2C_CODEC_PLL_EN_SHIFT) 7629 /* CLKGATE_CON12 */ 7630 #define CRU_CLKGATE_CON12_OFFSET (0x330U) 7631 #define CRU_CLKGATE_CON12_CLK_OTG_USBPHY_PLL_EN_SHIFT (3U) 7632 #define CRU_CLKGATE_CON12_CLK_OTG_USBPHY_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON12_CLK_OTG_USBPHY_PLL_EN_SHIFT) 7633 #define CRU_CLKGATE_CON12_CLK_32KTRIM_EN_SHIFT (4U) 7634 #define CRU_CLKGATE_CON12_CLK_32KTRIM_EN_MASK (0x1U << CRU_CLKGATE_CON12_CLK_32KTRIM_EN_SHIFT) 7635 #define CRU_CLKGATE_CON12_OUTCLOCK_TEST_EN_SHIFT (5U) 7636 #define CRU_CLKGATE_CON12_OUTCLOCK_TEST_EN_MASK (0x1U << CRU_CLKGATE_CON12_OUTCLOCK_TEST_EN_SHIFT) 7637 #define CRU_CLKGATE_CON12_CLK_PVTM_EN_SHIFT (7U) 7638 #define CRU_CLKGATE_CON12_CLK_PVTM_EN_MASK (0x1U << CRU_CLKGATE_CON12_CLK_PVTM_EN_SHIFT) 7639 #define CRU_CLKGATE_CON12_CLK_TOUCH_DETECT_EN_SHIFT (8U) 7640 #define CRU_CLKGATE_CON12_CLK_TOUCH_DETECT_EN_MASK (0x1U << CRU_CLKGATE_CON12_CLK_TOUCH_DETECT_EN_SHIFT) 7641 #define CRU_CLKGATE_CON12_CLK_TIMER_TOP_PLL_EN_SHIFT (9U) 7642 #define CRU_CLKGATE_CON12_CLK_TIMER_TOP_PLL_EN_MASK (0x1U << CRU_CLKGATE_CON12_CLK_TIMER_TOP_PLL_EN_SHIFT) 7643 #define CRU_CLKGATE_CON12_CLK_SARADC_EN_SHIFT (10U) 7644 #define CRU_CLKGATE_CON12_CLK_SARADC_EN_MASK (0x1U << CRU_CLKGATE_CON12_CLK_SARADC_EN_SHIFT) 7645 #define CRU_CLKGATE_CON12_CLK_TSADC_EN_SHIFT (11U) 7646 #define CRU_CLKGATE_CON12_CLK_TSADC_EN_MASK (0x1U << CRU_CLKGATE_CON12_CLK_TSADC_EN_SHIFT) 7647 /* SSCGTBL0_3 */ 7648 #define CRU_SSCGTBL0_3_OFFSET (0x380U) 7649 #define CRU_SSCGTBL0_3_SSCGTBL0_3_SHIFT (0U) 7650 #define CRU_SSCGTBL0_3_SSCGTBL0_3_MASK (0xFFFFFFFFU << CRU_SSCGTBL0_3_SSCGTBL0_3_SHIFT) 7651 /* SSCGTBL4_7 */ 7652 #define CRU_SSCGTBL4_7_OFFSET (0x384U) 7653 #define CRU_SSCGTBL4_7_SSCGTBL4_7_SHIFT (0U) 7654 #define CRU_SSCGTBL4_7_SSCGTBL4_7_MASK (0xFFFFFFFFU << CRU_SSCGTBL4_7_SSCGTBL4_7_SHIFT) 7655 /* SSCGTBL8_11 */ 7656 #define CRU_SSCGTBL8_11_OFFSET (0x388U) 7657 #define CRU_SSCGTBL8_11_SSCGTBL8_11_SHIFT (0U) 7658 #define CRU_SSCGTBL8_11_SSCGTBL8_11_MASK (0xFFFFFFFFU << CRU_SSCGTBL8_11_SSCGTBL8_11_SHIFT) 7659 /* SSCGTBL12_15 */ 7660 #define CRU_SSCGTBL12_15_OFFSET (0x38CU) 7661 #define CRU_SSCGTBL12_15_SSCGTBL12_15_SHIFT (0U) 7662 #define CRU_SSCGTBL12_15_SSCGTBL12_15_MASK (0xFFFFFFFFU << CRU_SSCGTBL12_15_SSCGTBL12_15_SHIFT) 7663 /* SSCGTBL16_19 */ 7664 #define CRU_SSCGTBL16_19_OFFSET (0x390U) 7665 #define CRU_SSCGTBL16_19_SSCGTBL16_19_SHIFT (0U) 7666 #define CRU_SSCGTBL16_19_SSCGTBL16_19_MASK (0xFFFFFFFFU << CRU_SSCGTBL16_19_SSCGTBL16_19_SHIFT) 7667 /* SSCGTBL20_23 */ 7668 #define CRU_SSCGTBL20_23_OFFSET (0x394U) 7669 #define CRU_SSCGTBL20_23_SSCGTBL20_23_SHIFT (0U) 7670 #define CRU_SSCGTBL20_23_SSCGTBL20_23_MASK (0xFFFFFFFFU << CRU_SSCGTBL20_23_SSCGTBL20_23_SHIFT) 7671 /* SSCGTBL24_27 */ 7672 #define CRU_SSCGTBL24_27_OFFSET (0x398U) 7673 #define CRU_SSCGTBL24_27_SSCGTBL24_27_SHIFT (0U) 7674 #define CRU_SSCGTBL24_27_SSCGTBL24_27_MASK (0xFFFFFFFFU << CRU_SSCGTBL24_27_SSCGTBL24_27_SHIFT) 7675 /* SSCGTBL28_31 */ 7676 #define CRU_SSCGTBL28_31_OFFSET (0x39CU) 7677 #define CRU_SSCGTBL28_31_SSCGTBL28_31_SHIFT (0U) 7678 #define CRU_SSCGTBL28_31_SSCGTBL28_31_MASK (0xFFFFFFFFU << CRU_SSCGTBL28_31_SSCGTBL28_31_SHIFT) 7679 /* SSCGTBL32_35 */ 7680 #define CRU_SSCGTBL32_35_OFFSET (0x3A0U) 7681 #define CRU_SSCGTBL32_35_SSCGTBL32_35_SHIFT (0U) 7682 #define CRU_SSCGTBL32_35_SSCGTBL32_35_MASK (0xFFFFFFFFU << CRU_SSCGTBL32_35_SSCGTBL32_35_SHIFT) 7683 /* SSCGTBL36_39 */ 7684 #define CRU_SSCGTBL36_39_OFFSET (0x3A4U) 7685 #define CRU_SSCGTBL36_39_SSCGTBL36_39_SHIFT (0U) 7686 #define CRU_SSCGTBL36_39_SSCGTBL36_39_MASK (0xFFFFFFFFU << CRU_SSCGTBL36_39_SSCGTBL36_39_SHIFT) 7687 /* SSCGTBL40_43 */ 7688 #define CRU_SSCGTBL40_43_OFFSET (0x3A8U) 7689 #define CRU_SSCGTBL40_43_SSCGTBL40_43_SHIFT (0U) 7690 #define CRU_SSCGTBL40_43_SSCGTBL40_43_MASK (0xFFFFFFFFU << CRU_SSCGTBL40_43_SSCGTBL40_43_SHIFT) 7691 /* SSCGTBL44_47 */ 7692 #define CRU_SSCGTBL44_47_OFFSET (0x3ACU) 7693 #define CRU_SSCGTBL44_47_SSCGTBL44_47_SHIFT (0U) 7694 #define CRU_SSCGTBL44_47_SSCGTBL44_47_MASK (0xFFFFFFFFU << CRU_SSCGTBL44_47_SSCGTBL44_47_SHIFT) 7695 /* SSCGTBL48_51 */ 7696 #define CRU_SSCGTBL48_51_OFFSET (0x3B0U) 7697 #define CRU_SSCGTBL48_51_SSCGTBL48_51_SHIFT (0U) 7698 #define CRU_SSCGTBL48_51_SSCGTBL48_51_MASK (0xFFFFFFFFU << CRU_SSCGTBL48_51_SSCGTBL48_51_SHIFT) 7699 /* SSCGTBL52_55 */ 7700 #define CRU_SSCGTBL52_55_OFFSET (0x3B4U) 7701 #define CRU_SSCGTBL52_55_SSCGTBL52_55_SHIFT (0U) 7702 #define CRU_SSCGTBL52_55_SSCGTBL52_55_MASK (0xFFFFFFFFU << CRU_SSCGTBL52_55_SSCGTBL52_55_SHIFT) 7703 /* SSCGTBL56_59 */ 7704 #define CRU_SSCGTBL56_59_OFFSET (0x3B8U) 7705 #define CRU_SSCGTBL56_59_SSCGTBL56_59_SHIFT (0U) 7706 #define CRU_SSCGTBL56_59_SSCGTBL56_59_MASK (0xFFFFFFFFU << CRU_SSCGTBL56_59_SSCGTBL56_59_SHIFT) 7707 /* SSCGTBL60_63 */ 7708 #define CRU_SSCGTBL60_63_OFFSET (0x3BCU) 7709 #define CRU_SSCGTBL60_63_SSCGTBL60_63_SHIFT (0U) 7710 #define CRU_SSCGTBL60_63_SSCGTBL60_63_MASK (0xFFFFFFFFU << CRU_SSCGTBL60_63_SSCGTBL60_63_SHIFT) 7711 /* SSCGTBL64_67 */ 7712 #define CRU_SSCGTBL64_67_OFFSET (0x3C0U) 7713 #define CRU_SSCGTBL64_67_SSCGTBL64_67_SHIFT (0U) 7714 #define CRU_SSCGTBL64_67_SSCGTBL64_67_MASK (0xFFFFFFFFU << CRU_SSCGTBL64_67_SSCGTBL64_67_SHIFT) 7715 /* SSCGTBL68_71 */ 7716 #define CRU_SSCGTBL68_71_OFFSET (0x3C4U) 7717 #define CRU_SSCGTBL68_71_SSCGTBL68_71_SHIFT (0U) 7718 #define CRU_SSCGTBL68_71_SSCGTBL68_71_MASK (0xFFFFFFFFU << CRU_SSCGTBL68_71_SSCGTBL68_71_SHIFT) 7719 /* SSCGTBL72_75 */ 7720 #define CRU_SSCGTBL72_75_OFFSET (0x3C8U) 7721 #define CRU_SSCGTBL72_75_SSCGTBL72_75_SHIFT (0U) 7722 #define CRU_SSCGTBL72_75_SSCGTBL72_75_MASK (0xFFFFFFFFU << CRU_SSCGTBL72_75_SSCGTBL72_75_SHIFT) 7723 /* SSCGTBL76_79 */ 7724 #define CRU_SSCGTBL76_79_OFFSET (0x3CCU) 7725 #define CRU_SSCGTBL76_79_SSCGTBL76_79_SHIFT (0U) 7726 #define CRU_SSCGTBL76_79_SSCGTBL76_79_MASK (0xFFFFFFFFU << CRU_SSCGTBL76_79_SSCGTBL76_79_SHIFT) 7727 /* SSCGTBL80_83 */ 7728 #define CRU_SSCGTBL80_83_OFFSET (0x3D0U) 7729 #define CRU_SSCGTBL80_83_SSCGTBL80_83_SHIFT (0U) 7730 #define CRU_SSCGTBL80_83_SSCGTBL80_83_MASK (0xFFFFFFFFU << CRU_SSCGTBL80_83_SSCGTBL80_83_SHIFT) 7731 /* SSCGTBL84_87 */ 7732 #define CRU_SSCGTBL84_87_OFFSET (0x3D4U) 7733 #define CRU_SSCGTBL84_87_SSCGTBL84_87_SHIFT (0U) 7734 #define CRU_SSCGTBL84_87_SSCGTBL84_87_MASK (0xFFFFFFFFU << CRU_SSCGTBL84_87_SSCGTBL84_87_SHIFT) 7735 /* SSCGTBL88_91 */ 7736 #define CRU_SSCGTBL88_91_OFFSET (0x3D8U) 7737 #define CRU_SSCGTBL88_91_SSCGTBL88_91_SHIFT (0U) 7738 #define CRU_SSCGTBL88_91_SSCGTBL88_91_MASK (0xFFFFFFFFU << CRU_SSCGTBL88_91_SSCGTBL88_91_SHIFT) 7739 /* SSCGTBL92_95 */ 7740 #define CRU_SSCGTBL92_95_OFFSET (0x3DCU) 7741 #define CRU_SSCGTBL92_95_SSCGTBL92_95_SHIFT (0U) 7742 #define CRU_SSCGTBL92_95_SSCGTBL92_95_MASK (0xFFFFFFFFU << CRU_SSCGTBL92_95_SSCGTBL92_95_SHIFT) 7743 /* SSCGTBL96_99 */ 7744 #define CRU_SSCGTBL96_99_OFFSET (0x3E0U) 7745 #define CRU_SSCGTBL96_99_SSCGTBL96_99_SHIFT (0U) 7746 #define CRU_SSCGTBL96_99_SSCGTBL96_99_MASK (0xFFFFFFFFU << CRU_SSCGTBL96_99_SSCGTBL96_99_SHIFT) 7747 /* SSCGTBL100_103 */ 7748 #define CRU_SSCGTBL100_103_OFFSET (0x3E4U) 7749 #define CRU_SSCGTBL100_103_SSCGTBL100_103_SHIFT (0U) 7750 #define CRU_SSCGTBL100_103_SSCGTBL100_103_MASK (0xFFFFFFFFU << CRU_SSCGTBL100_103_SSCGTBL100_103_SHIFT) 7751 /* SSCGTBL104_107 */ 7752 #define CRU_SSCGTBL104_107_OFFSET (0x3E8U) 7753 #define CRU_SSCGTBL104_107_SSCGTBL104_107_SHIFT (0U) 7754 #define CRU_SSCGTBL104_107_SSCGTBL104_107_MASK (0xFFFFFFFFU << CRU_SSCGTBL104_107_SSCGTBL104_107_SHIFT) 7755 /* SSCGTBL108_111 */ 7756 #define CRU_SSCGTBL108_111_OFFSET (0x3ECU) 7757 #define CRU_SSCGTBL108_111_SSCGTBL108_111_SHIFT (0U) 7758 #define CRU_SSCGTBL108_111_SSCGTBL108_111_MASK (0xFFFFFFFFU << CRU_SSCGTBL108_111_SSCGTBL108_111_SHIFT) 7759 /* SSCGTBL112_115 */ 7760 #define CRU_SSCGTBL112_115_OFFSET (0x3F0U) 7761 #define CRU_SSCGTBL112_115_SSCGTBL112_115_SHIFT (0U) 7762 #define CRU_SSCGTBL112_115_SSCGTBL112_115_MASK (0xFFFFFFFFU << CRU_SSCGTBL112_115_SSCGTBL112_115_SHIFT) 7763 /* SSCGTBL116_119 */ 7764 #define CRU_SSCGTBL116_119_OFFSET (0x3F4U) 7765 #define CRU_SSCGTBL116_119_SSCGTBL116_119_SHIFT (0U) 7766 #define CRU_SSCGTBL116_119_SSCGTBL116_119_MASK (0xFFFFFFFFU << CRU_SSCGTBL116_119_SSCGTBL116_119_SHIFT) 7767 /* SSCGTBL120_123 */ 7768 #define CRU_SSCGTBL120_123_OFFSET (0x3F8U) 7769 #define CRU_SSCGTBL120_123_SSCGTBL120_123_SHIFT (0U) 7770 #define CRU_SSCGTBL120_123_SSCGTBL120_123_MASK (0xFFFFFFFFU << CRU_SSCGTBL120_123_SSCGTBL120_123_SHIFT) 7771 /* SSCGTBL124_127 */ 7772 #define CRU_SSCGTBL124_127_OFFSET (0x3FCU) 7773 #define CRU_SSCGTBL124_127_SSCGTBL124_127_SHIFT (0U) 7774 #define CRU_SSCGTBL124_127_SSCGTBL124_127_MASK (0xFFFFFFFFU << CRU_SSCGTBL124_127_SSCGTBL124_127_SHIFT) 7775 /* SOFTRST_CON00 */ 7776 #define CRU_SOFTRST_CON00_OFFSET (0x400U) 7777 #define CRU_SOFTRST_CON00_HRESETN_MCU_BUS_AC_SHIFT (1U) 7778 #define CRU_SOFTRST_CON00_HRESETN_MCU_BUS_AC_MASK (0x1U << CRU_SOFTRST_CON00_HRESETN_MCU_BUS_AC_SHIFT) 7779 #define CRU_SOFTRST_CON00_PORESETN_M4F0_AC_SHIFT (2U) 7780 #define CRU_SOFTRST_CON00_PORESETN_M4F0_AC_MASK (0x1U << CRU_SOFTRST_CON00_PORESETN_M4F0_AC_SHIFT) 7781 #define CRU_SOFTRST_CON00_HRESETN_M4F0_AC_SHIFT (3U) 7782 #define CRU_SOFTRST_CON00_HRESETN_M4F0_AC_MASK (0x1U << CRU_SOFTRST_CON00_HRESETN_M4F0_AC_SHIFT) 7783 #define CRU_SOFTRST_CON00_PORESETN_M0_AC_SHIFT (4U) 7784 #define CRU_SOFTRST_CON00_PORESETN_M0_AC_MASK (0x1U << CRU_SOFTRST_CON00_PORESETN_M0_AC_SHIFT) 7785 #define CRU_SOFTRST_CON00_HRESETN_M0_AC_SHIFT (5U) 7786 #define CRU_SOFTRST_CON00_HRESETN_M0_AC_MASK (0x1U << CRU_SOFTRST_CON00_HRESETN_M0_AC_SHIFT) 7787 #define CRU_SOFTRST_CON00_DBRESETN_M0_AC_SHIFT (6U) 7788 #define CRU_SOFTRST_CON00_DBRESETN_M0_AC_MASK (0x1U << CRU_SOFTRST_CON00_DBRESETN_M0_AC_SHIFT) 7789 #define CRU_SOFTRST_CON00_PRESETN_TOP_BUS_AC_SHIFT (7U) 7790 #define CRU_SOFTRST_CON00_PRESETN_TOP_BUS_AC_MASK (0x1U << CRU_SOFTRST_CON00_PRESETN_TOP_BUS_AC_SHIFT) 7791 #define CRU_SOFTRST_CON00_PRESETN_CRU_AC_SHIFT (8U) 7792 #define CRU_SOFTRST_CON00_PRESETN_CRU_AC_MASK (0x1U << CRU_SOFTRST_CON00_PRESETN_CRU_AC_SHIFT) 7793 /* SOFTRST_CON01 */ 7794 #define CRU_SOFTRST_CON01_OFFSET (0x404U) 7795 #define CRU_SOFTRST_CON01_HRESETN_MCU_BUS_NIU_SHIFT (1U) 7796 #define CRU_SOFTRST_CON01_HRESETN_MCU_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_MCU_BUS_NIU_SHIFT) 7797 #define CRU_SOFTRST_CON01_PORESETN_M4F0_SHIFT (2U) 7798 #define CRU_SOFTRST_CON01_PORESETN_M4F0_MASK (0x1U << CRU_SOFTRST_CON01_PORESETN_M4F0_SHIFT) 7799 #define CRU_SOFTRST_CON01_HRESETN_M4F0_SHIFT (3U) 7800 #define CRU_SOFTRST_CON01_HRESETN_M4F0_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_M4F0_SHIFT) 7801 #define CRU_SOFTRST_CON01_PORESETN_M0_SHIFT (4U) 7802 #define CRU_SOFTRST_CON01_PORESETN_M0_MASK (0x1U << CRU_SOFTRST_CON01_PORESETN_M0_SHIFT) 7803 #define CRU_SOFTRST_CON01_HRESETN_M0_SHIFT (5U) 7804 #define CRU_SOFTRST_CON01_HRESETN_M0_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_M0_SHIFT) 7805 #define CRU_SOFTRST_CON01_DBRESETN_M0_SHIFT (6U) 7806 #define CRU_SOFTRST_CON01_DBRESETN_M0_MASK (0x1U << CRU_SOFTRST_CON01_DBRESETN_M0_SHIFT) 7807 #define CRU_SOFTRST_CON01_HRESETN_INTMEM0_SHIFT (9U) 7808 #define CRU_SOFTRST_CON01_HRESETN_INTMEM0_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_INTMEM0_SHIFT) 7809 #define CRU_SOFTRST_CON01_HRESETN_INTMEM1_SHIFT (10U) 7810 #define CRU_SOFTRST_CON01_HRESETN_INTMEM1_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_INTMEM1_SHIFT) 7811 #define CRU_SOFTRST_CON01_HRESETN_DMAC_SHIFT (11U) 7812 #define CRU_SOFTRST_CON01_HRESETN_DMAC_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_DMAC_SHIFT) 7813 #define CRU_SOFTRST_CON01_HRESETN_ROM_SHIFT (12U) 7814 #define CRU_SOFTRST_CON01_HRESETN_ROM_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_ROM_SHIFT) 7815 #define CRU_SOFTRST_CON01_HRESETN_HIFI3_TCM_SHIFT (13U) 7816 #define CRU_SOFTRST_CON01_HRESETN_HIFI3_TCM_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_HIFI3_TCM_SHIFT) 7817 #define CRU_SOFTRST_CON01_HRESETN_VOP_SHIFT (14U) 7818 #define CRU_SOFTRST_CON01_HRESETN_VOP_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_VOP_SHIFT) 7819 #define CRU_SOFTRST_CON01_HRESETN_SFC0_SHIFT (15U) 7820 #define CRU_SOFTRST_CON01_HRESETN_SFC0_MASK (0x1U << CRU_SOFTRST_CON01_HRESETN_SFC0_SHIFT) 7821 /* SOFTRST_CON02 */ 7822 #define CRU_SOFTRST_CON02_OFFSET (0x408U) 7823 #define CRU_SOFTRST_CON02_HRESETN_SFC0_XIP_SHIFT (0U) 7824 #define CRU_SOFTRST_CON02_HRESETN_SFC0_XIP_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_SFC0_XIP_SHIFT) 7825 #define CRU_SOFTRST_CON02_HRESETN_SFC1_SHIFT (1U) 7826 #define CRU_SOFTRST_CON02_HRESETN_SFC1_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_SFC1_SHIFT) 7827 #define CRU_SOFTRST_CON02_HRESETN_SFC1_XIP_SHIFT (2U) 7828 #define CRU_SOFTRST_CON02_HRESETN_SFC1_XIP_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_SFC1_XIP_SHIFT) 7829 #define CRU_SOFTRST_CON02_ARESETN_XIP_HYPERX8_SHIFT (3U) 7830 #define CRU_SOFTRST_CON02_ARESETN_XIP_HYPERX8_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_XIP_HYPERX8_SHIFT) 7831 #define CRU_SOFTRST_CON02_HRESETN_AUDIOPWM_SHIFT (4U) 7832 #define CRU_SOFTRST_CON02_HRESETN_AUDIOPWM_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_AUDIOPWM_SHIFT) 7833 #define CRU_SOFTRST_CON02_HRESETN_AHB2APB_SHIFT (9U) 7834 #define CRU_SOFTRST_CON02_HRESETN_AHB2APB_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_AHB2APB_SHIFT) 7835 #define CRU_SOFTRST_CON02_PRESETN_UART0_SHIFT (10U) 7836 #define CRU_SOFTRST_CON02_PRESETN_UART0_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_UART0_SHIFT) 7837 #define CRU_SOFTRST_CON02_PRESETN_UART1_SHIFT (11U) 7838 #define CRU_SOFTRST_CON02_PRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_UART1_SHIFT) 7839 #define CRU_SOFTRST_CON02_PRESETN_UART2_SHIFT (12U) 7840 #define CRU_SOFTRST_CON02_PRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_UART2_SHIFT) 7841 #define CRU_SOFTRST_CON02_PRESETN_I2C0_SHIFT (13U) 7842 #define CRU_SOFTRST_CON02_PRESETN_I2C0_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_I2C0_SHIFT) 7843 #define CRU_SOFTRST_CON02_PRESETN_I2C1_SHIFT (14U) 7844 #define CRU_SOFTRST_CON02_PRESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_I2C1_SHIFT) 7845 #define CRU_SOFTRST_CON02_PRESETN_I2C2_SHIFT (15U) 7846 #define CRU_SOFTRST_CON02_PRESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_I2C2_SHIFT) 7847 /* SOFTRST_CON03 */ 7848 #define CRU_SOFTRST_CON03_OFFSET (0x40CU) 7849 #define CRU_SOFTRST_CON03_PRESETN_PWM0_SHIFT (0U) 7850 #define CRU_SOFTRST_CON03_PRESETN_PWM0_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_PWM0_SHIFT) 7851 #define CRU_SOFTRST_CON03_PRESETN_PWM1_SHIFT (1U) 7852 #define CRU_SOFTRST_CON03_PRESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_PWM1_SHIFT) 7853 #define CRU_SOFTRST_CON03_PRESETN_PWM2_SHIFT (2U) 7854 #define CRU_SOFTRST_CON03_PRESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_PWM2_SHIFT) 7855 #define CRU_SOFTRST_CON03_PRESETN_SPI0_SHIFT (3U) 7856 #define CRU_SOFTRST_CON03_PRESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_SPI0_SHIFT) 7857 #define CRU_SOFTRST_CON03_PRESETN_SPI1_SHIFT (4U) 7858 #define CRU_SOFTRST_CON03_PRESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_SPI1_SHIFT) 7859 #define CRU_SOFTRST_CON03_PRESETN_SARADC_CONTROL_SHIFT (5U) 7860 #define CRU_SOFTRST_CON03_PRESETN_SARADC_CONTROL_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_SARADC_CONTROL_SHIFT) 7861 #define CRU_SOFTRST_CON03_PRESETN_EFUSE_SHIFT (6U) 7862 #define CRU_SOFTRST_CON03_PRESETN_EFUSE_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_EFUSE_SHIFT) 7863 #define CRU_SOFTRST_CON03_PRESETN_TIMER_SHIFT (7U) 7864 #define CRU_SOFTRST_CON03_PRESETN_TIMER_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_TIMER_SHIFT) 7865 #define CRU_SOFTRST_CON03_PRESETN_WDT0_SHIFT (8U) 7866 #define CRU_SOFTRST_CON03_PRESETN_WDT0_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_WDT0_SHIFT) 7867 #define CRU_SOFTRST_CON03_PRESETN_WDT1_SHIFT (9U) 7868 #define CRU_SOFTRST_CON03_PRESETN_WDT1_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_WDT1_SHIFT) 7869 #define CRU_SOFTRST_CON03_PRESETN_WDT2_SHIFT (10U) 7870 #define CRU_SOFTRST_CON03_PRESETN_WDT2_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_WDT2_SHIFT) 7871 #define CRU_SOFTRST_CON03_PRESETN_MAILBOX0_SHIFT (11U) 7872 #define CRU_SOFTRST_CON03_PRESETN_MAILBOX0_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_MAILBOX0_SHIFT) 7873 #define CRU_SOFTRST_CON03_PRESETN_MAILBOX1_SHIFT (12U) 7874 #define CRU_SOFTRST_CON03_PRESETN_MAILBOX1_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_MAILBOX1_SHIFT) 7875 #define CRU_SOFTRST_CON03_PRESETN_INT_CTRL_SHIFT (13U) 7876 #define CRU_SOFTRST_CON03_PRESETN_INT_CTRL_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_INT_CTRL_SHIFT) 7877 /* SOFTRST_CON04 */ 7878 #define CRU_SOFTRST_CON04_OFFSET (0x410U) 7879 #define CRU_SOFTRST_CON04_DRESETN_HIFI3_SHIFT (1U) 7880 #define CRU_SOFTRST_CON04_DRESETN_HIFI3_MASK (0x1U << CRU_SOFTRST_CON04_DRESETN_HIFI3_SHIFT) 7881 #define CRU_SOFTRST_CON04_BRESETN_HIFI3_SHIFT (2U) 7882 #define CRU_SOFTRST_CON04_BRESETN_HIFI3_MASK (0x1U << CRU_SOFTRST_CON04_BRESETN_HIFI3_SHIFT) 7883 #define CRU_SOFTRST_CON04_ARESETN_HIFI3_NIU_SHIFT (3U) 7884 #define CRU_SOFTRST_CON04_ARESETN_HIFI3_NIU_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_HIFI3_NIU_SHIFT) 7885 #define CRU_SOFTRST_CON04_SRESETN_UART0_SHIFT (6U) 7886 #define CRU_SOFTRST_CON04_SRESETN_UART0_MASK (0x1U << CRU_SOFTRST_CON04_SRESETN_UART0_SHIFT) 7887 #define CRU_SOFTRST_CON04_SRESETN_UART1_SHIFT (9U) 7888 #define CRU_SOFTRST_CON04_SRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON04_SRESETN_UART1_SHIFT) 7889 #define CRU_SOFTRST_CON04_SRESETN_UART2_SHIFT (12U) 7890 #define CRU_SOFTRST_CON04_SRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON04_SRESETN_UART2_SHIFT) 7891 /* SOFTRST_CON05 */ 7892 #define CRU_SOFTRST_CON05_OFFSET (0x414U) 7893 #define CRU_SOFTRST_CON05_RESETN_I2C0_SHIFT (0U) 7894 #define CRU_SOFTRST_CON05_RESETN_I2C0_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_I2C0_SHIFT) 7895 #define CRU_SOFTRST_CON05_RESETN_I2C1_SHIFT (1U) 7896 #define CRU_SOFTRST_CON05_RESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_I2C1_SHIFT) 7897 #define CRU_SOFTRST_CON05_RESETN_I2C2_SHIFT (2U) 7898 #define CRU_SOFTRST_CON05_RESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_I2C2_SHIFT) 7899 #define CRU_SOFTRST_CON05_RESETN_PWM0_SHIFT (3U) 7900 #define CRU_SOFTRST_CON05_RESETN_PWM0_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_PWM0_SHIFT) 7901 #define CRU_SOFTRST_CON05_RESETN_PWM1_SHIFT (4U) 7902 #define CRU_SOFTRST_CON05_RESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_PWM1_SHIFT) 7903 #define CRU_SOFTRST_CON05_RESETN_PWM2_SHIFT (5U) 7904 #define CRU_SOFTRST_CON05_RESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_PWM2_SHIFT) 7905 #define CRU_SOFTRST_CON05_RESETN_SPI0_SHIFT (6U) 7906 #define CRU_SOFTRST_CON05_RESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_SPI0_SHIFT) 7907 #define CRU_SOFTRST_CON05_RESETN_SPI1_SHIFT (7U) 7908 #define CRU_SOFTRST_CON05_RESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_SPI1_SHIFT) 7909 #define CRU_SOFTRST_CON05_RESETN_TIMER0_SHIFT (9U) 7910 #define CRU_SOFTRST_CON05_RESETN_TIMER0_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_TIMER0_SHIFT) 7911 #define CRU_SOFTRST_CON05_RESETN_TIMER1_SHIFT (10U) 7912 #define CRU_SOFTRST_CON05_RESETN_TIMER1_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_TIMER1_SHIFT) 7913 #define CRU_SOFTRST_CON05_RESETN_TIMER2_SHIFT (11U) 7914 #define CRU_SOFTRST_CON05_RESETN_TIMER2_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_TIMER2_SHIFT) 7915 #define CRU_SOFTRST_CON05_RESETN_TIMER3_SHIFT (12U) 7916 #define CRU_SOFTRST_CON05_RESETN_TIMER3_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_TIMER3_SHIFT) 7917 #define CRU_SOFTRST_CON05_RESETN_TIMER4_SHIFT (13U) 7918 #define CRU_SOFTRST_CON05_RESETN_TIMER4_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_TIMER4_SHIFT) 7919 #define CRU_SOFTRST_CON05_RESETN_TIMER5_SHIFT (14U) 7920 #define CRU_SOFTRST_CON05_RESETN_TIMER5_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_TIMER5_SHIFT) 7921 #define CRU_SOFTRST_CON05_M4F0_JTRST_SHIFT (15U) 7922 #define CRU_SOFTRST_CON05_M4F0_JTRST_MASK (0x1U << CRU_SOFTRST_CON05_M4F0_JTRST_SHIFT) 7923 /* SOFTRST_CON06 */ 7924 #define CRU_SOFTRST_CON06_OFFSET (0x418U) 7925 #define CRU_SOFTRST_CON06_M0_JTRST_SHIFT (0U) 7926 #define CRU_SOFTRST_CON06_M0_JTRST_MASK (0x1U << CRU_SOFTRST_CON06_M0_JTRST_SHIFT) 7927 #define CRU_SOFTRST_CON06_HIFI3_JTRST_SHIFT (1U) 7928 #define CRU_SOFTRST_CON06_HIFI3_JTRST_MASK (0x1U << CRU_SOFTRST_CON06_HIFI3_JTRST_SHIFT) 7929 #define CRU_SOFTRST_CON06_RESETN_EFUSE_SHIFT (2U) 7930 #define CRU_SOFTRST_CON06_RESETN_EFUSE_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_EFUSE_SHIFT) 7931 #define CRU_SOFTRST_CON06_RESETN_XIP_SFC0_SHIFT (3U) 7932 #define CRU_SOFTRST_CON06_RESETN_XIP_SFC0_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_XIP_SFC0_SHIFT) 7933 #define CRU_SOFTRST_CON06_RESETN_XIP_SFC1_SHIFT (4U) 7934 #define CRU_SOFTRST_CON06_RESETN_XIP_SFC1_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_XIP_SFC1_SHIFT) 7935 #define CRU_SOFTRST_CON06_SRESETN_AUDIOPWM_SHIFT (9U) 7936 #define CRU_SOFTRST_CON06_SRESETN_AUDIOPWM_MASK (0x1U << CRU_SOFTRST_CON06_SRESETN_AUDIOPWM_SHIFT) 7937 /* SOFTRST_CON07 */ 7938 #define CRU_SOFTRST_CON07_OFFSET (0x41CU) 7939 #define CRU_SOFTRST_CON07_ARESETN_PERI_BUS_NIU_SHIFT (2U) 7940 #define CRU_SOFTRST_CON07_ARESETN_PERI_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON07_ARESETN_PERI_BUS_NIU_SHIFT) 7941 #define CRU_SOFTRST_CON07_HRESETN_PERI_BUS_NIU_SHIFT (3U) 7942 #define CRU_SOFTRST_CON07_HRESETN_PERI_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_PERI_BUS_NIU_SHIFT) 7943 #define CRU_SOFTRST_CON07_ARESETN_VIP_SHIFT (4U) 7944 #define CRU_SOFTRST_CON07_ARESETN_VIP_MASK (0x1U << CRU_SOFTRST_CON07_ARESETN_VIP_SHIFT) 7945 #define CRU_SOFTRST_CON07_ARESETN_CRYPTO_SHIFT (5U) 7946 #define CRU_SOFTRST_CON07_ARESETN_CRYPTO_MASK (0x1U << CRU_SOFTRST_CON07_ARESETN_CRYPTO_SHIFT) 7947 #define CRU_SOFTRST_CON07_HRESETN_VIP_SHIFT (6U) 7948 #define CRU_SOFTRST_CON07_HRESETN_VIP_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_VIP_SHIFT) 7949 #define CRU_SOFTRST_CON07_HRESETN_CRYPTO_SHIFT (7U) 7950 #define CRU_SOFTRST_CON07_HRESETN_CRYPTO_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_CRYPTO_SHIFT) 7951 #define CRU_SOFTRST_CON07_HRESETN_SDMMC_SHIFT (8U) 7952 #define CRU_SOFTRST_CON07_HRESETN_SDMMC_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_SDMMC_SHIFT) 7953 #define CRU_SOFTRST_CON07_HRESETN_USBOTG_SHIFT (9U) 7954 #define CRU_SOFTRST_CON07_HRESETN_USBOTG_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_USBOTG_SHIFT) 7955 #define CRU_SOFTRST_CON07_HRESETN_USBOTG_PMU_SHIFT (10U) 7956 #define CRU_SOFTRST_CON07_HRESETN_USBOTG_PMU_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_USBOTG_PMU_SHIFT) 7957 #define CRU_SOFTRST_CON07_PRESETN_SPI2APB_SHIFT (13U) 7958 #define CRU_SOFTRST_CON07_PRESETN_SPI2APB_MASK (0x1U << CRU_SOFTRST_CON07_PRESETN_SPI2APB_SHIFT) 7959 #define CRU_SOFTRST_CON07_RESETN_VIP_SHIFT (15U) 7960 #define CRU_SOFTRST_CON07_RESETN_VIP_MASK (0x1U << CRU_SOFTRST_CON07_RESETN_VIP_SHIFT) 7961 /* SOFTRST_CON08 */ 7962 #define CRU_SOFTRST_CON08_OFFSET (0x420U) 7963 #define CRU_SOFTRST_CON08_RESETN_UTMI_SHIFT (0U) 7964 #define CRU_SOFTRST_CON08_RESETN_UTMI_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_UTMI_SHIFT) 7965 #define CRU_SOFTRST_CON08_RESETN_OTG_ADP_SHIFT (1U) 7966 #define CRU_SOFTRST_CON08_RESETN_OTG_ADP_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_OTG_ADP_SHIFT) 7967 #define CRU_SOFTRST_CON08_RESETN_CRYPTO_SHIFT (5U) 7968 #define CRU_SOFTRST_CON08_RESETN_CRYPTO_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_CRYPTO_SHIFT) 7969 #define CRU_SOFTRST_CON08_RESETN_CRYPTO_PKA_SHIFT (6U) 7970 #define CRU_SOFTRST_CON08_RESETN_CRYPTO_PKA_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_CRYPTO_PKA_SHIFT) 7971 #define CRU_SOFTRST_CON08_ARESETN_WIFI_BUS_NIU_SHIFT (9U) 7972 #define CRU_SOFTRST_CON08_ARESETN_WIFI_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON08_ARESETN_WIFI_BUS_NIU_SHIFT) 7973 #define CRU_SOFTRST_CON08_HRESETN_BUFFER_SHIFT (11U) 7974 #define CRU_SOFTRST_CON08_HRESETN_BUFFER_MASK (0x1U << CRU_SOFTRST_CON08_HRESETN_BUFFER_SHIFT) 7975 /* SOFTRST_CON09 */ 7976 #define CRU_SOFTRST_CON09_OFFSET (0x424U) 7977 #define CRU_SOFTRST_CON09_HRESETN_TOP_BUS_NIU_SHIFT (1U) 7978 #define CRU_SOFTRST_CON09_HRESETN_TOP_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON09_HRESETN_TOP_BUS_NIU_SHIFT) 7979 #define CRU_SOFTRST_CON09_HRESETN_PDM_SHIFT (2U) 7980 #define CRU_SOFTRST_CON09_HRESETN_PDM_MASK (0x1U << CRU_SOFTRST_CON09_HRESETN_PDM_SHIFT) 7981 #define CRU_SOFTRST_CON09_HRESETN_I2S0_SHIFT (3U) 7982 #define CRU_SOFTRST_CON09_HRESETN_I2S0_MASK (0x1U << CRU_SOFTRST_CON09_HRESETN_I2S0_SHIFT) 7983 #define CRU_SOFTRST_CON09_HRESETN_I2S1_SHIFT (4U) 7984 #define CRU_SOFTRST_CON09_HRESETN_I2S1_MASK (0x1U << CRU_SOFTRST_CON09_HRESETN_I2S1_SHIFT) 7985 #define CRU_SOFTRST_CON09_HRESETN_VAD_SHIFT (5U) 7986 #define CRU_SOFTRST_CON09_HRESETN_VAD_MASK (0x1U << CRU_SOFTRST_CON09_HRESETN_VAD_SHIFT) 7987 #define CRU_SOFTRST_CON09_PRESETN_TOP_BUS_NIU_SHIFT (7U) 7988 #define CRU_SOFTRST_CON09_PRESETN_TOP_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_TOP_BUS_NIU_SHIFT) 7989 #define CRU_SOFTRST_CON09_PRESETN_GPIO0_SHIFT (8U) 7990 #define CRU_SOFTRST_CON09_PRESETN_GPIO0_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_GPIO0_SHIFT) 7991 #define CRU_SOFTRST_CON09_PRESETN_GPIO1_SHIFT (9U) 7992 #define CRU_SOFTRST_CON09_PRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_GPIO1_SHIFT) 7993 #define CRU_SOFTRST_CON09_PRESETN_CRU_SHIFT (11U) 7994 #define CRU_SOFTRST_CON09_PRESETN_CRU_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_CRU_SHIFT) 7995 #define CRU_SOFTRST_CON09_PRESETN_GRF_SHIFT (12U) 7996 #define CRU_SOFTRST_CON09_PRESETN_GRF_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_GRF_SHIFT) 7997 #define CRU_SOFTRST_CON09_PRESETN_ACODEC_SHIFT (13U) 7998 #define CRU_SOFTRST_CON09_PRESETN_ACODEC_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_ACODEC_SHIFT) 7999 #define CRU_SOFTRST_CON09_PRESETN_32KTRIM_SHIFT (14U) 8000 #define CRU_SOFTRST_CON09_PRESETN_32KTRIM_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_32KTRIM_SHIFT) 8001 #define CRU_SOFTRST_CON09_PRESETN_TOP_TIMER_SHIFT (15U) 8002 #define CRU_SOFTRST_CON09_PRESETN_TOP_TIMER_MASK (0x1U << CRU_SOFTRST_CON09_PRESETN_TOP_TIMER_SHIFT) 8003 /* SOFTRST_CON10 */ 8004 #define CRU_SOFTRST_CON10_OFFSET (0x428U) 8005 #define CRU_SOFTRST_CON10_PRESETN_PVTM_SHIFT (0U) 8006 #define CRU_SOFTRST_CON10_PRESETN_PVTM_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_PVTM_SHIFT) 8007 #define CRU_SOFTRST_CON10_PRESETN_TOUCH_DETECT_SHIFT (1U) 8008 #define CRU_SOFTRST_CON10_PRESETN_TOUCH_DETECT_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_TOUCH_DETECT_SHIFT) 8009 #define CRU_SOFTRST_CON10_PRESETN_TSADC_SHIFT (2U) 8010 #define CRU_SOFTRST_CON10_PRESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_TSADC_SHIFT) 8011 #define CRU_SOFTRST_CON10_RESETN_AON_SHIFT (5U) 8012 #define CRU_SOFTRST_CON10_RESETN_AON_MASK (0x1U << CRU_SOFTRST_CON10_RESETN_AON_SHIFT) 8013 #define CRU_SOFTRST_CON10_DBRESETN_GPIO0_SHIFT (8U) 8014 #define CRU_SOFTRST_CON10_DBRESETN_GPIO0_MASK (0x1U << CRU_SOFTRST_CON10_DBRESETN_GPIO0_SHIFT) 8015 #define CRU_SOFTRST_CON10_DBRESETN_GPIO1_SHIFT (9U) 8016 #define CRU_SOFTRST_CON10_DBRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON10_DBRESETN_GPIO1_SHIFT) 8017 #define CRU_SOFTRST_CON10_MRESETN_PDM_SHIFT (12U) 8018 #define CRU_SOFTRST_CON10_MRESETN_PDM_MASK (0x1U << CRU_SOFTRST_CON10_MRESETN_PDM_SHIFT) 8019 #define CRU_SOFTRST_CON10_MRESETN_I2S8CH_0_TX_SHIFT (15U) 8020 #define CRU_SOFTRST_CON10_MRESETN_I2S8CH_0_TX_MASK (0x1U << CRU_SOFTRST_CON10_MRESETN_I2S8CH_0_TX_SHIFT) 8021 /* SOFTRST_CON11 */ 8022 #define CRU_SOFTRST_CON11_OFFSET (0x42CU) 8023 #define CRU_SOFTRST_CON11_MRESETN_I2S8CH_0_RX_SHIFT (2U) 8024 #define CRU_SOFTRST_CON11_MRESETN_I2S8CH_0_RX_MASK (0x1U << CRU_SOFTRST_CON11_MRESETN_I2S8CH_0_RX_SHIFT) 8025 #define CRU_SOFTRST_CON11_MRESETN_I2S8CH_1_TX_SHIFT (6U) 8026 #define CRU_SOFTRST_CON11_MRESETN_I2S8CH_1_TX_MASK (0x1U << CRU_SOFTRST_CON11_MRESETN_I2S8CH_1_TX_SHIFT) 8027 #define CRU_SOFTRST_CON11_MRESETN_I2S8CH_1_RX_SHIFT (9U) 8028 #define CRU_SOFTRST_CON11_MRESETN_I2S8CH_1_RX_MASK (0x1U << CRU_SOFTRST_CON11_MRESETN_I2S8CH_1_RX_SHIFT) 8029 #define CRU_SOFTRST_CON11_RESETN_CODEC_SHIFT (10U) 8030 #define CRU_SOFTRST_CON11_RESETN_CODEC_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_CODEC_SHIFT) 8031 /* SOFTRST_CON12 */ 8032 #define CRU_SOFTRST_CON12_OFFSET (0x430U) 8033 #define CRU_SOFTRST_CON12_AON_JTRST_SHIFT (1U) 8034 #define CRU_SOFTRST_CON12_AON_JTRST_MASK (0x1U << CRU_SOFTRST_CON12_AON_JTRST_SHIFT) 8035 #define CRU_SOFTRST_CON12_RESETN_OTG_USBPHY_SHIFT (3U) 8036 #define CRU_SOFTRST_CON12_RESETN_OTG_USBPHY_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_OTG_USBPHY_SHIFT) 8037 #define CRU_SOFTRST_CON12_RESETN_32KTRIM_SHIFT (4U) 8038 #define CRU_SOFTRST_CON12_RESETN_32KTRIM_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_32KTRIM_SHIFT) 8039 #define CRU_SOFTRST_CON12_RESETN_PVTM_SHIFT (7U) 8040 #define CRU_SOFTRST_CON12_RESETN_PVTM_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_PVTM_SHIFT) 8041 #define CRU_SOFTRST_CON12_RESETN_TOUCH_DETECT_SHIFT (8U) 8042 #define CRU_SOFTRST_CON12_RESETN_TOUCH_DETECT_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_TOUCH_DETECT_SHIFT) 8043 #define CRU_SOFTRST_CON12_RESETN_TOP_TIMER_SHIFT (9U) 8044 #define CRU_SOFTRST_CON12_RESETN_TOP_TIMER_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_TOP_TIMER_SHIFT) 8045 #define CRU_SOFTRST_CON12_RESETN_TSADC_SHIFT (11U) 8046 #define CRU_SOFTRST_CON12_RESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_TSADC_SHIFT) 8047 /* SDMMC_CON00 */ 8048 #define CRU_SDMMC_CON00_OFFSET (0x480U) 8049 #define CRU_SDMMC_CON00_INIT_STATE_SHIFT (0U) 8050 #define CRU_SDMMC_CON00_INIT_STATE_MASK (0x1U << CRU_SDMMC_CON00_INIT_STATE_SHIFT) 8051 #define CRU_SDMMC_CON00_DRV_DEGREE_SHIFT (1U) 8052 #define CRU_SDMMC_CON00_DRV_DEGREE_MASK (0x3U << CRU_SDMMC_CON00_DRV_DEGREE_SHIFT) 8053 #define CRU_SDMMC_CON00_DRV_DELAYNUM_SHIFT (3U) 8054 #define CRU_SDMMC_CON00_DRV_DELAYNUM_MASK (0xFFU << CRU_SDMMC_CON00_DRV_DELAYNUM_SHIFT) 8055 #define CRU_SDMMC_CON00_DRV_SEL_SHIFT (11U) 8056 #define CRU_SDMMC_CON00_DRV_SEL_MASK (0x1U << CRU_SDMMC_CON00_DRV_SEL_SHIFT) 8057 /* SDMMC_CON01 */ 8058 #define CRU_SDMMC_CON01_OFFSET (0x484U) 8059 #define CRU_SDMMC_CON01_SAMPLE_DEGREE_SHIFT (1U) 8060 #define CRU_SDMMC_CON01_SAMPLE_DEGREE_MASK (0x3U << CRU_SDMMC_CON01_SAMPLE_DEGREE_SHIFT) 8061 #define CRU_SDMMC_CON01_SAMPLE_DELAYNUM_SHIFT (3U) 8062 #define CRU_SDMMC_CON01_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_SDMMC_CON01_SAMPLE_DELAYNUM_SHIFT) 8063 #define CRU_SDMMC_CON01_SAMPLE_SEL_SHIFT (11U) 8064 #define CRU_SDMMC_CON01_SAMPLE_SEL_MASK (0x1U << CRU_SDMMC_CON01_SAMPLE_SEL_SHIFT) 8065 /******************************************PVTM******************************************/ 8066 /* VERSION */ 8067 #define PVTM_VERSION_OFFSET (0x0U) 8068 #define PVTM_VERSION_VERSION_SHIFT (0U) 8069 #define PVTM_VERSION_VERSION_MASK (0xFFFFU << PVTM_VERSION_VERSION_SHIFT) 8070 /* CON0 */ 8071 #define PVTM_CON0_OFFSET (0x4U) 8072 #define PVTM_CON0_PVTM_START_SHIFT (0U) 8073 #define PVTM_CON0_PVTM_START_MASK (0x1U << PVTM_CON0_PVTM_START_SHIFT) 8074 #define PVTM_CON0_PVTM_OSC_EN_SHIFT (1U) 8075 #define PVTM_CON0_PVTM_OSC_EN_MASK (0x1U << PVTM_CON0_PVTM_OSC_EN_SHIFT) 8076 #define PVTM_CON0_PVTM_OSC_SEL_SHIFT (2U) 8077 #define PVTM_CON0_PVTM_OSC_SEL_MASK (0x3U << PVTM_CON0_PVTM_OSC_SEL_SHIFT) 8078 /* CON1 */ 8079 #define PVTM_CON1_OFFSET (0x8U) 8080 #define PVTM_CON1_PVTM_CAL_CNT_SHIFT (0U) 8081 #define PVTM_CON1_PVTM_CAL_CNT_MASK (0xFFFFFFFFU << PVTM_CON1_PVTM_CAL_CNT_SHIFT) 8082 /* STATUS0 */ 8083 #define PVTM_STATUS0_OFFSET (0x80U) 8084 #define PVTM_STATUS0_PVTM_FREQ_DONE_SHIFT (0U) 8085 #define PVTM_STATUS0_PVTM_FREQ_DONE_MASK (0x1U << PVTM_STATUS0_PVTM_FREQ_DONE_SHIFT) 8086 /* STATUS1 */ 8087 #define PVTM_STATUS1_OFFSET (0x84U) 8088 #define PVTM_STATUS1_PVTM_FREQ_CNT_SHIFT (0U) 8089 #define PVTM_STATUS1_PVTM_FREQ_CNT_MASK (0xFFFFFFFFU << PVTM_STATUS1_PVTM_FREQ_CNT_SHIFT) 8090 /**************************************TOUCH_SENSOR**************************************/ 8091 /* CH_START */ 8092 #define TOUCH_SENSOR_CH_START_OFFSET (0x0U) 8093 #define TOUCH_SENSOR_CH_START_START_SHIFT (0U) 8094 #define TOUCH_SENSOR_CH_START_START_MASK (0x1U << TOUCH_SENSOR_CH_START_START_SHIFT) 8095 /* CH_ENABLE0 */ 8096 #define TOUCH_SENSOR_CH_ENABLE0_OFFSET (0x4U) 8097 #define TOUCH_SENSOR_CH_ENABLE0_ENABLE_SHIFT (0U) 8098 #define TOUCH_SENSOR_CH_ENABLE0_ENABLE_MASK (0xFFFFU << TOUCH_SENSOR_CH_ENABLE0_ENABLE_SHIFT) 8099 /* CH_ENABLE1 */ 8100 #define TOUCH_SENSOR_CH_ENABLE1_OFFSET (0x8U) 8101 #define TOUCH_SENSOR_CH_ENABLE1_ENABLE_SHIFT (0U) 8102 #define TOUCH_SENSOR_CH_ENABLE1_ENABLE_MASK (0xFU << TOUCH_SENSOR_CH_ENABLE1_ENABLE_SHIFT) 8103 /* CH_DIV */ 8104 #define TOUCH_SENSOR_CH_DIV_OFFSET (0xCU) 8105 #define TOUCH_SENSOR_CH_DIV_DRIVE_PULSE_DIV_SHIFT (0U) 8106 #define TOUCH_SENSOR_CH_DIV_DRIVE_PULSE_DIV_MASK (0xFFFFFU << TOUCH_SENSOR_CH_DIV_DRIVE_PULSE_DIV_SHIFT) 8107 /* CH_IRQ_EN0 */ 8108 #define TOUCH_SENSOR_CH_IRQ_EN0_OFFSET (0x10U) 8109 #define TOUCH_SENSOR_CH_IRQ_EN0_CHARGE_IRQ_POS_EN_SHIFT (0U) 8110 #define TOUCH_SENSOR_CH_IRQ_EN0_CHARGE_IRQ_POS_EN_MASK \ 8111 (0xFFFFU << TOUCH_SENSOR_CH_IRQ_EN0_CHARGE_IRQ_POS_EN_SHIFT) 8112 /* CH_IRQ_EN1 */ 8113 #define TOUCH_SENSOR_CH_IRQ_EN1_OFFSET (0x14U) 8114 #define TOUCH_SENSOR_CH_IRQ_EN1_CHARGE_IRQ_POS_EN_SHIFT (0U) 8115 #define TOUCH_SENSOR_CH_IRQ_EN1_CHARGE_IRQ_POS_EN_MASK (0xFU << TOUCH_SENSOR_CH_IRQ_EN1_CHARGE_IRQ_POS_EN_SHIFT) 8116 /* CH_IRQ_EN2 */ 8117 #define TOUCH_SENSOR_CH_IRQ_EN2_OFFSET (0x18U) 8118 #define TOUCH_SENSOR_CH_IRQ_EN2_CHARGE_IRQ_NEG_EN_SHIFT (0U) 8119 #define TOUCH_SENSOR_CH_IRQ_EN2_CHARGE_IRQ_NEG_EN_MASK (0xFU << TOUCH_SENSOR_CH_IRQ_EN2_CHARGE_IRQ_NEG_EN_SHIFT) 8120 /* CH_IRQ_EN3 */ 8121 #define TOUCH_SENSOR_CH_IRQ_EN3_OFFSET (0x1CU) 8122 #define TOUCH_SENSOR_CH_IRQ_EN3_CHARGE_IRQ_NEG_EN_SHIFT (0U) 8123 #define TOUCH_SENSOR_CH_IRQ_EN3_CHARGE_IRQ_NEG_EN_MASK (0xFU << TOUCH_SENSOR_CH_IRQ_EN3_CHARGE_IRQ_NEG_EN_SHIFT) 8124 /* CH_IRQ_ST_POS */ 8125 #define TOUCH_SENSOR_CH_IRQ_ST_POS_OFFSET (0x20U) 8126 #define TOUCH_SENSOR_CH_IRQ_ST_POS_CHARGE_IRQ_SHIFT (0U) 8127 #define TOUCH_SENSOR_CH_IRQ_ST_POS_CHARGE_IRQ_MASK (0xFFFFFU << TOUCH_SENSOR_CH_IRQ_ST_POS_CHARGE_IRQ_SHIFT) 8128 /* CH_IRQ_ST_NEG */ 8129 #define TOUCH_SENSOR_CH_IRQ_ST_NEG_OFFSET (0x24U) 8130 #define TOUCH_SENSOR_CH_IRQ_ST_NEG_CHARGE_IRQ_SHIFT (0U) 8131 #define TOUCH_SENSOR_CH_IRQ_ST_NEG_CHARGE_IRQ_MASK (0xFFFFFU << TOUCH_SENSOR_CH_IRQ_ST_NEG_CHARGE_IRQ_SHIFT) 8132 /* CH_IRQ_RAW */ 8133 #define TOUCH_SENSOR_CH_IRQ_RAW_OFFSET (0x28U) 8134 #define TOUCH_SENSOR_CH_IRQ_RAW_CHARGE_IRQ_SHIFT (0U) 8135 #define TOUCH_SENSOR_CH_IRQ_RAW_CHARGE_IRQ_MASK (0xFFFFFU << TOUCH_SENSOR_CH_IRQ_RAW_CHARGE_IRQ_SHIFT) 8136 /* CH_IRQ_CLEAR0 */ 8137 #define TOUCH_SENSOR_CH_IRQ_CLEAR0_OFFSET (0x2CU) 8138 #define TOUCH_SENSOR_CH_IRQ_CLEAR0_CHARGE_IRQ_POS_CLEAR_SHIFT (0U) 8139 #define TOUCH_SENSOR_CH_IRQ_CLEAR0_CHARGE_IRQ_POS_CLEAR_MASK \ 8140 (0xFFFFFU << TOUCH_SENSOR_CH_IRQ_CLEAR0_CHARGE_IRQ_POS_CLEAR_SHIFT) 8141 /* CH_IRQ_CLEAR1 */ 8142 #define TOUCH_SENSOR_CH_IRQ_CLEAR1_OFFSET (0x30U) 8143 #define TOUCH_SENSOR_CH_IRQ_CLEAR1_CHARGE_IRQ_NEG_CLEAR_SHIFT (0U) 8144 #define TOUCH_SENSOR_CH_IRQ_CLEAR1_CHARGE_IRQ_NEG_CLEAR_MASK \ 8145 (0xFFFFFU << TOUCH_SENSOR_CH_IRQ_CLEAR1_CHARGE_IRQ_NEG_CLEAR_SHIFT) 8146 /* CH_CHARGE_THRESHOLD */ 8147 #define TOUCH_SENSOR_CH_CHARGE_THRESHOLD_OFFSET (0x34U) 8148 #define TOUCH_SENSOR_CH_CHARGE_THRESHOLD_CHARGE_THRESHOLD_SHIFT (0U) 8149 #define TOUCH_SENSOR_CH_CHARGE_THRESHOLD_CHARGE_THRESHOLD_MASK \ 8150 (0xFFFFFU << TOUCH_SENSOR_CH_CHARGE_THRESHOLD_CHARGE_THRESHOLD_SHIFT) 8151 /* CH_FILTER_STABLE_TIME */ 8152 #define TOUCH_SENSOR_CH_FILTER_STABLE_TIME_OFFSET (0x38U) 8153 #define TOUCH_SENSOR_CH_FILTER_STABLE_TIME_FILTER_THRESHOLD_SHIFT (0U) 8154 #define TOUCH_SENSOR_CH_FILTER_STABLE_TIME_FILTER_THRESHOLD_MASK \ 8155 (0xFFFFU << TOUCH_SENSOR_CH_FILTER_STABLE_TIME_FILTER_THRESHOLD_SHIFT) 8156 /* CH_IRQ_SEL */ 8157 #define TOUCH_SENSOR_CH_IRQ_SEL_OFFSET (0x3CU) 8158 #define TOUCH_SENSOR_CH_IRQ_SEL_IRQ_SEL_SHIFT (0U) 8159 #define TOUCH_SENSOR_CH_IRQ_SEL_IRQ_SEL_MASK (0x1U << TOUCH_SENSOR_CH_IRQ_SEL_IRQ_SEL_SHIFT) 8160 /* CH_LOCK */ 8161 #define TOUCH_SENSOR_CH_LOCK_OFFSET (0x40U) 8162 #define TOUCH_SENSOR_CH_LOCK_CH_LOCK_SHIFT (0U) 8163 #define TOUCH_SENSOR_CH_LOCK_CH_LOCK_MASK (0x1U << TOUCH_SENSOR_CH_LOCK_CH_LOCK_SHIFT) 8164 #define TOUCH_SENSOR_CH_LOCK_CH_KICK_SHIFT (1U) 8165 #define TOUCH_SENSOR_CH_LOCK_CH_KICK_MASK (0x1U << TOUCH_SENSOR_CH_LOCK_CH_KICK_SHIFT) 8166 /* CH_RC_TYPE_SEL */ 8167 #define TOUCH_SENSOR_CH_RC_TYPE_SEL_OFFSET (0x44U) 8168 #define TOUCH_SENSOR_CH_RC_TYPE_SEL_RC_TYPE_SEL_SHIFT (0U) 8169 #define TOUCH_SENSOR_CH_RC_TYPE_SEL_RC_TYPE_SEL_MASK (0x3U << TOUCH_SENSOR_CH_RC_TYPE_SEL_RC_TYPE_SEL_SHIFT) 8170 /* CH_RC_SPEED_STEP_CNT */ 8171 #define TOUCH_SENSOR_CH_RC_SPEED_STEP_CNT_OFFSET (0x48U) 8172 #define TOUCH_SENSOR_CH_RC_SPEED_STEP_CNT_RC_SPEED_STEP_CNT_SHIFT (0U) 8173 #define TOUCH_SENSOR_CH_RC_SPEED_STEP_CNT_RC_SPEED_STEP_CNT_MASK \ 8174 (0xFFFFFU << TOUCH_SENSOR_CH_RC_SPEED_STEP_CNT_RC_SPEED_STEP_CNT_SHIFT) 8175 /* CH0_CNT */ 8176 #define TOUCH_SENSOR_CH0_CNT_OFFSET (0x100U) 8177 #define TOUCH_SENSOR_CH0_CNT_CH0_CNT_SHIFT (0U) 8178 #define TOUCH_SENSOR_CH0_CNT_CH0_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH0_CNT_CH0_CNT_SHIFT) 8179 /* CH0_CNT_DC */ 8180 #define TOUCH_SENSOR_CH0_CNT_DC_OFFSET (0x104U) 8181 #define TOUCH_SENSOR_CH0_CNT_DC_CH0_CNT_DC_SHIFT (0U) 8182 #define TOUCH_SENSOR_CH0_CNT_DC_CH0_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH0_CNT_DC_CH0_CNT_DC_SHIFT) 8183 /* CH0_CNT_DO */ 8184 #define TOUCH_SENSOR_CH0_CNT_DO_OFFSET (0x108U) 8185 #define TOUCH_SENSOR_CH0_CNT_DO_CH0_CNT_DO_SHIFT (0U) 8186 #define TOUCH_SENSOR_CH0_CNT_DO_CH0_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH0_CNT_DO_CH0_CNT_DO_SHIFT) 8187 /* CH0_CNT_FILTER */ 8188 #define TOUCH_SENSOR_CH0_CNT_FILTER_OFFSET (0x10CU) 8189 #define TOUCH_SENSOR_CH0_CNT_FILTER_CH0_CNT_FILTER_SHIFT (0U) 8190 #define TOUCH_SENSOR_CH0_CNT_FILTER_CH0_CNT_FILTER_MASK \ 8191 (0xFFFFU << TOUCH_SENSOR_CH0_CNT_FILTER_CH0_CNT_FILTER_SHIFT) 8192 /* CH1_CNT */ 8193 #define TOUCH_SENSOR_CH1_CNT_OFFSET (0x200U) 8194 #define TOUCH_SENSOR_CH1_CNT_CH1_CNT_SHIFT (0U) 8195 #define TOUCH_SENSOR_CH1_CNT_CH1_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH1_CNT_CH1_CNT_SHIFT) 8196 /* CH1_CNT_DC */ 8197 #define TOUCH_SENSOR_CH1_CNT_DC_OFFSET (0x204U) 8198 #define TOUCH_SENSOR_CH1_CNT_DC_CH1_CNT_DC_SHIFT (0U) 8199 #define TOUCH_SENSOR_CH1_CNT_DC_CH1_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH1_CNT_DC_CH1_CNT_DC_SHIFT) 8200 /* CH1_CNT_DO */ 8201 #define TOUCH_SENSOR_CH1_CNT_DO_OFFSET (0x208U) 8202 #define TOUCH_SENSOR_CH1_CNT_DO_CH1_CNT_DO_SHIFT (0U) 8203 #define TOUCH_SENSOR_CH1_CNT_DO_CH1_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH1_CNT_DO_CH1_CNT_DO_SHIFT) 8204 /* CH1_CNT_FILTER */ 8205 #define TOUCH_SENSOR_CH1_CNT_FILTER_OFFSET (0x20CU) 8206 #define TOUCH_SENSOR_CH1_CNT_FILTER_CH1_CNT_FILTER_SHIFT (0U) 8207 #define TOUCH_SENSOR_CH1_CNT_FILTER_CH1_CNT_FILTER_MASK \ 8208 (0xFFFFU << TOUCH_SENSOR_CH1_CNT_FILTER_CH1_CNT_FILTER_SHIFT) 8209 /* CH2_CNT */ 8210 #define TOUCH_SENSOR_CH2_CNT_OFFSET (0x300U) 8211 #define TOUCH_SENSOR_CH2_CNT_CH2_CNT_SHIFT (0U) 8212 #define TOUCH_SENSOR_CH2_CNT_CH2_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH2_CNT_CH2_CNT_SHIFT) 8213 /* CH2_CNT_DC */ 8214 #define TOUCH_SENSOR_CH2_CNT_DC_OFFSET (0x304U) 8215 #define TOUCH_SENSOR_CH2_CNT_DC_CH2_CNT_DC_SHIFT (0U) 8216 #define TOUCH_SENSOR_CH2_CNT_DC_CH2_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH2_CNT_DC_CH2_CNT_DC_SHIFT) 8217 /* CH2_CNT_DO */ 8218 #define TOUCH_SENSOR_CH2_CNT_DO_OFFSET (0x308U) 8219 #define TOUCH_SENSOR_CH2_CNT_DO_CH2_CNT_DO_SHIFT (0U) 8220 #define TOUCH_SENSOR_CH2_CNT_DO_CH2_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH2_CNT_DO_CH2_CNT_DO_SHIFT) 8221 /* CH2_CNT_FILTER */ 8222 #define TOUCH_SENSOR_CH2_CNT_FILTER_OFFSET (0x30CU) 8223 #define TOUCH_SENSOR_CH2_CNT_FILTER_CH2_CNT_FILTER_SHIFT (0U) 8224 #define TOUCH_SENSOR_CH2_CNT_FILTER_CH2_CNT_FILTER_MASK \ 8225 (0xFFFFU << TOUCH_SENSOR_CH2_CNT_FILTER_CH2_CNT_FILTER_SHIFT) 8226 /* CH3_CNT */ 8227 #define TOUCH_SENSOR_CH3_CNT_OFFSET (0x400U) 8228 #define TOUCH_SENSOR_CH3_CNT_CH3_CNT_SHIFT (0U) 8229 #define TOUCH_SENSOR_CH3_CNT_CH3_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH3_CNT_CH3_CNT_SHIFT) 8230 /* CH3_CNT_DC */ 8231 #define TOUCH_SENSOR_CH3_CNT_DC_OFFSET (0x404U) 8232 #define TOUCH_SENSOR_CH3_CNT_DC_CH3_CNT_DC_SHIFT (0U) 8233 #define TOUCH_SENSOR_CH3_CNT_DC_CH3_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH3_CNT_DC_CH3_CNT_DC_SHIFT) 8234 /* CH3_CNT_DO */ 8235 #define TOUCH_SENSOR_CH3_CNT_DO_OFFSET (0x408U) 8236 #define TOUCH_SENSOR_CH3_CNT_DO_CH3_CNT_DO_SHIFT (0U) 8237 #define TOUCH_SENSOR_CH3_CNT_DO_CH3_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH3_CNT_DO_CH3_CNT_DO_SHIFT) 8238 /* CH3_CNT_FILTER */ 8239 #define TOUCH_SENSOR_CH3_CNT_FILTER_OFFSET (0x40CU) 8240 #define TOUCH_SENSOR_CH3_CNT_FILTER_CH3_CNT_FILTER_SHIFT (0U) 8241 #define TOUCH_SENSOR_CH3_CNT_FILTER_CH3_CNT_FILTER_MASK \ 8242 (0xFFFFU << TOUCH_SENSOR_CH3_CNT_FILTER_CH3_CNT_FILTER_SHIFT) 8243 /* CH4_CNT */ 8244 #define TOUCH_SENSOR_CH4_CNT_OFFSET (0x500U) 8245 #define TOUCH_SENSOR_CH4_CNT_CH4_CNT_SHIFT (0U) 8246 #define TOUCH_SENSOR_CH4_CNT_CH4_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH4_CNT_CH4_CNT_SHIFT) 8247 /* CH4_CNT_DC */ 8248 #define TOUCH_SENSOR_CH4_CNT_DC_OFFSET (0x504U) 8249 #define TOUCH_SENSOR_CH4_CNT_DC_CH4_CNT_DC_SHIFT (0U) 8250 #define TOUCH_SENSOR_CH4_CNT_DC_CH4_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH4_CNT_DC_CH4_CNT_DC_SHIFT) 8251 /* CH4_CNT_DO */ 8252 #define TOUCH_SENSOR_CH4_CNT_DO_OFFSET (0x508U) 8253 #define TOUCH_SENSOR_CH4_CNT_DO_CH4_CNT_DO_SHIFT (0U) 8254 #define TOUCH_SENSOR_CH4_CNT_DO_CH4_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH4_CNT_DO_CH4_CNT_DO_SHIFT) 8255 /* CH4_CNT_FILTER */ 8256 #define TOUCH_SENSOR_CH4_CNT_FILTER_OFFSET (0x50CU) 8257 #define TOUCH_SENSOR_CH4_CNT_FILTER_CH4_CNT_FILTER_SHIFT (0U) 8258 #define TOUCH_SENSOR_CH4_CNT_FILTER_CH4_CNT_FILTER_MASK \ 8259 (0xFFFFU << TOUCH_SENSOR_CH4_CNT_FILTER_CH4_CNT_FILTER_SHIFT) 8260 /* CH5_CNT */ 8261 #define TOUCH_SENSOR_CH5_CNT_OFFSET (0x600U) 8262 #define TOUCH_SENSOR_CH5_CNT_CH5_CNT_SHIFT (0U) 8263 #define TOUCH_SENSOR_CH5_CNT_CH5_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH5_CNT_CH5_CNT_SHIFT) 8264 /* CH5_CNT_DC */ 8265 #define TOUCH_SENSOR_CH5_CNT_DC_OFFSET (0x604U) 8266 #define TOUCH_SENSOR_CH5_CNT_DC_CH5_CNT_DC_SHIFT (0U) 8267 #define TOUCH_SENSOR_CH5_CNT_DC_CH5_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH5_CNT_DC_CH5_CNT_DC_SHIFT) 8268 /* CH5_CNT_DO */ 8269 #define TOUCH_SENSOR_CH5_CNT_DO_OFFSET (0x608U) 8270 #define TOUCH_SENSOR_CH5_CNT_DO_CH5_CNT_DO_SHIFT (0U) 8271 #define TOUCH_SENSOR_CH5_CNT_DO_CH5_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH5_CNT_DO_CH5_CNT_DO_SHIFT) 8272 /* CH5_CNT_FILTER */ 8273 #define TOUCH_SENSOR_CH5_CNT_FILTER_OFFSET (0x60CU) 8274 #define TOUCH_SENSOR_CH5_CNT_FILTER_CH5_CNT_FILTER_SHIFT (0U) 8275 #define TOUCH_SENSOR_CH5_CNT_FILTER_CH5_CNT_FILTER_MASK \ 8276 (0xFFFFU << TOUCH_SENSOR_CH5_CNT_FILTER_CH5_CNT_FILTER_SHIFT) 8277 /* CH6_CNT */ 8278 #define TOUCH_SENSOR_CH6_CNT_OFFSET (0x700U) 8279 #define TOUCH_SENSOR_CH6_CNT_CH6_CNT_SHIFT (0U) 8280 #define TOUCH_SENSOR_CH6_CNT_CH6_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH6_CNT_CH6_CNT_SHIFT) 8281 /* CH6_CNT_DC */ 8282 #define TOUCH_SENSOR_CH6_CNT_DC_OFFSET (0x704U) 8283 #define TOUCH_SENSOR_CH6_CNT_DC_CH6_CNT_DC_SHIFT (0U) 8284 #define TOUCH_SENSOR_CH6_CNT_DC_CH6_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH6_CNT_DC_CH6_CNT_DC_SHIFT) 8285 /* CH6_CNT_DO */ 8286 #define TOUCH_SENSOR_CH6_CNT_DO_OFFSET (0x708U) 8287 #define TOUCH_SENSOR_CH6_CNT_DO_CH6_CNT_DO_SHIFT (0U) 8288 #define TOUCH_SENSOR_CH6_CNT_DO_CH6_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH6_CNT_DO_CH6_CNT_DO_SHIFT) 8289 /* CH6_CNT_FILTER */ 8290 #define TOUCH_SENSOR_CH6_CNT_FILTER_OFFSET (0x70CU) 8291 #define TOUCH_SENSOR_CH6_CNT_FILTER_CH6_CNT_FILTER_SHIFT (0U) 8292 #define TOUCH_SENSOR_CH6_CNT_FILTER_CH6_CNT_FILTER_MASK \ 8293 (0xFFFFU << TOUCH_SENSOR_CH6_CNT_FILTER_CH6_CNT_FILTER_SHIFT) 8294 /* CH7_CNT */ 8295 #define TOUCH_SENSOR_CH7_CNT_OFFSET (0x800U) 8296 #define TOUCH_SENSOR_CH7_CNT_CH7_CNT_SHIFT (0U) 8297 #define TOUCH_SENSOR_CH7_CNT_CH7_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH7_CNT_CH7_CNT_SHIFT) 8298 /* CH7_CNT_DC */ 8299 #define TOUCH_SENSOR_CH7_CNT_DC_OFFSET (0x804U) 8300 #define TOUCH_SENSOR_CH7_CNT_DC_CH7_CNT_DC_SHIFT (0U) 8301 #define TOUCH_SENSOR_CH7_CNT_DC_CH7_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH7_CNT_DC_CH7_CNT_DC_SHIFT) 8302 /* CH7_CNT_DO */ 8303 #define TOUCH_SENSOR_CH7_CNT_DO_OFFSET (0x808U) 8304 #define TOUCH_SENSOR_CH7_CNT_DO_CH7_CNT_DO_SHIFT (0U) 8305 #define TOUCH_SENSOR_CH7_CNT_DO_CH7_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH7_CNT_DO_CH7_CNT_DO_SHIFT) 8306 /* CH7_CNT_FILTER */ 8307 #define TOUCH_SENSOR_CH7_CNT_FILTER_OFFSET (0x80CU) 8308 #define TOUCH_SENSOR_CH7_CNT_FILTER_CH7_CNT_FILTER_SHIFT (0U) 8309 #define TOUCH_SENSOR_CH7_CNT_FILTER_CH7_CNT_FILTER_MASK \ 8310 (0xFFFFU << TOUCH_SENSOR_CH7_CNT_FILTER_CH7_CNT_FILTER_SHIFT) 8311 /* CH8_CNT */ 8312 #define TOUCH_SENSOR_CH8_CNT_OFFSET (0x900U) 8313 #define TOUCH_SENSOR_CH8_CNT_CH8_CNT_SHIFT (0U) 8314 #define TOUCH_SENSOR_CH8_CNT_CH8_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH8_CNT_CH8_CNT_SHIFT) 8315 /* CH8_CNT_DC */ 8316 #define TOUCH_SENSOR_CH8_CNT_DC_OFFSET (0x904U) 8317 #define TOUCH_SENSOR_CH8_CNT_DC_CH8_CNT_DC_SHIFT (0U) 8318 #define TOUCH_SENSOR_CH8_CNT_DC_CH8_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH8_CNT_DC_CH8_CNT_DC_SHIFT) 8319 /* CH8_CNT_DO */ 8320 #define TOUCH_SENSOR_CH8_CNT_DO_OFFSET (0x908U) 8321 #define TOUCH_SENSOR_CH8_CNT_DO_CH8_CNT_DO_SHIFT (0U) 8322 #define TOUCH_SENSOR_CH8_CNT_DO_CH8_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH8_CNT_DO_CH8_CNT_DO_SHIFT) 8323 /* CH8_CNT_FILTER */ 8324 #define TOUCH_SENSOR_CH8_CNT_FILTER_OFFSET (0x90CU) 8325 #define TOUCH_SENSOR_CH8_CNT_FILTER_CH8_CNT_FILTER_SHIFT (0U) 8326 #define TOUCH_SENSOR_CH8_CNT_FILTER_CH8_CNT_FILTER_MASK \ 8327 (0xFFFFU << TOUCH_SENSOR_CH8_CNT_FILTER_CH8_CNT_FILTER_SHIFT) 8328 /* CH9_CNT */ 8329 #define TOUCH_SENSOR_CH9_CNT_OFFSET (0x1000U) 8330 #define TOUCH_SENSOR_CH9_CNT_CH9_CNT_SHIFT (0U) 8331 #define TOUCH_SENSOR_CH9_CNT_CH9_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH9_CNT_CH9_CNT_SHIFT) 8332 /* CH9_CNT_DC */ 8333 #define TOUCH_SENSOR_CH9_CNT_DC_OFFSET (0x1004U) 8334 #define TOUCH_SENSOR_CH9_CNT_DC_CH9_CNT_DC_SHIFT (0U) 8335 #define TOUCH_SENSOR_CH9_CNT_DC_CH9_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH9_CNT_DC_CH9_CNT_DC_SHIFT) 8336 /* CH9_CNT_DO */ 8337 #define TOUCH_SENSOR_CH9_CNT_DO_OFFSET (0x1008U) 8338 #define TOUCH_SENSOR_CH9_CNT_DO_CH9_CNT_DO_SHIFT (0U) 8339 #define TOUCH_SENSOR_CH9_CNT_DO_CH9_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH9_CNT_DO_CH9_CNT_DO_SHIFT) 8340 /* CH9_CNT_FILTER */ 8341 #define TOUCH_SENSOR_CH9_CNT_FILTER_OFFSET (0x100CU) 8342 #define TOUCH_SENSOR_CH9_CNT_FILTER_CH9_CNT_FILTER_SHIFT (0U) 8343 #define TOUCH_SENSOR_CH9_CNT_FILTER_CH9_CNT_FILTER_MASK \ 8344 (0xFFFFU << TOUCH_SENSOR_CH9_CNT_FILTER_CH9_CNT_FILTER_SHIFT) 8345 /* CH10_CNT */ 8346 #define TOUCH_SENSOR_CH10_CNT_OFFSET (0x1100U) 8347 #define TOUCH_SENSOR_CH10_CNT_CH10_CNT_SHIFT (0U) 8348 #define TOUCH_SENSOR_CH10_CNT_CH10_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH10_CNT_CH10_CNT_SHIFT) 8349 /* CH10_CNT_DC */ 8350 #define TOUCH_SENSOR_CH10_CNT_DC_OFFSET (0x1104U) 8351 #define TOUCH_SENSOR_CH10_CNT_DC_CH10_CNT_DC_SHIFT (0U) 8352 #define TOUCH_SENSOR_CH10_CNT_DC_CH10_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH10_CNT_DC_CH10_CNT_DC_SHIFT) 8353 /* CH10_CNT_DO */ 8354 #define TOUCH_SENSOR_CH10_CNT_DO_OFFSET (0x1108U) 8355 #define TOUCH_SENSOR_CH10_CNT_DO_CH10_CNT_DO_SHIFT (0U) 8356 #define TOUCH_SENSOR_CH10_CNT_DO_CH10_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH10_CNT_DO_CH10_CNT_DO_SHIFT) 8357 /* CH10_CNT_FILTER */ 8358 #define TOUCH_SENSOR_CH10_CNT_FILTER_OFFSET (0x110CU) 8359 #define TOUCH_SENSOR_CH10_CNT_FILTER_CH10_CNT_FILTER_SHIFT (0U) 8360 #define TOUCH_SENSOR_CH10_CNT_FILTER_CH10_CNT_FILTER_MASK \ 8361 (0xFFFFU << TOUCH_SENSOR_CH10_CNT_FILTER_CH10_CNT_FILTER_SHIFT) 8362 /* CH11_CNT */ 8363 #define TOUCH_SENSOR_CH11_CNT_OFFSET (0x1200U) 8364 #define TOUCH_SENSOR_CH11_CNT_CH11_CNT_SHIFT (0U) 8365 #define TOUCH_SENSOR_CH11_CNT_CH11_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH11_CNT_CH11_CNT_SHIFT) 8366 /* CH11_CNT_DC */ 8367 #define TOUCH_SENSOR_CH11_CNT_DC_OFFSET (0x1204U) 8368 #define TOUCH_SENSOR_CH11_CNT_DC_CH11_CNT_DC_SHIFT (0U) 8369 #define TOUCH_SENSOR_CH11_CNT_DC_CH11_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH11_CNT_DC_CH11_CNT_DC_SHIFT) 8370 /* CH11_CNT_DO */ 8371 #define TOUCH_SENSOR_CH11_CNT_DO_OFFSET (0x1208U) 8372 #define TOUCH_SENSOR_CH11_CNT_DO_CH11_CNT_DO_SHIFT (0U) 8373 #define TOUCH_SENSOR_CH11_CNT_DO_CH11_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH11_CNT_DO_CH11_CNT_DO_SHIFT) 8374 /* CH11_CNT_FILTER */ 8375 #define TOUCH_SENSOR_CH11_CNT_FILTER_OFFSET (0x120CU) 8376 #define TOUCH_SENSOR_CH11_CNT_FILTER_CH11_CNT_FILTER_SHIFT (0U) 8377 #define TOUCH_SENSOR_CH11_CNT_FILTER_CH11_CNT_FILTER_MASK \ 8378 (0xFFFFU << TOUCH_SENSOR_CH11_CNT_FILTER_CH11_CNT_FILTER_SHIFT) 8379 /* CH12_CNT */ 8380 #define TOUCH_SENSOR_CH12_CNT_OFFSET (0x1300U) 8381 #define TOUCH_SENSOR_CH12_CNT_CH12_CNT_SHIFT (0U) 8382 #define TOUCH_SENSOR_CH12_CNT_CH12_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH12_CNT_CH12_CNT_SHIFT) 8383 /* CH12_CNT_DC */ 8384 #define TOUCH_SENSOR_CH12_CNT_DC_OFFSET (0x1304U) 8385 #define TOUCH_SENSOR_CH12_CNT_DC_CH12_CNT_DC_SHIFT (0U) 8386 #define TOUCH_SENSOR_CH12_CNT_DC_CH12_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH12_CNT_DC_CH12_CNT_DC_SHIFT) 8387 /* CH12_CNT_DO */ 8388 #define TOUCH_SENSOR_CH12_CNT_DO_OFFSET (0x1308U) 8389 #define TOUCH_SENSOR_CH12_CNT_DO_CH12_CNT_DO_SHIFT (0U) 8390 #define TOUCH_SENSOR_CH12_CNT_DO_CH12_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH12_CNT_DO_CH12_CNT_DO_SHIFT) 8391 /* CH12_CNT_FILTER */ 8392 #define TOUCH_SENSOR_CH12_CNT_FILTER_OFFSET (0x130CU) 8393 #define TOUCH_SENSOR_CH12_CNT_FILTER_CH12_CNT_FILTER_SHIFT (0U) 8394 #define TOUCH_SENSOR_CH12_CNT_FILTER_CH12_CNT_FILTER_MASK \ 8395 (0xFFFFU << TOUCH_SENSOR_CH12_CNT_FILTER_CH12_CNT_FILTER_SHIFT) 8396 /* CH13_CNT */ 8397 #define TOUCH_SENSOR_CH13_CNT_OFFSET (0x1400U) 8398 #define TOUCH_SENSOR_CH13_CNT_CH13_CNT_SHIFT (0U) 8399 #define TOUCH_SENSOR_CH13_CNT_CH13_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH13_CNT_CH13_CNT_SHIFT) 8400 /* CH13_CNT_DC */ 8401 #define TOUCH_SENSOR_CH13_CNT_DC_OFFSET (0x1404U) 8402 #define TOUCH_SENSOR_CH13_CNT_DC_CH13_CNT_DC_SHIFT (0U) 8403 #define TOUCH_SENSOR_CH13_CNT_DC_CH13_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH13_CNT_DC_CH13_CNT_DC_SHIFT) 8404 /* CH13_CNT_DO */ 8405 #define TOUCH_SENSOR_CH13_CNT_DO_OFFSET (0x1408U) 8406 #define TOUCH_SENSOR_CH13_CNT_DO_CH13_CNT_DO_SHIFT (0U) 8407 #define TOUCH_SENSOR_CH13_CNT_DO_CH13_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH13_CNT_DO_CH13_CNT_DO_SHIFT) 8408 /* CH13_CNT_FILTER */ 8409 #define TOUCH_SENSOR_CH13_CNT_FILTER_OFFSET (0x140CU) 8410 #define TOUCH_SENSOR_CH13_CNT_FILTER_CH13_CNT_FILTER_SHIFT (0U) 8411 #define TOUCH_SENSOR_CH13_CNT_FILTER_CH13_CNT_FILTER_MASK \ 8412 (0xFFFFU << TOUCH_SENSOR_CH13_CNT_FILTER_CH13_CNT_FILTER_SHIFT) 8413 /* CH14_CNT */ 8414 #define TOUCH_SENSOR_CH14_CNT_OFFSET (0x1500U) 8415 #define TOUCH_SENSOR_CH14_CNT_CH14_CNT_SHIFT (0U) 8416 #define TOUCH_SENSOR_CH14_CNT_CH14_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH14_CNT_CH14_CNT_SHIFT) 8417 /* CH14_CNT_DC */ 8418 #define TOUCH_SENSOR_CH14_CNT_DC_OFFSET (0x1504U) 8419 #define TOUCH_SENSOR_CH14_CNT_DC_CH14_CNT_DC_SHIFT (0U) 8420 #define TOUCH_SENSOR_CH14_CNT_DC_CH14_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH14_CNT_DC_CH14_CNT_DC_SHIFT) 8421 /* CH14_CNT_DO */ 8422 #define TOUCH_SENSOR_CH14_CNT_DO_OFFSET (0x1508U) 8423 #define TOUCH_SENSOR_CH14_CNT_DO_CH14_CNT_DO_SHIFT (0U) 8424 #define TOUCH_SENSOR_CH14_CNT_DO_CH14_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH14_CNT_DO_CH14_CNT_DO_SHIFT) 8425 /* CH14_CNT_FILTER */ 8426 #define TOUCH_SENSOR_CH14_CNT_FILTER_OFFSET (0x150CU) 8427 #define TOUCH_SENSOR_CH14_CNT_FILTER_CH14_CNT_FILTER_SHIFT (0U) 8428 #define TOUCH_SENSOR_CH14_CNT_FILTER_CH14_CNT_FILTER_MASK \ 8429 (0xFFFFU << TOUCH_SENSOR_CH14_CNT_FILTER_CH14_CNT_FILTER_SHIFT) 8430 /* CH15_CNT */ 8431 #define TOUCH_SENSOR_CH15_CNT_OFFSET (0x1600U) 8432 #define TOUCH_SENSOR_CH15_CNT_CH15_CNT_SHIFT (0U) 8433 #define TOUCH_SENSOR_CH15_CNT_CH15_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH15_CNT_CH15_CNT_SHIFT) 8434 /* CH15_CNT_DC */ 8435 #define TOUCH_SENSOR_CH15_CNT_DC_OFFSET (0x1604U) 8436 #define TOUCH_SENSOR_CH15_CNT_DC_CH15_CNT_DC_SHIFT (0U) 8437 #define TOUCH_SENSOR_CH15_CNT_DC_CH15_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH15_CNT_DC_CH15_CNT_DC_SHIFT) 8438 /* CH15_CNT_DO */ 8439 #define TOUCH_SENSOR_CH15_CNT_DO_OFFSET (0x1608U) 8440 #define TOUCH_SENSOR_CH15_CNT_DO_CH15_CNT_DO_SHIFT (0U) 8441 #define TOUCH_SENSOR_CH15_CNT_DO_CH15_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH15_CNT_DO_CH15_CNT_DO_SHIFT) 8442 /* CH15_CNT_FILTER */ 8443 #define TOUCH_SENSOR_CH15_CNT_FILTER_OFFSET (0x160CU) 8444 #define TOUCH_SENSOR_CH15_CNT_FILTER_CH15_CNT_FILTER_SHIFT (0U) 8445 #define TOUCH_SENSOR_CH15_CNT_FILTER_CH15_CNT_FILTER_MASK \ 8446 (0xFFFFU << TOUCH_SENSOR_CH15_CNT_FILTER_CH15_CNT_FILTER_SHIFT) 8447 /* CH16_CNT */ 8448 #define TOUCH_SENSOR_CH16_CNT_OFFSET (0x1700U) 8449 #define TOUCH_SENSOR_CH16_CNT_CH16_CNT_SHIFT (0U) 8450 #define TOUCH_SENSOR_CH16_CNT_CH16_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH16_CNT_CH16_CNT_SHIFT) 8451 /* CH16_CNT_DC */ 8452 #define TOUCH_SENSOR_CH16_CNT_DC_OFFSET (0x1704U) 8453 #define TOUCH_SENSOR_CH16_CNT_DC_CH16_CNT_DC_SHIFT (0U) 8454 #define TOUCH_SENSOR_CH16_CNT_DC_CH16_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH16_CNT_DC_CH16_CNT_DC_SHIFT) 8455 /* CH16_CNT_DO */ 8456 #define TOUCH_SENSOR_CH16_CNT_DO_OFFSET (0x1708U) 8457 #define TOUCH_SENSOR_CH16_CNT_DO_CH16_CNT_DO_SHIFT (0U) 8458 #define TOUCH_SENSOR_CH16_CNT_DO_CH16_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH16_CNT_DO_CH16_CNT_DO_SHIFT) 8459 /* CH16_CNT_FILTER */ 8460 #define TOUCH_SENSOR_CH16_CNT_FILTER_OFFSET (0x170CU) 8461 #define TOUCH_SENSOR_CH16_CNT_FILTER_CH16_CNT_FILTER_SHIFT (0U) 8462 #define TOUCH_SENSOR_CH16_CNT_FILTER_CH16_CNT_FILTER_MASK \ 8463 (0xFFFFU << TOUCH_SENSOR_CH16_CNT_FILTER_CH16_CNT_FILTER_SHIFT) 8464 /* CH17_CNT */ 8465 #define TOUCH_SENSOR_CH17_CNT_OFFSET (0x1800U) 8466 #define TOUCH_SENSOR_CH17_CNT_CH17_CNT_SHIFT (0U) 8467 #define TOUCH_SENSOR_CH17_CNT_CH17_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH17_CNT_CH17_CNT_SHIFT) 8468 /* CH17_CNT_DC */ 8469 #define TOUCH_SENSOR_CH17_CNT_DC_OFFSET (0x1804U) 8470 #define TOUCH_SENSOR_CH17_CNT_DC_CH17_CNT_DC_SHIFT (0U) 8471 #define TOUCH_SENSOR_CH17_CNT_DC_CH17_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH17_CNT_DC_CH17_CNT_DC_SHIFT) 8472 /* CH17_CNT_DO */ 8473 #define TOUCH_SENSOR_CH17_CNT_DO_OFFSET (0x1808U) 8474 #define TOUCH_SENSOR_CH17_CNT_DO_CH17_CNT_DO_SHIFT (0U) 8475 #define TOUCH_SENSOR_CH17_CNT_DO_CH17_CNT_DO_MASK (0xFFFFU << TOUCH_SENSOR_CH17_CNT_DO_CH17_CNT_DO_SHIFT) 8476 /* CH17_CNT_FILTER */ 8477 #define TOUCH_SENSOR_CH17_CNT_FILTER_OFFSET (0x180CU) 8478 #define TOUCH_SENSOR_CH17_CNT_FILTER_CH17_CNT_FILTER_SHIFT (0U) 8479 #define TOUCH_SENSOR_CH17_CNT_FILTER_CH17_CNT_FILTER_MASK \ 8480 (0xFFFFU << TOUCH_SENSOR_CH17_CNT_FILTER_CH17_CNT_FILTER_SHIFT) 8481 /* CH18_CNT */ 8482 #define TOUCH_SENSOR_CH18_CNT_OFFSET (0x1900U) 8483 #define TOUCH_SENSOR_CH18_CNT_CH18_CNT_SHIFT (0U) 8484 #define TOUCH_SENSOR_CH18_CNT_CH18_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH18_CNT_CH18_CNT_SHIFT) 8485 /* CH18_CNT_DC */ 8486 #define TOUCH_SENSOR_CH18_CNT_DC_OFFSET (0x1904U) 8487 #define TOUCH_SENSOR_CH18_CNT_DC_CH18_CNT_DC_SHIFT (0U) 8488 #define TOUCH_SENSOR_CH18_CNT_DC_CH18_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH18_CNT_DC_CH18_CNT_DC_SHIFT) 8489 /* CH18_CNT_DO */ 8490 #define TOUCH_SENSOR_CH18_CNT_DO_OFFSET (0x1908U) 8491 #define TOUCH_SENSOR_CH18_CNT_DO_CH18_CNT_DC_SHIFT (0U) 8492 #define TOUCH_SENSOR_CH18_CNT_DO_CH18_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH18_CNT_DO_CH18_CNT_DC_SHIFT) 8493 /* CH18_CNT_FILTER */ 8494 #define TOUCH_SENSOR_CH18_CNT_FILTER_OFFSET (0x190CU) 8495 #define TOUCH_SENSOR_CH18_CNT_FILTER_CH18_CNT_FILTER_SHIFT (0U) 8496 #define TOUCH_SENSOR_CH18_CNT_FILTER_CH18_CNT_FILTER_MASK \ 8497 (0xFFFFU << TOUCH_SENSOR_CH18_CNT_FILTER_CH18_CNT_FILTER_SHIFT) 8498 /* CH19_CNT */ 8499 #define TOUCH_SENSOR_CH19_CNT_OFFSET (0x2000U) 8500 #define TOUCH_SENSOR_CH19_CNT_CH19_CNT_SHIFT (0U) 8501 #define TOUCH_SENSOR_CH19_CNT_CH19_CNT_MASK (0xFFFFU << TOUCH_SENSOR_CH19_CNT_CH19_CNT_SHIFT) 8502 /* CH19_CNT_DC */ 8503 #define TOUCH_SENSOR_CH19_CNT_DC_OFFSET (0x2004U) 8504 #define TOUCH_SENSOR_CH19_CNT_DC_CH19_CNT_DC_SHIFT (0U) 8505 #define TOUCH_SENSOR_CH19_CNT_DC_CH19_CNT_DC_MASK (0xFFFFFFU << TOUCH_SENSOR_CH19_CNT_DC_CH19_CNT_DC_SHIFT) 8506 /* CH19_CNT_DO */ 8507 #define TOUCH_SENSOR_CH19_CNT_DO_OFFSET (0x2008U) 8508 #define TOUCH_SENSOR_CH19_CNT_DO_CH19_CNT_DO_SHIFT (0U) 8509 #define TOUCH_SENSOR_CH19_CNT_DO_CH19_CNT_DO_MASK (0xFFFFFFU << TOUCH_SENSOR_CH19_CNT_DO_CH19_CNT_DO_SHIFT) 8510 /* CH19_CNT_FILTER */ 8511 #define TOUCH_SENSOR_CH19_CNT_FILTER_OFFSET (0x200CU) 8512 #define TOUCH_SENSOR_CH19_CNT_FILTER_CH19_CNT_FILTER_SHIFT (0U) 8513 #define TOUCH_SENSOR_CH19_CNT_FILTER_CH19_CNT_FILTER_MASK \ 8514 (0xFFFFU << TOUCH_SENSOR_CH19_CNT_FILTER_CH19_CNT_FILTER_SHIFT) 8515 /*****************************************TSADC******************************************/ 8516 /* USER_CON */ 8517 #define TSADC_USER_CON_OFFSET (0x0U) 8518 #define TSADC_USER_CON_ADC_INPUT_SRC_SEL_SHIFT (0U) 8519 #define TSADC_USER_CON_ADC_INPUT_SRC_SEL_MASK (0x7U << TSADC_USER_CON_ADC_INPUT_SRC_SEL_SHIFT) 8520 #define TSADC_USER_CON_ADC_POWER_CTRL_SHIFT (3U) 8521 #define TSADC_USER_CON_ADC_POWER_CTRL_MASK (0x1U << TSADC_USER_CON_ADC_POWER_CTRL_SHIFT) 8522 #define TSADC_USER_CON_START_MODE_SHIFT (4U) 8523 #define TSADC_USER_CON_START_MODE_MASK (0x1U << TSADC_USER_CON_START_MODE_SHIFT) 8524 #define TSADC_USER_CON_START_SHIFT (5U) 8525 #define TSADC_USER_CON_START_MASK (0x1U << TSADC_USER_CON_START_SHIFT) 8526 #define TSADC_USER_CON_INTER_PD_SOC_SHIFT (6U) 8527 #define TSADC_USER_CON_INTER_PD_SOC_MASK (0x3FU << TSADC_USER_CON_INTER_PD_SOC_SHIFT) 8528 #define TSADC_USER_CON_ADC_STATUS_SHIFT (12U) 8529 #define TSADC_USER_CON_ADC_STATUS_MASK (0x1U << TSADC_USER_CON_ADC_STATUS_SHIFT) 8530 /* AUTO_CON */ 8531 #define TSADC_AUTO_CON_OFFSET (0x4U) 8532 #define TSADC_AUTO_CON_AUTO_EN_SHIFT (0U) 8533 #define TSADC_AUTO_CON_AUTO_EN_MASK (0x1U << TSADC_AUTO_CON_AUTO_EN_SHIFT) 8534 #define TSADC_AUTO_CON_TSADC_Q_SEL_SHIFT (1U) 8535 #define TSADC_AUTO_CON_TSADC_Q_SEL_MASK (0x1U << TSADC_AUTO_CON_TSADC_Q_SEL_SHIFT) 8536 #define TSADC_AUTO_CON_SRC0_EN_SHIFT (4U) 8537 #define TSADC_AUTO_CON_SRC0_EN_MASK (0x1U << TSADC_AUTO_CON_SRC0_EN_SHIFT) 8538 #define TSADC_AUTO_CON_SRC1_EN_SHIFT (5U) 8539 #define TSADC_AUTO_CON_SRC1_EN_MASK (0x1U << TSADC_AUTO_CON_SRC1_EN_SHIFT) 8540 #define TSADC_AUTO_CON_TSHUT_PROLARITY_SHIFT (8U) 8541 #define TSADC_AUTO_CON_TSHUT_PROLARITY_MASK (0x1U << TSADC_AUTO_CON_TSHUT_PROLARITY_SHIFT) 8542 #define TSADC_AUTO_CON_SRC0_LT_EN_SHIFT (12U) 8543 #define TSADC_AUTO_CON_SRC0_LT_EN_MASK (0x1U << TSADC_AUTO_CON_SRC0_LT_EN_SHIFT) 8544 #define TSADC_AUTO_CON_SRC1_LT_EN_SHIFT (13U) 8545 #define TSADC_AUTO_CON_SRC1_LT_EN_MASK (0x1U << TSADC_AUTO_CON_SRC1_LT_EN_SHIFT) 8546 #define TSADC_AUTO_CON_AUTO_STATUS_SHIFT (16U) 8547 #define TSADC_AUTO_CON_AUTO_STATUS_MASK (0x1U << TSADC_AUTO_CON_AUTO_STATUS_SHIFT) 8548 #define TSADC_AUTO_CON_SAMPLE_DLY_SEL_SHIFT (17U) 8549 #define TSADC_AUTO_CON_SAMPLE_DLY_SEL_MASK (0x1U << TSADC_AUTO_CON_SAMPLE_DLY_SEL_SHIFT) 8550 #define TSADC_AUTO_CON_LAST_TSHUT_2GPIO_SHIFT (24U) 8551 #define TSADC_AUTO_CON_LAST_TSHUT_2GPIO_MASK (0x1U << TSADC_AUTO_CON_LAST_TSHUT_2GPIO_SHIFT) 8552 #define TSADC_AUTO_CON_LAST_TSHUT_2CRU_SHIFT (25U) 8553 #define TSADC_AUTO_CON_LAST_TSHUT_2CRU_MASK (0x1U << TSADC_AUTO_CON_LAST_TSHUT_2CRU_SHIFT) 8554 /* INT_EN */ 8555 #define TSADC_INT_EN_OFFSET (0x8U) 8556 #define TSADC_INT_EN_HT_INTEN_SRC0_SHIFT (0U) 8557 #define TSADC_INT_EN_HT_INTEN_SRC0_MASK (0x1U << TSADC_INT_EN_HT_INTEN_SRC0_SHIFT) 8558 #define TSADC_INT_EN_HT_INTEN_SRC1_SHIFT (1U) 8559 #define TSADC_INT_EN_HT_INTEN_SRC1_MASK (0x1U << TSADC_INT_EN_HT_INTEN_SRC1_SHIFT) 8560 #define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_SHIFT (4U) 8561 #define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_MASK (0x1U << TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_SHIFT) 8562 #define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_SHIFT (5U) 8563 #define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_MASK (0x1U << TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_SHIFT) 8564 #define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_SHIFT (8U) 8565 #define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_MASK (0x1U << TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_SHIFT) 8566 #define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_SHIFT (9U) 8567 #define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_MASK (0x1U << TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_SHIFT) 8568 #define TSADC_INT_EN_LT_INTEN_SRC0_SHIFT (12U) 8569 #define TSADC_INT_EN_LT_INTEN_SRC0_MASK (0x1U << TSADC_INT_EN_LT_INTEN_SRC0_SHIFT) 8570 #define TSADC_INT_EN_LT_INTEN_SRC1_SHIFT (13U) 8571 #define TSADC_INT_EN_LT_INTEN_SRC1_MASK (0x1U << TSADC_INT_EN_LT_INTEN_SRC1_SHIFT) 8572 #define TSADC_INT_EN_EOC_INT_EN_SHIFT (16U) 8573 #define TSADC_INT_EN_EOC_INT_EN_MASK (0x1U << TSADC_INT_EN_EOC_INT_EN_SHIFT) 8574 /* INT_PD */ 8575 #define TSADC_INT_PD_OFFSET (0xCU) 8576 #define TSADC_INT_PD_HT_IRQ_SRC0_SHIFT (0U) 8577 #define TSADC_INT_PD_HT_IRQ_SRC0_MASK (0x1U << TSADC_INT_PD_HT_IRQ_SRC0_SHIFT) 8578 #define TSADC_INT_PD_HT_IRQ_SRC1_SHIFT (1U) 8579 #define TSADC_INT_PD_HT_IRQ_SRC1_MASK (0x1U << TSADC_INT_PD_HT_IRQ_SRC1_SHIFT) 8580 #define TSADC_INT_PD_TSHUT_O_SRC0_SHIFT (4U) 8581 #define TSADC_INT_PD_TSHUT_O_SRC0_MASK (0x1U << TSADC_INT_PD_TSHUT_O_SRC0_SHIFT) 8582 #define TSADC_INT_PD_TSHUT_O_SRC1_SHIFT (5U) 8583 #define TSADC_INT_PD_TSHUT_O_SRC1_MASK (0x1U << TSADC_INT_PD_TSHUT_O_SRC1_SHIFT) 8584 #define TSADC_INT_PD_LT_IRQ_SRC0_SHIFT (12U) 8585 #define TSADC_INT_PD_LT_IRQ_SRC0_MASK (0x1U << TSADC_INT_PD_LT_IRQ_SRC0_SHIFT) 8586 #define TSADC_INT_PD_LT_IRQ_SRC1_SHIFT (13U) 8587 #define TSADC_INT_PD_LT_IRQ_SRC1_MASK (0x1U << TSADC_INT_PD_LT_IRQ_SRC1_SHIFT) 8588 #define TSADC_INT_PD_EOC_INT_PD_SHIFT (16U) 8589 #define TSADC_INT_PD_EOC_INT_PD_MASK (0x1U << TSADC_INT_PD_EOC_INT_PD_SHIFT) 8590 /* DATA0 */ 8591 #define TSADC_DATA0_OFFSET (0x20U) 8592 #define TSADC_DATA0 (0x0U) 8593 #define TSADC_DATA0_ADC_DATA_SHIFT (0U) 8594 #define TSADC_DATA0_ADC_DATA_MASK (0xFFFU << TSADC_DATA0_ADC_DATA_SHIFT) 8595 /* DATA1 */ 8596 #define TSADC_DATA1_OFFSET (0x24U) 8597 #define TSADC_DATA1 (0x0U) 8598 #define TSADC_DATA1_ADC_DATA_SHIFT (0U) 8599 #define TSADC_DATA1_ADC_DATA_MASK (0xFFFU << TSADC_DATA1_ADC_DATA_SHIFT) 8600 /* COMP0_INT */ 8601 #define TSADC_COMP0_INT_OFFSET (0x30U) 8602 #define TSADC_COMP0_INT_TSADC_COMP_SRC0_SHIFT (0U) 8603 #define TSADC_COMP0_INT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_INT_TSADC_COMP_SRC0_SHIFT) 8604 /* COMP1_INT */ 8605 #define TSADC_COMP1_INT_OFFSET (0x34U) 8606 #define TSADC_COMP1_INT_TSADC_COMP_SRC1_SHIFT (0U) 8607 #define TSADC_COMP1_INT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_INT_TSADC_COMP_SRC1_SHIFT) 8608 /* COMP0_SHUT */ 8609 #define TSADC_COMP0_SHUT_OFFSET (0x40U) 8610 #define TSADC_COMP0_SHUT_TSADC_COMP_SRC0_SHIFT (0U) 8611 #define TSADC_COMP0_SHUT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_SHUT_TSADC_COMP_SRC0_SHIFT) 8612 /* COMP1_SHUT */ 8613 #define TSADC_COMP1_SHUT_OFFSET (0x44U) 8614 #define TSADC_COMP1_SHUT_TSADC_COMP_SRC1_SHIFT (0U) 8615 #define TSADC_COMP1_SHUT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_SHUT_TSADC_COMP_SRC1_SHIFT) 8616 /* HIGHT_INT_DEBOUNCE */ 8617 #define TSADC_HIGHT_INT_DEBOUNCE_OFFSET (0x60U) 8618 #define TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_SHIFT (0U) 8619 #define TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_MASK (0xFFU << TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_SHIFT) 8620 /* HIGHT_TSHUT_DEBOUNCE */ 8621 #define TSADC_HIGHT_TSHUT_DEBOUNCE_OFFSET (0x64U) 8622 #define TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_SHIFT (0U) 8623 #define TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_MASK (0xFFU << TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_SHIFT) 8624 /* AUTO_PERIOD */ 8625 #define TSADC_AUTO_PERIOD_OFFSET (0x68U) 8626 #define TSADC_AUTO_PERIOD_AUTO_PERIOD_SHIFT (0U) 8627 #define TSADC_AUTO_PERIOD_AUTO_PERIOD_MASK (0xFFFFFFFFU << TSADC_AUTO_PERIOD_AUTO_PERIOD_SHIFT) 8628 /* AUTO_PERIOD_HT */ 8629 #define TSADC_AUTO_PERIOD_HT_OFFSET (0x6CU) 8630 #define TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_SHIFT (0U) 8631 #define TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_MASK (0xFFFFFFFFU << TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_SHIFT) 8632 /* COMP0_LOW_INT */ 8633 #define TSADC_COMP0_LOW_INT_OFFSET (0x80U) 8634 #define TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_SHIFT (0U) 8635 #define TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_SHIFT) 8636 /* COMP1_LOW_INT */ 8637 #define TSADC_COMP1_LOW_INT_OFFSET (0x84U) 8638 #define TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_SHIFT (0U) 8639 #define TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_SHIFT) 8640 /*****************************************I2STDM*****************************************/ 8641 /* TXCR */ 8642 #define I2STDM_TXCR_OFFSET (0x0U) 8643 #define I2STDM_TXCR_VDW_SHIFT (0U) 8644 #define I2STDM_TXCR_VDW_MASK (0x1FU << I2STDM_TXCR_VDW_SHIFT) 8645 #define I2STDM_TXCR_TFS_SHIFT (5U) 8646 #define I2STDM_TXCR_TFS_MASK (0x3U << I2STDM_TXCR_TFS_SHIFT) 8647 #define I2STDM_TXCR_PBM_SHIFT (7U) 8648 #define I2STDM_TXCR_PBM_MASK (0x3U << I2STDM_TXCR_PBM_SHIFT) 8649 #define I2STDM_TXCR_IBM_SHIFT (9U) 8650 #define I2STDM_TXCR_IBM_MASK (0x3U << I2STDM_TXCR_IBM_SHIFT) 8651 #define I2STDM_TXCR_FBM_SHIFT (11U) 8652 #define I2STDM_TXCR_FBM_MASK (0x1U << I2STDM_TXCR_FBM_SHIFT) 8653 #define I2STDM_TXCR_SJM_SHIFT (12U) 8654 #define I2STDM_TXCR_SJM_MASK (0x1U << I2STDM_TXCR_SJM_SHIFT) 8655 #define I2STDM_TXCR_HWT_SHIFT (14U) 8656 #define I2STDM_TXCR_HWT_MASK (0x1U << I2STDM_TXCR_HWT_SHIFT) 8657 #define I2STDM_TXCR_TCSR_SHIFT (15U) 8658 #define I2STDM_TXCR_TCSR_MASK (0x3U << I2STDM_TXCR_TCSR_SHIFT) 8659 #define I2STDM_TXCR_RCNT_SHIFT (17U) 8660 #define I2STDM_TXCR_RCNT_MASK (0x3FU << I2STDM_TXCR_RCNT_SHIFT) 8661 #define I2STDM_TXCR_TX_PATH_SELECT0_SHIFT (23U) 8662 #define I2STDM_TXCR_TX_PATH_SELECT0_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT0_SHIFT) 8663 #define I2STDM_TXCR_TX_PATH_SELECT1_SHIFT (25U) 8664 #define I2STDM_TXCR_TX_PATH_SELECT1_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT1_SHIFT) 8665 #define I2STDM_TXCR_TX_PATH_SELECT2_SHIFT (27U) 8666 #define I2STDM_TXCR_TX_PATH_SELECT2_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT2_SHIFT) 8667 #define I2STDM_TXCR_TX_PATH_SELECT3_SHIFT (29U) 8668 #define I2STDM_TXCR_TX_PATH_SELECT3_MASK (0x3U << I2STDM_TXCR_TX_PATH_SELECT3_SHIFT) 8669 /* RXCR */ 8670 #define I2STDM_RXCR_OFFSET (0x4U) 8671 #define I2STDM_RXCR_VDW_SHIFT (0U) 8672 #define I2STDM_RXCR_VDW_MASK (0x1FU << I2STDM_RXCR_VDW_SHIFT) 8673 #define I2STDM_RXCR_TFS_SHIFT (5U) 8674 #define I2STDM_RXCR_TFS_MASK (0x3U << I2STDM_RXCR_TFS_SHIFT) 8675 #define I2STDM_RXCR_PBM_SHIFT (7U) 8676 #define I2STDM_RXCR_PBM_MASK (0x3U << I2STDM_RXCR_PBM_SHIFT) 8677 #define I2STDM_RXCR_IBM_SHIFT (9U) 8678 #define I2STDM_RXCR_IBM_MASK (0x3U << I2STDM_RXCR_IBM_SHIFT) 8679 #define I2STDM_RXCR_FBM_SHIFT (11U) 8680 #define I2STDM_RXCR_FBM_MASK (0x1U << I2STDM_RXCR_FBM_SHIFT) 8681 #define I2STDM_RXCR_SJM_SHIFT (12U) 8682 #define I2STDM_RXCR_SJM_MASK (0x1U << I2STDM_RXCR_SJM_SHIFT) 8683 #define I2STDM_RXCR_HWT_SHIFT (14U) 8684 #define I2STDM_RXCR_HWT_MASK (0x1U << I2STDM_RXCR_HWT_SHIFT) 8685 #define I2STDM_RXCR_RCSR_SHIFT (15U) 8686 #define I2STDM_RXCR_RCSR_MASK (0x3U << I2STDM_RXCR_RCSR_SHIFT) 8687 #define I2STDM_RXCR_RX_PATH_SELECT0_SHIFT (17U) 8688 #define I2STDM_RXCR_RX_PATH_SELECT0_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT0_SHIFT) 8689 #define I2STDM_RXCR_RX_PATH_SELECT1_SHIFT (19U) 8690 #define I2STDM_RXCR_RX_PATH_SELECT1_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT1_SHIFT) 8691 #define I2STDM_RXCR_RX_PATH_SELECT2_SHIFT (21U) 8692 #define I2STDM_RXCR_RX_PATH_SELECT2_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT2_SHIFT) 8693 #define I2STDM_RXCR_RX_PATH_SELECT3_SHIFT (23U) 8694 #define I2STDM_RXCR_RX_PATH_SELECT3_MASK (0x3U << I2STDM_RXCR_RX_PATH_SELECT3_SHIFT) 8695 /* CKR */ 8696 #define I2STDM_CKR_OFFSET (0x8U) 8697 #define I2STDM_CKR_TSD_SHIFT (0U) 8698 #define I2STDM_CKR_TSD_MASK (0xFFU << I2STDM_CKR_TSD_SHIFT) 8699 #define I2STDM_CKR_RSD_SHIFT (8U) 8700 #define I2STDM_CKR_RSD_MASK (0xFFU << I2STDM_CKR_RSD_SHIFT) 8701 #define I2STDM_CKR_TLP_SHIFT (24U) 8702 #define I2STDM_CKR_TLP_MASK (0x1U << I2STDM_CKR_TLP_SHIFT) 8703 #define I2STDM_CKR_RLP_SHIFT (25U) 8704 #define I2STDM_CKR_RLP_MASK (0x1U << I2STDM_CKR_RLP_SHIFT) 8705 #define I2STDM_CKR_CKP_SHIFT (26U) 8706 #define I2STDM_CKR_CKP_MASK (0x1U << I2STDM_CKR_CKP_SHIFT) 8707 #define I2STDM_CKR_MSS_SHIFT (27U) 8708 #define I2STDM_CKR_MSS_MASK (0x1U << I2STDM_CKR_MSS_SHIFT) 8709 #define I2STDM_CKR_LRCK_COMMON_SHIFT (28U) 8710 #define I2STDM_CKR_LRCK_COMMON_MASK (0x3U << I2STDM_CKR_LRCK_COMMON_SHIFT) 8711 /* TXFIFOLR */ 8712 #define I2STDM_TXFIFOLR_OFFSET (0xCU) 8713 #define I2STDM_TXFIFOLR_TFL0_SHIFT (0U) 8714 #define I2STDM_TXFIFOLR_TFL0_MASK (0x3FU << I2STDM_TXFIFOLR_TFL0_SHIFT) 8715 #define I2STDM_TXFIFOLR_TFL1_SHIFT (6U) 8716 #define I2STDM_TXFIFOLR_TFL1_MASK (0x3FU << I2STDM_TXFIFOLR_TFL1_SHIFT) 8717 #define I2STDM_TXFIFOLR_TFL2_SHIFT (12U) 8718 #define I2STDM_TXFIFOLR_TFL2_MASK (0x3FU << I2STDM_TXFIFOLR_TFL2_SHIFT) 8719 #define I2STDM_TXFIFOLR_TFL3_SHIFT (18U) 8720 #define I2STDM_TXFIFOLR_TFL3_MASK (0x3FU << I2STDM_TXFIFOLR_TFL3_SHIFT) 8721 /* DMACR */ 8722 #define I2STDM_DMACR_OFFSET (0x10U) 8723 #define I2STDM_DMACR_TDL_SHIFT (0U) 8724 #define I2STDM_DMACR_TDL_MASK (0x1FU << I2STDM_DMACR_TDL_SHIFT) 8725 #define I2STDM_DMACR_TDE_SHIFT (8U) 8726 #define I2STDM_DMACR_TDE_MASK (0x1U << I2STDM_DMACR_TDE_SHIFT) 8727 #define I2STDM_DMACR_RDL_SHIFT (16U) 8728 #define I2STDM_DMACR_RDL_MASK (0x1FU << I2STDM_DMACR_RDL_SHIFT) 8729 #define I2STDM_DMACR_RDE_SHIFT (24U) 8730 #define I2STDM_DMACR_RDE_MASK (0x1U << I2STDM_DMACR_RDE_SHIFT) 8731 /* INTCR */ 8732 #define I2STDM_INTCR_OFFSET (0x14U) 8733 #define I2STDM_INTCR_TXEIE_SHIFT (0U) 8734 #define I2STDM_INTCR_TXEIE_MASK (0x1U << I2STDM_INTCR_TXEIE_SHIFT) 8735 #define I2STDM_INTCR_TXUIE_SHIFT (1U) 8736 #define I2STDM_INTCR_TXUIE_MASK (0x1U << I2STDM_INTCR_TXUIE_SHIFT) 8737 #define I2STDM_INTCR_TXUIC_SHIFT (2U) 8738 #define I2STDM_INTCR_TXUIC_MASK (0x1U << I2STDM_INTCR_TXUIC_SHIFT) 8739 #define I2STDM_INTCR_TFT_SHIFT (4U) 8740 #define I2STDM_INTCR_TFT_MASK (0x1FU << I2STDM_INTCR_TFT_SHIFT) 8741 #define I2STDM_INTCR_RXFIE_SHIFT (16U) 8742 #define I2STDM_INTCR_RXFIE_MASK (0x1U << I2STDM_INTCR_RXFIE_SHIFT) 8743 #define I2STDM_INTCR_RXOIE_SHIFT (17U) 8744 #define I2STDM_INTCR_RXOIE_MASK (0x1U << I2STDM_INTCR_RXOIE_SHIFT) 8745 #define I2STDM_INTCR_RXOIC_SHIFT (18U) 8746 #define I2STDM_INTCR_RXOIC_MASK (0x1U << I2STDM_INTCR_RXOIC_SHIFT) 8747 #define I2STDM_INTCR_RFT_SHIFT (20U) 8748 #define I2STDM_INTCR_RFT_MASK (0x1FU << I2STDM_INTCR_RFT_SHIFT) 8749 /* INTSR */ 8750 #define I2STDM_INTSR_OFFSET (0x18U) 8751 #define I2STDM_INTSR_TXEI_SHIFT (0U) 8752 #define I2STDM_INTSR_TXEI_MASK (0x1U << I2STDM_INTSR_TXEI_SHIFT) 8753 #define I2STDM_INTSR_TXUI_SHIFT (1U) 8754 #define I2STDM_INTSR_TXUI_MASK (0x1U << I2STDM_INTSR_TXUI_SHIFT) 8755 #define I2STDM_INTSR_RXFI_SHIFT (16U) 8756 #define I2STDM_INTSR_RXFI_MASK (0x1U << I2STDM_INTSR_RXFI_SHIFT) 8757 #define I2STDM_INTSR_RXOI_SHIFT (17U) 8758 #define I2STDM_INTSR_RXOI_MASK (0x1U << I2STDM_INTSR_RXOI_SHIFT) 8759 /* XFER */ 8760 #define I2STDM_XFER_OFFSET (0x1CU) 8761 #define I2STDM_XFER_TXS_SHIFT (0U) 8762 #define I2STDM_XFER_TXS_MASK (0x1U << I2STDM_XFER_TXS_SHIFT) 8763 #define I2STDM_XFER_RXS_SHIFT (1U) 8764 #define I2STDM_XFER_RXS_MASK (0x1U << I2STDM_XFER_RXS_SHIFT) 8765 /* CLR */ 8766 #define I2STDM_CLR_OFFSET (0x20U) 8767 #define I2STDM_CLR_TXC_SHIFT (0U) 8768 #define I2STDM_CLR_TXC_MASK (0x1U << I2STDM_CLR_TXC_SHIFT) 8769 #define I2STDM_CLR_RXC_SHIFT (1U) 8770 #define I2STDM_CLR_RXC_MASK (0x1U << I2STDM_CLR_RXC_SHIFT) 8771 /* TXDR */ 8772 #define I2STDM_TXDR_OFFSET (0x24U) 8773 #define I2STDM_TXDR_TXDR_SHIFT (0U) 8774 #define I2STDM_TXDR_TXDR_MASK (0xFFFFFFFFU << I2STDM_TXDR_TXDR_SHIFT) 8775 /* RXDR */ 8776 #define I2STDM_RXDR_OFFSET (0x28U) 8777 #define I2STDM_RXDR_RXDR_SHIFT (0U) 8778 #define I2STDM_RXDR_RXDR_MASK (0xFFFFFFFFU << I2STDM_RXDR_RXDR_SHIFT) 8779 /* RXFIFOLR */ 8780 #define I2STDM_RXFIFOLR_OFFSET (0x2CU) 8781 #define I2STDM_RXFIFOLR_RFL0_SHIFT (0U) 8782 #define I2STDM_RXFIFOLR_RFL0_MASK (0x3FU << I2STDM_RXFIFOLR_RFL0_SHIFT) 8783 #define I2STDM_RXFIFOLR_RFL1_SHIFT (6U) 8784 #define I2STDM_RXFIFOLR_RFL1_MASK (0x3FU << I2STDM_RXFIFOLR_RFL1_SHIFT) 8785 #define I2STDM_RXFIFOLR_RFL2_SHIFT (12U) 8786 #define I2STDM_RXFIFOLR_RFL2_MASK (0x3FU << I2STDM_RXFIFOLR_RFL2_SHIFT) 8787 #define I2STDM_RXFIFOLR_RFL3_SHIFT (18U) 8788 #define I2STDM_RXFIFOLR_RFL3_MASK (0x3FU << I2STDM_RXFIFOLR_RFL3_SHIFT) 8789 /* TDM_TXCTRL */ 8790 #define I2STDM_TDM_TXCTRL_OFFSET (0x30U) 8791 #define I2STDM_TDM_TXCTRL_TDM_TX_FRAME_WIDTH_SHIFT (0U) 8792 #define I2STDM_TDM_TXCTRL_TDM_TX_FRAME_WIDTH_MASK (0x1FFU << I2STDM_TDM_TXCTRL_TDM_TX_FRAME_WIDTH_SHIFT) 8793 #define I2STDM_TDM_TXCTRL_TDM_TX_SLOT_BIT_WIDTH_SHIFT (9U) 8794 #define I2STDM_TDM_TXCTRL_TDM_TX_SLOT_BIT_WIDTH_MASK (0x1FU << I2STDM_TDM_TXCTRL_TDM_TX_SLOT_BIT_WIDTH_SHIFT) 8795 #define I2STDM_TDM_TXCTRL_TDM_TX_SHIFT_CTRL_SHIFT (14U) 8796 #define I2STDM_TDM_TXCTRL_TDM_TX_SHIFT_CTRL_MASK (0x7U << I2STDM_TDM_TXCTRL_TDM_TX_SHIFT_CTRL_SHIFT) 8797 #define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL0_SHIFT (17U) 8798 #define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL0_MASK (0x1U << I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL0_SHIFT) 8799 #define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL1_SHIFT (18U) 8800 #define I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL1_MASK (0x7U << I2STDM_TDM_TXCTRL_TX_TDM_FSYNC_WIDTH_SEL1_SHIFT) 8801 /* TDM_RXCTRL */ 8802 #define I2STDM_TDM_RXCTRL_OFFSET (0x34U) 8803 #define I2STDM_TDM_RXCTRL_TDM_RX_FRAME_WIDTH_SHIFT (0U) 8804 #define I2STDM_TDM_RXCTRL_TDM_RX_FRAME_WIDTH_MASK (0x1FFU << I2STDM_TDM_RXCTRL_TDM_RX_FRAME_WIDTH_SHIFT) 8805 #define I2STDM_TDM_RXCTRL_TDM_RX_SLOT_BIT_WIDTH_SHIFT (9U) 8806 #define I2STDM_TDM_RXCTRL_TDM_RX_SLOT_BIT_WIDTH_MASK (0x1FU << I2STDM_TDM_RXCTRL_TDM_RX_SLOT_BIT_WIDTH_SHIFT) 8807 #define I2STDM_TDM_RXCTRL_TDM_RX_SHIFT_CTRL_SHIFT (14U) 8808 #define I2STDM_TDM_RXCTRL_TDM_RX_SHIFT_CTRL_MASK (0x7U << I2STDM_TDM_RXCTRL_TDM_RX_SHIFT_CTRL_SHIFT) 8809 #define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL0_SHIFT (17U) 8810 #define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL0_MASK (0x1U << I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL0_SHIFT) 8811 #define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL1_SHIFT (18U) 8812 #define I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL1_MASK (0x7U << I2STDM_TDM_RXCTRL_RX_TDM_FSYNC_WIDTH_SEL1_SHIFT) 8813 /* CLKDIV */ 8814 #define I2STDM_CLKDIV_OFFSET (0x38U) 8815 #define I2STDM_CLKDIV_TX_MDIV_SHIFT (0U) 8816 #define I2STDM_CLKDIV_TX_MDIV_MASK (0xFFU << I2STDM_CLKDIV_TX_MDIV_SHIFT) 8817 #define I2STDM_CLKDIV_RX_MDIV_SHIFT (8U) 8818 #define I2STDM_CLKDIV_RX_MDIV_MASK (0xFFU << I2STDM_CLKDIV_RX_MDIV_SHIFT) 8819 /* VERSION */ 8820 #define I2STDM_VERSION_OFFSET (0x3CU) 8821 #define I2STDM_VERSION_I2S_VERSION_SHIFT (0U) 8822 #define I2STDM_VERSION_I2S_VERSION_MASK (0xFFFFFFFFU << I2STDM_VERSION_I2S_VERSION_SHIFT) 8823 /******************************************PDM*******************************************/ 8824 /* SYSCONFIG */ 8825 #define PDM_SYSCONFIG_OFFSET (0x0U) 8826 #define PDM_SYSCONFIG_RX_CLR_SHIFT (0U) 8827 #define PDM_SYSCONFIG_RX_CLR_MASK (0x1U << PDM_SYSCONFIG_RX_CLR_SHIFT) 8828 #define PDM_SYSCONFIG_RX_START_SHIFT (2U) 8829 #define PDM_SYSCONFIG_RX_START_MASK (0x1U << PDM_SYSCONFIG_RX_START_SHIFT) 8830 /* CTRL0 */ 8831 #define PDM_CTRL0_OFFSET (0x4U) 8832 #define PDM_CTRL0_DATA_VLD_WIDTH_SHIFT (0U) 8833 #define PDM_CTRL0_DATA_VLD_WIDTH_MASK (0x1FU << PDM_CTRL0_DATA_VLD_WIDTH_SHIFT) 8834 #define PDM_CTRL0_SAMPLE_RATE_SEL_SHIFT (5U) 8835 #define PDM_CTRL0_SAMPLE_RATE_SEL_MASK (0x7U << PDM_CTRL0_SAMPLE_RATE_SEL_SHIFT) 8836 #define PDM_CTRL0_INT_DIV_CON_SHIFT (8U) 8837 #define PDM_CTRL0_INT_DIV_CON_MASK (0xFFU << PDM_CTRL0_INT_DIV_CON_SHIFT) 8838 #define PDM_CTRL0_INT_DIV_20X_CON_SHIFT (16U) 8839 #define PDM_CTRL0_INT_DIV_20X_CON_MASK (0xFFU << PDM_CTRL0_INT_DIV_20X_CON_SHIFT) 8840 #define PDM_CTRL0_SIG_SCALE_MODE_SHIFT (24U) 8841 #define PDM_CTRL0_SIG_SCALE_MODE_MASK (0x1U << PDM_CTRL0_SIG_SCALE_MODE_SHIFT) 8842 #define PDM_CTRL0_FILTER_GATE_EN_SHIFT (25U) 8843 #define PDM_CTRL0_FILTER_GATE_EN_MASK (0x1U << PDM_CTRL0_FILTER_GATE_EN_SHIFT) 8844 #define PDM_CTRL0_HWT_EN_SHIFT (26U) 8845 #define PDM_CTRL0_HWT_EN_MASK (0x1U << PDM_CTRL0_HWT_EN_SHIFT) 8846 #define PDM_CTRL0_PATH0_EN_SHIFT (27U) 8847 #define PDM_CTRL0_PATH0_EN_MASK (0x1U << PDM_CTRL0_PATH0_EN_SHIFT) 8848 #define PDM_CTRL0_SJM_SEL_SHIFT (31U) 8849 #define PDM_CTRL0_SJM_SEL_MASK (0x1U << PDM_CTRL0_SJM_SEL_SHIFT) 8850 /* CTRL1 */ 8851 #define PDM_CTRL1_OFFSET (0x8U) 8852 #define PDM_CTRL1_FRAC_DIV_DENOMONATOR_SHIFT (0U) 8853 #define PDM_CTRL1_FRAC_DIV_DENOMONATOR_MASK (0xFFFFU << PDM_CTRL1_FRAC_DIV_DENOMONATOR_SHIFT) 8854 #define PDM_CTRL1_FRAC_DIV_NUMERATOR_SHIFT (16U) 8855 #define PDM_CTRL1_FRAC_DIV_NUMERATOR_MASK (0xFFFFU << PDM_CTRL1_FRAC_DIV_NUMERATOR_SHIFT) 8856 /* CLK_CTRL */ 8857 #define PDM_CLK_CTRL_OFFSET (0xCU) 8858 #define PDM_CLK_CTRL_CIC_DS_RATIO_SHIFT (0U) 8859 #define PDM_CLK_CTRL_CIC_DS_RATIO_MASK (0x3U << PDM_CLK_CTRL_CIC_DS_RATIO_SHIFT) 8860 #define PDM_CLK_CTRL_FIR_COM_BPS_SHIFT (2U) 8861 #define PDM_CLK_CTRL_FIR_COM_BPS_MASK (0x1U << PDM_CLK_CTRL_FIR_COM_BPS_SHIFT) 8862 #define PDM_CLK_CTRL_LR_CH_EX_SHIFT (3U) 8863 #define PDM_CLK_CTRL_LR_CH_EX_MASK (0x1U << PDM_CLK_CTRL_LR_CH_EX_SHIFT) 8864 #define PDM_CLK_CTRL_DIV_TYPE_SEL_SHIFT (4U) 8865 #define PDM_CLK_CTRL_DIV_TYPE_SEL_MASK (0x1U << PDM_CLK_CTRL_DIV_TYPE_SEL_SHIFT) 8866 #define PDM_CLK_CTRL_PDM_CLK_EN_SHIFT (5U) 8867 #define PDM_CLK_CTRL_PDM_CLK_EN_MASK (0x1U << PDM_CLK_CTRL_PDM_CLK_EN_SHIFT) 8868 /* HPF_CTRL */ 8869 #define PDM_HPF_CTRL_OFFSET (0x10U) 8870 #define PDM_HPF_CTRL_HPF_CF_SHIFT (0U) 8871 #define PDM_HPF_CTRL_HPF_CF_MASK (0x3U << PDM_HPF_CTRL_HPF_CF_SHIFT) 8872 #define PDM_HPF_CTRL_HPFRE_SHIFT (2U) 8873 #define PDM_HPF_CTRL_HPFRE_MASK (0x1U << PDM_HPF_CTRL_HPFRE_SHIFT) 8874 #define PDM_HPF_CTRL_HPFLE_SHIFT (3U) 8875 #define PDM_HPF_CTRL_HPFLE_MASK (0x1U << PDM_HPF_CTRL_HPFLE_SHIFT) 8876 /* FIFO_CTRL */ 8877 #define PDM_FIFO_CTRL_OFFSET (0x14U) 8878 #define PDM_FIFO_CTRL_RFL_SHIFT (0U) 8879 #define PDM_FIFO_CTRL_RFL_MASK (0xFFU << PDM_FIFO_CTRL_RFL_SHIFT) 8880 #define PDM_FIFO_CTRL_RFT_SHIFT (8U) 8881 #define PDM_FIFO_CTRL_RFT_MASK (0x7FU << PDM_FIFO_CTRL_RFT_SHIFT) 8882 /* DMA_CTRL */ 8883 #define PDM_DMA_CTRL_OFFSET (0x18U) 8884 #define PDM_DMA_CTRL_RDL_SHIFT (0U) 8885 #define PDM_DMA_CTRL_RDL_MASK (0x7FU << PDM_DMA_CTRL_RDL_SHIFT) 8886 #define PDM_DMA_CTRL_RDE_SHIFT (8U) 8887 #define PDM_DMA_CTRL_RDE_MASK (0x1U << PDM_DMA_CTRL_RDE_SHIFT) 8888 /* INT_EN */ 8889 #define PDM_INT_EN_OFFSET (0x1CU) 8890 #define PDM_INT_EN_RXTIE_SHIFT (0U) 8891 #define PDM_INT_EN_RXTIE_MASK (0x1U << PDM_INT_EN_RXTIE_SHIFT) 8892 #define PDM_INT_EN_RXOIE_SHIFT (1U) 8893 #define PDM_INT_EN_RXOIE_MASK (0x1U << PDM_INT_EN_RXOIE_SHIFT) 8894 /* INT_CLR */ 8895 #define PDM_INT_CLR_OFFSET (0x20U) 8896 #define PDM_INT_CLR_RXOIC_SHIFT (1U) 8897 #define PDM_INT_CLR_RXOIC_MASK (0x1U << PDM_INT_CLR_RXOIC_SHIFT) 8898 /* INT_ST */ 8899 #define PDM_INT_ST_OFFSET (0x24U) 8900 #define PDM_INT_ST (0x0U) 8901 #define PDM_INT_ST_RXFI_SHIFT (0U) 8902 #define PDM_INT_ST_RXFI_MASK (0x1U << PDM_INT_ST_RXFI_SHIFT) 8903 #define PDM_INT_ST_RXOI_SHIFT (1U) 8904 #define PDM_INT_ST_RXOI_MASK (0x1U << PDM_INT_ST_RXOI_SHIFT) 8905 /* RXFIFO_DATA_REG */ 8906 #define PDM_RXFIFO_DATA_REG_OFFSET (0x30U) 8907 #define PDM_RXFIFO_DATA_REG (0x0U) 8908 #define PDM_RXFIFO_DATA_REG_RXDR_SHIFT (0U) 8909 #define PDM_RXFIFO_DATA_REG_RXDR_MASK (0xFFFFFFFFU << PDM_RXFIFO_DATA_REG_RXDR_SHIFT) 8910 /* DATA0R_REG */ 8911 #define PDM_DATA0R_REG_OFFSET (0x34U) 8912 #define PDM_DATA0R_REG (0x0U) 8913 #define PDM_DATA0R_REG_DATA0R_SHIFT (0U) 8914 #define PDM_DATA0R_REG_DATA0R_MASK (0xFFFFFFFFU << PDM_DATA0R_REG_DATA0R_SHIFT) 8915 /* DATA0L_REG */ 8916 #define PDM_DATA0L_REG_OFFSET (0x38U) 8917 #define PDM_DATA0L_REG (0x0U) 8918 #define PDM_DATA0L_REG_DATA0L_SHIFT (0U) 8919 #define PDM_DATA0L_REG_DATA0L_MASK (0xFFFFFFFFU << PDM_DATA0L_REG_DATA0L_SHIFT) 8920 /* DATA_VALID */ 8921 #define PDM_DATA_VALID_OFFSET (0x54U) 8922 #define PDM_DATA_VALID (0x0U) 8923 #define PDM_DATA_VALID_PATH0_VLD_SHIFT (3U) 8924 #define PDM_DATA_VALID_PATH0_VLD_MASK (0x1U << PDM_DATA_VALID_PATH0_VLD_SHIFT) 8925 /* VERSION */ 8926 #define PDM_VERSION_OFFSET (0x58U) 8927 #define PDM_VERSION_VERSION_SHIFT (0U) 8928 #define PDM_VERSION_VERSION_MASK (0xFFFFFFFFU << PDM_VERSION_VERSION_SHIFT) 8929 /* INCR_RXDR */ 8930 #define PDM_INCR_RXDR_OFFSET (0x400U) 8931 #define PDM_INCR_RXDR_RECEIVE_FIFO_DATA_SHIFT (0U) 8932 #define PDM_INCR_RXDR_RECEIVE_FIFO_DATA_MASK (0xFFFFFFFFU << PDM_INCR_RXDR_RECEIVE_FIFO_DATA_SHIFT) 8933 /******************************************VAD*******************************************/ 8934 /* CONTROL */ 8935 #define VAD_CONTROL_OFFSET (0x0U) 8936 #define VAD_CONTROL_VAD_EN_SHIFT (0U) 8937 #define VAD_CONTROL_VAD_EN_MASK (0x1U << VAD_CONTROL_VAD_EN_SHIFT) 8938 #define VAD_CONTROL_SOURCE_SELECT_SHIFT (1U) 8939 #define VAD_CONTROL_SOURCE_SELECT_MASK (0x7U << VAD_CONTROL_SOURCE_SELECT_SHIFT) 8940 #define VAD_CONTROL_SOURCE_BURST_SHIFT (4U) 8941 #define VAD_CONTROL_SOURCE_BURST_MASK (0x7U << VAD_CONTROL_SOURCE_BURST_SHIFT) 8942 #define VAD_CONTROL_SOURCE_BURST_NUM_SHIFT (7U) 8943 #define VAD_CONTROL_SOURCE_BURST_NUM_MASK (0x7U << VAD_CONTROL_SOURCE_BURST_NUM_SHIFT) 8944 #define VAD_CONTROL_INCR_LENGTH_SHIFT (10U) 8945 #define VAD_CONTROL_INCR_LENGTH_MASK (0xFU << VAD_CONTROL_INCR_LENGTH_SHIFT) 8946 #define VAD_CONTROL_SOURCE_FIXADDR_EN_SHIFT (14U) 8947 #define VAD_CONTROL_SOURCE_FIXADDR_EN_MASK (0x1U << VAD_CONTROL_SOURCE_FIXADDR_EN_SHIFT) 8948 #define VAD_CONTROL_VAD_MODE_SHIFT (20U) 8949 #define VAD_CONTROL_VAD_MODE_MASK (0x3U << VAD_CONTROL_VAD_MODE_SHIFT) 8950 #define VAD_CONTROL_VOICE_CHANNEL_NUM_SHIFT (23U) 8951 #define VAD_CONTROL_VOICE_CHANNEL_NUM_MASK (0x7U << VAD_CONTROL_VOICE_CHANNEL_NUM_SHIFT) 8952 #define VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_SHIFT (26U) 8953 #define VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_MASK (0x1U << VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_SHIFT) 8954 #define VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_SHIFT (27U) 8955 #define VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_MASK (0x1U << VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_SHIFT) 8956 #define VAD_CONTROL_VOICE_24BIT_SAT_SHIFT (28U) 8957 #define VAD_CONTROL_VOICE_24BIT_SAT_MASK (0x1U << VAD_CONTROL_VOICE_24BIT_SAT_SHIFT) 8958 #define VAD_CONTROL_VAD_DET_CHANNEL_SHIFT (29U) 8959 #define VAD_CONTROL_VAD_DET_CHANNEL_MASK (0x7U << VAD_CONTROL_VAD_DET_CHANNEL_SHIFT) 8960 /* VS_ADDR */ 8961 #define VAD_VS_ADDR_OFFSET (0x4U) 8962 #define VAD_VS_ADDR_VS_ADDR_SHIFT (0U) 8963 #define VAD_VS_ADDR_VS_ADDR_MASK (0xFFFFFFFFU << VAD_VS_ADDR_VS_ADDR_SHIFT) 8964 /* TIMEOUT */ 8965 #define VAD_TIMEOUT_OFFSET (0x4CU) 8966 #define VAD_TIMEOUT_IDLE_TIMEOUT_THD_SHIFT (0U) 8967 #define VAD_TIMEOUT_IDLE_TIMEOUT_THD_MASK (0xFFFFFU << VAD_TIMEOUT_IDLE_TIMEOUT_THD_SHIFT) 8968 #define VAD_TIMEOUT_WORK_TIMEOUT_THD_SHIFT (20U) 8969 #define VAD_TIMEOUT_WORK_TIMEOUT_THD_MASK (0x3FFU << VAD_TIMEOUT_WORK_TIMEOUT_THD_SHIFT) 8970 #define VAD_TIMEOUT_IDLE_TIMEOUT_EN_SHIFT (30U) 8971 #define VAD_TIMEOUT_IDLE_TIMEOUT_EN_MASK (0x1U << VAD_TIMEOUT_IDLE_TIMEOUT_EN_SHIFT) 8972 #define VAD_TIMEOUT_WORK_TIMEOUT_EN_SHIFT (31U) 8973 #define VAD_TIMEOUT_WORK_TIMEOUT_EN_MASK (0x1U << VAD_TIMEOUT_WORK_TIMEOUT_EN_SHIFT) 8974 /* RAM_START_ADDR */ 8975 #define VAD_RAM_START_ADDR_OFFSET (0x50U) 8976 #define VAD_RAM_START_ADDR_RAM_START_ADDR_SHIFT (0U) 8977 #define VAD_RAM_START_ADDR_RAM_START_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_START_ADDR_RAM_START_ADDR_SHIFT) 8978 /* RAM_END_ADDR */ 8979 #define VAD_RAM_END_ADDR_OFFSET (0x54U) 8980 #define VAD_RAM_END_ADDR_RAM_END_ADDR_SHIFT (0U) 8981 #define VAD_RAM_END_ADDR_RAM_END_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_END_ADDR_RAM_END_ADDR_SHIFT) 8982 /* RAM_CUR_ADDR */ 8983 #define VAD_RAM_CUR_ADDR_OFFSET (0x58U) 8984 #define VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_SHIFT (0U) 8985 #define VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_SHIFT) 8986 /* DET_CON0 */ 8987 #define VAD_DET_CON0_OFFSET (0x5CU) 8988 #define VAD_DET_CON0_GAIN_SHIFT (0U) 8989 #define VAD_DET_CON0_GAIN_MASK (0xFFFU << VAD_DET_CON0_GAIN_SHIFT) 8990 #define VAD_DET_CON0_NOISE_LEVEL_SHIFT (12U) 8991 #define VAD_DET_CON0_NOISE_LEVEL_MASK (0x7U << VAD_DET_CON0_NOISE_LEVEL_SHIFT) 8992 #define VAD_DET_CON0_VAD_CON_THD_SHIFT (16U) 8993 #define VAD_DET_CON0_VAD_CON_THD_MASK (0xFFU << VAD_DET_CON0_VAD_CON_THD_SHIFT) 8994 #define VAD_DET_CON0_DIS_VAD_CON_THD_SHIFT (24U) 8995 #define VAD_DET_CON0_DIS_VAD_CON_THD_MASK (0xFU << VAD_DET_CON0_DIS_VAD_CON_THD_SHIFT) 8996 #define VAD_DET_CON0_VAD_THD_MODE_SHIFT (28U) 8997 #define VAD_DET_CON0_VAD_THD_MODE_MASK (0x3U << VAD_DET_CON0_VAD_THD_MODE_SHIFT) 8998 /* DET_CON1 */ 8999 #define VAD_DET_CON1_OFFSET (0x60U) 9000 #define VAD_DET_CON1_SOUND_THD_SHIFT (0U) 9001 #define VAD_DET_CON1_SOUND_THD_MASK (0xFFFFU << VAD_DET_CON1_SOUND_THD_SHIFT) 9002 #define VAD_DET_CON1_NOISE_SAMPLE_NUM_SHIFT (16U) 9003 #define VAD_DET_CON1_NOISE_SAMPLE_NUM_MASK (0x3FFU << VAD_DET_CON1_NOISE_SAMPLE_NUM_SHIFT) 9004 #define VAD_DET_CON1_CLEAN_IIR_EN_SHIFT (26U) 9005 #define VAD_DET_CON1_CLEAN_IIR_EN_MASK (0x1U << VAD_DET_CON1_CLEAN_IIR_EN_SHIFT) 9006 #define VAD_DET_CON1_FORCE_NOISE_CLK_EN_SHIFT (28U) 9007 #define VAD_DET_CON1_FORCE_NOISE_CLK_EN_MASK (0x1U << VAD_DET_CON1_FORCE_NOISE_CLK_EN_SHIFT) 9008 #define VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_SHIFT (29U) 9009 #define VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_MASK (0x1U << VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_SHIFT) 9010 #define VAD_DET_CON1_MIN_NOISE_FIND_MODE_SHIFT (30U) 9011 #define VAD_DET_CON1_MIN_NOISE_FIND_MODE_MASK (0x1U << VAD_DET_CON1_MIN_NOISE_FIND_MODE_SHIFT) 9012 /* DET_CON2 */ 9013 #define VAD_DET_CON2_OFFSET (0x64U) 9014 #define VAD_DET_CON2_NOISE_FRM_NUM_SHIFT (0U) 9015 #define VAD_DET_CON2_NOISE_FRM_NUM_MASK (0x7FU << VAD_DET_CON2_NOISE_FRM_NUM_SHIFT) 9016 #define VAD_DET_CON2_NOISE_ALPHA_SHIFT (8U) 9017 #define VAD_DET_CON2_NOISE_ALPHA_MASK (0xFFU << VAD_DET_CON2_NOISE_ALPHA_SHIFT) 9018 #define VAD_DET_CON2_IIR_ANUM_0_SHIFT (16U) 9019 #define VAD_DET_CON2_IIR_ANUM_0_MASK (0xFFFFU << VAD_DET_CON2_IIR_ANUM_0_SHIFT) 9020 /* DET_CON3 */ 9021 #define VAD_DET_CON3_OFFSET (0x68U) 9022 #define VAD_DET_CON3_IIR_ANUM_1_SHIFT (0U) 9023 #define VAD_DET_CON3_IIR_ANUM_1_MASK (0xFFFFU << VAD_DET_CON3_IIR_ANUM_1_SHIFT) 9024 #define VAD_DET_CON3_IIR_ANUM_2_SHIFT (16U) 9025 #define VAD_DET_CON3_IIR_ANUM_2_MASK (0xFFFFU << VAD_DET_CON3_IIR_ANUM_2_SHIFT) 9026 /* DET_CON4 */ 9027 #define VAD_DET_CON4_OFFSET (0x6CU) 9028 #define VAD_DET_CON4_IIR_ADEN_1_SHIFT (0U) 9029 #define VAD_DET_CON4_IIR_ADEN_1_MASK (0xFFFFU << VAD_DET_CON4_IIR_ADEN_1_SHIFT) 9030 #define VAD_DET_CON4_IIR_ADEN_2_SHIFT (16U) 9031 #define VAD_DET_CON4_IIR_ADEN_2_MASK (0xFFFFU << VAD_DET_CON4_IIR_ADEN_2_SHIFT) 9032 /* DET_CON5 */ 9033 #define VAD_DET_CON5_OFFSET (0x70U) 9034 #define VAD_DET_CON5_NOISE_ABS_SHIFT (0U) 9035 #define VAD_DET_CON5_NOISE_ABS_MASK (0xFFFFU << VAD_DET_CON5_NOISE_ABS_SHIFT) 9036 #define VAD_DET_CON5_IIR_RESULT_SHIFT (16U) 9037 #define VAD_DET_CON5_IIR_RESULT_MASK (0xFFFFU << VAD_DET_CON5_IIR_RESULT_SHIFT) 9038 /* INT */ 9039 #define VAD_INT_OFFSET (0x74U) 9040 #define VAD_INT_VAD_DET_INT_EN_SHIFT (0U) 9041 #define VAD_INT_VAD_DET_INT_EN_MASK (0x1U << VAD_INT_VAD_DET_INT_EN_SHIFT) 9042 #define VAD_INT_ERROR_INT_EN_SHIFT (1U) 9043 #define VAD_INT_ERROR_INT_EN_MASK (0x1U << VAD_INT_ERROR_INT_EN_SHIFT) 9044 #define VAD_INT_IDLE_TIMEOUT_INT_EN_SHIFT (2U) 9045 #define VAD_INT_IDLE_TIMEOUT_INT_EN_MASK (0x1U << VAD_INT_IDLE_TIMEOUT_INT_EN_SHIFT) 9046 #define VAD_INT_WORK_TIMEOUT_INT_EN_SHIFT (3U) 9047 #define VAD_INT_WORK_TIMEOUT_INT_EN_MASK (0x1U << VAD_INT_WORK_TIMEOUT_INT_EN_SHIFT) 9048 #define VAD_INT_VAD_DET_INT_SHIFT (4U) 9049 #define VAD_INT_VAD_DET_INT_MASK (0x1U << VAD_INT_VAD_DET_INT_SHIFT) 9050 #define VAD_INT_ERROR_INT_SHIFT (5U) 9051 #define VAD_INT_ERROR_INT_MASK (0x1U << VAD_INT_ERROR_INT_SHIFT) 9052 #define VAD_INT_IDLE_TIMEOUT_INT_SHIFT (6U) 9053 #define VAD_INT_IDLE_TIMEOUT_INT_MASK (0x1U << VAD_INT_IDLE_TIMEOUT_INT_SHIFT) 9054 #define VAD_INT_WORK_TIMEOUT_INT_SHIFT (7U) 9055 #define VAD_INT_WORK_TIMEOUT_INT_MASK (0x1U << VAD_INT_WORK_TIMEOUT_INT_SHIFT) 9056 #define VAD_INT_RAMP_LOOP_FLAG_SHIFT (8U) 9057 #define VAD_INT_RAMP_LOOP_FLAG_MASK (0x1U << VAD_INT_RAMP_LOOP_FLAG_SHIFT) 9058 #define VAD_INT_VAD_IDLE_SHIFT (9U) 9059 #define VAD_INT_VAD_IDLE_MASK (0x1U << VAD_INT_VAD_IDLE_SHIFT) 9060 #define VAD_INT_VAD_DATA_TRANS_INT_EN_SHIFT (10U) 9061 #define VAD_INT_VAD_DATA_TRANS_INT_EN_MASK (0x1U << VAD_INT_VAD_DATA_TRANS_INT_EN_SHIFT) 9062 #define VAD_INT_VAD_DATA_TRANS_INT_SHIFT (11U) 9063 #define VAD_INT_VAD_DATA_TRANS_INT_MASK (0x1U << VAD_INT_VAD_DATA_TRANS_INT_SHIFT) 9064 #define VAD_INT_RAMP_LOOP_FLAG_BUS_SHIFT (12U) 9065 #define VAD_INT_RAMP_LOOP_FLAG_BUS_MASK (0x1U << VAD_INT_RAMP_LOOP_FLAG_BUS_SHIFT) 9066 /* AUX_CON0 */ 9067 #define VAD_AUX_CON0_OFFSET (0x78U) 9068 #define VAD_AUX_CON0_BUS_WRITE_EN_SHIFT (0U) 9069 #define VAD_AUX_CON0_BUS_WRITE_EN_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_EN_SHIFT) 9070 #define VAD_AUX_CON0_DIS_RAM_ITF_SHIFT (1U) 9071 #define VAD_AUX_CON0_DIS_RAM_ITF_MASK (0x1U << VAD_AUX_CON0_DIS_RAM_ITF_SHIFT) 9072 #define VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_SHIFT (2U) 9073 #define VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_MASK (0x1U << VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_SHIFT) 9074 #define VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_SHIFT (4U) 9075 #define VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_MASK (0xFFU << VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_SHIFT) 9076 #define VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_SHIFT (12U) 9077 #define VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_SHIFT) 9078 #define VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_SHIFT (13U) 9079 #define VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_SHIFT) 9080 #define VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_SHIFT (14U) 9081 #define VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_SHIFT) 9082 #define VAD_AUX_CON0_INT_TRIG_VALID_THD_SHIFT (16U) 9083 #define VAD_AUX_CON0_INT_TRIG_VALID_THD_MASK (0xFFFU << VAD_AUX_CON0_INT_TRIG_VALID_THD_SHIFT) 9084 #define VAD_AUX_CON0_INT_TRIG_CTRL_EN_SHIFT (28U) 9085 #define VAD_AUX_CON0_INT_TRIG_CTRL_EN_MASK (0x1U << VAD_AUX_CON0_INT_TRIG_CTRL_EN_SHIFT) 9086 #define VAD_AUX_CON0_SAMPLE_CNT_EN_SHIFT (29U) 9087 #define VAD_AUX_CON0_SAMPLE_CNT_EN_MASK (0x1U << VAD_AUX_CON0_SAMPLE_CNT_EN_SHIFT) 9088 /* SAMPLE_CNT */ 9089 #define VAD_SAMPLE_CNT_OFFSET (0x7CU) 9090 #define VAD_SAMPLE_CNT (0x0U) 9091 #define VAD_SAMPLE_CNT_SAMPLE_CNT_SHIFT (0U) 9092 #define VAD_SAMPLE_CNT_SAMPLE_CNT_MASK (0xFFFFFFFFU << VAD_SAMPLE_CNT_SAMPLE_CNT_SHIFT) 9093 /* RAM_START_ADDR_BUS */ 9094 #define VAD_RAM_START_ADDR_BUS_OFFSET (0x80U) 9095 #define VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_SHIFT (0U) 9096 #define VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_MASK \ 9097 (0xFFFFFFFFU << VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_SHIFT) 9098 /* RAM_END_ADDR_BUS */ 9099 #define VAD_RAM_END_ADDR_BUS_OFFSET (0x84U) 9100 #define VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_SHIFT (0U) 9101 #define VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_MASK \ 9102 (0xFFFFFFFFU << VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_SHIFT) 9103 /* RAM_CUR_ADDR_BUS */ 9104 #define VAD_RAM_CUR_ADDR_BUS_OFFSET (0x88U) 9105 #define VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_SHIFT (0U) 9106 #define VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_MASK \ 9107 (0xFFFFFFFFU << VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_SHIFT) 9108 /* AUX_CON1 */ 9109 #define VAD_AUX_CON1_OFFSET (0x8CU) 9110 #define VAD_AUX_CON1_DATA_TRANS_WORD_THD_SHIFT (0U) 9111 #define VAD_AUX_CON1_DATA_TRANS_WORD_THD_MASK (0xFFFFU << VAD_AUX_CON1_DATA_TRANS_WORD_THD_SHIFT) 9112 #define VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_SHIFT (16U) 9113 #define VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_MASK (0x1U << VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_SHIFT) 9114 /* NOISE_FIRST_DATA */ 9115 #define VAD_NOISE_FIRST_DATA_OFFSET (0x100U) 9116 #define VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_SHIFT (0U) 9117 #define VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_MASK (0xFFFFU << VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_SHIFT) 9118 /* NOISE_LAST_DATA */ 9119 #define VAD_NOISE_LAST_DATA_OFFSET (0x2FCU) 9120 #define VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_SHIFT (0U) 9121 #define VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_MASK (0xFFFFU << VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_SHIFT) 9122 /***************************************LPW_SYSBUS***************************************/ 9123 /* MIPS_MCU_CONTROL */ 9124 #define LPW_SYSBUS_MIPS_MCU_CONTROL_OFFSET (0x0U) 9125 #define LPW_SYSBUS_MIPS_MCU_CONTROL_MIPS_MCU_PULSE_SOFT_RESET_SHIFT (0U) 9126 #define LPW_SYSBUS_MIPS_MCU_CONTROL_MIPS_MCU_PULSE_SOFT_RESET_MASK \ 9127 (0x1U << LPW_SYSBUS_MIPS_MCU_CONTROL_MIPS_MCU_PULSE_SOFT_RESET_SHIFT) 9128 #define LPW_SYSBUS_MIPS_MCU_CONTROL_MIPS_MCU_LATCH_SOFT_RESET_SHIFT (1U) 9129 #define LPW_SYSBUS_MIPS_MCU_CONTROL_MIPS_MCU_LATCH_SOFT_RESET_MASK \ 9130 (0x1U << LPW_SYSBUS_MIPS_MCU_CONTROL_MIPS_MCU_LATCH_SOFT_RESET_SHIFT) 9131 /* MIPS_MCU_SYS_CORE_MEM_CTRL */ 9132 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_OFFSET (0x30U) 9133 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_ADDR_SHIFT (0U) 9134 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_ADDR_MASK \ 9135 (0x1U << LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_ADDR_SHIFT) 9136 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_REGION_SHIFT (30U) 9137 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_REGION_MASK \ 9138 (0x1U << LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_REGION_SHIFT) 9139 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_RDNWR_SHIFT (31U) 9140 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_RDNWR_MASK \ 9141 (0x1U << LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_CTRL_MIPS_MCU_CORE_MEM_RDNWR_SHIFT) 9142 /* MIPS_MCU_SYS_CORE_MEM_WDATA */ 9143 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_WDATA_OFFSET (0x34U) 9144 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_WDATA_MIPS_MCU_CORE_MEM_WDATA_SHIFT (0U) 9145 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_WDATA_MIPS_MCU_CORE_MEM_WDATA_MASK \ 9146 (0x1U << LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_WDATA_MIPS_MCU_CORE_MEM_WDATA_SHIFT) 9147 /* MIPS_MCU_SYS_CORE_MEM_RDATA */ 9148 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_RDATA_OFFSET (0x38U) 9149 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_RDATA_MIPS_MCU_CORE_MEM_RDATA_SHIFT (0U) 9150 #define LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_RDATA_MIPS_MCU_CORE_MEM_RDATA_MASK \ 9151 (0x1U << LPW_SYSBUS_MIPS_MCU_SYS_CORE_MEM_RDATA_MIPS_MCU_CORE_MEM_RDATA_SHIFT) 9152 /* MIPS_MCU_BOOT_EXCP_INSTR_0 */ 9153 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_0_OFFSET (0x50U) 9154 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_0_MCU_BOOT_EXCP_INSTR_0_SHIFT (0U) 9155 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_0_MCU_BOOT_EXCP_INSTR_0_MASK \ 9156 (0xFFFFFFFFU << LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_0_MCU_BOOT_EXCP_INSTR_0_SHIFT) 9157 /* MIPS_MCU_BOOT_EXCP_INSTR_1 */ 9158 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_1_OFFSET (0x54U) 9159 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_1_MIPS_MCU_BOOT_EXCP_INSTR_1_SHIFT (0U) 9160 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_1_MIPS_MCU_BOOT_EXCP_INSTR_1_MASK \ 9161 (0xFFFFFFFFU << LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_1_MIPS_MCU_BOOT_EXCP_INSTR_1_SHIFT) 9162 /* MIPS_MCU_BOOT_EXCP_INSTR_2 */ 9163 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_2_OFFSET (0x58U) 9164 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_2_MCU_BOOT_EXCP_INSTR_2_SHIFT (0U) 9165 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_2_MCU_BOOT_EXCP_INSTR_2_MASK \ 9166 (0xFFFFFFFFU << LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_2_MCU_BOOT_EXCP_INSTR_2_SHIFT) 9167 /* MIPS_MCU_BOOT_EXCP_INSTR_3 */ 9168 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_3_OFFSET (0x5CU) 9169 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_3_MCU_BOOT_EXCP_INSTR_3_SHIFT (0U) 9170 #define LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_3_MCU_BOOT_EXCP_INSTR_3_MASK \ 9171 (0xFFFFFFFFU << LPW_SYSBUS_MIPS_MCU_BOOT_EXCP_INSTR_3_MCU_BOOT_EXCP_INSTR_3_SHIFT) 9172 /* UCCP_CORE_HOST_TO_MTX_CMD */ 9173 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_CMD_OFFSET (0x430U) 9174 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_CMD_HOST_DATA_SHIFT (0U) 9175 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_CMD_HOST_DATA_MASK \ 9176 (0x7FFFFFFFU << LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_CMD_HOST_DATA_SHIFT) 9177 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_CMD_HOST_INT_SHIFT (31U) 9178 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_CMD_HOST_INT_MASK \ 9179 (0x1U << LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_CMD_HOST_INT_SHIFT) 9180 /* UCCP_CORE_MTX_TO_HOST_CMD */ 9181 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_CMD_OFFSET (0x434U) 9182 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_CMD_MTX_DATA_SHIFT (0U) 9183 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_CMD_MTX_DATA_MASK \ 9184 (0x7FFFFFFFU << LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_CMD_MTX_DATA_SHIFT) 9185 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_CMD_MTX_INT_SHIFT (31U) 9186 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_CMD_MTX_INT_MASK \ 9187 (0x1U << LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_CMD_MTX_INT_SHIFT) 9188 /* UCCP_CORE_HOST_TO_MTX_ACK */ 9189 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_ACK_OFFSET (0x438U) 9190 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_ACK_MTX_INT_CLR_SHIFT (31U) 9191 #define LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_ACK_MTX_INT_CLR_MASK \ 9192 (0x1U << LPW_SYSBUS_UCCP_CORE_HOST_TO_MTX_ACK_MTX_INT_CLR_SHIFT) 9193 /* UCCP_CORE_MTX_TO_HOST_ACK */ 9194 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_ACK_OFFSET (0x43CU) 9195 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_ACK_HOST_INT_CLR_SHIFT (31U) 9196 #define LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_ACK_HOST_INT_CLR_MASK \ 9197 (0x1U << LPW_SYSBUS_UCCP_CORE_MTX_TO_HOST_ACK_HOST_INT_CLR_SHIFT) 9198 /* UCCP_CORE_HOST_INT_ENABLE */ 9199 #define LPW_SYSBUS_UCCP_CORE_HOST_INT_ENABLE_OFFSET (0x440U) 9200 #define LPW_SYSBUS_UCCP_CORE_HOST_INT_ENABLE_HOST_INT_EN_SHIFT (31U) 9201 #define LPW_SYSBUS_UCCP_CORE_HOST_INT_ENABLE_HOST_INT_EN_MASK \ 9202 (0x1U << LPW_SYSBUS_UCCP_CORE_HOST_INT_ENABLE_HOST_INT_EN_SHIFT) 9203 /* UCCP_CORE_MTX_INT_ENABLE */ 9204 #define LPW_SYSBUS_UCCP_CORE_MTX_INT_ENABLE_OFFSET (0x444U) 9205 #define LPW_SYSBUS_UCCP_CORE_MTX_INT_ENABLE_MTX_INT_EN_SHIFT (0U) 9206 #define LPW_SYSBUS_UCCP_CORE_MTX_INT_ENABLE_MTX_INT_EN_MASK \ 9207 (0x1U << LPW_SYSBUS_UCCP_CORE_MTX_INT_ENABLE_MTX_INT_EN_SHIFT) 9208 /* UCCP_SOC_FAB_STATUS */ 9209 #define LPW_SYSBUS_UCCP_SOC_FAB_STATUS_OFFSET (0x78CU) 9210 #define LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_MEMOPT_IDLE_SHIFT (2U) 9211 #define LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_MEMOPT_IDLE_MASK \ 9212 (0x1U << LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_MEMOPT_IDLE_SHIFT) 9213 #define LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_EXTOPT_REQ_IDLE_SHIFT (4U) 9214 #define LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_EXTOPT_REQ_IDLE_MASK \ 9215 (0x1U << LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_EXTOPT_REQ_IDLE_SHIFT) 9216 #define LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_EXTOPT_MEM_IDLE_SHIFT (5U) 9217 #define LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_EXTOPT_MEM_IDLE_MASK \ 9218 (0x1U << LPW_SYSBUS_UCCP_SOC_FAB_STATUS_CR_EXTOPT_MEM_IDLE_SHIFT) 9219 /* UCC_SLEEP_CTRL_DATA_0 */ 9220 #define LPW_SYSBUS_UCC_SLEEP_CTRL_DATA_0_OFFSET (0x2C2CU) 9221 #define LPW_SYSBUS_UCC_SLEEP_CTRL_DATA_0_DATA_0_SHIFT (0U) 9222 #define LPW_SYSBUS_UCC_SLEEP_CTRL_DATA_0_DATA_0_MASK \ 9223 (0xFFFFFU << LPW_SYSBUS_UCC_SLEEP_CTRL_DATA_0_DATA_0_SHIFT) 9224 /* UCC_SLEEP_CTRL_MCU_BOOT_ADDR_MS */ 9225 #define LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_MS_OFFSET (0x2DD4U) 9226 #define LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_MS_MCU_BOOT_ADDR_MS_SHIFT (0U) 9227 #define LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_MS_MCU_BOOT_ADDR_MS_MASK \ 9228 (0x3FFFU << LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_MS_MCU_BOOT_ADDR_MS_SHIFT) 9229 /* UCC_SLEEP_CTRL_MCU_BOOT_ADDR_LS */ 9230 #define LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_LS_OFFSET (0x2DD8U) 9231 #define LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_LS_MCU_BOOT_ADDR_LS_SHIFT (0U) 9232 #define LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_LS_MCU_BOOT_ADDR_LS_MASK \ 9233 (0xFFFFU << LPW_SYSBUS_UCC_SLEEP_CTRL_MCU_BOOT_ADDR_LS_MCU_BOOT_ADDR_LS_SHIFT) 9234 /****************************************LPW_PBUS****************************************/ 9235 /* EDC_GPIO0_OUT */ 9236 #define LPW_PBUS_EDC_GPIO0_OUT_OFFSET (0x3C00U) 9237 #define LPW_PBUS_EDC_GPIO0_OUT_GPIO0_OUT_SHIFT (0U) 9238 #define LPW_PBUS_EDC_GPIO0_OUT_GPIO0_OUT_MASK (0xFFFFU << LPW_PBUS_EDC_GPIO0_OUT_GPIO0_OUT_SHIFT) 9239 /* EDC_GPIO1_OUT */ 9240 #define LPW_PBUS_EDC_GPIO1_OUT_OFFSET (0x3C04U) 9241 #define LPW_PBUS_EDC_GPIO1_OUT_GPIO1_OUT_SHIFT (0U) 9242 #define LPW_PBUS_EDC_GPIO1_OUT_GPIO1_OUT_MASK (0xFFFFU << LPW_PBUS_EDC_GPIO1_OUT_GPIO1_OUT_SHIFT) 9243 /* EDC_GPIO0_IN */ 9244 #define LPW_PBUS_EDC_GPIO0_IN_OFFSET (0x3C08U) 9245 #define LPW_PBUS_EDC_GPIO0_IN_GPIO0_IN_SHIFT (0U) 9246 #define LPW_PBUS_EDC_GPIO0_IN_GPIO0_IN_MASK (0xFFFFU << LPW_PBUS_EDC_GPIO0_IN_GPIO0_IN_SHIFT) 9247 /* EDC_GPIO1_IN */ 9248 #define LPW_PBUS_EDC_GPIO1_IN_OFFSET (0x3C0CU) 9249 #define LPW_PBUS_EDC_GPIO1_IN_GPIO1_IN_SHIFT (0U) 9250 #define LPW_PBUS_EDC_GPIO1_IN_GPIO1_IN_MASK (0xFFFFU << LPW_PBUS_EDC_GPIO1_IN_GPIO1_IN_SHIFT) 9251 /* RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1 */ 9252 #define LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_OFFSET (0x8C20U) 9253 #define LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_ALL_SHIFT (0U) 9254 #define LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_ALL_MASK \ 9255 (0x1U << LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_ALL_SHIFT) 9256 #define LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_MCU_SHIFT (4U) 9257 #define LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_MCU_MASK \ 9258 (0x1U << LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_MCU_SHIFT) 9259 #define LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_MCP_SHIFT (16U) 9260 #define LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_MCP_MASK \ 9261 (0x1U << LPW_PBUS_RPU_CLOCK_RESET_CTRL_CLOCK_ENABLE_1_CLOCK_ENABLE_MCP_SHIFT) 9262 /*****************************************VICAP******************************************/ 9263 /* DVP_CTRL */ 9264 #define VICAP_DVP_CTRL_OFFSET (0x0U) 9265 #define VICAP_DVP_CTRL_CAP_EN_SHIFT (0U) 9266 #define VICAP_DVP_CTRL_CAP_EN_MASK (0x1U << VICAP_DVP_CTRL_CAP_EN_SHIFT) 9267 #define VICAP_DVP_CTRL_WORK_MODE_SHIFT (1U) 9268 #define VICAP_DVP_CTRL_WORK_MODE_MASK (0x3U << VICAP_DVP_CTRL_WORK_MODE_SHIFT) 9269 #define VICAP_DVP_CTRL_AXI_BURST_TYPE_SHIFT (12U) 9270 #define VICAP_DVP_CTRL_AXI_BURST_TYPE_MASK (0xFU << VICAP_DVP_CTRL_AXI_BURST_TYPE_SHIFT) 9271 /* DVP_INTEN */ 9272 #define VICAP_DVP_INTEN_OFFSET (0x4U) 9273 #define VICAP_DVP_INTEN_DMA_FRAME_END_EN_SHIFT (0U) 9274 #define VICAP_DVP_INTEN_DMA_FRAME_END_EN_MASK (0x1U << VICAP_DVP_INTEN_DMA_FRAME_END_EN_SHIFT) 9275 #define VICAP_DVP_INTEN_LINE_END_EN_SHIFT (1U) 9276 #define VICAP_DVP_INTEN_LINE_END_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE_END_EN_SHIFT) 9277 #define VICAP_DVP_INTEN_LINE_ERR_EN_SHIFT (2U) 9278 #define VICAP_DVP_INTEN_LINE_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE_ERR_EN_SHIFT) 9279 #define VICAP_DVP_INTEN_PIX_ERR_EN_SHIFT (3U) 9280 #define VICAP_DVP_INTEN_PIX_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_PIX_ERR_EN_SHIFT) 9281 #define VICAP_DVP_INTEN_IFIFO_OF_EN_SHIFT (4U) 9282 #define VICAP_DVP_INTEN_IFIFO_OF_EN_MASK (0x1U << VICAP_DVP_INTEN_IFIFO_OF_EN_SHIFT) 9283 #define VICAP_DVP_INTEN_DFIFO_OF_EN_SHIFT (5U) 9284 #define VICAP_DVP_INTEN_DFIFO_OF_EN_MASK (0x1U << VICAP_DVP_INTEN_DFIFO_OF_EN_SHIFT) 9285 #define VICAP_DVP_INTEN_BUS_ERR_EN_SHIFT (6U) 9286 #define VICAP_DVP_INTEN_BUS_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_BUS_ERR_EN_SHIFT) 9287 #define VICAP_DVP_INTEN_FRAME_START_EN_SHIFT (7U) 9288 #define VICAP_DVP_INTEN_FRAME_START_EN_MASK (0x1U << VICAP_DVP_INTEN_FRAME_START_EN_SHIFT) 9289 #define VICAP_DVP_INTEN_PRE_INF_FRAME_END_EN_SHIFT (8U) 9290 #define VICAP_DVP_INTEN_PRE_INF_FRAME_END_EN_MASK (0x1U << VICAP_DVP_INTEN_PRE_INF_FRAME_END_EN_SHIFT) 9291 #define VICAP_DVP_INTEN_PST_INF_FRAME_END_EN_SHIFT (9U) 9292 #define VICAP_DVP_INTEN_PST_INF_FRAME_END_EN_MASK (0x1U << VICAP_DVP_INTEN_PST_INF_FRAME_END_EN_SHIFT) 9293 #define VICAP_DVP_INTEN_BLOCK0_END_EN_SHIFT (10U) 9294 #define VICAP_DVP_INTEN_BLOCK0_END_EN_MASK (0x1U << VICAP_DVP_INTEN_BLOCK0_END_EN_SHIFT) 9295 #define VICAP_DVP_INTEN_BLOCK1_END_EN_SHIFT (11U) 9296 #define VICAP_DVP_INTEN_BLOCK1_END_EN_MASK (0x1U << VICAP_DVP_INTEN_BLOCK1_END_EN_SHIFT) 9297 #define VICAP_DVP_INTEN_LINE0_END_EN_SHIFT (12U) 9298 #define VICAP_DVP_INTEN_LINE0_END_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE0_END_EN_SHIFT) 9299 #define VICAP_DVP_INTEN_LINE1_END_EN_SHIFT (13U) 9300 #define VICAP_DVP_INTEN_LINE1_END_EN_MASK (0x1U << VICAP_DVP_INTEN_LINE1_END_EN_SHIFT) 9301 #define VICAP_DVP_INTEN_BLOCK_ERR_EN_SHIFT (14U) 9302 #define VICAP_DVP_INTEN_BLOCK_ERR_EN_MASK (0x1U << VICAP_DVP_INTEN_BLOCK_ERR_EN_SHIFT) 9303 /* DVP_INTSTAT */ 9304 #define VICAP_DVP_INTSTAT_OFFSET (0x8U) 9305 #define VICAP_DVP_INTSTAT_DMA_FRAME_END_SHIFT (0U) 9306 #define VICAP_DVP_INTSTAT_DMA_FRAME_END_MASK (0x1U << VICAP_DVP_INTSTAT_DMA_FRAME_END_SHIFT) 9307 #define VICAP_DVP_INTSTAT_LINE_END_SHIFT (1U) 9308 #define VICAP_DVP_INTSTAT_LINE_END_MASK (0x1U << VICAP_DVP_INTSTAT_LINE_END_SHIFT) 9309 #define VICAP_DVP_INTSTAT_LINE_ERR_SHIFT (2U) 9310 #define VICAP_DVP_INTSTAT_LINE_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_LINE_ERR_SHIFT) 9311 #define VICAP_DVP_INTSTAT_PIX_ERR_SHIFT (3U) 9312 #define VICAP_DVP_INTSTAT_PIX_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_PIX_ERR_SHIFT) 9313 #define VICAP_DVP_INTSTAT_IFIFO_OF_SHIFT (4U) 9314 #define VICAP_DVP_INTSTAT_IFIFO_OF_MASK (0x1U << VICAP_DVP_INTSTAT_IFIFO_OF_SHIFT) 9315 #define VICAP_DVP_INTSTAT_DFIFO_OF_SHIFT (5U) 9316 #define VICAP_DVP_INTSTAT_DFIFO_OF_MASK (0x1U << VICAP_DVP_INTSTAT_DFIFO_OF_SHIFT) 9317 #define VICAP_DVP_INTSTAT_BUS_ERR_SHIFT (6U) 9318 #define VICAP_DVP_INTSTAT_BUS_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_BUS_ERR_SHIFT) 9319 #define VICAP_DVP_INTSTAT_FRAME_START_SHIFT (7U) 9320 #define VICAP_DVP_INTSTAT_FRAME_START_MASK (0x1U << VICAP_DVP_INTSTAT_FRAME_START_SHIFT) 9321 #define VICAP_DVP_INTSTAT_PRE_INF_FRAME_END_SHIFT (8U) 9322 #define VICAP_DVP_INTSTAT_PRE_INF_FRAME_END_MASK (0x1U << VICAP_DVP_INTSTAT_PRE_INF_FRAME_END_SHIFT) 9323 #define VICAP_DVP_INTSTAT_PST_INF_FRAME_END_SHIFT (9U) 9324 #define VICAP_DVP_INTSTAT_PST_INF_FRAME_END_MASK (0x1U << VICAP_DVP_INTSTAT_PST_INF_FRAME_END_SHIFT) 9325 #define VICAP_DVP_INTSTAT_BLOCK0_END_SHIFT (10U) 9326 #define VICAP_DVP_INTSTAT_BLOCK0_END_MASK (0x1U << VICAP_DVP_INTSTAT_BLOCK0_END_SHIFT) 9327 #define VICAP_DVP_INTSTAT_BLOCK1_END_SHIFT (11U) 9328 #define VICAP_DVP_INTSTAT_BLOCK1_END_MASK (0x1U << VICAP_DVP_INTSTAT_BLOCK1_END_SHIFT) 9329 #define VICAP_DVP_INTSTAT_LINE0_END_SHIFT (12U) 9330 #define VICAP_DVP_INTSTAT_LINE0_END_MASK (0x1U << VICAP_DVP_INTSTAT_LINE0_END_SHIFT) 9331 #define VICAP_DVP_INTSTAT_LINE1_END_SHIFT (13U) 9332 #define VICAP_DVP_INTSTAT_LINE1_END_MASK (0x1U << VICAP_DVP_INTSTAT_LINE1_END_SHIFT) 9333 #define VICAP_DVP_INTSTAT_BLOCK_ERR_SHIFT (14U) 9334 #define VICAP_DVP_INTSTAT_BLOCK_ERR_MASK (0x1U << VICAP_DVP_INTSTAT_BLOCK_ERR_SHIFT) 9335 /* DVP_FOR */ 9336 #define VICAP_DVP_FOR_OFFSET (0xCU) 9337 #define VICAP_DVP_FOR_VSYNC_POL_SHIFT (0U) 9338 #define VICAP_DVP_FOR_VSYNC_POL_MASK (0x1U << VICAP_DVP_FOR_VSYNC_POL_SHIFT) 9339 #define VICAP_DVP_FOR_HREF_POL_SHIFT (1U) 9340 #define VICAP_DVP_FOR_HREF_POL_MASK (0x1U << VICAP_DVP_FOR_HREF_POL_SHIFT) 9341 #define VICAP_DVP_FOR_INPUT_MODE_SHIFT (2U) 9342 #define VICAP_DVP_FOR_INPUT_MODE_MASK (0x7U << VICAP_DVP_FOR_INPUT_MODE_SHIFT) 9343 #define VICAP_DVP_FOR_YUV_IN_ORDER_SHIFT (5U) 9344 #define VICAP_DVP_FOR_YUV_IN_ORDER_MASK (0x3U << VICAP_DVP_FOR_YUV_IN_ORDER_SHIFT) 9345 #define VICAP_DVP_FOR_FIELD_ORDER_SHIFT (9U) 9346 #define VICAP_DVP_FOR_FIELD_ORDER_MASK (0x1U << VICAP_DVP_FOR_FIELD_ORDER_SHIFT) 9347 #define VICAP_DVP_FOR_JPEG_MODE_SHIFT (10U) 9348 #define VICAP_DVP_FOR_JPEG_MODE_MASK (0x1U << VICAP_DVP_FOR_JPEG_MODE_SHIFT) 9349 #define VICAP_DVP_FOR_RAW_WIDTH_SHIFT (11U) 9350 #define VICAP_DVP_FOR_RAW_WIDTH_MASK (0x3U << VICAP_DVP_FOR_RAW_WIDTH_SHIFT) 9351 #define VICAP_DVP_FOR_ONLY_Y_MODE_SHIFT (15U) 9352 #define VICAP_DVP_FOR_ONLY_Y_MODE_MASK (0x1U << VICAP_DVP_FOR_ONLY_Y_MODE_SHIFT) 9353 #define VICAP_DVP_FOR_OUTPUT_420_SHIFT (16U) 9354 #define VICAP_DVP_FOR_OUTPUT_420_MASK (0x1U << VICAP_DVP_FOR_OUTPUT_420_SHIFT) 9355 #define VICAP_DVP_FOR_OUT_420_ORDER_SHIFT (17U) 9356 #define VICAP_DVP_FOR_OUT_420_ORDER_MASK (0x1U << VICAP_DVP_FOR_OUT_420_ORDER_SHIFT) 9357 #define VICAP_DVP_FOR_RAW_END_SHIFT (18U) 9358 #define VICAP_DVP_FOR_RAW_END_MASK (0x1U << VICAP_DVP_FOR_RAW_END_SHIFT) 9359 #define VICAP_DVP_FOR_UV_STORE_ORDER_SHIFT (19U) 9360 #define VICAP_DVP_FOR_UV_STORE_ORDER_MASK (0x1U << VICAP_DVP_FOR_UV_STORE_ORDER_SHIFT) 9361 #define VICAP_DVP_FOR_HSYNC_MODE_SHIFT (20U) 9362 #define VICAP_DVP_FOR_HSYNC_MODE_MASK (0x1U << VICAP_DVP_FOR_HSYNC_MODE_SHIFT) 9363 /* DVP_DMA_IDLE_REQ */ 9364 #define VICAP_DVP_DMA_IDLE_REQ_OFFSET (0x10U) 9365 #define VICAP_DVP_DMA_IDLE_REQ_DMA_IDLE_REQ_SHIFT (0U) 9366 #define VICAP_DVP_DMA_IDLE_REQ_DMA_IDLE_REQ_MASK (0x1U << VICAP_DVP_DMA_IDLE_REQ_DMA_IDLE_REQ_SHIFT) 9367 /* DVP_FRM0_ADDR_Y */ 9368 #define VICAP_DVP_FRM0_ADDR_Y_OFFSET (0x14U) 9369 #define VICAP_DVP_FRM0_ADDR_Y_FRM0_ADDR_Y_SHIFT (0U) 9370 #define VICAP_DVP_FRM0_ADDR_Y_FRM0_ADDR_Y_MASK (0xFFFFFFFFU << VICAP_DVP_FRM0_ADDR_Y_FRM0_ADDR_Y_SHIFT) 9371 /* DVP_FRM0_ADDR_UV */ 9372 #define VICAP_DVP_FRM0_ADDR_UV_OFFSET (0x18U) 9373 #define VICAP_DVP_FRM0_ADDR_UV_FRM0_ADDR_UV_SHIFT (0U) 9374 #define VICAP_DVP_FRM0_ADDR_UV_FRM0_ADDR_UV_MASK (0xFFFFFFFFU << VICAP_DVP_FRM0_ADDR_UV_FRM0_ADDR_UV_SHIFT) 9375 /* DVP_FRM1_ADDR_Y */ 9376 #define VICAP_DVP_FRM1_ADDR_Y_OFFSET (0x1CU) 9377 #define VICAP_DVP_FRM1_ADDR_Y_FRM1_ADDR_Y_SHIFT (0U) 9378 #define VICAP_DVP_FRM1_ADDR_Y_FRM1_ADDR_Y_MASK (0xFFFFFFFFU << VICAP_DVP_FRM1_ADDR_Y_FRM1_ADDR_Y_SHIFT) 9379 /* DVP_FRM1_ADDR_UV */ 9380 #define VICAP_DVP_FRM1_ADDR_UV_OFFSET (0x20U) 9381 #define VICAP_DVP_FRM1_ADDR_UV_FRM1_ADDR_UV_SHIFT (0U) 9382 #define VICAP_DVP_FRM1_ADDR_UV_FRM1_ADDR_UV_MASK (0xFFFFFFFFU << VICAP_DVP_FRM1_ADDR_UV_FRM1_ADDR_UV_SHIFT) 9383 /* DVP_VIR_LINE_WIDTH */ 9384 #define VICAP_DVP_VIR_LINE_WIDTH_OFFSET (0x24U) 9385 #define VICAP_DVP_VIR_LINE_WIDTH_VIR_LINE_WIDTH_SHIFT (0U) 9386 #define VICAP_DVP_VIR_LINE_WIDTH_VIR_LINE_WIDTH_MASK (0x7FFFU << VICAP_DVP_VIR_LINE_WIDTH_VIR_LINE_WIDTH_SHIFT) 9387 /* DVP_SET_SIZE */ 9388 #define VICAP_DVP_SET_SIZE_OFFSET (0x28U) 9389 #define VICAP_DVP_SET_SIZE_SET_WIDTH_SHIFT (0U) 9390 #define VICAP_DVP_SET_SIZE_SET_WIDTH_MASK (0x1FFFU << VICAP_DVP_SET_SIZE_SET_WIDTH_SHIFT) 9391 #define VICAP_DVP_SET_SIZE_SET_HEIGHT_SHIFT (16U) 9392 #define VICAP_DVP_SET_SIZE_SET_HEIGHT_MASK (0x1FFFU << VICAP_DVP_SET_SIZE_SET_HEIGHT_SHIFT) 9393 /* DVP_BLOCK_LINE_NUM */ 9394 #define VICAP_DVP_BLOCK_LINE_NUM_OFFSET (0x2CU) 9395 #define VICAP_DVP_BLOCK_LINE_NUM_BLOCK_LINE_NUM_SHIFT (0U) 9396 #define VICAP_DVP_BLOCK_LINE_NUM_BLOCK_LINE_NUM_MASK \ 9397 (0x1FFFU << VICAP_DVP_BLOCK_LINE_NUM_BLOCK_LINE_NUM_SHIFT) 9398 /* DVP_BLOCK0_ADDR_Y */ 9399 #define VICAP_DVP_BLOCK0_ADDR_Y_OFFSET (0x30U) 9400 #define VICAP_DVP_BLOCK0_ADDR_Y_BLOCK0_ADDR_Y_SHIFT (0U) 9401 #define VICAP_DVP_BLOCK0_ADDR_Y_BLOCK0_ADDR_Y_MASK \ 9402 (0xFFFFFFFFU << VICAP_DVP_BLOCK0_ADDR_Y_BLOCK0_ADDR_Y_SHIFT) 9403 /* DVP_BLOCK0_ADDR_UV */ 9404 #define VICAP_DVP_BLOCK0_ADDR_UV_OFFSET (0x34U) 9405 #define VICAP_DVP_BLOCK0_ADDR_UV_BLOCK0_ADDR_UV_SHIFT (0U) 9406 #define VICAP_DVP_BLOCK0_ADDR_UV_BLOCK0_ADDR_UV_MASK \ 9407 (0xFFFFFFFFU << VICAP_DVP_BLOCK0_ADDR_UV_BLOCK0_ADDR_UV_SHIFT) 9408 /* DVP_BLOCK1_ADDR_Y */ 9409 #define VICAP_DVP_BLOCK1_ADDR_Y_OFFSET (0x38U) 9410 #define VICAP_DVP_BLOCK1_ADDR_Y_BLOCK1_ADDR_Y_SHIFT (0U) 9411 #define VICAP_DVP_BLOCK1_ADDR_Y_BLOCK1_ADDR_Y_MASK \ 9412 (0xFFFFFFFFU << VICAP_DVP_BLOCK1_ADDR_Y_BLOCK1_ADDR_Y_SHIFT) 9413 /* DVP_BLOCK1_ADDR_UV */ 9414 #define VICAP_DVP_BLOCK1_ADDR_UV_OFFSET (0x3CU) 9415 #define VICAP_DVP_BLOCK1_ADDR_UV_BLOCK1_ADDR_UV_SHIFT (0U) 9416 #define VICAP_DVP_BLOCK1_ADDR_UV_BLOCK1_ADDR_UV_MASK \ 9417 (0xFFFFFFFFU << VICAP_DVP_BLOCK1_ADDR_UV_BLOCK1_ADDR_UV_SHIFT) 9418 /* DVP_BLOCK_STATUS */ 9419 #define VICAP_DVP_BLOCK_STATUS_OFFSET (0x40U) 9420 #define VICAP_DVP_BLOCK_STATUS_BLK0_STATUS_SHIFT (0U) 9421 #define VICAP_DVP_BLOCK_STATUS_BLK0_STATUS_MASK (0x1U << VICAP_DVP_BLOCK_STATUS_BLK0_STATUS_SHIFT) 9422 #define VICAP_DVP_BLOCK_STATUS_BLK1_STATUS_SHIFT (1U) 9423 #define VICAP_DVP_BLOCK_STATUS_BLK1_STATUS_MASK (0x1U << VICAP_DVP_BLOCK_STATUS_BLK1_STATUS_SHIFT) 9424 #define VICAP_DVP_BLOCK_STATUS_BLK_ID_SHIFT (16U) 9425 #define VICAP_DVP_BLOCK_STATUS_BLK_ID_MASK (0xFFU << VICAP_DVP_BLOCK_STATUS_BLK_ID_SHIFT) 9426 /* DVP_CROP */ 9427 #define VICAP_DVP_CROP_OFFSET (0x44U) 9428 #define VICAP_DVP_CROP_START_X_SHIFT (0U) 9429 #define VICAP_DVP_CROP_START_X_MASK (0x1FFFU << VICAP_DVP_CROP_START_X_SHIFT) 9430 #define VICAP_DVP_CROP_START_Y_SHIFT (16U) 9431 #define VICAP_DVP_CROP_START_Y_MASK (0x1FFFU << VICAP_DVP_CROP_START_Y_SHIFT) 9432 /* DVP_PATH_SEL */ 9433 #define VICAP_DVP_PATH_SEL_OFFSET (0x48U) 9434 #define VICAP_DVP_PATH_SEL_YUV_SEL_SHIFT (4U) 9435 #define VICAP_DVP_PATH_SEL_YUV_SEL_MASK (0x1U << VICAP_DVP_PATH_SEL_YUV_SEL_SHIFT) 9436 #define VICAP_DVP_PATH_SEL_RAW_SEL_SHIFT (5U) 9437 #define VICAP_DVP_PATH_SEL_RAW_SEL_MASK (0x1U << VICAP_DVP_PATH_SEL_RAW_SEL_SHIFT) 9438 /* DVP_LINE_INT_NUM */ 9439 #define VICAP_DVP_LINE_INT_NUM_OFFSET (0x4CU) 9440 #define VICAP_DVP_LINE_INT_NUM_LINE0_INT_NUM_SHIFT (0U) 9441 #define VICAP_DVP_LINE_INT_NUM_LINE0_INT_NUM_MASK (0x1FFFU << VICAP_DVP_LINE_INT_NUM_LINE0_INT_NUM_SHIFT) 9442 #define VICAP_DVP_LINE_INT_NUM_LINE1_INT_NUM_SHIFT (16U) 9443 #define VICAP_DVP_LINE_INT_NUM_LINE1_INT_NUM_MASK (0x1FFFU << VICAP_DVP_LINE_INT_NUM_LINE1_INT_NUM_SHIFT) 9444 /* DVP_WATER_LINE */ 9445 #define VICAP_DVP_WATER_LINE_OFFSET (0x50U) 9446 #define VICAP_DVP_WATER_LINE_HURRY_EN_SHIFT (0U) 9447 #define VICAP_DVP_WATER_LINE_HURRY_EN_MASK (0x1U << VICAP_DVP_WATER_LINE_HURRY_EN_SHIFT) 9448 #define VICAP_DVP_WATER_LINE_HURRY_VALUE_SHIFT (4U) 9449 #define VICAP_DVP_WATER_LINE_HURRY_VALUE_MASK (0x3U << VICAP_DVP_WATER_LINE_HURRY_VALUE_SHIFT) 9450 #define VICAP_DVP_WATER_LINE_WATER_LINE_SHIFT (8U) 9451 #define VICAP_DVP_WATER_LINE_WATER_LINE_MASK (0x3U << VICAP_DVP_WATER_LINE_WATER_LINE_SHIFT) 9452 /* DVP_FIFO_ENTRY */ 9453 #define VICAP_DVP_FIFO_ENTRY_OFFSET (0x54U) 9454 #define VICAP_DVP_FIFO_ENTRY_Y_FIFO_ENTRY_SHIFT (0U) 9455 #define VICAP_DVP_FIFO_ENTRY_Y_FIFO_ENTRY_MASK (0x1FFU << VICAP_DVP_FIFO_ENTRY_Y_FIFO_ENTRY_SHIFT) 9456 #define VICAP_DVP_FIFO_ENTRY_UV_FIFO_ENTRY_SHIFT (9U) 9457 #define VICAP_DVP_FIFO_ENTRY_UV_FIFO_ENTRY_MASK (0x1FFU << VICAP_DVP_FIFO_ENTRY_UV_FIFO_ENTRY_SHIFT) 9458 /* DVP_FRAME_STATUS */ 9459 #define VICAP_DVP_FRAME_STATUS_OFFSET (0x60U) 9460 #define VICAP_DVP_FRAME_STATUS (0x0U) 9461 #define VICAP_DVP_FRAME_STATUS_F0_STS_SHIFT (0U) 9462 #define VICAP_DVP_FRAME_STATUS_F0_STS_MASK (0x1U << VICAP_DVP_FRAME_STATUS_F0_STS_SHIFT) 9463 #define VICAP_DVP_FRAME_STATUS_F1_STS_SHIFT (1U) 9464 #define VICAP_DVP_FRAME_STATUS_F1_STS_MASK (0x1U << VICAP_DVP_FRAME_STATUS_F1_STS_SHIFT) 9465 #define VICAP_DVP_FRAME_STATUS_IDLE_SHIFT (2U) 9466 #define VICAP_DVP_FRAME_STATUS_IDLE_MASK (0x1U << VICAP_DVP_FRAME_STATUS_IDLE_SHIFT) 9467 #define VICAP_DVP_FRAME_STATUS_FRAME_NUM_SHIFT (16U) 9468 #define VICAP_DVP_FRAME_STATUS_FRAME_NUM_MASK (0xFFFFU << VICAP_DVP_FRAME_STATUS_FRAME_NUM_SHIFT) 9469 /* DVP_CUR_DST */ 9470 #define VICAP_DVP_CUR_DST_OFFSET (0x64U) 9471 #define VICAP_DVP_CUR_DST (0x0U) 9472 #define VICAP_DVP_CUR_DST_CUR_DST_SHIFT (0U) 9473 #define VICAP_DVP_CUR_DST_CUR_DST_MASK (0xFFFFFFFFU << VICAP_DVP_CUR_DST_CUR_DST_SHIFT) 9474 /* DVP_LAST_LINE */ 9475 #define VICAP_DVP_LAST_LINE_OFFSET (0x68U) 9476 #define VICAP_DVP_LAST_LINE_LAST_Y_NUM_SHIFT (0U) 9477 #define VICAP_DVP_LAST_LINE_LAST_Y_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_LINE_LAST_Y_NUM_SHIFT) 9478 #define VICAP_DVP_LAST_LINE_LAST_UV_NUM_SHIFT (16U) 9479 #define VICAP_DVP_LAST_LINE_LAST_UV_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_LINE_LAST_UV_NUM_SHIFT) 9480 /* DVP_LAST_PIX */ 9481 #define VICAP_DVP_LAST_PIX_OFFSET (0x6CU) 9482 #define VICAP_DVP_LAST_PIX_LAST_Y_NUM_SHIFT (0U) 9483 #define VICAP_DVP_LAST_PIX_LAST_Y_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_PIX_LAST_Y_NUM_SHIFT) 9484 #define VICAP_DVP_LAST_PIX_LAST_UV_NUM_SHIFT (16U) 9485 #define VICAP_DVP_LAST_PIX_LAST_UV_NUM_MASK (0x1FFFU << VICAP_DVP_LAST_PIX_LAST_UV_NUM_SHIFT) 9486 /******************************************MMC*******************************************/ 9487 /* CTRL */ 9488 #define MMC_CTRL_OFFSET (0x0U) 9489 #define MMC_CTRL_CONTROLLER_RESET_SHIFT (0U) 9490 #define MMC_CTRL_CONTROLLER_RESET_MASK (0x1U << MMC_CTRL_CONTROLLER_RESET_SHIFT) 9491 #define MMC_CTRL_FIFO_RESET_SHIFT (1U) 9492 #define MMC_CTRL_FIFO_RESET_MASK (0x1U << MMC_CTRL_FIFO_RESET_SHIFT) 9493 #define MMC_CTRL_DMA_RESET_SHIFT (2U) 9494 #define MMC_CTRL_DMA_RESET_MASK (0x1U << MMC_CTRL_DMA_RESET_SHIFT) 9495 #define MMC_CTRL_INT_ENABLE_SHIFT (4U) 9496 #define MMC_CTRL_INT_ENABLE_MASK (0x1U << MMC_CTRL_INT_ENABLE_SHIFT) 9497 #define MMC_CTRL_DMA_ENABLE_SHIFT (5U) 9498 #define MMC_CTRL_DMA_ENABLE_MASK (0x1U << MMC_CTRL_DMA_ENABLE_SHIFT) 9499 #define MMC_CTRL_READ_WAIT_SHIFT (6U) 9500 #define MMC_CTRL_READ_WAIT_MASK (0x1U << MMC_CTRL_READ_WAIT_SHIFT) 9501 #define MMC_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) 9502 #define MMC_CTRL_SEND_IRQ_RESPONSE_MASK (0x1U << MMC_CTRL_SEND_IRQ_RESPONSE_SHIFT) 9503 #define MMC_CTRL_ABORT_READ_DATA_SHIFT (8U) 9504 #define MMC_CTRL_ABORT_READ_DATA_MASK (0x1U << MMC_CTRL_ABORT_READ_DATA_SHIFT) 9505 #define MMC_CTRL_SEND_CCSD_SHIFT (9U) 9506 #define MMC_CTRL_SEND_CCSD_MASK (0x1U << MMC_CTRL_SEND_CCSD_SHIFT) 9507 #define MMC_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) 9508 #define MMC_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x1U << MMC_CTRL_SEND_AUTO_STOP_CCSD_SHIFT) 9509 #define MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) 9510 #define MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x1U << MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT) 9511 #define MMC_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) 9512 #define MMC_CTRL_USE_INTERNAL_DMAC_MASK (0x1U << MMC_CTRL_USE_INTERNAL_DMAC_SHIFT) 9513 /* PWREN */ 9514 #define MMC_PWREN_OFFSET (0x4U) 9515 #define MMC_PWREN_POWER_ENABLE_SHIFT (0U) 9516 #define MMC_PWREN_POWER_ENABLE_MASK (0x1U << MMC_PWREN_POWER_ENABLE_SHIFT) 9517 /* CLKDIV */ 9518 #define MMC_CLKDIV_OFFSET (0x8U) 9519 #define MMC_CLKDIV_CLK_DIVIDER0_SHIFT (0U) 9520 #define MMC_CLKDIV_CLK_DIVIDER0_MASK (0xFFU << MMC_CLKDIV_CLK_DIVIDER0_SHIFT) 9521 /* CLKSRC */ 9522 #define MMC_CLKSRC_OFFSET (0xCU) 9523 #define MMC_CLKSRC_CLK_SOURCE_SHIFT (0U) 9524 #define MMC_CLKSRC_CLK_SOURCE_MASK (0x3U << MMC_CLKSRC_CLK_SOURCE_SHIFT) 9525 /* CLKENA */ 9526 #define MMC_CLKENA_OFFSET (0x10U) 9527 #define MMC_CLKENA_CCLK_ENABLE_SHIFT (0U) 9528 #define MMC_CLKENA_CCLK_ENABLE_MASK (0x1U << MMC_CLKENA_CCLK_ENABLE_SHIFT) 9529 #define MMC_CLKENA_CCLK_LOW_POWER_SHIFT (16U) 9530 #define MMC_CLKENA_CCLK_LOW_POWER_MASK (0x1U << MMC_CLKENA_CCLK_LOW_POWER_SHIFT) 9531 /* TMOUT */ 9532 #define MMC_TMOUT_OFFSET (0x14U) 9533 #define MMC_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) 9534 #define MMC_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU << MMC_TMOUT_RESPONSE_TIMEOUT_SHIFT) 9535 #define MMC_TMOUT_DATA_TIMEOUT_SHIFT (8U) 9536 #define MMC_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFFU << MMC_TMOUT_DATA_TIMEOUT_SHIFT) 9537 /* CTYPE */ 9538 #define MMC_CTYPE_OFFSET (0x18U) 9539 #define MMC_CTYPE_CARD_WIDTH_SHIFT (0U) 9540 #define MMC_CTYPE_CARD_WIDTH_MASK (0x1U << MMC_CTYPE_CARD_WIDTH_SHIFT) 9541 #define MMC_CTYPE_CARD_WIDTH_8_SHIFT (16U) 9542 #define MMC_CTYPE_CARD_WIDTH_8_MASK (0x1U << MMC_CTYPE_CARD_WIDTH_8_SHIFT) 9543 /* BLKSIZ */ 9544 #define MMC_BLKSIZ_OFFSET (0x1CU) 9545 #define MMC_BLKSIZ_BLOCK_SIZE_SHIFT (0U) 9546 #define MMC_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU << MMC_BLKSIZ_BLOCK_SIZE_SHIFT) 9547 /* BYTCNT */ 9548 #define MMC_BYTCNT_OFFSET (0x20U) 9549 #define MMC_BYTCNT_BYTE_COUNT_SHIFT (0U) 9550 #define MMC_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_BYTCNT_BYTE_COUNT_SHIFT) 9551 /* INTMASK */ 9552 #define MMC_INTMASK_OFFSET (0x24U) 9553 #define MMC_INTMASK_INT_MASK_SHIFT (0U) 9554 #define MMC_INTMASK_INT_MASK_MASK (0xFFFFU << MMC_INTMASK_INT_MASK_SHIFT) 9555 #define MMC_INTMASK_DATA_NOBUSY_INT_MASK_SHIFT (16U) 9556 #define MMC_INTMASK_DATA_NOBUSY_INT_MASK_MASK (0x1U << MMC_INTMASK_DATA_NOBUSY_INT_MASK_SHIFT) 9557 #define MMC_INTMASK_SDIO_INT_MASK_SHIFT (24U) 9558 #define MMC_INTMASK_SDIO_INT_MASK_MASK (0x1U << MMC_INTMASK_SDIO_INT_MASK_SHIFT) 9559 /* CMDARG */ 9560 #define MMC_CMDARG_OFFSET (0x28U) 9561 #define MMC_CMDARG_CMD_ARG_SHIFT (0U) 9562 #define MMC_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU << MMC_CMDARG_CMD_ARG_SHIFT) 9563 /* CMD */ 9564 #define MMC_CMD_OFFSET (0x2CU) 9565 #define MMC_CMD_CMD_INDEX_SHIFT (0U) 9566 #define MMC_CMD_CMD_INDEX_MASK (0x3FU << MMC_CMD_CMD_INDEX_SHIFT) 9567 #define MMC_CMD_RESPONSE_EXPECT_SHIFT (6U) 9568 #define MMC_CMD_RESPONSE_EXPECT_MASK (0x1U << MMC_CMD_RESPONSE_EXPECT_SHIFT) 9569 #define MMC_CMD_RESPONSE_LENGTH_SHIFT (7U) 9570 #define MMC_CMD_RESPONSE_LENGTH_MASK (0x1U << MMC_CMD_RESPONSE_LENGTH_SHIFT) 9571 #define MMC_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) 9572 #define MMC_CMD_CHECK_RESPONSE_CRC_MASK (0x1U << MMC_CMD_CHECK_RESPONSE_CRC_SHIFT) 9573 #define MMC_CMD_DATA_EXPECTED_SHIFT (9U) 9574 #define MMC_CMD_DATA_EXPECTED_MASK (0x1U << MMC_CMD_DATA_EXPECTED_SHIFT) 9575 #define MMC_CMD_WR_SHIFT (10U) 9576 #define MMC_CMD_WR_MASK (0x1U << MMC_CMD_WR_SHIFT) 9577 #define MMC_CMD_TRANSFER_MODE_SHIFT (11U) 9578 #define MMC_CMD_TRANSFER_MODE_MASK (0x1U << MMC_CMD_TRANSFER_MODE_SHIFT) 9579 #define MMC_CMD_SEND_AUTO_STOP_SHIFT (12U) 9580 #define MMC_CMD_SEND_AUTO_STOP_MASK (0x1U << MMC_CMD_SEND_AUTO_STOP_SHIFT) 9581 #define MMC_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) 9582 #define MMC_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x1U << MMC_CMD_WAIT_PRVDATA_COMPLETE_SHIFT) 9583 #define MMC_CMD_STOP_ABORT_CMD_SHIFT (14U) 9584 #define MMC_CMD_STOP_ABORT_CMD_MASK (0x1U << MMC_CMD_STOP_ABORT_CMD_SHIFT) 9585 #define MMC_CMD_SEND_INITIALIZATION_SHIFT (15U) 9586 #define MMC_CMD_SEND_INITIALIZATION_MASK (0x1U << MMC_CMD_SEND_INITIALIZATION_SHIFT) 9587 #define MMC_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT (21U) 9588 #define MMC_CMD_UPDATE_CLOCK_REGS_ONLY_MASK (0x1U << MMC_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT) 9589 #define MMC_CMD_READ_CEATA_DEVICE_SHIFT (22U) 9590 #define MMC_CMD_READ_CEATA_DEVICE_MASK (0x1U << MMC_CMD_READ_CEATA_DEVICE_SHIFT) 9591 #define MMC_CMD_CCS_EXPECTED_SHIFT (23U) 9592 #define MMC_CMD_CCS_EXPECTED_MASK (0x1U << MMC_CMD_CCS_EXPECTED_SHIFT) 9593 #define MMC_CMD_ENABLE_BOOT_SHIFT (24U) 9594 #define MMC_CMD_ENABLE_BOOT_MASK (0x1U << MMC_CMD_ENABLE_BOOT_SHIFT) 9595 #define MMC_CMD_EXPECT_BOOT_ACK_SHIFT (25U) 9596 #define MMC_CMD_EXPECT_BOOT_ACK_MASK (0x1U << MMC_CMD_EXPECT_BOOT_ACK_SHIFT) 9597 #define MMC_CMD_DISABLE_BOOT_SHIFT (26U) 9598 #define MMC_CMD_DISABLE_BOOT_MASK (0x1U << MMC_CMD_DISABLE_BOOT_SHIFT) 9599 #define MMC_CMD_BOOT_MODE_SHIFT (27U) 9600 #define MMC_CMD_BOOT_MODE_MASK (0x1U << MMC_CMD_BOOT_MODE_SHIFT) 9601 #define MMC_CMD_VOLT_SWITCH_SHIFT (28U) 9602 #define MMC_CMD_VOLT_SWITCH_MASK (0x1U << MMC_CMD_VOLT_SWITCH_SHIFT) 9603 #define MMC_CMD_USE_HOLD_REG_SHIFT (29U) 9604 #define MMC_CMD_USE_HOLD_REG_MASK (0x1U << MMC_CMD_USE_HOLD_REG_SHIFT) 9605 #define MMC_CMD_START_CMD_SHIFT (31U) 9606 #define MMC_CMD_START_CMD_MASK (0x1U << MMC_CMD_START_CMD_SHIFT) 9607 /* RESP0 */ 9608 #define MMC_RESP0_OFFSET (0x30U) 9609 #define MMC_RESP0 (0x0U) 9610 #define MMC_RESP0_RESPONSE0_SHIFT (0U) 9611 #define MMC_RESP0_RESPONSE0_MASK (0xFFFFFFFFU << MMC_RESP0_RESPONSE0_SHIFT) 9612 /* RESP1 */ 9613 #define MMC_RESP1_OFFSET (0x34U) 9614 #define MMC_RESP1 (0x0U) 9615 #define MMC_RESP1_RESPONSE_SHIFT (0U) 9616 #define MMC_RESP1_RESPONSE_MASK (0xFFFFFFFFU << MMC_RESP1_RESPONSE_SHIFT) 9617 /* RESP2 */ 9618 #define MMC_RESP2_OFFSET (0x38U) 9619 #define MMC_RESP2 (0x0U) 9620 #define MMC_RESP2_RESPONSE2_SHIFT (0U) 9621 #define MMC_RESP2_RESPONSE2_MASK (0xFFFFFFFFU << MMC_RESP2_RESPONSE2_SHIFT) 9622 /* RESP3 */ 9623 #define MMC_RESP3_OFFSET (0x3CU) 9624 #define MMC_RESP3 (0x0U) 9625 #define MMC_RESP3_RESPONSE3_SHIFT (0U) 9626 #define MMC_RESP3_RESPONSE3_MASK (0xFFFFFFFFU << MMC_RESP3_RESPONSE3_SHIFT) 9627 /* MINTSTS */ 9628 #define MMC_MINTSTS_OFFSET (0x40U) 9629 #define MMC_MINTSTS_INT_STATUS_SHIFT (0U) 9630 #define MMC_MINTSTS_INT_STATUS_MASK (0xFFFFU << MMC_MINTSTS_INT_STATUS_SHIFT) 9631 #define MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT (16U) 9632 #define MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_MASK (0x1U << MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT) 9633 #define MMC_MINTSTS_SDIO_INTERRUPT_SHIFT (24U) 9634 #define MMC_MINTSTS_SDIO_INTERRUPT_MASK (0x1U << MMC_MINTSTS_SDIO_INTERRUPT_SHIFT) 9635 /* RINTSTS */ 9636 #define MMC_RINTSTS_OFFSET (0x44U) 9637 #define MMC_RINTSTS_INT_STATUS_SHIFT (0U) 9638 #define MMC_RINTSTS_INT_STATUS_MASK (0xFFFFU << MMC_RINTSTS_INT_STATUS_SHIFT) 9639 #define MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT (16U) 9640 #define MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_MASK (0x1U << MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT) 9641 #define MMC_RINTSTS_SDIO_INTERRUPT_SHIFT (24U) 9642 #define MMC_RINTSTS_SDIO_INTERRUPT_MASK (0x1U << MMC_RINTSTS_SDIO_INTERRUPT_SHIFT) 9643 /* STATUS */ 9644 #define MMC_STATUS_OFFSET (0x48U) 9645 #define MMC_STATUS (0x506U) 9646 #define MMC_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) 9647 #define MMC_STATUS_FIFO_RX_WATERMARK_MASK (0x1U << MMC_STATUS_FIFO_RX_WATERMARK_SHIFT) 9648 #define MMC_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) 9649 #define MMC_STATUS_FIFO_TX_WATERMARK_MASK (0x1U << MMC_STATUS_FIFO_TX_WATERMARK_SHIFT) 9650 #define MMC_STATUS_FIFO_EMPTY_SHIFT (2U) 9651 #define MMC_STATUS_FIFO_EMPTY_MASK (0x1U << MMC_STATUS_FIFO_EMPTY_SHIFT) 9652 #define MMC_STATUS_FIFO_FULL_SHIFT (3U) 9653 #define MMC_STATUS_FIFO_FULL_MASK (0x1U << MMC_STATUS_FIFO_FULL_SHIFT) 9654 #define MMC_STATUS_COMMAND_FSM_STATES_SHIFT (4U) 9655 #define MMC_STATUS_COMMAND_FSM_STATES_MASK (0xFU << MMC_STATUS_COMMAND_FSM_STATES_SHIFT) 9656 #define MMC_STATUS_DATA_3_STATUS_SHIFT (8U) 9657 #define MMC_STATUS_DATA_3_STATUS_MASK (0x1U << MMC_STATUS_DATA_3_STATUS_SHIFT) 9658 #define MMC_STATUS_DATA_BUSY_SHIFT (9U) 9659 #define MMC_STATUS_DATA_BUSY_MASK (0x1U << MMC_STATUS_DATA_BUSY_SHIFT) 9660 #define MMC_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) 9661 #define MMC_STATUS_DATA_STATE_MC_BUSY_MASK (0x1U << MMC_STATUS_DATA_STATE_MC_BUSY_SHIFT) 9662 #define MMC_STATUS_RESPONSE_INDEX_SHIFT (11U) 9663 #define MMC_STATUS_RESPONSE_INDEX_MASK (0x3FU << MMC_STATUS_RESPONSE_INDEX_SHIFT) 9664 #define MMC_STATUS_FIFO_COUNT_SHIFT (17U) 9665 #define MMC_STATUS_FIFO_COUNT_MASK (0x1FFFU << MMC_STATUS_FIFO_COUNT_SHIFT) 9666 #define MMC_STATUS_DMA_ACK_SHIFT (30U) 9667 #define MMC_STATUS_DMA_ACK_MASK (0x1U << MMC_STATUS_DMA_ACK_SHIFT) 9668 #define MMC_STATUS_DMA_REQ_SHIFT (31U) 9669 #define MMC_STATUS_DMA_REQ_MASK (0x1U << MMC_STATUS_DMA_REQ_SHIFT) 9670 /* FIFOTH */ 9671 #define MMC_FIFOTH_OFFSET (0x4CU) 9672 #define MMC_FIFOTH_TX_WMARK_SHIFT (0U) 9673 #define MMC_FIFOTH_TX_WMARK_MASK (0xFFFU << MMC_FIFOTH_TX_WMARK_SHIFT) 9674 #define MMC_FIFOTH_RX_WMARK_SHIFT (16U) 9675 #define MMC_FIFOTH_RX_WMARK_MASK (0xFFFU << MMC_FIFOTH_RX_WMARK_SHIFT) 9676 #define MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_SHIFT (28U) 9677 #define MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_MASK (0x7U << MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_SHIFT) 9678 /* CDETECT */ 9679 #define MMC_CDETECT_OFFSET (0x50U) 9680 #define MMC_CDETECT (0x0U) 9681 #define MMC_CDETECT_CARD_DETECT_N_SHIFT (0U) 9682 #define MMC_CDETECT_CARD_DETECT_N_MASK (0x1U << MMC_CDETECT_CARD_DETECT_N_SHIFT) 9683 /* WRTPRT */ 9684 #define MMC_WRTPRT_OFFSET (0x54U) 9685 #define MMC_WRTPRT_WRITE_PROTECT_SHIFT (0U) 9686 #define MMC_WRTPRT_WRITE_PROTECT_MASK (0x1U << MMC_WRTPRT_WRITE_PROTECT_SHIFT) 9687 /* TCBCNT */ 9688 #define MMC_TCBCNT_OFFSET (0x5CU) 9689 #define MMC_TCBCNT (0x0U) 9690 #define MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) 9691 #define MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT) 9692 /* TBBCNT */ 9693 #define MMC_TBBCNT_OFFSET (0x60U) 9694 #define MMC_TBBCNT (0x0U) 9695 #define MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) 9696 #define MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT) 9697 /* DEBNCE */ 9698 #define MMC_DEBNCE_OFFSET (0x64U) 9699 #define MMC_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) 9700 #define MMC_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU << MMC_DEBNCE_DEBOUNCE_COUNT_SHIFT) 9701 /* USRID */ 9702 #define MMC_USRID_OFFSET (0x68U) 9703 #define MMC_USRID_USRID_SHIFT (0U) 9704 #define MMC_USRID_USRID_MASK (0xFFFFFFFFU << MMC_USRID_USRID_SHIFT) 9705 /* VERID */ 9706 #define MMC_VERID_OFFSET (0x6CU) 9707 #define MMC_VERID (0x5342270AU) 9708 #define MMC_VERID_VERID_SHIFT (0U) 9709 #define MMC_VERID_VERID_MASK (0xFFFFFFFFU << MMC_VERID_VERID_SHIFT) 9710 /* HCON */ 9711 #define MMC_HCON_OFFSET (0x70U) 9712 #define MMC_HCON (0x4C47CC1U) 9713 #define MMC_HCON_CARD_TYPE_SHIFT (0U) 9714 #define MMC_HCON_CARD_TYPE_MASK (0x1U << MMC_HCON_CARD_TYPE_SHIFT) 9715 #define MMC_HCON_CARD_NUM_SHIFT (1U) 9716 #define MMC_HCON_CARD_NUM_MASK (0x1FU << MMC_HCON_CARD_NUM_SHIFT) 9717 #define MMC_HCON_H_BUS_TYPE_SHIFT (6U) 9718 #define MMC_HCON_H_BUS_TYPE_MASK (0x1U << MMC_HCON_H_BUS_TYPE_SHIFT) 9719 #define MMC_HCON_H_DATA_WIDTH_SHIFT (7U) 9720 #define MMC_HCON_H_DATA_WIDTH_MASK (0x7U << MMC_HCON_H_DATA_WIDTH_SHIFT) 9721 #define MMC_HCON_H_ADDR_WIDTH_SHIFT (10U) 9722 #define MMC_HCON_H_ADDR_WIDTH_MASK (0x3FU << MMC_HCON_H_ADDR_WIDTH_SHIFT) 9723 #define MMC_HCON_DMA_INTERFACE_SHIFT (16U) 9724 #define MMC_HCON_DMA_INTERFACE_MASK (0x3U << MMC_HCON_DMA_INTERFACE_SHIFT) 9725 #define MMC_HCON_GE_DMA_DATA_WIDTH_SHIFT (18U) 9726 #define MMC_HCON_GE_DMA_DATA_WIDTH_MASK (0x7U << MMC_HCON_GE_DMA_DATA_WIDTH_SHIFT) 9727 #define MMC_HCON_FIFO_RAM_INSIDE_SHIFT (21U) 9728 #define MMC_HCON_FIFO_RAM_INSIDE_MASK (0x1U << MMC_HCON_FIFO_RAM_INSIDE_SHIFT) 9729 #define MMC_HCON_IMPL_HOLD_REG_SHIFT (22U) 9730 #define MMC_HCON_IMPL_HOLD_REG_MASK (0x1U << MMC_HCON_IMPL_HOLD_REG_SHIFT) 9731 #define MMC_HCON_SET_CLK_FALSE_PATH_SHIFT (23U) 9732 #define MMC_HCON_SET_CLK_FALSE_PATH_MASK (0x1U << MMC_HCON_SET_CLK_FALSE_PATH_SHIFT) 9733 #define MMC_HCON_NUM_CLK_DIV_SHIFT (24U) 9734 #define MMC_HCON_NUM_CLK_DIV_MASK (0x3U << MMC_HCON_NUM_CLK_DIV_SHIFT) 9735 #define MMC_HCON_AREA_OPTIMIZED_SHIFT (26U) 9736 #define MMC_HCON_AREA_OPTIMIZED_MASK (0x1U << MMC_HCON_AREA_OPTIMIZED_SHIFT) 9737 /* UHSREG */ 9738 #define MMC_UHSREG_OFFSET (0x74U) 9739 #define MMC_UHSREG_DDR_REG_SHIFT (16U) 9740 #define MMC_UHSREG_DDR_REG_MASK (0x1U << MMC_UHSREG_DDR_REG_SHIFT) 9741 /* RSTN */ 9742 #define MMC_RSTN_OFFSET (0x78U) 9743 #define MMC_RSTN_CARD_RESET_SHIFT (0U) 9744 #define MMC_RSTN_CARD_RESET_MASK (0x1U << MMC_RSTN_CARD_RESET_SHIFT) 9745 /* BMOD */ 9746 #define MMC_BMOD_OFFSET (0x80U) 9747 #define MMC_BMOD_SWR_SHIFT (0U) 9748 #define MMC_BMOD_SWR_MASK (0x1U << MMC_BMOD_SWR_SHIFT) 9749 #define MMC_BMOD_FB_SHIFT (1U) 9750 #define MMC_BMOD_FB_MASK (0x1U << MMC_BMOD_FB_SHIFT) 9751 #define MMC_BMOD_DSL_SHIFT (2U) 9752 #define MMC_BMOD_DSL_MASK (0x1FU << MMC_BMOD_DSL_SHIFT) 9753 #define MMC_BMOD_DE_SHIFT (7U) 9754 #define MMC_BMOD_DE_MASK (0x1U << MMC_BMOD_DE_SHIFT) 9755 #define MMC_BMOD_PBL_SHIFT (8U) 9756 #define MMC_BMOD_PBL_MASK (0x7U << MMC_BMOD_PBL_SHIFT) 9757 /* PLDMND */ 9758 #define MMC_PLDMND_OFFSET (0x84U) 9759 #define MMC_PLDMND_PD_SHIFT (0U) 9760 #define MMC_PLDMND_PD_MASK (0xFFFFFFFFU << MMC_PLDMND_PD_SHIFT) 9761 /* DBADDR */ 9762 #define MMC_DBADDR_OFFSET (0x88U) 9763 #define MMC_DBADDR_SBL_SHIFT (0U) 9764 #define MMC_DBADDR_SBL_MASK (0xFFFFFFFFU << MMC_DBADDR_SBL_SHIFT) 9765 /* IDSTS */ 9766 #define MMC_IDSTS_OFFSET (0x8CU) 9767 #define MMC_IDSTS_TI_SHIFT (0U) 9768 #define MMC_IDSTS_TI_MASK (0x1U << MMC_IDSTS_TI_SHIFT) 9769 #define MMC_IDSTS_RI_SHIFT (1U) 9770 #define MMC_IDSTS_RI_MASK (0x1U << MMC_IDSTS_RI_SHIFT) 9771 #define MMC_IDSTS_FBE_SHIFT (2U) 9772 #define MMC_IDSTS_FBE_MASK (0x1U << MMC_IDSTS_FBE_SHIFT) 9773 #define MMC_IDSTS_DUI_SHIFT (4U) 9774 #define MMC_IDSTS_DUI_MASK (0x1U << MMC_IDSTS_DUI_SHIFT) 9775 #define MMC_IDSTS_CES_SHIFT (5U) 9776 #define MMC_IDSTS_CES_MASK (0x1U << MMC_IDSTS_CES_SHIFT) 9777 #define MMC_IDSTS_NIS_SHIFT (8U) 9778 #define MMC_IDSTS_NIS_MASK (0x1U << MMC_IDSTS_NIS_SHIFT) 9779 #define MMC_IDSTS_AIS_SHIFT (9U) 9780 #define MMC_IDSTS_AIS_MASK (0x1U << MMC_IDSTS_AIS_SHIFT) 9781 #define MMC_IDSTS_EB_SHIFT (10U) 9782 #define MMC_IDSTS_EB_MASK (0x7U << MMC_IDSTS_EB_SHIFT) 9783 #define MMC_IDSTS_FSM_SHIFT (13U) 9784 #define MMC_IDSTS_FSM_MASK (0xFU << MMC_IDSTS_FSM_SHIFT) 9785 /* IDINTEN */ 9786 #define MMC_IDINTEN_OFFSET (0x90U) 9787 #define MMC_IDINTEN_TI_SHIFT (0U) 9788 #define MMC_IDINTEN_TI_MASK (0x1U << MMC_IDINTEN_TI_SHIFT) 9789 #define MMC_IDINTEN_RI_SHIFT (1U) 9790 #define MMC_IDINTEN_RI_MASK (0x1U << MMC_IDINTEN_RI_SHIFT) 9791 #define MMC_IDINTEN_FBE_SHIFT (2U) 9792 #define MMC_IDINTEN_FBE_MASK (0x1U << MMC_IDINTEN_FBE_SHIFT) 9793 #define MMC_IDINTEN_DU_SHIFT (4U) 9794 #define MMC_IDINTEN_DU_MASK (0x1U << MMC_IDINTEN_DU_SHIFT) 9795 #define MMC_IDINTEN_CES_SHIFT (5U) 9796 #define MMC_IDINTEN_CES_MASK (0x1U << MMC_IDINTEN_CES_SHIFT) 9797 #define MMC_IDINTEN_NI_SHIFT (8U) 9798 #define MMC_IDINTEN_NI_MASK (0x1U << MMC_IDINTEN_NI_SHIFT) 9799 #define MMC_IDINTEN_AI_SHIFT (9U) 9800 #define MMC_IDINTEN_AI_MASK (0x1U << MMC_IDINTEN_AI_SHIFT) 9801 /* DSCADDR */ 9802 #define MMC_DSCADDR_OFFSET (0x94U) 9803 #define MMC_DSCADDR_HDA_SHIFT (0U) 9804 #define MMC_DSCADDR_HDA_MASK (0xFFFFFFFFU << MMC_DSCADDR_HDA_SHIFT) 9805 /* BUFADDR */ 9806 #define MMC_BUFADDR_OFFSET (0x98U) 9807 #define MMC_BUFADDR_HBA_SHIFT (0U) 9808 #define MMC_BUFADDR_HBA_MASK (0xFFFFFFFFU << MMC_BUFADDR_HBA_SHIFT) 9809 /* CARDTHRCTL */ 9810 #define MMC_CARDTHRCTL_OFFSET (0x100U) 9811 #define MMC_CARDTHRCTL_CARD_RD_THRES_EN_SHIFT (0U) 9812 #define MMC_CARDTHRCTL_CARD_RD_THRES_EN_MASK (0x1U << MMC_CARDTHRCTL_CARD_RD_THRES_EN_SHIFT) 9813 #define MMC_CARDTHRCTL_BUSY_CLR_INT_EN_SHIFT (1U) 9814 #define MMC_CARDTHRCTL_BUSY_CLR_INT_EN_MASK (0x1U << MMC_CARDTHRCTL_BUSY_CLR_INT_EN_SHIFT) 9815 #define MMC_CARDTHRCTL_CARD_RD_THRES_SHIFT (16U) 9816 #define MMC_CARDTHRCTL_CARD_RD_THRES_MASK (0xFFFU << MMC_CARDTHRCTL_CARD_RD_THRES_SHIFT) 9817 /* BACKEND_POWER */ 9818 #define MMC_BACKEND_POWER_OFFSET (0x104U) 9819 #define MMC_BACKEND_POWER_BACK_END_POWER_SHIFT (0U) 9820 #define MMC_BACKEND_POWER_BACK_END_POWER_MASK (0x1U << MMC_BACKEND_POWER_BACK_END_POWER_SHIFT) 9821 /* EMMCDDR_REG */ 9822 #define MMC_EMMCDDR_REG_OFFSET (0x10CU) 9823 #define MMC_EMMCDDR_REG_HALF_START_BIT_SHIFT (0U) 9824 #define MMC_EMMCDDR_REG_HALF_START_BIT_MASK (0x1U << MMC_EMMCDDR_REG_HALF_START_BIT_SHIFT) 9825 /* RDYINT_GEN */ 9826 #define MMC_RDYINT_GEN_OFFSET (0x120U) 9827 #define MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_SHIFT (0U) 9828 #define MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_MASK (0xFFU << MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_SHIFT) 9829 #define MMC_RDYINT_GEN_RDYINT_GEN_WORKING_SHIFT (8U) 9830 #define MMC_RDYINT_GEN_RDYINT_GEN_WORKING_MASK (0x1U << MMC_RDYINT_GEN_RDYINT_GEN_WORKING_SHIFT) 9831 #define MMC_RDYINT_GEN_RDYINT_CNT_STATUS_SHIFT (16U) 9832 #define MMC_RDYINT_GEN_RDYINT_CNT_STATUS_MASK (0xFFU << MMC_RDYINT_GEN_RDYINT_CNT_STATUS_SHIFT) 9833 #define MMC_RDYINT_GEN_RDYINT_CNT_FINISH_SHIFT (24U) 9834 #define MMC_RDYINT_GEN_RDYINT_CNT_FINISH_MASK (0x1U << MMC_RDYINT_GEN_RDYINT_CNT_FINISH_SHIFT) 9835 /* FIFO_BASE */ 9836 #define MMC_FIFO_BASE_OFFSET (0x200U) 9837 #define MMC_FIFO_BASE_FIFO_BASE_ADDR_SHIFT (0U) 9838 #define MMC_FIFO_BASE_FIFO_BASE_ADDR_MASK (0xFFFFFFFFU << MMC_FIFO_BASE_FIFO_BASE_ADDR_SHIFT) 9839 /*****************************************CRYPTO*****************************************/ 9840 /* CLK_CTL */ 9841 #define CRYPTO_CLK_CTL_OFFSET (0x0U) 9842 #define CRYPTO_CLK_CTL_AUTO_CLKGATE_EN_SHIFT (0U) 9843 #define CRYPTO_CLK_CTL_AUTO_CLKGATE_EN_MASK (0x1U << CRYPTO_CLK_CTL_AUTO_CLKGATE_EN_SHIFT) 9844 /* RST_CTL */ 9845 #define CRYPTO_RST_CTL_OFFSET (0x4U) 9846 #define CRYPTO_RST_CTL_SW_CC_RESET_SHIFT (0U) 9847 #define CRYPTO_RST_CTL_SW_CC_RESET_MASK (0x1U << CRYPTO_RST_CTL_SW_CC_RESET_SHIFT) 9848 #define CRYPTO_RST_CTL_SW_RNG_RESET_SHIFT (1U) 9849 #define CRYPTO_RST_CTL_SW_RNG_RESET_MASK (0x1U << CRYPTO_RST_CTL_SW_RNG_RESET_SHIFT) 9850 #define CRYPTO_RST_CTL_SW_PKA_RESET_SHIFT (2U) 9851 #define CRYPTO_RST_CTL_SW_PKA_RESET_MASK (0x1U << CRYPTO_RST_CTL_SW_PKA_RESET_SHIFT) 9852 /* DMA_INT_EN */ 9853 #define CRYPTO_DMA_INT_EN_OFFSET (0x8U) 9854 #define CRYPTO_DMA_INT_EN_LIST_DONE_INT_EN_SHIFT (0U) 9855 #define CRYPTO_DMA_INT_EN_LIST_DONE_INT_EN_MASK (0x1U << CRYPTO_DMA_INT_EN_LIST_DONE_INT_EN_SHIFT) 9856 #define CRYPTO_DMA_INT_EN_DST_ITEM_DONE_INT_EN_SHIFT (1U) 9857 #define CRYPTO_DMA_INT_EN_DST_ITEM_DONE_INT_EN_MASK (0x1U << CRYPTO_DMA_INT_EN_DST_ITEM_DONE_INT_EN_SHIFT) 9858 #define CRYPTO_DMA_INT_EN_SRC_ITEM_DONE_INT_EN_SHIFT (2U) 9859 #define CRYPTO_DMA_INT_EN_SRC_ITEM_DONE_INT_EN_MASK (0x1U << CRYPTO_DMA_INT_EN_SRC_ITEM_DONE_INT_EN_SHIFT) 9860 #define CRYPTO_DMA_INT_EN_DST_ERR_INT_EN_SHIFT (3U) 9861 #define CRYPTO_DMA_INT_EN_DST_ERR_INT_EN_MASK (0x1U << CRYPTO_DMA_INT_EN_DST_ERR_INT_EN_SHIFT) 9862 #define CRYPTO_DMA_INT_EN_SRC_ERR_INT_EN_SHIFT (4U) 9863 #define CRYPTO_DMA_INT_EN_SRC_ERR_INT_EN_MASK (0x1U << CRYPTO_DMA_INT_EN_SRC_ERR_INT_EN_SHIFT) 9864 #define CRYPTO_DMA_INT_EN_LIST_ERR_INT_EN_SHIFT (5U) 9865 #define CRYPTO_DMA_INT_EN_LIST_ERR_INT_EN_MASK (0x1U << CRYPTO_DMA_INT_EN_LIST_ERR_INT_EN_SHIFT) 9866 #define CRYPTO_DMA_INT_EN_ZERO_LEN_INT_EN_SHIFT (6U) 9867 #define CRYPTO_DMA_INT_EN_ZERO_LEN_INT_EN_MASK (0x1U << CRYPTO_DMA_INT_EN_ZERO_LEN_INT_EN_SHIFT) 9868 /* DMA_INT_ST */ 9869 #define CRYPTO_DMA_INT_ST_OFFSET (0xCU) 9870 #define CRYPTO_DMA_INT_ST_LIST_DONE_SHIFT (0U) 9871 #define CRYPTO_DMA_INT_ST_LIST_DONE_MASK (0x1U << CRYPTO_DMA_INT_ST_LIST_DONE_SHIFT) 9872 #define CRYPTO_DMA_INT_ST_DST_ITEM_DONE_SHIFT (1U) 9873 #define CRYPTO_DMA_INT_ST_DST_ITEM_DONE_MASK (0x1U << CRYPTO_DMA_INT_ST_DST_ITEM_DONE_SHIFT) 9874 #define CRYPTO_DMA_INT_ST_SRC_ITEM_DONE_SHIFT (2U) 9875 #define CRYPTO_DMA_INT_ST_SRC_ITEM_DONE_MASK (0x1U << CRYPTO_DMA_INT_ST_SRC_ITEM_DONE_SHIFT) 9876 #define CRYPTO_DMA_INT_ST_DST_ERR_SHIFT (3U) 9877 #define CRYPTO_DMA_INT_ST_DST_ERR_MASK (0x1U << CRYPTO_DMA_INT_ST_DST_ERR_SHIFT) 9878 #define CRYPTO_DMA_INT_ST_SRC_ERR_SHIFT (4U) 9879 #define CRYPTO_DMA_INT_ST_SRC_ERR_MASK (0x1U << CRYPTO_DMA_INT_ST_SRC_ERR_SHIFT) 9880 #define CRYPTO_DMA_INT_ST_LIST_ERR_SHIFT (5U) 9881 #define CRYPTO_DMA_INT_ST_LIST_ERR_MASK (0x1U << CRYPTO_DMA_INT_ST_LIST_ERR_SHIFT) 9882 #define CRYPTO_DMA_INT_ST_ZERO_LEN_SHIFT (6U) 9883 #define CRYPTO_DMA_INT_ST_ZERO_LEN_MASK (0x1U << CRYPTO_DMA_INT_ST_ZERO_LEN_SHIFT) 9884 /* DMA_CTL */ 9885 #define CRYPTO_DMA_CTL_OFFSET (0x10U) 9886 #define CRYPTO_DMA_CTL_DMA_START_SHIFT (0U) 9887 #define CRYPTO_DMA_CTL_DMA_START_MASK (0x1U << CRYPTO_DMA_CTL_DMA_START_SHIFT) 9888 #define CRYPTO_DMA_CTL_DMA_RESTART_SHIFT (1U) 9889 #define CRYPTO_DMA_CTL_DMA_RESTART_MASK (0x1U << CRYPTO_DMA_CTL_DMA_RESTART_SHIFT) 9890 /* DMA_LLI_ADDR */ 9891 #define CRYPTO_DMA_LLI_ADDR_OFFSET (0x14U) 9892 #define CRYPTO_DMA_LLI_ADDR_DMA_LLI_ADDR_SHIFT (3U) 9893 #define CRYPTO_DMA_LLI_ADDR_DMA_LLI_ADDR_MASK (0x1FFFFFFFU << CRYPTO_DMA_LLI_ADDR_DMA_LLI_ADDR_SHIFT) 9894 /* DMA_ST */ 9895 #define CRYPTO_DMA_ST_OFFSET (0x18U) 9896 #define CRYPTO_DMA_ST_DMA_BUSY_SHIFT (0U) 9897 #define CRYPTO_DMA_ST_DMA_BUSY_MASK (0x1U << CRYPTO_DMA_ST_DMA_BUSY_SHIFT) 9898 /* DMA_STATE */ 9899 #define CRYPTO_DMA_STATE_OFFSET (0x1CU) 9900 #define CRYPTO_DMA_STATE (0x0U) 9901 #define CRYPTO_DMA_STATE_DMA_DST_STATE_SHIFT (0U) 9902 #define CRYPTO_DMA_STATE_DMA_DST_STATE_MASK (0x3U << CRYPTO_DMA_STATE_DMA_DST_STATE_SHIFT) 9903 #define CRYPTO_DMA_STATE_DMA_SRC_STATE_SHIFT (2U) 9904 #define CRYPTO_DMA_STATE_DMA_SRC_STATE_MASK (0x3U << CRYPTO_DMA_STATE_DMA_SRC_STATE_SHIFT) 9905 #define CRYPTO_DMA_STATE_DMA_LLI_STATE_SHIFT (4U) 9906 #define CRYPTO_DMA_STATE_DMA_LLI_STATE_MASK (0x3U << CRYPTO_DMA_STATE_DMA_LLI_STATE_SHIFT) 9907 /* DMA_LLI_RADDR */ 9908 #define CRYPTO_DMA_LLI_RADDR_OFFSET (0x20U) 9909 #define CRYPTO_DMA_LLI_RADDR_DMA_LLI_RADDR_SHIFT (0U) 9910 #define CRYPTO_DMA_LLI_RADDR_DMA_LLI_RADDR_MASK (0xFFFFFFFFU << CRYPTO_DMA_LLI_RADDR_DMA_LLI_RADDR_SHIFT) 9911 /* DMA_SRC_RADDR */ 9912 #define CRYPTO_DMA_SRC_RADDR_OFFSET (0x24U) 9913 #define CRYPTO_DMA_SRC_RADDR_DMA_SRC_RADDR_SHIFT (0U) 9914 #define CRYPTO_DMA_SRC_RADDR_DMA_SRC_RADDR_MASK (0xFFFFFFFFU << CRYPTO_DMA_SRC_RADDR_DMA_SRC_RADDR_SHIFT) 9915 /* DMA_DST_WADDR */ 9916 #define CRYPTO_DMA_DST_WADDR_OFFSET (0x28U) 9917 #define CRYPTO_DMA_DST_WADDR_DMA_DST_WADDR_SHIFT (0U) 9918 #define CRYPTO_DMA_DST_WADDR_DMA_DST_WADDR_MASK (0xFFFFFFFFU << CRYPTO_DMA_DST_WADDR_DMA_DST_WADDR_SHIFT) 9919 /* DMA_ITEM_ID */ 9920 #define CRYPTO_DMA_ITEM_ID_OFFSET (0x2CU) 9921 #define CRYPTO_DMA_ITEM_ID (0x0U) 9922 #define CRYPTO_DMA_ITEM_ID_DMA_ITEM_ID_SHIFT (0U) 9923 #define CRYPTO_DMA_ITEM_ID_DMA_ITEM_ID_MASK (0xFFU << CRYPTO_DMA_ITEM_ID_DMA_ITEM_ID_SHIFT) 9924 /* FIFO_CTL */ 9925 #define CRYPTO_FIFO_CTL_OFFSET (0x40U) 9926 #define CRYPTO_FIFO_CTL_DIN_BYTESWAP_SHIFT (0U) 9927 #define CRYPTO_FIFO_CTL_DIN_BYTESWAP_MASK (0x1U << CRYPTO_FIFO_CTL_DIN_BYTESWAP_SHIFT) 9928 #define CRYPTO_FIFO_CTL_DOUT_BYTESWAP_SHIFT (1U) 9929 #define CRYPTO_FIFO_CTL_DOUT_BYTESWAP_MASK (0x1U << CRYPTO_FIFO_CTL_DOUT_BYTESWAP_SHIFT) 9930 /* BC_CTL */ 9931 #define CRYPTO_BC_CTL_OFFSET (0x44U) 9932 #define CRYPTO_BC_CTL_BC_ENABLE_SHIFT (0U) 9933 #define CRYPTO_BC_CTL_BC_ENABLE_MASK (0x1U << CRYPTO_BC_CTL_BC_ENABLE_SHIFT) 9934 #define CRYPTO_BC_CTL_DECRYPT_SHIFT (1U) 9935 #define CRYPTO_BC_CTL_DECRYPT_MASK (0x1U << CRYPTO_BC_CTL_DECRYPT_SHIFT) 9936 #define CRYPTO_BC_CTL_KEY_SIZE_SHIFT (2U) 9937 #define CRYPTO_BC_CTL_KEY_SIZE_MASK (0x3U << CRYPTO_BC_CTL_KEY_SIZE_SHIFT) 9938 #define CRYPTO_BC_CTL_MODE_SHIFT (4U) 9939 #define CRYPTO_BC_CTL_MODE_MASK (0xFU << CRYPTO_BC_CTL_MODE_SHIFT) 9940 #define CRYPTO_BC_CTL_BC_CIPHER_SEL_SHIFT (8U) 9941 #define CRYPTO_BC_CTL_BC_CIPHER_SEL_MASK (0x3U << CRYPTO_BC_CTL_BC_CIPHER_SEL_SHIFT) 9942 /* HASH_CTL */ 9943 #define CRYPTO_HASH_CTL_OFFSET (0x48U) 9944 #define CRYPTO_HASH_CTL_HASH_ENABLE_SHIFT (0U) 9945 #define CRYPTO_HASH_CTL_HASH_ENABLE_MASK (0x1U << CRYPTO_HASH_CTL_HASH_ENABLE_SHIFT) 9946 #define CRYPTO_HASH_CTL_HASH_SRC_SEL_SHIFT (1U) 9947 #define CRYPTO_HASH_CTL_HASH_SRC_SEL_MASK (0x1U << CRYPTO_HASH_CTL_HASH_SRC_SEL_SHIFT) 9948 #define CRYPTO_HASH_CTL_HW_PAD_ENABLE_SHIFT (2U) 9949 #define CRYPTO_HASH_CTL_HW_PAD_ENABLE_MASK (0x1U << CRYPTO_HASH_CTL_HW_PAD_ENABLE_SHIFT) 9950 #define CRYPTO_HASH_CTL_HMAC_ENABLE_SHIFT (3U) 9951 #define CRYPTO_HASH_CTL_HMAC_ENABLE_MASK (0x1U << CRYPTO_HASH_CTL_HMAC_ENABLE_SHIFT) 9952 #define CRYPTO_HASH_CTL_HASH_CIPHER_SEL_SHIFT (4U) 9953 #define CRYPTO_HASH_CTL_HASH_CIPHER_SEL_MASK (0xFU << CRYPTO_HASH_CTL_HASH_CIPHER_SEL_SHIFT) 9954 /* CIPHER_ST */ 9955 #define CRYPTO_CIPHER_ST_OFFSET (0x4CU) 9956 #define CRYPTO_CIPHER_ST (0x0U) 9957 #define CRYPTO_CIPHER_ST_BLOCK_CIPHER_BUSY_SHIFT (0U) 9958 #define CRYPTO_CIPHER_ST_BLOCK_CIPHER_BUSY_MASK (0x1U << CRYPTO_CIPHER_ST_BLOCK_CIPHER_BUSY_SHIFT) 9959 #define CRYPTO_CIPHER_ST_HASH_BUSY_SHIFT (1U) 9960 #define CRYPTO_CIPHER_ST_HASH_BUSY_MASK (0x1U << CRYPTO_CIPHER_ST_HASH_BUSY_SHIFT) 9961 #define CRYPTO_CIPHER_ST_OTP_KEY_VALID_SHIFT (2U) 9962 #define CRYPTO_CIPHER_ST_OTP_KEY_VALID_MASK (0x1U << CRYPTO_CIPHER_ST_OTP_KEY_VALID_SHIFT) 9963 /* CIPHER_STATE */ 9964 #define CRYPTO_CIPHER_STATE_OFFSET (0x50U) 9965 #define CRYPTO_CIPHER_STATE_SERIAL_STATE_SHIFT (0U) 9966 #define CRYPTO_CIPHER_STATE_SERIAL_STATE_MASK (0x3U << CRYPTO_CIPHER_STATE_SERIAL_STATE_SHIFT) 9967 #define CRYPTO_CIPHER_STATE_MAC_STATE_SHIFT (2U) 9968 #define CRYPTO_CIPHER_STATE_MAC_STATE_MASK (0x3U << CRYPTO_CIPHER_STATE_MAC_STATE_SHIFT) 9969 #define CRYPTO_CIPHER_STATE_PARALLEL_STATE_SHIFT (4U) 9970 #define CRYPTO_CIPHER_STATE_PARALLEL_STATE_MASK (0x3U << CRYPTO_CIPHER_STATE_PARALLEL_STATE_SHIFT) 9971 #define CRYPTO_CIPHER_STATE_CCM_STATE_SHIFT (6U) 9972 #define CRYPTO_CIPHER_STATE_CCM_STATE_MASK (0x3U << CRYPTO_CIPHER_STATE_CCM_STATE_SHIFT) 9973 #define CRYPTO_CIPHER_STATE_GCM_STATE_SHIFT (8U) 9974 #define CRYPTO_CIPHER_STATE_GCM_STATE_MASK (0x3U << CRYPTO_CIPHER_STATE_GCM_STATE_SHIFT) 9975 #define CRYPTO_CIPHER_STATE_HASH_STATE_SHIFT (10U) 9976 #define CRYPTO_CIPHER_STATE_HASH_STATE_MASK (0x1FU << CRYPTO_CIPHER_STATE_HASH_STATE_SHIFT) 9977 /* CHN_IV_0 */ 9978 #define CRYPTO_CHN_IV_0_OFFSET (0x100U) 9979 #define CRYPTO_CHN_IV_0_CHN_IV_0_SHIFT (0U) 9980 #define CRYPTO_CHN_IV_0_CHN_IV_0_MASK (0xFFFFFFFFU << CRYPTO_CHN_IV_0_CHN_IV_0_SHIFT) 9981 /* CHN_IV_1 */ 9982 #define CRYPTO_CHN_IV_1_OFFSET (0x104U) 9983 #define CRYPTO_CHN_IV_1_CHN_IV_1_SHIFT (0U) 9984 #define CRYPTO_CHN_IV_1_CHN_IV_1_MASK (0xFFFFFFFFU << CRYPTO_CHN_IV_1_CHN_IV_1_SHIFT) 9985 /* CHN_IV_2 */ 9986 #define CRYPTO_CHN_IV_2_OFFSET (0x108U) 9987 #define CRYPTO_CHN_IV_2_CHN_IV_2_SHIFT (0U) 9988 #define CRYPTO_CHN_IV_2_CHN_IV_2_MASK (0xFFFFFFFFU << CRYPTO_CHN_IV_2_CHN_IV_2_SHIFT) 9989 /* CHN_IV_3 */ 9990 #define CRYPTO_CHN_IV_3_OFFSET (0x10CU) 9991 #define CRYPTO_CHN_IV_3_CHN_IV_3_SHIFT (0U) 9992 #define CRYPTO_CHN_IV_3_CHN_IV_3_MASK (0xFFFFFFFFU << CRYPTO_CHN_IV_3_CHN_IV_3_SHIFT) 9993 /* CHN_KEY_0 */ 9994 #define CRYPTO_CHN_KEY_0_OFFSET (0x180U) 9995 #define CRYPTO_CHN_KEY_0_CHN_KEY_0_SHIFT (0U) 9996 #define CRYPTO_CHN_KEY_0_CHN_KEY_0_MASK (0xFFFFFFFFU << CRYPTO_CHN_KEY_0_CHN_KEY_0_SHIFT) 9997 /* CHN_KEY_1 */ 9998 #define CRYPTO_CHN_KEY_1_OFFSET (0x184U) 9999 #define CRYPTO_CHN_KEY_1_CHN_KEY_1_SHIFT (0U) 10000 #define CRYPTO_CHN_KEY_1_CHN_KEY_1_MASK (0xFFFFFFFFU << CRYPTO_CHN_KEY_1_CHN_KEY_1_SHIFT) 10001 /* CHN_KEY_2 */ 10002 #define CRYPTO_CHN_KEY_2_OFFSET (0x188U) 10003 #define CRYPTO_CHN_KEY_2_CHN_KEY_2_SHIFT (0U) 10004 #define CRYPTO_CHN_KEY_2_CHN_KEY_2_MASK (0xFFFFFFFFU << CRYPTO_CHN_KEY_2_CHN_KEY_2_SHIFT) 10005 /* CHN_KEY_3 */ 10006 #define CRYPTO_CHN_KEY_3_OFFSET (0x18CU) 10007 #define CRYPTO_CHN_KEY_3_CHN_KEY_3_SHIFT (0U) 10008 #define CRYPTO_CHN_KEY_3_CHN_KEY_3_MASK (0xFFFFFFFFU << CRYPTO_CHN_KEY_3_CHN_KEY_3_SHIFT) 10009 /* CHN_PKEY_0 */ 10010 #define CRYPTO_CHN_PKEY_0_OFFSET (0x200U) 10011 #define CRYPTO_CHN_PKEY_0_CHN_PKEY_0_SHIFT (0U) 10012 #define CRYPTO_CHN_PKEY_0_CHN_PKEY_0_MASK (0xFFFFFFFFU << CRYPTO_CHN_PKEY_0_CHN_PKEY_0_SHIFT) 10013 /* CHN_PKEY_1 */ 10014 #define CRYPTO_CHN_PKEY_1_OFFSET (0x204U) 10015 #define CRYPTO_CHN_PKEY_1_CHN_PKEY_1_SHIFT (0U) 10016 #define CRYPTO_CHN_PKEY_1_CHN_PKEY_1_MASK (0xFFFFFFFFU << CRYPTO_CHN_PKEY_1_CHN_PKEY_1_SHIFT) 10017 /* CHN_PKEY_2 */ 10018 #define CRYPTO_CHN_PKEY_2_OFFSET (0x208U) 10019 #define CRYPTO_CHN_PKEY_2_CHN_PKEY_2_SHIFT (0U) 10020 #define CRYPTO_CHN_PKEY_2_CHN_PKEY_2_MASK (0xFFFFFFFFU << CRYPTO_CHN_PKEY_2_CHN_PKEY_2_SHIFT) 10021 /* CHN_PKEY_3 */ 10022 #define CRYPTO_CHN_PKEY_3_OFFSET (0x20CU) 10023 #define CRYPTO_CHN_PKEY_3_CHN_KEY_3_SHIFT (0U) 10024 #define CRYPTO_CHN_PKEY_3_CHN_KEY_3_MASK (0xFFFFFFFFU << CRYPTO_CHN_PKEY_3_CHN_KEY_3_SHIFT) 10025 /* CHN_PC_LEN_0 */ 10026 #define CRYPTO_CHN_PC_LEN_0_OFFSET (0x280U) 10027 #define CRYPTO_CHN_PC_LEN_0_CHN_PC_LEN_0_SHIFT (0U) 10028 #define CRYPTO_CHN_PC_LEN_0_CHN_PC_LEN_0_MASK (0xFFFFFFFFU << CRYPTO_CHN_PC_LEN_0_CHN_PC_LEN_0_SHIFT) 10029 /* CHN_PC_LEN_1 */ 10030 #define CRYPTO_CHN_PC_LEN_1_OFFSET (0x284U) 10031 #define CRYPTO_CHN_PC_LEN_1_CHN_PC_LEN_1_SHIFT (0U) 10032 #define CRYPTO_CHN_PC_LEN_1_CHN_PC_LEN_1_MASK (0x1FFFFFFFU << CRYPTO_CHN_PC_LEN_1_CHN_PC_LEN_1_SHIFT) 10033 /* CHN_ADA_LEN_0 */ 10034 #define CRYPTO_CHN_ADA_LEN_0_OFFSET (0x2C0U) 10035 #define CRYPTO_CHN_ADA_LEN_0_CHN_ADA_LEN_0_SHIFT (0U) 10036 #define CRYPTO_CHN_ADA_LEN_0_CHN_ADA_LEN_0_MASK (0xFFFFFFFFU << CRYPTO_CHN_ADA_LEN_0_CHN_ADA_LEN_0_SHIFT) 10037 /* CHN_ADA_LEN_1 */ 10038 #define CRYPTO_CHN_ADA_LEN_1_OFFSET (0x2C4U) 10039 #define CRYPTO_CHN_ADA_LEN_1_CHN_ADA_LEN_1_SHIFT (0U) 10040 #define CRYPTO_CHN_ADA_LEN_1_CHN_ADA_LEN_1_MASK (0x1FFFFFFFU << CRYPTO_CHN_ADA_LEN_1_CHN_ADA_LEN_1_SHIFT) 10041 /* CHN_IV_LEN_0 */ 10042 #define CRYPTO_CHN_IV_LEN_0_OFFSET (0x300U) 10043 #define CRYPTO_CHN_IV_LEN_0_CHN_IV_LEN_SHIFT (0U) 10044 #define CRYPTO_CHN_IV_LEN_0_CHN_IV_LEN_MASK (0x1FU << CRYPTO_CHN_IV_LEN_0_CHN_IV_LEN_SHIFT) 10045 /* CHN_TAG_0 */ 10046 #define CRYPTO_CHN_TAG_0_OFFSET (0x320U) 10047 #define CRYPTO_CHN_TAG_0 (0x0U) 10048 #define CRYPTO_CHN_TAG_0_CHN_TAG_0_SHIFT (0U) 10049 #define CRYPTO_CHN_TAG_0_CHN_TAG_0_MASK (0xFFFFFFFFU << CRYPTO_CHN_TAG_0_CHN_TAG_0_SHIFT) 10050 /* CHN_TAG_1 */ 10051 #define CRYPTO_CHN_TAG_1_OFFSET (0x324U) 10052 #define CRYPTO_CHN_TAG_1 (0x0U) 10053 #define CRYPTO_CHN_TAG_1_CHN_TAG_1_SHIFT (0U) 10054 #define CRYPTO_CHN_TAG_1_CHN_TAG_1_MASK (0xFFFFFFFFU << CRYPTO_CHN_TAG_1_CHN_TAG_1_SHIFT) 10055 /* CHN_TAG_2 */ 10056 #define CRYPTO_CHN_TAG_2_OFFSET (0x328U) 10057 #define CRYPTO_CHN_TAG_2 (0x0U) 10058 #define CRYPTO_CHN_TAG_2_CHN_TAG_2_SHIFT (0U) 10059 #define CRYPTO_CHN_TAG_2_CHN_TAG_2_MASK (0xFFFFFFFFU << CRYPTO_CHN_TAG_2_CHN_TAG_2_SHIFT) 10060 /* CHN_TAG_3 */ 10061 #define CRYPTO_CHN_TAG_3_OFFSET (0x32CU) 10062 #define CRYPTO_CHN_TAG_3 (0x0U) 10063 #define CRYPTO_CHN_TAG_3_CHN_TAG_3_SHIFT (0U) 10064 #define CRYPTO_CHN_TAG_3_CHN_TAG_3_MASK (0xFFFFFFFFU << CRYPTO_CHN_TAG_3_CHN_TAG_3_SHIFT) 10065 /* HASH_DOUT_0 */ 10066 #define CRYPTO_HASH_DOUT_0_OFFSET (0x3A0U) 10067 #define CRYPTO_HASH_DOUT_0 (0x0U) 10068 #define CRYPTO_HASH_DOUT_0_HASH_DOUT_0_SHIFT (0U) 10069 #define CRYPTO_HASH_DOUT_0_HASH_DOUT_0_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_0_HASH_DOUT_0_SHIFT) 10070 /* HASH_DOUT_1 */ 10071 #define CRYPTO_HASH_DOUT_1_OFFSET (0x3A4U) 10072 #define CRYPTO_HASH_DOUT_1 (0x0U) 10073 #define CRYPTO_HASH_DOUT_1_HASH_DOUT_1_SHIFT (0U) 10074 #define CRYPTO_HASH_DOUT_1_HASH_DOUT_1_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_1_HASH_DOUT_1_SHIFT) 10075 /* HASH_DOUT_2 */ 10076 #define CRYPTO_HASH_DOUT_2_OFFSET (0x3A8U) 10077 #define CRYPTO_HASH_DOUT_2 (0x0U) 10078 #define CRYPTO_HASH_DOUT_2_HASH_DOUT_2_SHIFT (0U) 10079 #define CRYPTO_HASH_DOUT_2_HASH_DOUT_2_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_2_HASH_DOUT_2_SHIFT) 10080 /* HASH_DOUT_3 */ 10081 #define CRYPTO_HASH_DOUT_3_OFFSET (0x3ACU) 10082 #define CRYPTO_HASH_DOUT_3 (0x0U) 10083 #define CRYPTO_HASH_DOUT_3_HASH_DOUT_3_SHIFT (0U) 10084 #define CRYPTO_HASH_DOUT_3_HASH_DOUT_3_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_3_HASH_DOUT_3_SHIFT) 10085 /* HASH_DOUT_4 */ 10086 #define CRYPTO_HASH_DOUT_4_OFFSET (0x3B0U) 10087 #define CRYPTO_HASH_DOUT_4 (0x0U) 10088 #define CRYPTO_HASH_DOUT_4_HASH_DOUT_4_SHIFT (0U) 10089 #define CRYPTO_HASH_DOUT_4_HASH_DOUT_4_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_4_HASH_DOUT_4_SHIFT) 10090 /* HASH_DOUT_5 */ 10091 #define CRYPTO_HASH_DOUT_5_OFFSET (0x3B4U) 10092 #define CRYPTO_HASH_DOUT_5 (0x0U) 10093 #define CRYPTO_HASH_DOUT_5_HASH_DOUT_5_SHIFT (0U) 10094 #define CRYPTO_HASH_DOUT_5_HASH_DOUT_5_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_5_HASH_DOUT_5_SHIFT) 10095 /* HASH_DOUT_6 */ 10096 #define CRYPTO_HASH_DOUT_6_OFFSET (0x3B8U) 10097 #define CRYPTO_HASH_DOUT_6 (0x0U) 10098 #define CRYPTO_HASH_DOUT_6_HASH_DOUT_6_SHIFT (0U) 10099 #define CRYPTO_HASH_DOUT_6_HASH_DOUT_6_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_6_HASH_DOUT_6_SHIFT) 10100 /* HASH_DOUT_7 */ 10101 #define CRYPTO_HASH_DOUT_7_OFFSET (0x3BCU) 10102 #define CRYPTO_HASH_DOUT_7 (0x0U) 10103 #define CRYPTO_HASH_DOUT_7_HASH_DOUT_7_SHIFT (0U) 10104 #define CRYPTO_HASH_DOUT_7_HASH_DOUT_7_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_7_HASH_DOUT_7_SHIFT) 10105 /* HASH_DOUT_8 */ 10106 #define CRYPTO_HASH_DOUT_8_OFFSET (0x3C0U) 10107 #define CRYPTO_HASH_DOUT_8 (0x0U) 10108 #define CRYPTO_HASH_DOUT_8_HASH_DOUT_8_SHIFT (0U) 10109 #define CRYPTO_HASH_DOUT_8_HASH_DOUT_8_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_8_HASH_DOUT_8_SHIFT) 10110 /* HASH_DOUT_9 */ 10111 #define CRYPTO_HASH_DOUT_9_OFFSET (0x3C4U) 10112 #define CRYPTO_HASH_DOUT_9 (0x0U) 10113 #define CRYPTO_HASH_DOUT_9_HASH_DOUT_9_SHIFT (0U) 10114 #define CRYPTO_HASH_DOUT_9_HASH_DOUT_9_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_9_HASH_DOUT_9_SHIFT) 10115 /* HASH_DOUT_10 */ 10116 #define CRYPTO_HASH_DOUT_10_OFFSET (0x3C8U) 10117 #define CRYPTO_HASH_DOUT_10 (0x0U) 10118 #define CRYPTO_HASH_DOUT_10_HASH_DOUT_10_SHIFT (0U) 10119 #define CRYPTO_HASH_DOUT_10_HASH_DOUT_10_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_10_HASH_DOUT_10_SHIFT) 10120 /* HASH_DOUT_11 */ 10121 #define CRYPTO_HASH_DOUT_11_OFFSET (0x3CCU) 10122 #define CRYPTO_HASH_DOUT_11 (0x0U) 10123 #define CRYPTO_HASH_DOUT_11_HASH_DOUT_11_SHIFT (0U) 10124 #define CRYPTO_HASH_DOUT_11_HASH_DOUT_11_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_11_HASH_DOUT_11_SHIFT) 10125 /* HASH_DOUT_12 */ 10126 #define CRYPTO_HASH_DOUT_12_OFFSET (0x3D0U) 10127 #define CRYPTO_HASH_DOUT_12 (0x0U) 10128 #define CRYPTO_HASH_DOUT_12_HASH_DOUT_12_SHIFT (0U) 10129 #define CRYPTO_HASH_DOUT_12_HASH_DOUT_12_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_12_HASH_DOUT_12_SHIFT) 10130 /* HASH_DOUT_13 */ 10131 #define CRYPTO_HASH_DOUT_13_OFFSET (0x3D4U) 10132 #define CRYPTO_HASH_DOUT_13 (0x0U) 10133 #define CRYPTO_HASH_DOUT_13_HASH_DOUT_13_SHIFT (0U) 10134 #define CRYPTO_HASH_DOUT_13_HASH_DOUT_13_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_13_HASH_DOUT_13_SHIFT) 10135 /* HASH_DOUT_14 */ 10136 #define CRYPTO_HASH_DOUT_14_OFFSET (0x3D8U) 10137 #define CRYPTO_HASH_DOUT_14 (0x0U) 10138 #define CRYPTO_HASH_DOUT_14_HASH_DOUT_14_SHIFT (0U) 10139 #define CRYPTO_HASH_DOUT_14_HASH_DOUT_14_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_14_HASH_DOUT_14_SHIFT) 10140 /* HASH_DOUT_15 */ 10141 #define CRYPTO_HASH_DOUT_15_OFFSET (0x3DCU) 10142 #define CRYPTO_HASH_DOUT_15 (0x0U) 10143 #define CRYPTO_HASH_DOUT_15_HASH_DOUT_15_SHIFT (0U) 10144 #define CRYPTO_HASH_DOUT_15_HASH_DOUT_15_MASK (0xFFFFFFFFU << CRYPTO_HASH_DOUT_15_HASH_DOUT_15_SHIFT) 10145 /* TAG_VALID */ 10146 #define CRYPTO_TAG_VALID_OFFSET (0x3E0U) 10147 #define CRYPTO_TAG_VALID_CH0_TAG_VALID_SHIFT (0U) 10148 #define CRYPTO_TAG_VALID_CH0_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH0_TAG_VALID_SHIFT) 10149 #define CRYPTO_TAG_VALID_CH1_TAG_VALID_SHIFT (1U) 10150 #define CRYPTO_TAG_VALID_CH1_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH1_TAG_VALID_SHIFT) 10151 #define CRYPTO_TAG_VALID_CH2_TAG_VALID_SHIFT (2U) 10152 #define CRYPTO_TAG_VALID_CH2_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH2_TAG_VALID_SHIFT) 10153 #define CRYPTO_TAG_VALID_CH3_TAG_VALID_SHIFT (3U) 10154 #define CRYPTO_TAG_VALID_CH3_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH3_TAG_VALID_SHIFT) 10155 #define CRYPTO_TAG_VALID_CH4_TAG_VALID_SHIFT (4U) 10156 #define CRYPTO_TAG_VALID_CH4_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH4_TAG_VALID_SHIFT) 10157 #define CRYPTO_TAG_VALID_CH5_TAG_VALID_SHIFT (5U) 10158 #define CRYPTO_TAG_VALID_CH5_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH5_TAG_VALID_SHIFT) 10159 #define CRYPTO_TAG_VALID_CH6_TAG_VALID_SHIFT (6U) 10160 #define CRYPTO_TAG_VALID_CH6_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH6_TAG_VALID_SHIFT) 10161 #define CRYPTO_TAG_VALID_CH7_TAG_VALID_SHIFT (7U) 10162 #define CRYPTO_TAG_VALID_CH7_TAG_VALID_MASK (0x1U << CRYPTO_TAG_VALID_CH7_TAG_VALID_SHIFT) 10163 /* HASH_VALID */ 10164 #define CRYPTO_HASH_VALID_OFFSET (0x3E4U) 10165 #define CRYPTO_HASH_VALID_HASH_VALID_SHIFT (0U) 10166 #define CRYPTO_HASH_VALID_HASH_VALID_MASK (0x1U << CRYPTO_HASH_VALID_HASH_VALID_SHIFT) 10167 /* VERSION */ 10168 #define CRYPTO_VERSION_OFFSET (0x3F0U) 10169 #define CRYPTO_VERSION_VERSION_NUM_SHIFT (0U) 10170 #define CRYPTO_VERSION_VERSION_NUM_MASK (0xFFFFFFFFU << CRYPTO_VERSION_VERSION_NUM_SHIFT) 10171 /* RNG_CTL */ 10172 #define CRYPTO_RNG_CTL_OFFSET (0x400U) 10173 #define CRYPTO_RNG_CTL_RNG_START_SHIFT (0U) 10174 #define CRYPTO_RNG_CTL_RNG_START_MASK (0x1U << CRYPTO_RNG_CTL_RNG_START_SHIFT) 10175 #define CRYPTO_RNG_CTL_RNG_ENABLE_SHIFT (1U) 10176 #define CRYPTO_RNG_CTL_RNG_ENABLE_MASK (0x1U << CRYPTO_RNG_CTL_RNG_ENABLE_SHIFT) 10177 #define CRYPTO_RNG_CTL_RING_SEL_SHIFT (2U) 10178 #define CRYPTO_RNG_CTL_RING_SEL_MASK (0x3U << CRYPTO_RNG_CTL_RING_SEL_SHIFT) 10179 #define CRYPTO_RNG_CTL_RNG_LEN_SHIFT (4U) 10180 #define CRYPTO_RNG_CTL_RNG_LEN_MASK (0x3U << CRYPTO_RNG_CTL_RNG_LEN_SHIFT) 10181 /* RNG_SAMPLE_CNT */ 10182 #define CRYPTO_RNG_SAMPLE_CNT_OFFSET (0x404U) 10183 #define CRYPTO_RNG_SAMPLE_CNT_RNG_SAMPLE_CNT_SHIFT (0U) 10184 #define CRYPTO_RNG_SAMPLE_CNT_RNG_SAMPLE_CNT_MASK (0xFFFFU << CRYPTO_RNG_SAMPLE_CNT_RNG_SAMPLE_CNT_SHIFT) 10185 /* RNG_DOUT_0 */ 10186 #define CRYPTO_RNG_DOUT_0_OFFSET (0x410U) 10187 #define CRYPTO_RNG_DOUT_0 (0x0U) 10188 #define CRYPTO_RNG_DOUT_0_RNG_DOUT_0_SHIFT (0U) 10189 #define CRYPTO_RNG_DOUT_0_RNG_DOUT_0_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_0_RNG_DOUT_0_SHIFT) 10190 /* RNG_DOUT_1 */ 10191 #define CRYPTO_RNG_DOUT_1_OFFSET (0x414U) 10192 #define CRYPTO_RNG_DOUT_1 (0x0U) 10193 #define CRYPTO_RNG_DOUT_1_RNG_DOUT_1_SHIFT (0U) 10194 #define CRYPTO_RNG_DOUT_1_RNG_DOUT_1_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_1_RNG_DOUT_1_SHIFT) 10195 /* RNG_DOUT_2 */ 10196 #define CRYPTO_RNG_DOUT_2_OFFSET (0x418U) 10197 #define CRYPTO_RNG_DOUT_2 (0x0U) 10198 #define CRYPTO_RNG_DOUT_2_RNG_DOUT_2_SHIFT (0U) 10199 #define CRYPTO_RNG_DOUT_2_RNG_DOUT_2_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_2_RNG_DOUT_2_SHIFT) 10200 /* RNG_DOUT_3 */ 10201 #define CRYPTO_RNG_DOUT_3_OFFSET (0x41CU) 10202 #define CRYPTO_RNG_DOUT_3 (0x0U) 10203 #define CRYPTO_RNG_DOUT_3_RNG_DOUT_3_SHIFT (0U) 10204 #define CRYPTO_RNG_DOUT_3_RNG_DOUT_3_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_3_RNG_DOUT_3_SHIFT) 10205 /* RNG_DOUT_4 */ 10206 #define CRYPTO_RNG_DOUT_4_OFFSET (0x420U) 10207 #define CRYPTO_RNG_DOUT_4 (0x0U) 10208 #define CRYPTO_RNG_DOUT_4_RNG_DOUT_4_SHIFT (0U) 10209 #define CRYPTO_RNG_DOUT_4_RNG_DOUT_4_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_4_RNG_DOUT_4_SHIFT) 10210 /* RNG_DOUT_5 */ 10211 #define CRYPTO_RNG_DOUT_5_OFFSET (0x424U) 10212 #define CRYPTO_RNG_DOUT_5 (0x0U) 10213 #define CRYPTO_RNG_DOUT_5_RNG_DOUT_5_SHIFT (0U) 10214 #define CRYPTO_RNG_DOUT_5_RNG_DOUT_5_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_5_RNG_DOUT_5_SHIFT) 10215 /* RNG_DOUT_6 */ 10216 #define CRYPTO_RNG_DOUT_6_OFFSET (0x428U) 10217 #define CRYPTO_RNG_DOUT_6_RNG_DOUT_6_SHIFT (0U) 10218 #define CRYPTO_RNG_DOUT_6_RNG_DOUT_6_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_6_RNG_DOUT_6_SHIFT) 10219 /* RNG_DOUT_7 */ 10220 #define CRYPTO_RNG_DOUT_7_OFFSET (0x42CU) 10221 #define CRYPTO_RNG_DOUT_7_RNG_DOUT_7_SHIFT (0U) 10222 #define CRYPTO_RNG_DOUT_7_RNG_DOUT_7_MASK (0xFFFFFFFFU << CRYPTO_RNG_DOUT_7_RNG_DOUT_7_SHIFT) 10223 /* RAM_CTL */ 10224 #define CRYPTO_RAM_CTL_OFFSET (0x480U) 10225 #define CRYPTO_RAM_CTL_RAM_PKA_RDY_SHIFT (0U) 10226 #define CRYPTO_RAM_CTL_RAM_PKA_RDY_MASK (0x1U << CRYPTO_RAM_CTL_RAM_PKA_RDY_SHIFT) 10227 /* RAM_ST */ 10228 #define CRYPTO_RAM_ST_OFFSET (0x484U) 10229 #define CRYPTO_RAM_ST (0x1U) 10230 #define CRYPTO_RAM_ST_CLK_RAM_RDY_SHIFT (0U) 10231 #define CRYPTO_RAM_ST_CLK_RAM_RDY_MASK (0x1U << CRYPTO_RAM_ST_CLK_RAM_RDY_SHIFT) 10232 /* DEBUG_CTL */ 10233 #define CRYPTO_DEBUG_CTL_OFFSET (0x4A0U) 10234 #define CRYPTO_DEBUG_CTL_PKA_DEBUG_MODE_SHIFT (0U) 10235 #define CRYPTO_DEBUG_CTL_PKA_DEBUG_MODE_MASK (0x1U << CRYPTO_DEBUG_CTL_PKA_DEBUG_MODE_SHIFT) 10236 /* DEBUG_ST */ 10237 #define CRYPTO_DEBUG_ST_OFFSET (0x4A4U) 10238 #define CRYPTO_DEBUG_ST (0x1U) 10239 #define CRYPTO_DEBUG_ST_PKA_DEBUG_CLK_EN_SHIFT (0U) 10240 #define CRYPTO_DEBUG_ST_PKA_DEBUG_CLK_EN_MASK (0x1U << CRYPTO_DEBUG_ST_PKA_DEBUG_CLK_EN_SHIFT) 10241 /* DEBUG_MONITOR */ 10242 #define CRYPTO_DEBUG_MONITOR_OFFSET (0x4A8U) 10243 #define CRYPTO_DEBUG_MONITOR_PKA_MONITOR_BUS_SHIFT (0U) 10244 #define CRYPTO_DEBUG_MONITOR_PKA_MONITOR_BUS_MASK (0xFFFFFFFFU << CRYPTO_DEBUG_MONITOR_PKA_MONITOR_BUS_SHIFT) 10245 /* PKA_MEM_MAP0 */ 10246 #define CRYPTO_PKA_MEM_MAP0_OFFSET (0x800U) 10247 #define CRYPTO_PKA_MEM_MAP0_MEMORY_MAP0_SHIFT (2U) 10248 #define CRYPTO_PKA_MEM_MAP0_MEMORY_MAP0_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP0_MEMORY_MAP0_SHIFT) 10249 /* PKA_MEM_MAP1 */ 10250 #define CRYPTO_PKA_MEM_MAP1_OFFSET (0x804U) 10251 #define CRYPTO_PKA_MEM_MAP1_MEMORY_MAP1_SHIFT (2U) 10252 #define CRYPTO_PKA_MEM_MAP1_MEMORY_MAP1_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP1_MEMORY_MAP1_SHIFT) 10253 /* PKA_MEM_MAP2 */ 10254 #define CRYPTO_PKA_MEM_MAP2_OFFSET (0x808U) 10255 #define CRYPTO_PKA_MEM_MAP2_MEMORY_MAP2_SHIFT (2U) 10256 #define CRYPTO_PKA_MEM_MAP2_MEMORY_MAP2_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP2_MEMORY_MAP2_SHIFT) 10257 /* PKA_MEM_MAP3 */ 10258 #define CRYPTO_PKA_MEM_MAP3_OFFSET (0x80CU) 10259 #define CRYPTO_PKA_MEM_MAP3_MEMORY_MAP3_SHIFT (2U) 10260 #define CRYPTO_PKA_MEM_MAP3_MEMORY_MAP3_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP3_MEMORY_MAP3_SHIFT) 10261 /* PKA_MEM_MAP4 */ 10262 #define CRYPTO_PKA_MEM_MAP4_OFFSET (0x810U) 10263 #define CRYPTO_PKA_MEM_MAP4_MEMORY_MAP4_SHIFT (2U) 10264 #define CRYPTO_PKA_MEM_MAP4_MEMORY_MAP4_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP4_MEMORY_MAP4_SHIFT) 10265 /* PKA_MEM_MAP5 */ 10266 #define CRYPTO_PKA_MEM_MAP5_OFFSET (0x814U) 10267 #define CRYPTO_PKA_MEM_MAP5_MEMORY_MAP5_SHIFT (2U) 10268 #define CRYPTO_PKA_MEM_MAP5_MEMORY_MAP5_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP5_MEMORY_MAP5_SHIFT) 10269 /* PKA_MEM_MAP6 */ 10270 #define CRYPTO_PKA_MEM_MAP6_OFFSET (0x818U) 10271 #define CRYPTO_PKA_MEM_MAP6_MEMORY_MAP6_SHIFT (2U) 10272 #define CRYPTO_PKA_MEM_MAP6_MEMORY_MAP6_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP6_MEMORY_MAP6_SHIFT) 10273 /* PKA_MEM_MAP7 */ 10274 #define CRYPTO_PKA_MEM_MAP7_OFFSET (0x81CU) 10275 #define CRYPTO_PKA_MEM_MAP7_MEMORY_MAP7_SHIFT (2U) 10276 #define CRYPTO_PKA_MEM_MAP7_MEMORY_MAP7_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP7_MEMORY_MAP7_SHIFT) 10277 /* PKA_MEM_MAP8 */ 10278 #define CRYPTO_PKA_MEM_MAP8_OFFSET (0x820U) 10279 #define CRYPTO_PKA_MEM_MAP8_MEMORY_MAP8_SHIFT (2U) 10280 #define CRYPTO_PKA_MEM_MAP8_MEMORY_MAP8_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP8_MEMORY_MAP8_SHIFT) 10281 /* PKA_MEM_MAP9 */ 10282 #define CRYPTO_PKA_MEM_MAP9_OFFSET (0x824U) 10283 #define CRYPTO_PKA_MEM_MAP9_MEMORY_MAP9_SHIFT (2U) 10284 #define CRYPTO_PKA_MEM_MAP9_MEMORY_MAP9_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP9_MEMORY_MAP9_SHIFT) 10285 /* PKA_MEM_MAP10 */ 10286 #define CRYPTO_PKA_MEM_MAP10_OFFSET (0x828U) 10287 #define CRYPTO_PKA_MEM_MAP10_MEMORY_MAP10_SHIFT (2U) 10288 #define CRYPTO_PKA_MEM_MAP10_MEMORY_MAP10_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP10_MEMORY_MAP10_SHIFT) 10289 /* PKA_MEM_MAP11 */ 10290 #define CRYPTO_PKA_MEM_MAP11_OFFSET (0x82CU) 10291 #define CRYPTO_PKA_MEM_MAP11_MEMORY_MAP11_SHIFT (2U) 10292 #define CRYPTO_PKA_MEM_MAP11_MEMORY_MAP11_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP11_MEMORY_MAP11_SHIFT) 10293 /* PKA_MEM_MAP12 */ 10294 #define CRYPTO_PKA_MEM_MAP12_OFFSET (0x830U) 10295 #define CRYPTO_PKA_MEM_MAP12_MEMORY_MAP12_SHIFT (2U) 10296 #define CRYPTO_PKA_MEM_MAP12_MEMORY_MAP12_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP12_MEMORY_MAP12_SHIFT) 10297 /* PKA_MEM_MAP13 */ 10298 #define CRYPTO_PKA_MEM_MAP13_OFFSET (0x834U) 10299 #define CRYPTO_PKA_MEM_MAP13_MEMORY_MAP13_SHIFT (2U) 10300 #define CRYPTO_PKA_MEM_MAP13_MEMORY_MAP13_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP13_MEMORY_MAP13_SHIFT) 10301 /* PKA_MEM_MAP14 */ 10302 #define CRYPTO_PKA_MEM_MAP14_OFFSET (0x838U) 10303 #define CRYPTO_PKA_MEM_MAP14_MEMORY_MAP14_SHIFT (2U) 10304 #define CRYPTO_PKA_MEM_MAP14_MEMORY_MAP14_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP14_MEMORY_MAP14_SHIFT) 10305 /* PKA_MEM_MAP15 */ 10306 #define CRYPTO_PKA_MEM_MAP15_OFFSET (0x83CU) 10307 #define CRYPTO_PKA_MEM_MAP15_MEMORY_MAP15_SHIFT (2U) 10308 #define CRYPTO_PKA_MEM_MAP15_MEMORY_MAP15_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP15_MEMORY_MAP15_SHIFT) 10309 /* PKA_MEM_MAP16 */ 10310 #define CRYPTO_PKA_MEM_MAP16_OFFSET (0x840U) 10311 #define CRYPTO_PKA_MEM_MAP16_MEMORY_MAP16_SHIFT (2U) 10312 #define CRYPTO_PKA_MEM_MAP16_MEMORY_MAP16_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP16_MEMORY_MAP16_SHIFT) 10313 /* PKA_MEM_MAP17 */ 10314 #define CRYPTO_PKA_MEM_MAP17_OFFSET (0x844U) 10315 #define CRYPTO_PKA_MEM_MAP17_MEMORY_MAP17_SHIFT (2U) 10316 #define CRYPTO_PKA_MEM_MAP17_MEMORY_MAP17_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP17_MEMORY_MAP17_SHIFT) 10317 /* PKA_MEM_MAP18 */ 10318 #define CRYPTO_PKA_MEM_MAP18_OFFSET (0x848U) 10319 #define CRYPTO_PKA_MEM_MAP18_MEMORY_MAP18_SHIFT (2U) 10320 #define CRYPTO_PKA_MEM_MAP18_MEMORY_MAP18_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP18_MEMORY_MAP18_SHIFT) 10321 /* PKA_MEM_MAP19 */ 10322 #define CRYPTO_PKA_MEM_MAP19_OFFSET (0x84CU) 10323 #define CRYPTO_PKA_MEM_MAP19_MEMORY_MAP19_SHIFT (2U) 10324 #define CRYPTO_PKA_MEM_MAP19_MEMORY_MAP19_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP19_MEMORY_MAP19_SHIFT) 10325 /* PKA_MEM_MAP20 */ 10326 #define CRYPTO_PKA_MEM_MAP20_OFFSET (0x850U) 10327 #define CRYPTO_PKA_MEM_MAP20_MEMORY_MAP20_SHIFT (2U) 10328 #define CRYPTO_PKA_MEM_MAP20_MEMORY_MAP20_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP20_MEMORY_MAP20_SHIFT) 10329 /* PKA_MEM_MAP21 */ 10330 #define CRYPTO_PKA_MEM_MAP21_OFFSET (0x854U) 10331 #define CRYPTO_PKA_MEM_MAP21_MEMORY_MAP21_SHIFT (2U) 10332 #define CRYPTO_PKA_MEM_MAP21_MEMORY_MAP21_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP21_MEMORY_MAP21_SHIFT) 10333 /* PKA_MEM_MAP22 */ 10334 #define CRYPTO_PKA_MEM_MAP22_OFFSET (0x858U) 10335 #define CRYPTO_PKA_MEM_MAP22_MEMORY_MAP22_SHIFT (2U) 10336 #define CRYPTO_PKA_MEM_MAP22_MEMORY_MAP22_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP22_MEMORY_MAP22_SHIFT) 10337 /* PKA_MEM_MAP23 */ 10338 #define CRYPTO_PKA_MEM_MAP23_OFFSET (0x85CU) 10339 #define CRYPTO_PKA_MEM_MAP23_MEMORY_MAP23_SHIFT (2U) 10340 #define CRYPTO_PKA_MEM_MAP23_MEMORY_MAP23_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP23_MEMORY_MAP23_SHIFT) 10341 /* PKA_MEM_MAP24 */ 10342 #define CRYPTO_PKA_MEM_MAP24_OFFSET (0x860U) 10343 #define CRYPTO_PKA_MEM_MAP24_MEMORY_MAP24_SHIFT (2U) 10344 #define CRYPTO_PKA_MEM_MAP24_MEMORY_MAP24_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP24_MEMORY_MAP24_SHIFT) 10345 /* PKA_MEM_MAP25 */ 10346 #define CRYPTO_PKA_MEM_MAP25_OFFSET (0x864U) 10347 #define CRYPTO_PKA_MEM_MAP25_MEMORY_MAP25_SHIFT (2U) 10348 #define CRYPTO_PKA_MEM_MAP25_MEMORY_MAP25_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP25_MEMORY_MAP25_SHIFT) 10349 /* PKA_MEM_MAP26 */ 10350 #define CRYPTO_PKA_MEM_MAP26_OFFSET (0x868U) 10351 #define CRYPTO_PKA_MEM_MAP26_MEMORY_MAP26_SHIFT (2U) 10352 #define CRYPTO_PKA_MEM_MAP26_MEMORY_MAP26_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP26_MEMORY_MAP26_SHIFT) 10353 /* PKA_MEM_MAP27 */ 10354 #define CRYPTO_PKA_MEM_MAP27_OFFSET (0x86CU) 10355 #define CRYPTO_PKA_MEM_MAP27_MEMORY_MAP27_SHIFT (2U) 10356 #define CRYPTO_PKA_MEM_MAP27_MEMORY_MAP27_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP27_MEMORY_MAP27_SHIFT) 10357 /* PKA_MEM_MAP28 */ 10358 #define CRYPTO_PKA_MEM_MAP28_OFFSET (0x870U) 10359 #define CRYPTO_PKA_MEM_MAP28_MEMORY_MAP28_SHIFT (2U) 10360 #define CRYPTO_PKA_MEM_MAP28_MEMORY_MAP28_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP28_MEMORY_MAP28_SHIFT) 10361 /* PKA_MEM_MAP29 */ 10362 #define CRYPTO_PKA_MEM_MAP29_OFFSET (0x874U) 10363 #define CRYPTO_PKA_MEM_MAP29_MEMORY_MAP29_SHIFT (2U) 10364 #define CRYPTO_PKA_MEM_MAP29_MEMORY_MAP29_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP29_MEMORY_MAP29_SHIFT) 10365 /* PKA_MEM_MAP30 */ 10366 #define CRYPTO_PKA_MEM_MAP30_OFFSET (0x878U) 10367 #define CRYPTO_PKA_MEM_MAP30_MEMORY_MAP30_SHIFT (2U) 10368 #define CRYPTO_PKA_MEM_MAP30_MEMORY_MAP30_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP30_MEMORY_MAP30_SHIFT) 10369 /* PKA_MEM_MAP31 */ 10370 #define CRYPTO_PKA_MEM_MAP31_OFFSET (0x87CU) 10371 #define CRYPTO_PKA_MEM_MAP31_MEMORY_MAP31_SHIFT (2U) 10372 #define CRYPTO_PKA_MEM_MAP31_MEMORY_MAP31_MASK (0x3FFU << CRYPTO_PKA_MEM_MAP31_MEMORY_MAP31_SHIFT) 10373 /* PKA_OPCODE */ 10374 #define CRYPTO_PKA_OPCODE_OFFSET (0x880U) 10375 #define CRYPTO_PKA_OPCODE_TAG_SHIFT (0U) 10376 #define CRYPTO_PKA_OPCODE_TAG_MASK (0x3FU << CRYPTO_PKA_OPCODE_TAG_SHIFT) 10377 #define CRYPTO_PKA_OPCODE_REG_R_SHIFT (6U) 10378 #define CRYPTO_PKA_OPCODE_REG_R_MASK (0x3FU << CRYPTO_PKA_OPCODE_REG_R_SHIFT) 10379 #define CRYPTO_PKA_OPCODE_REG_B_SHIFT (12U) 10380 #define CRYPTO_PKA_OPCODE_REG_B_MASK (0x3FU << CRYPTO_PKA_OPCODE_REG_B_SHIFT) 10381 #define CRYPTO_PKA_OPCODE_REG_A_SHIFT (18U) 10382 #define CRYPTO_PKA_OPCODE_REG_A_MASK (0x3FU << CRYPTO_PKA_OPCODE_REG_A_SHIFT) 10383 #define CRYPTO_PKA_OPCODE_LEN_SHIFT (24U) 10384 #define CRYPTO_PKA_OPCODE_LEN_MASK (0x7U << CRYPTO_PKA_OPCODE_LEN_SHIFT) 10385 #define CRYPTO_PKA_OPCODE_OPCODE_SHIFT (27U) 10386 #define CRYPTO_PKA_OPCODE_OPCODE_MASK (0x1FU << CRYPTO_PKA_OPCODE_OPCODE_SHIFT) 10387 /* N_NP_TO_T1_ADDR */ 10388 #define CRYPTO_N_NP_TO_T1_ADDR_OFFSET (0x884U) 10389 #define CRYPTO_N_NP_TO_T1_ADDR_REG_N_SHIFT (0U) 10390 #define CRYPTO_N_NP_TO_T1_ADDR_REG_N_MASK (0x1FU << CRYPTO_N_NP_TO_T1_ADDR_REG_N_SHIFT) 10391 #define CRYPTO_N_NP_TO_T1_ADDR_REG_NP_SHIFT (5U) 10392 #define CRYPTO_N_NP_TO_T1_ADDR_REG_NP_MASK (0x1FU << CRYPTO_N_NP_TO_T1_ADDR_REG_NP_SHIFT) 10393 #define CRYPTO_N_NP_TO_T1_ADDR_REG_T0_SHIFT (10U) 10394 #define CRYPTO_N_NP_TO_T1_ADDR_REG_T0_MASK (0x1FU << CRYPTO_N_NP_TO_T1_ADDR_REG_T0_SHIFT) 10395 #define CRYPTO_N_NP_TO_T1_ADDR_REG_T1_SHIFT (15U) 10396 #define CRYPTO_N_NP_TO_T1_ADDR_REG_T1_MASK (0x1FU << CRYPTO_N_NP_TO_T1_ADDR_REG_T1_SHIFT) 10397 /* PKA_STATUS */ 10398 #define CRYPTO_PKA_STATUS_OFFSET (0x888U) 10399 #define CRYPTO_PKA_STATUS (0x1U) 10400 #define CRYPTO_PKA_STATUS_PIPE_IS_BUSY_SHIFT (0U) 10401 #define CRYPTO_PKA_STATUS_PIPE_IS_BUSY_MASK (0x1U << CRYPTO_PKA_STATUS_PIPE_IS_BUSY_SHIFT) 10402 #define CRYPTO_PKA_STATUS_PKA_BUSY_SHIFT (1U) 10403 #define CRYPTO_PKA_STATUS_PKA_BUSY_MASK (0x1U << CRYPTO_PKA_STATUS_PKA_BUSY_SHIFT) 10404 #define CRYPTO_PKA_STATUS_ALU_OUT_ZERO_SHIFT (2U) 10405 #define CRYPTO_PKA_STATUS_ALU_OUT_ZERO_MASK (0x1U << CRYPTO_PKA_STATUS_ALU_OUT_ZERO_SHIFT) 10406 #define CRYPTO_PKA_STATUS_ALU_MOD_OVFLW_SHIFT (3U) 10407 #define CRYPTO_PKA_STATUS_ALU_MOD_OVFLW_MASK (0x1U << CRYPTO_PKA_STATUS_ALU_MOD_OVFLW_SHIFT) 10408 #define CRYPTO_PKA_STATUS_DIV_BY_ZERO_SHIFT (4U) 10409 #define CRYPTO_PKA_STATUS_DIV_BY_ZERO_MASK (0x1U << CRYPTO_PKA_STATUS_DIV_BY_ZERO_SHIFT) 10410 #define CRYPTO_PKA_STATUS_ALU_CARRY_SHIFT (5U) 10411 #define CRYPTO_PKA_STATUS_ALU_CARRY_MASK (0x1U << CRYPTO_PKA_STATUS_ALU_CARRY_SHIFT) 10412 #define CRYPTO_PKA_STATUS_ALU_SIGN_OUT_SHIFT (6U) 10413 #define CRYPTO_PKA_STATUS_ALU_SIGN_OUT_MASK (0x1U << CRYPTO_PKA_STATUS_ALU_SIGN_OUT_SHIFT) 10414 #define CRYPTO_PKA_STATUS_MODINV_OF_ZERO_SHIFT (7U) 10415 #define CRYPTO_PKA_STATUS_MODINV_OF_ZERO_MASK (0x1U << CRYPTO_PKA_STATUS_MODINV_OF_ZERO_SHIFT) 10416 #define CRYPTO_PKA_STATUS_PKA_CPU_BUSY_SHIFT (8U) 10417 #define CRYPTO_PKA_STATUS_PKA_CPU_BUSY_MASK (0x1U << CRYPTO_PKA_STATUS_PKA_CPU_BUSY_SHIFT) 10418 #define CRYPTO_PKA_STATUS_OPCODE_SHIFT (9U) 10419 #define CRYPTO_PKA_STATUS_OPCODE_MASK (0x1FU << CRYPTO_PKA_STATUS_OPCODE_SHIFT) 10420 #define CRYPTO_PKA_STATUS_TAG_SHIFT (14U) 10421 #define CRYPTO_PKA_STATUS_TAG_MASK (0x3FU << CRYPTO_PKA_STATUS_TAG_SHIFT) 10422 /* PKA_SW_RESET */ 10423 #define CRYPTO_PKA_SW_RESET_OFFSET (0x88CU) 10424 #define CRYPTO_PKA_SW_RESET_PKA_SW_RESET_SHIFT (0U) 10425 #define CRYPTO_PKA_SW_RESET_PKA_SW_RESET_MASK (0x1U << CRYPTO_PKA_SW_RESET_PKA_SW_RESET_SHIFT) 10426 /* PKA_L0 */ 10427 #define CRYPTO_PKA_L0_OFFSET (0x890U) 10428 #define CRYPTO_PKA_L0_PKA_L0_SHIFT (0U) 10429 #define CRYPTO_PKA_L0_PKA_L0_MASK (0x1FFFU << CRYPTO_PKA_L0_PKA_L0_SHIFT) 10430 /* PKA_L1 */ 10431 #define CRYPTO_PKA_L1_OFFSET (0x894U) 10432 #define CRYPTO_PKA_L1_PKA_L1_SHIFT (0U) 10433 #define CRYPTO_PKA_L1_PKA_L1_MASK (0x1FFFU << CRYPTO_PKA_L1_PKA_L1_SHIFT) 10434 /* PKA_L2 */ 10435 #define CRYPTO_PKA_L2_OFFSET (0x898U) 10436 #define CRYPTO_PKA_L2_PKA_L2_SHIFT (0U) 10437 #define CRYPTO_PKA_L2_PKA_L2_MASK (0x1FFFU << CRYPTO_PKA_L2_PKA_L2_SHIFT) 10438 /* PKA_L3 */ 10439 #define CRYPTO_PKA_L3_OFFSET (0x89CU) 10440 #define CRYPTO_PKA_L3_PKA_L3_SHIFT (0U) 10441 #define CRYPTO_PKA_L3_PKA_L3_MASK (0x1FFFU << CRYPTO_PKA_L3_PKA_L3_SHIFT) 10442 /* PKA_L4 */ 10443 #define CRYPTO_PKA_L4_OFFSET (0x8A0U) 10444 #define CRYPTO_PKA_L4_PKA_L4_SHIFT (0U) 10445 #define CRYPTO_PKA_L4_PKA_L4_MASK (0x1FFFU << CRYPTO_PKA_L4_PKA_L4_SHIFT) 10446 /* PKA_L5 */ 10447 #define CRYPTO_PKA_L5_OFFSET (0x8A4U) 10448 #define CRYPTO_PKA_L5_PKA_L5_SHIFT (0U) 10449 #define CRYPTO_PKA_L5_PKA_L5_MASK (0x1FFFU << CRYPTO_PKA_L5_PKA_L5_SHIFT) 10450 /* PKA_L6 */ 10451 #define CRYPTO_PKA_L6_OFFSET (0x8A8U) 10452 #define CRYPTO_PKA_L6_PKA_L6_SHIFT (0U) 10453 #define CRYPTO_PKA_L6_PKA_L6_MASK (0x1FFFU << CRYPTO_PKA_L6_PKA_L6_SHIFT) 10454 /* PKA_L7 */ 10455 #define CRYPTO_PKA_L7_OFFSET (0x8ACU) 10456 #define CRYPTO_PKA_L7_PKA_L7_SHIFT (0U) 10457 #define CRYPTO_PKA_L7_PKA_L7_MASK (0x1FFFU << CRYPTO_PKA_L7_PKA_L7_SHIFT) 10458 /* PKA_PIPE_RDY */ 10459 #define CRYPTO_PKA_PIPE_RDY_OFFSET (0x8B0U) 10460 #define CRYPTO_PKA_PIPE_RDY (0x1U) 10461 #define CRYPTO_PKA_PIPE_RDY_PKA_PIPE_RDY_SHIFT (0U) 10462 #define CRYPTO_PKA_PIPE_RDY_PKA_PIPE_RDY_MASK (0x1U << CRYPTO_PKA_PIPE_RDY_PKA_PIPE_RDY_SHIFT) 10463 /* PKA_DONE */ 10464 #define CRYPTO_PKA_DONE_OFFSET (0x8B4U) 10465 #define CRYPTO_PKA_DONE (0x1U) 10466 #define CRYPTO_PKA_DONE_PKA_DONE_SHIFT (0U) 10467 #define CRYPTO_PKA_DONE_PKA_DONE_MASK (0x1U << CRYPTO_PKA_DONE_PKA_DONE_SHIFT) 10468 /* PKA_MON_SELECT */ 10469 #define CRYPTO_PKA_MON_SELECT_OFFSET (0x8B8U) 10470 #define CRYPTO_PKA_MON_SELECT_PKA_MON_SELECT_SHIFT (0U) 10471 #define CRYPTO_PKA_MON_SELECT_PKA_MON_SELECT_MASK (0xFU << CRYPTO_PKA_MON_SELECT_PKA_MON_SELECT_SHIFT) 10472 /* PKA_DEBUG_REG_EN */ 10473 #define CRYPTO_PKA_DEBUG_REG_EN_OFFSET (0x8BCU) 10474 #define CRYPTO_PKA_DEBUG_REG_EN_PKA_DEBUG_REG_EN_SHIFT (0U) 10475 #define CRYPTO_PKA_DEBUG_REG_EN_PKA_DEBUG_REG_EN_MASK (0x1U << CRYPTO_PKA_DEBUG_REG_EN_PKA_DEBUG_REG_EN_SHIFT) 10476 /* DEBUG_CNT_ADDR */ 10477 #define CRYPTO_DEBUG_CNT_ADDR_OFFSET (0x8C0U) 10478 #define CRYPTO_DEBUG_CNT_ADDR_DEBUG_CNT_ADDR_SHIFT (0U) 10479 #define CRYPTO_DEBUG_CNT_ADDR_DEBUG_CNT_ADDR_MASK (0xFFFFFU << CRYPTO_DEBUG_CNT_ADDR_DEBUG_CNT_ADDR_SHIFT) 10480 /* DEBUG_EXT_ADDR */ 10481 #define CRYPTO_DEBUG_EXT_ADDR_OFFSET (0x8C4U) 10482 #define CRYPTO_DEBUG_EXT_ADDR_DEBUG_EXT_ADDR_SHIFT (0U) 10483 #define CRYPTO_DEBUG_EXT_ADDR_DEBUG_EXT_ADDR_MASK (0x1U << CRYPTO_DEBUG_EXT_ADDR_DEBUG_EXT_ADDR_SHIFT) 10484 /* PKA_DEBUG_HALT */ 10485 #define CRYPTO_PKA_DEBUG_HALT_OFFSET (0x8C8U) 10486 #define CRYPTO_PKA_DEBUG_HALT (0x0U) 10487 #define CRYPTO_PKA_DEBUG_HALT_PKA_DEBUG_HALT_SHIFT (0U) 10488 #define CRYPTO_PKA_DEBUG_HALT_PKA_DEBUG_HALT_MASK (0x1U << CRYPTO_PKA_DEBUG_HALT_PKA_DEBUG_HALT_SHIFT) 10489 /* PKA_MON_READ */ 10490 #define CRYPTO_PKA_MON_READ_OFFSET (0x8D0U) 10491 #define CRYPTO_PKA_MON_READ (0xFEEFU) 10492 #define CRYPTO_PKA_MON_READ_PKA_MON_READ_SHIFT (0U) 10493 #define CRYPTO_PKA_MON_READ_PKA_MON_READ_MASK (0xFFFFFFFFU << CRYPTO_PKA_MON_READ_PKA_MON_READ_SHIFT) 10494 /* PKA_INT_ENA */ 10495 #define CRYPTO_PKA_INT_ENA_OFFSET (0x8D4U) 10496 #define CRYPTO_PKA_INT_ENA_PKA_INT_ENA_SHIFT (0U) 10497 #define CRYPTO_PKA_INT_ENA_PKA_INT_ENA_MASK (0x1U << CRYPTO_PKA_INT_ENA_PKA_INT_ENA_SHIFT) 10498 /* PKA_INT_ST */ 10499 #define CRYPTO_PKA_INT_ST_OFFSET (0x8D8U) 10500 #define CRYPTO_PKA_INT_ST_PKA_INT_ST_SHIFT (0U) 10501 #define CRYPTO_PKA_INT_ST_PKA_INT_ST_MASK (0x1U << CRYPTO_PKA_INT_ST_PKA_INT_ST_SHIFT) 10502 /* SRAM_ADDR */ 10503 #define CRYPTO_SRAM_ADDR_OFFSET (0x1000U) 10504 #define CRYPTO_SRAM_ADDR_SRAM_ADDR_SHIFT (0U) 10505 #define CRYPTO_SRAM_ADDR_SRAM_ADDR_MASK (0xFFFFFFFFU << CRYPTO_SRAM_ADDR_SRAM_ADDR_SHIFT) 10506 /****************************************SPI2APB*****************************************/ 10507 /* CTRL0 */ 10508 #define SPI2APB_CTRL0_OFFSET (0x0U) 10509 #define SPI2APB_CTRL0_FBM_SHIFT (0U) 10510 #define SPI2APB_CTRL0_FBM_MASK (0x1U << SPI2APB_CTRL0_FBM_SHIFT) 10511 #define SPI2APB_CTRL0_EM_SHIFT (1U) 10512 #define SPI2APB_CTRL0_EM_MASK (0x1U << SPI2APB_CTRL0_EM_SHIFT) 10513 #define SPI2APB_CTRL0_RXCP_SHIFT (2U) 10514 #define SPI2APB_CTRL0_RXCP_MASK (0x1U << SPI2APB_CTRL0_RXCP_SHIFT) 10515 #define SPI2APB_CTRL0_TXCP_SHIFT (3U) 10516 #define SPI2APB_CTRL0_TXCP_MASK (0x1U << SPI2APB_CTRL0_TXCP_SHIFT) 10517 /* SR */ 10518 #define SPI2APB_SR_OFFSET (0x24U) 10519 #define SPI2APB_SR (0x0U) 10520 #define SPI2APB_SR_BSF_SHIFT (0U) 10521 #define SPI2APB_SR_BSF_MASK (0x1U << SPI2APB_SR_BSF_SHIFT) 10522 #define SPI2APB_SR_TFF_SHIFT (1U) 10523 #define SPI2APB_SR_TFF_MASK (0x1U << SPI2APB_SR_TFF_SHIFT) 10524 #define SPI2APB_SR_TFE_SHIFT (2U) 10525 #define SPI2APB_SR_TFE_MASK (0x1U << SPI2APB_SR_TFE_SHIFT) 10526 #define SPI2APB_SR_RFF_SHIFT (3U) 10527 #define SPI2APB_SR_RFF_MASK (0x1U << SPI2APB_SR_RFF_SHIFT) 10528 #define SPI2APB_SR_RFE_SHIFT (4U) 10529 #define SPI2APB_SR_RFE_MASK (0x1U << SPI2APB_SR_RFE_SHIFT) 10530 /* IMR */ 10531 #define SPI2APB_IMR_OFFSET (0x2CU) 10532 #define SPI2APB_IMR_QWIM_SHIFT (0U) 10533 #define SPI2APB_IMR_QWIM_MASK (0x1U << SPI2APB_IMR_QWIM_SHIFT) 10534 /* RISR */ 10535 #define SPI2APB_RISR_OFFSET (0x34U) 10536 #define SPI2APB_RISR_QWRIS_SHIFT (0U) 10537 #define SPI2APB_RISR_QWRIS_MASK (0x1U << SPI2APB_RISR_QWRIS_SHIFT) 10538 /* ICR */ 10539 #define SPI2APB_ICR_OFFSET (0x38U) 10540 #define SPI2APB_ICR_CQWI_SHIFT (0U) 10541 #define SPI2APB_ICR_CQWI_MASK (0x1U << SPI2APB_ICR_CQWI_SHIFT) 10542 /* VERSION */ 10543 #define SPI2APB_VERSION_OFFSET (0x48U) 10544 #define SPI2APB_VERSION_VERSION_SHIFT (0U) 10545 #define SPI2APB_VERSION_VERSION_MASK (0xFFFFFFFFU << SPI2APB_VERSION_VERSION_SHIFT) 10546 /* QUICK_REG0 */ 10547 #define SPI2APB_QUICK_REG0_OFFSET (0x50U) 10548 #define SPI2APB_QUICK_REG0_QWV0_SHIFT (0U) 10549 #define SPI2APB_QUICK_REG0_QWV0_MASK (0xFFFFFFFFU << SPI2APB_QUICK_REG0_QWV0_SHIFT) 10550 /* QUICK_REG1 */ 10551 #define SPI2APB_QUICK_REG1_OFFSET (0x54U) 10552 #define SPI2APB_QUICK_REG1_QWV1_SHIFT (0U) 10553 #define SPI2APB_QUICK_REG1_QWV1_MASK (0xFFFFFFFFU << SPI2APB_QUICK_REG1_QWV1_SHIFT) 10554 /* QUICK_REG2 */ 10555 #define SPI2APB_QUICK_REG2_OFFSET (0x58U) 10556 #define SPI2APB_QUICK_REG2_QRV_SHIFT (0U) 10557 #define SPI2APB_QUICK_REG2_QRV_MASK (0xFFFFFFFFU << SPI2APB_QUICK_REG2_QRV_SHIFT) 10558 10559 /****************************************************************************************/ 10560 /* */ 10561 /* Clock Description Section */ 10562 /* */ 10563 /****************************************************************************************/ 10564 /********Name=SOFTRST_CON00,Offset=0x400********/ 10565 #define SRST_H_MCU_BUS_AC 1U 10566 #define SRST_M4F0_AC 2U 10567 #define SRST_H_M4F0_AC 3U 10568 #define SRST_PO_M0_AC 4U 10569 #define SRST_H_M0_AC 5U 10570 #define SRST_DB_M0_AC 6U 10571 #define SRST_P_TOP_BUS_AC 7U 10572 #define SRST_P_CRU_AC 8U 10573 /********Name=SOFTRST_CON01,Offset=0x404********/ 10574 #define SRST_H_MCU_BUS_NIU 17U 10575 #define SRST_M4F0 18U 10576 #define SRST_H_M4F0 19U 10577 #define SRST_PO_M0 20U 10578 #define SRST_H_M0 21U 10579 #define SRST_DB_M0 22U 10580 #define SRST_H_INTMEM0 25U 10581 #define SRST_H_INTMEM1 26U 10582 #define SRST_H_DMAC 27U 10583 #define SRST_H_ROM 28U 10584 #define SRST_H_HIFI3_TCM 29U 10585 #define SRST_H_VOP 30U 10586 #define SRST_H_SFC0 31U 10587 /********Name=SOFTRST_CON02,Offset=0x408********/ 10588 #define SRST_H_SFC0_XIP 32U 10589 #define SRST_H_SFC1 33U 10590 #define SRST_H_SFC1_XIP 34U 10591 #define SRST_A_XIP_HYPERX8 35U 10592 #define SRST_H_AUDIOPWM 36U 10593 #define SRST_P_MCU_BUS_NIU 41U 10594 #define SRST_P_UART0 42U 10595 #define SRST_P_UART1 43U 10596 #define SRST_P_UART2 44U 10597 #define SRST_P_I2C0 45U 10598 #define SRST_P_I2C1 46U 10599 #define SRST_P_I2C2 47U 10600 /********Name=SOFTRST_CON03,Offset=0x40C********/ 10601 #define SRST_P_PWM0 48U 10602 #define SRST_P_PWM1 49U 10603 #define SRST_P_PWM2 50U 10604 #define SRST_P_SPI0 51U 10605 #define SRST_P_SPI1 52U 10606 #define SRST_P_SARADC_CONTROL 53U 10607 #define SRST_P_EFUSE 54U 10608 #define SRST_P_TIMER 55U 10609 #define SRST_P_WDT0 56U 10610 #define SRST_P_WDT1 57U 10611 #define SRST_P_WDT2 58U 10612 #define SRST_P_MAILBOX0 59U 10613 #define SRST_P_MAILBOX1 60U 10614 #define SRST_P_INT_CTRL 61U 10615 /********Name=SOFTRST_CON04,Offset=0x410********/ 10616 #define SRST_D_HIFI3 65U 10617 #define SRST_B_HIFI3 66U 10618 #define SRST_A_HIFI3_NIU 67U 10619 #define SRST_S_UART1 69U 10620 #define SRST_S_UART0 70U 10621 #define SRST_S_UART2 76U 10622 /********Name=SOFTRST_CON05,Offset=0x414********/ 10623 #define SRST_I2C0 80U 10624 #define SRST_I2C1 81U 10625 #define SRST_I2C2 82U 10626 #define SRST_PWM0 83U 10627 #define SRST_PWM1 84U 10628 #define SRST_PWM2 85U 10629 #define SRST_SPI0 86U 10630 #define SRST_SPI1 87U 10631 #define SRST_TIMER0 89U 10632 #define SRST_TIMER1 90U 10633 #define SRST_TIMER2 91U 10634 #define SRST_TIMER3 92U 10635 #define SRST_TIMER4 93U 10636 #define SRST_TIMER5 94U 10637 #define SRST_M4F0_JTRST 95U 10638 /********Name=SOFTRST_CON06,Offset=0x418********/ 10639 #define SRST_M0_JTRST 96U 10640 #define SRST_HIFI3_JTRST 97U 10641 #define SRST_EFUSE 98U 10642 #define SRST_XIP_SFC0 99U 10643 #define SRST_XIP_SFC1 100U 10644 #define SRST_S_AUDIOPWM 105U 10645 /********Name=SOFTRST_CON07,Offset=0x41C********/ 10646 #define SRST_A_PERI_BUS_NIU 114U 10647 #define SRST_H_PERI_BUS_NIU 115U 10648 #define SRST_A_VIP 116U 10649 #define SRST_A_CRYPTO 117U 10650 #define SRST_H_VIP 118U 10651 #define SRST_H_CRYPTO 119U 10652 #define SRST_H_SDMMC 120U 10653 #define SRST_H_USBOTG 121U 10654 #define SRST_H_USBOTG_PMU 122U 10655 #define SRST_P_SPI2APB 125U 10656 #define SRST_VIP 127U 10657 /********Name=SOFTRST_CON08,Offset=0x420********/ 10658 #define SRST_UTMI 128U 10659 #define SRST_OTG_ADP 129U 10660 #define SRST_CRYPTO 133U 10661 #define SRST_CRYPTO_PKA 134U 10662 #define SRST_A_WIFI_BUS_NIU 137U 10663 #define SRST_H_BUFFER 139U 10664 /********Name=SOFTRST_CON09,Offset=0x424********/ 10665 #define SRST_H_TOP_BUS_NIU 145U 10666 #define SRST_H_PDM 146U 10667 #define SRST_H_I2S0 147U 10668 #define SRST_H_I2S1 148U 10669 #define SRST_H_VAD 149U 10670 #define SRST_P_TOP_BUS_NIU 151U 10671 #define SRST_P_GPIO0 152U 10672 #define SRST_P_GPIO1 153U 10673 #define SRST_P_CRU 155U 10674 #define SRST_P_GRF 156U 10675 #define SRST_P_ACODEC 157U 10676 #define SRST_P_32KTRIM 158U 10677 #define SRST_P_TOP_TIMER 159U 10678 /********Name=SOFTRST_CON10,Offset=0x428********/ 10679 #define SRST_P_PVTM 160U 10680 #define SRST_P_TOUCH_DETECT 161U 10681 #define SRST_P_TSADC 162U 10682 #define SRST_AON 165U 10683 #define SRST_GPIO0 168U 10684 #define SRST_GPIO1 169U 10685 #define SRST_M_PDM 172U 10686 #define SRST_M_I2S8CH_0_TX 175U 10687 /********Name=SOFTRST_CON11,Offset=0x42C********/ 10688 #define SRST_M_I2S8CH_0_RX 178U 10689 #define SRST_M_I2S8CH_1_TX 182U 10690 #define SRST_M_I2S8CH_1_RX 185U 10691 #define SRST_CODEC 186U 10692 /********Name=SOFTRST_CON12,Offset=0x430********/ 10693 #define SRST_AON_JTRST 193U 10694 #define SRST_OTG_USBPHY 195U 10695 #define SRST_32KTRIM 196U 10696 #define SRST_PVTM 199U 10697 #define SRST_TOUCH_DETECT 200U 10698 #define SRST_TOP_TIMER 201U 10699 #define SRST_TSADC 203U 10700 10701 /********Name=CLKGATE_CON00,Offset=0x300********/ 10702 #define CLK_32K_FRAC_DIV_GATE 1U 10703 #define CLK_32K_GATE 2U 10704 #define CLK_GPLL_MUX_DIV_NP5_GATE 4U 10705 /********Name=CLKGATE_CON01,Offset=0x304********/ 10706 #define HCLK_MCU_BUS_PLL_GATE 16U 10707 #define HCLK_MCU_BUS_NIU_GATE 17U 10708 #define FCLK_M4F0_GATE 18U 10709 #define FCLK_M0_GATE 20U 10710 #define DCLK_M0_GATE 22U 10711 #define SCLK_M0_GATE 23U 10712 #define HCLK_INTMEM0_MCU_GATE 25U 10713 #define HCLK_INTMEM1_MCU_GATE 26U 10714 #define HCLK_DMAC_GATE 27U 10715 #define HCLK_ROM_GATE 28U 10716 #define HCLK_HIFI3_TCM_GATE 29U 10717 #define HCLK_VOP_GATE 30U 10718 #define HCLK_SFC0_GATE 31U 10719 /********Name=CLKGATE_CON02,Offset=0x308********/ 10720 #define HCLK_SFC0_XIP_GATE 32U 10721 #define HCLK_SFC1_GATE 33U 10722 #define HCLK_SFC1_XIP_GATE 34U 10723 #define ACLK_XIP_HYPERX8_GATE 35U 10724 #define HCLK_AUDIOPWM_GATE 36U 10725 #define PCLK_MCU_BUS_PLL_GATE 40U 10726 #define PCLK_MCU_BUS_NIU_GATE 41U 10727 #define PCLK_UART0_GATE 42U 10728 #define PCLK_UART1_GATE 43U 10729 #define PCLK_UART2_GATE 44U 10730 #define PCLK_I2C0_GATE 45U 10731 #define PCLK_I2C1_GATE 46U 10732 #define PCLK_I2C2_GATE 47U 10733 /********Name=CLKGATE_CON03,Offset=0x30C********/ 10734 #define PCLK_PWM0_GATE 48U 10735 #define PCLK_PWM1_GATE 49U 10736 #define PCLK_PWM2_GATE 50U 10737 #define PCLK_SPI0_GATE 51U 10738 #define PCLK_SPI1_GATE 52U 10739 #define PCLK_SARADC_CONTROL_GATE 53U 10740 #define PCLK_EFUSE_GATE 54U 10741 #define PCLK_TIMER_GATE 55U 10742 #define PCLK_WDT0_GATE 56U 10743 #define PCLK_WDT1_GATE 57U 10744 #define PCLK_WDT2_GATE 58U 10745 #define PCLK_MAILBOX0_GATE 59U 10746 #define PCLK_MAILBOX1_GATE 60U 10747 #define PCLK_INT_CTRL_GATE 61U 10748 /********Name=CLKGATE_CON04,Offset=0x310********/ 10749 #define CLK_HIFI3_DIV_GATE 64U 10750 #define CLK_HIFI3_NP5_DIV_GATE 65U 10751 #define CLK_HIFI3_GATE 66U 10752 #define ACLK_HIFI3_NIU_GATE 67U 10753 #define CLK_UART0_PLL_GATE 68U 10754 #define CLK_UART0_FRAC_GATE 69U 10755 #define SCLK_UART0_GATE 70U 10756 #define CLK_UART1_GATE 71U 10757 #define CLK_UART1_FRAC_GATE 72U 10758 #define SCLK_UART1_GATE 73U 10759 #define CLK_UART2_PLL_GATE 74U 10760 #define CLK_UART2_FRAC_GATE 75U 10761 #define SCLK_UART2_GATE 76U 10762 /********Name=CLKGATE_CON05,Offset=0x314********/ 10763 #define CLK_I2C0_PLL_GATE 80U 10764 #define CLK_I2C1_PLL_GATE 81U 10765 #define CLK_I2C2_PLL_GATE 82U 10766 #define CLK_PWM0_PLL_GATE 83U 10767 #define CLK_PWM1_PLL_GATE 84U 10768 #define CLK_PWM2_PLL_GATE 85U 10769 #define CLK_SPI0_PLL_GATE 86U 10770 #define CLK_SPI1_PLL_GATE 87U 10771 #define CLK_TIMER_PLL_GATE 88U 10772 #define CLK_TIMER0_GATE 89U 10773 #define CLK_TIMER1_GATE 90U 10774 #define CLK_TIMER2_GATE 91U 10775 #define CLK_TIMER3_GATE 92U 10776 #define CLK_TIMER4_GATE 93U 10777 #define CLK_TIMER5_GATE 94U 10778 /********Name=CLKGATE_CON06,Offset=0x318********/ 10779 #define CLK_EFUSE_GATE 98U 10780 #define CLK_XIP_SFC0_DT50_GATE 99U 10781 #define CLK_XIP_SFC1_DT50_GATE 100U 10782 #define CLK_XIP_HYPERX8_DT50_GATE 101U 10783 #define SCLK_M4F0_GATE 102U 10784 #define CLK_AUDIOPWM_PLL_GATE 103U 10785 #define CLK_AUDIOPWM_FRAC_GATE 104U 10786 #define SCLK_AUDIOPWM_GATE 105U 10787 #define CLK_PWM_CAPTURE0_PLL_GATE 106U 10788 #define CLK_PWM_CAPTURE1_PLL_GATE 107U 10789 #define CLK_PWM_CAPTURE2_PLL_GATE 108U 10790 /********Name=CLKGATE_CON07,Offset=0x31C********/ 10791 #define ACLK_PERI_BUS_PLL_GATE 112U 10792 #define HCLK_PERI_BUS_PLL_GATE 113U 10793 #define ACLK_PERI_BUS_NIU_GATE 114U 10794 #define HCLK_PERI_BUS_NIU_GATE 115U 10795 #define ACLK_VIP_GATE 116U 10796 #define ACLK_CRYPTO_GATE 117U 10797 #define HCLK_VIP_GATE 118U 10798 #define HCLK_CRYPTO_GATE 119U 10799 #define HCLK_SDMMC_GATE 120U 10800 #define HCLK_USBOTG_GATE 121U 10801 #define HCLK_USBOTG_PMU_GATE 122U 10802 #define PCLK_SPI2APB_GATE 125U 10803 #define CLK_VIP_PLL_GATE 126U 10804 /********Name=CLKGATE_CON08,Offset=0x320********/ 10805 #define CLK_OTG_ADP_GATE 129U 10806 #define CLK_SDMMC_DT50_GATE 130U 10807 #define CLK_CRYPTO_DIV_GATE 131U 10808 #define CLK_CRYPTO_NP5_DIV_GATE 132U 10809 #define CLK_CRYPTO_GATE 133U 10810 #define CLK_CRYPTO_PKA_GATE 134U 10811 #define ACLK_WIFI_BUS_GATE 136U 10812 #define ACLK_WIFI_BUS_NIU_GATE 137U 10813 #define HCLK_BUFFER_GATE 139U 10814 #define CLK80_LPW_GATE 140U 10815 #define CLK40_LPW_GATE 141U 10816 /********Name=CLKGATE_CON09,Offset=0x324********/ 10817 #define HCLK_TOP_BUS_PLL_GATE 144U 10818 #define HCLK_TOP_BUS_NIU_GATE 145U 10819 #define HCLK_PDM_GATE 146U 10820 #define HCLK_I2S0_GATE 147U 10821 #define HCLK_I2S1_GATE 148U 10822 #define HCLK_VAD_GATE 149U 10823 #define PCLK_TOP_BUS_PLL_GATE 150U 10824 #define PCLK_TOP_BUS_NIU_GATE 151U 10825 #define PCLK_GPIO0_GATE 152U 10826 #define PCLK_GPIO1_GATE 153U 10827 #define PCLK_PMU_GATE 154U 10828 #define PCLK_CRU_GATE 155U 10829 #define PCLK_GRF_GATE 156U 10830 #define PCLK_ACODEC_GATE 157U 10831 #define PCLK_32KTRIM_GATE 158U 10832 #define PCLK_TOP_TIMER_GATE 159U 10833 /********Name=CLKGATE_CON10,Offset=0x328********/ 10834 #define PCLK_PVTM_GATE 160U 10835 #define PCLK_TOUCH_DETECT_GATE 161U 10836 #define PCLK_TSADC_GATE 162U 10837 #define AON_SLEEP_CLK_GATE 165U 10838 #define CLK_32K_TOP_GATE 166U 10839 #define CLK_PMU_GATE 167U 10840 #define DBCLK_GPIO0_GATE 168U 10841 #define DBCLK_GPIO1_GATE 169U 10842 #define CLK_PMU_OSC_GATE 170U 10843 #define MCLK_PDM_PLL_GATE 172U 10844 #define CLK_I2S8CH_0_TX_PLL_GATE 173U 10845 #define CLK_I2S8CH_0_TX_FRAC_DIV_GATE 174U 10846 #define MCLK_I2S8CH_0_TX_GATE 175U 10847 /********Name=CLKGATE_CON11,Offset=0x32C********/ 10848 #define CLK_I2S8CH_0_RX_PLL_GATE 176U 10849 #define CLK_I2S8CH_0_RX_FRAC_DIV_GATE 177U 10850 #define MCLK_I2S8CH_0_RX_GATE 178U 10851 #define MCLKOUT_I2S8CH_0_GATE 179U 10852 #define CLK_I2S8CH_1_TX_PLL_GATE 180U 10853 #define CLK_I2S8CH_1_TX_FRAC_DIV_GATE 181U 10854 #define MCLK_I2S8CH_1_TX_GATE 182U 10855 #define CLK_I2S8CH_1_RX_PLL_GATE 183U 10856 #define CLK_I2S8CH_1_RX_FRAC_DIV_GATE 184U 10857 #define MCLK_I2S8CH_1_RX_GATE 185U 10858 #define SCLK_CODEC_GATE 186U 10859 #define CLK_I2C_CODEC_PLL_GATE 187U 10860 /********Name=CLKGATE_CON12,Offset=0x330********/ 10861 #define CLK_OTG_USBPHY_PLL_GATE 195U 10862 #define CLK_32KTRIM_GATE 196U 10863 #define OUTCLOCK_TEST_GATE 197U 10864 #define CLK_PVTM_GATE 199U 10865 #define CLK_TOUCH_DETECT_GATE 200U 10866 #define CLK_TIMER_TOP_PLL_GATE 201U 10867 #define CLK_SARADC_GATE 202U 10868 #define CLK_TSADC_GATE 203U 10869 10870 /********Name=CLKSEL_CON00,Offset=0x100********/ 10871 #define CLK_GPLL_MUX_NP5_DIV 0x04080000U 10872 /********Name=CLKSEL_CON01,Offset=0x104********/ 10873 #define CLK_32K_FRAC_DIV 0x20000001U 10874 /********Name=CLKSEL_CON02,Offset=0x108********/ 10875 #define HCLK_MCU_BUS_DIV 0x05000002U 10876 #define PCLK_MCU_BUS_DIV 0x05080002U 10877 /********Name=CLKSEL_CON03,Offset=0x10C********/ 10878 #define CLK_HIFI3_DIV 0x05000003U 10879 #define CLK_HIFI3_NP5_DIV 0x05080003U 10880 /********Name=CLKSEL_CON04,Offset=0x110********/ 10881 #define CLK_UART0_DIV 0x05000004U 10882 /********Name=CLKSEL_CON05,Offset=0x114********/ 10883 #define CLK_UART0_FRAC_DIV 0x20000005U 10884 /********Name=CLKSEL_CON06,Offset=0x118********/ 10885 #define CLK_UART1_DIV 0x05000006U 10886 /********Name=CLKSEL_CON07,Offset=0x11C********/ 10887 #define CLK_UART1_FRAC_DIV 0x20000007U 10888 /********Name=CLKSEL_CON08,Offset=0x120********/ 10889 #define CLK_UART2_DIV 0x05000008U 10890 /********Name=CLKSEL_CON09,Offset=0x124********/ 10891 #define CLK_UART2_FRAC_DIV 0x20000009U 10892 /********Name=CLKSEL_CON10,Offset=0x128********/ 10893 #define CLK_I2C0_DIV 0x0600000AU 10894 #define CLK_I2C1_DIV 0x0608000AU 10895 /********Name=CLKSEL_CON11,Offset=0x12C********/ 10896 #define CLK_I2C2_DIV 0x0600000BU 10897 #define CLK_I2C_CODEC_DIV 0x0608000BU 10898 /********Name=CLKSEL_CON12,Offset=0x130********/ 10899 #define CLK_PWM0_DIV 0x0600000CU 10900 #define CLK_PWM1_DIV 0x0608000CU 10901 /********Name=CLKSEL_CON13,Offset=0x134********/ 10902 #define CLK_PWM2_DIV 0x0500000DU 10903 #define CLK_EFUSE_DIV 0x0608000DU 10904 /********Name=CLKSEL_CON14,Offset=0x138********/ 10905 #define CLK_SPI0_DIV 0x0600000EU 10906 #define CLK_SPI1_DIV 0x0608000EU 10907 /********Name=CLKSEL_CON15,Offset=0x13C********/ 10908 #define CLK_TIMER_DIV 0x0600000FU 10909 #define CLK_TOP_TIMER_DIV 0x0608000FU 10910 /********Name=CLKSEL_CON16,Offset=0x140********/ 10911 #define CLK_XIP_SFC0_DIV 0x06000010U 10912 #define CLK_XIP_SFC1_DIV 0x06080010U 10913 /********Name=CLKSEL_CON17,Offset=0x144********/ 10914 #define CLK_XIP_HYPERX8_DIV 0x06000011U 10915 /********Name=CLKSEL_CON18,Offset=0x148********/ 10916 #define CLK_AUDIOPWM_DIV 0x05000012U 10917 /********Name=CLKSEL_CON19,Offset=0x14C********/ 10918 #define CLK_AUDIOPWM_FRAC_DIV 0x20000013U 10919 /********Name=CLKSEL_CON20,Offset=0x150********/ 10920 #define ACLK_PERI_BUS_DIV 0x05000014U 10921 #define HCLK_PERI_BUS_DIV 0x05080014U 10922 /********Name=CLKSEL_CON21,Offset=0x154********/ 10923 #define CLK_VIP_OUT_DIV 0x06000015U 10924 #define CLK_SDMMC_DIV 0x07080015U 10925 /********Name=CLKSEL_CON22,Offset=0x158********/ 10926 #define CLK_CRYPTO_DIV 0x05000016U 10927 #define CLK_CRYPTO_NP5_DIV 0x05080016U 10928 /********Name=CLKSEL_CON23,Offset=0x15C********/ 10929 #define CLK_SARADC_DIV 0x08000017U 10930 #define CLK_TSADC_DIV 0x08080017U 10931 /********Name=CLKSEL_CON24,Offset=0x160********/ 10932 #define HCLK_TOP_BUS_DIV 0x06000018U 10933 #define PCLK_TOP_BUS_DIV 0x06080018U 10934 /********Name=CLKSEL_CON25,Offset=0x164********/ 10935 #define MCLK_PDM_DIV 0x06000019U 10936 /********Name=CLKSEL_CON26,Offset=0x168********/ 10937 #define CLK_I2S8CH_0_TX_DIV 0x0700001AU 10938 /********Name=CLKSEL_CON27,Offset=0x16C********/ 10939 #define CLK_I2S8CH_0_TX_FRAC_DIV 0x2000001BU 10940 /********Name=CLKSEL_CON28,Offset=0x170********/ 10941 #define CLK_I2S8CH_0_RX_DIV 0x0700001CU 10942 /********Name=CLKSEL_CON29,Offset=0x174********/ 10943 #define CLK_I2S8CH_0_RX_FRAC_DIV 0x2000001DU 10944 /********Name=CLKSEL_CON30,Offset=0x178********/ 10945 #define CLK_I2S8CH_1_TX_DIV 0x0700001EU 10946 /********Name=CLKSEL_CON31,Offset=0x17C********/ 10947 #define CLK_I2S8CH_1_TX_FRAC_DIV 0x2000001FU 10948 /********Name=CLKSEL_CON32,Offset=0x180********/ 10949 #define CLK_I2S8CH_1_RX_DIV 0x07000020U 10950 /********Name=CLKSEL_CON33,Offset=0x184********/ 10951 #define CLK_I2S8CH_1_RX_FRAC_DIV 0x20000021U 10952 /********Name=CLKSEL_CON34,Offset=0x188********/ 10953 #define CLK_OTG_USBPHY_DIV 0x05000022U 10954 /********Name=CLKSEL_CON35,Offset=0x18C********/ 10955 #define OUTCLOCK_TEST_DIV 0x04000023U 10956 /********Name=CLKSEL_CON36,Offset=0x190********/ 10957 #define SCLK_M4F0_DIV 0x06000024U 10958 #define SCLK_M0_DIV 0x06080024U 10959 10960 /********Name=CLKSEL_CON00,Offset=0x100********/ 10961 #define CLK_32K_FRAC_SEL 0x01070000U 10962 #define CLK_32K_SEL 0x02050000U 10963 #define CLK_32K_SEL_CLK_32K_FRAC_DIV 0U 10964 #define CLK_32K_SEL_CLK_RTC 1U 10965 #define CLK_32K_SEL_CLK_RTC_NPOR 2U 10966 /********Name=CLKSEL_CON01,Offset=0x104********/ 10967 /********Name=CLKSEL_CON02,Offset=0x108********/ 10968 #define HCLK_MCU_BUS_SEL 0x01070002U 10969 #define HCLK_MCU_BUS_SEL_CLK_GPLL_MUX 0U 10970 #define HCLK_MCU_BUS_SEL_CLK_GPLL_MUX_NP5 1U 10971 /********Name=CLKSEL_CON03,Offset=0x10C********/ 10972 #define CLK_HIFI3_SRC_SEL 0x02060003U 10973 #define CLK_HIFI3_SRC_SEL_CLK_GPLL_MUX 0U 10974 #define CLK_HIFI3_SRC_SEL_CLK_VPLL_MUX 1U 10975 #define CLK_HIFI3_SRC_SEL_XIN_OSC0_FUNC 2U 10976 #define CLK_HIFI3_SEL 0x010F0003U 10977 #define CLK_HIFI3_SEL_CLK_HIFI3_DIV 0U 10978 #define CLK_HIFI3_SEL_CLK_HIFI3_NP5_DIV 1U 10979 /********Name=CLKSEL_CON04,Offset=0x110********/ 10980 #define CLK_UART0_PLL_SEL 0x01070004U 10981 #define CLK_UART0_PLL_SEL_CLK_GPLL_MUX 0U 10982 #define CLK_UART0_PLL_SEL_XIN_OSC0_FUNC 1U 10983 #define CLK_UART0_SEL 0x010F0004U 10984 #define CLK_UART0_SEL_CLK_UART0_DIV 0U 10985 #define CLK_UART0_SEL_CLK_UART0_FRAC_DIV 1U 10986 /********Name=CLKSEL_CON05,Offset=0x114********/ 10987 /********Name=CLKSEL_CON06,Offset=0x118********/ 10988 #define CLK_UART1_PLL_SEL 0x01070006U 10989 #define CLK_UART1_PLL_SEL_CLK_GPLL_MUX 0U 10990 #define CLK_UART1_PLL_SEL_XIN_OSC0_FUNC 1U 10991 #define CLK_UART1_SEL 0x010F0006U 10992 #define CLK_UART1_SEL_CLK_UART1_DIV 0U 10993 #define CLK_UART1_SEL_CLK_UART1_FRAC_DIV 1U 10994 /********Name=CLKSEL_CON07,Offset=0x11C********/ 10995 /********Name=CLKSEL_CON08,Offset=0x120********/ 10996 #define CLK_UART2_PLL_SEL 0x01070008U 10997 #define CLK_UART2_PLL_SEL_CLK_GPLL_MUX 0U 10998 #define CLK_UART2_PLL_SEL_XIN_OSC0_FUNC 1U 10999 #define CLK_UART2_SEL 0x010F0008U 11000 #define CLK_UART2_SEL_CLK_UART2_DIV 0U 11001 #define CLK_UART2_SEL_CLK_UART2_FRAC_DIV 1U 11002 /********Name=CLKSEL_CON09,Offset=0x124********/ 11003 /********Name=CLKSEL_CON10,Offset=0x128********/ 11004 #define CLK_I2C0_SEL 0x0206000AU 11005 #define CLK_I2C0_SEL_CLK_GPLL_MUX 0U 11006 #define CLK_I2C0_SEL_CLK_GPLL_MUX_NP5 1U 11007 #define CLK_I2C0_SEL_XIN_OSC0_FUNC 2U 11008 #define CLK_I2C1_SEL 0x020E000AU 11009 #define CLK_I2C1_SEL_CLK_GPLL_MUX 0U 11010 #define CLK_I2C1_SEL_CLK_GPLL_MUX_NP5 1U 11011 #define CLK_I2C1_SEL_XIN_OSC0_FUNC 2U 11012 /********Name=CLKSEL_CON11,Offset=0x12C********/ 11013 #define CLK_I2C2_SEL 0x0206000BU 11014 #define CLK_I2C2_SEL_CLK_GPLL_MUX 0U 11015 #define CLK_I2C2_SEL_CLK_GPLL_MUX_NP5 1U 11016 #define CLK_I2C2_SEL_XIN_OSC0_FUNC 2U 11017 #define CLK_I2C_CODEC_SEL 0x020E000BU 11018 #define CLK_I2C_CODEC_SEL_CLK_GPLL_MUX 0U 11019 #define CLK_I2C_CODEC_SEL_CLK_GPLL_MUX_NP5 1U 11020 #define CLK_I2C_CODEC_SEL_RF_AD_CLK80_SOC 2U 11021 #define CLK_I2C_CODEC_SEL_XIN_OSC0_FUNC 3U 11022 /********Name=CLKSEL_CON12,Offset=0x130********/ 11023 #define CLK_PWM0_SEL 0x0107000CU 11024 #define CLK_PWM0_SEL_CLK_GPLL_MUX 0U 11025 #define CLK_PWM0_SEL_XIN_OSC0_FUNC 1U 11026 #define CLK_PWM1_SEL 0x010F000CU 11027 #define CLK_PWM1_SEL_CLK_GPLL_MUX 0U 11028 #define CLK_PWM1_SEL_XIN_OSC0_FUNC 1U 11029 /********Name=CLKSEL_CON13,Offset=0x134********/ 11030 #define CLK_PWM2_SEL 0x0107000DU 11031 #define CLK_PWM2_SEL_CLK_GPLL_MUX 0U 11032 #define CLK_PWM2_SEL_XIN_OSC0_FUNC 1U 11033 /********Name=CLKSEL_CON14,Offset=0x138********/ 11034 #define CLK_SPI0_SEL 0x0107000EU 11035 #define CLK_SPI0_SEL_CLK_GPLL_MUX 0U 11036 #define CLK_SPI0_SEL_XIN_OSC0_FUNC 1U 11037 #define CLK_SPI1_SEL 0x010F000EU 11038 #define CLK_SPI1_SEL_CLK_GPLL_MUX 0U 11039 #define CLK_SPI1_SEL_XIN_OSC0_FUNC 1U 11040 /********Name=CLKSEL_CON15,Offset=0x13C********/ 11041 #define CLK_TIMER_SEL 0x0107000FU 11042 #define CLK_TIMER_SEL_CLK_GPLL_MUX 0U 11043 #define CLK_TIMER_SEL_XIN_OSC0_FUNC 1U 11044 #define CLK_TOP_TIMER_SEL 0x020E000FU 11045 #define CLK_TOP_TIMER_SEL_CLK_GPLL_MUX 0U 11046 #define CLK_TOP_TIMER_SEL_XIN_OSC0_FUNC 1U 11047 #define CLK_TOP_TIMER_SEL_CLK_32K 2U 11048 /********Name=CLKSEL_CON16,Offset=0x140********/ 11049 #define CLK_XIP_SFC0_SEL 0x02060010U 11050 #define CLK_XIP_SFC0_SEL_CLK_GPLL_MUX 0U 11051 #define CLK_XIP_SFC0_SEL_CLK_VPLL_MUX 1U 11052 #define CLK_XIP_SFC0_SEL_CLK_USBPLL_MUX 2U 11053 #define CLK_XIP_SFC0_SEL_XIN_OSC0_FUNC 3U 11054 #define CLK_XIP_SFC1_SEL 0x020E0010U 11055 #define CLK_XIP_SFC1_SEL_CLK_GPLL_MUX 0U 11056 #define CLK_XIP_SFC1_SEL_CLK_VPLL_MUX 1U 11057 #define CLK_XIP_SFC1_SEL_CLK_USBPLL_MUX 2U 11058 #define CLK_XIP_SFC1_SEL_XIN_OSC0_FUNC 3U 11059 /********Name=CLKSEL_CON17,Offset=0x144********/ 11060 #define CLK_XIP_HYPERX8_SEL 0x02060011U 11061 #define CLK_XIP_HYPERX8_SEL_CLK_GPLL_MUX 0U 11062 #define CLK_XIP_HYPERX8_SEL_CLK_VPLL_MUX 1U 11063 #define CLK_XIP_HYPERX8_SEL_CLK_USBPLL_MUX 2U 11064 #define CLK_XIP_HYPERX8_SEL_XIN_OSC0_FUNC 3U 11065 /********Name=CLKSEL_CON18,Offset=0x148********/ 11066 #define CLK_AUDIOPWM_SRC_SEL 0x02060012U 11067 #define CLK_AUDIOPWM_SRC_SEL_CLK_GPLL_MUX 0U 11068 #define CLK_AUDIOPWM_SRC_SEL_CLK_VPLL_MUX 1U 11069 #define CLK_AUDIOPWM_SRC_SEL_CLK_USBPLL_MUX 2U 11070 #define CLK_AUDIOPWM_SRC_SEL_XIN_OSC0_FUNC 3U 11071 #define SCLK_AUDIOPWM_SEL 0x010F0012U 11072 #define SCLK_AUDIOPWM_SEL_CLK_AUDIOPWM_DIV 0U 11073 #define SCLK_AUDIOPWM_SEL_CLK_AUDIOPWM_FRAC_DIV 1U 11074 /********Name=CLKSEL_CON19,Offset=0x14C********/ 11075 /********Name=CLKSEL_CON20,Offset=0x150********/ 11076 #define ACLK_PERI_BUS_SEL 0x01070014U 11077 #define ACLK_PERI_BUS_SEL_CLK_GPLL_MUX 0U 11078 #define ACLK_PERI_BUS_SEL_CLK_GPLL_MUX_NP5 1U 11079 /********Name=CLKSEL_CON21,Offset=0x154********/ 11080 #define CLK_VIP_OUT_SEL 0x02060015U 11081 #define CLK_VIP_OUT_SEL_CLK_GPLL_MUX 0U 11082 #define CLK_VIP_OUT_SEL_CLK_VPLL_MUX 1U 11083 #define CLK_VIP_OUT_SEL_XIN_OSC0_FUNC 2U 11084 #define CLK_SDMMC_SEL 0x010F0015U 11085 #define CLK_SDMMC_SEL_CLK_GPLL_MUX 0U 11086 #define CLK_SDMMC_SEL_XIN_OSC0_FUNC 1U 11087 /********Name=CLKSEL_CON22,Offset=0x158********/ 11088 #define CLK_CRYPTO_SRC_SEL 0x01070016U 11089 #define CLK_CRYPTO_SRC_SEL_CLK_GPLL_MUX 0U 11090 #define CLK_CRYPTO_SRC_SEL_XIN_OSC0_FUNC 1U 11091 #define CLK_CRYPTO_PKA_SEL 0x010E0016U 11092 #define CLK_CRYPTO_PKA_SEL_CLK_CRYPTO_DIV 0U 11093 #define CLK_CRYPTO_PKA_SEL_CLK_CRYPTO_NP5_DIV 1U 11094 #define CLK_CRYPTO_SEL 0x010F0016U 11095 #define CLK_CRYPTO_SEL_CLK_CRYPTO_DIV 0U 11096 #define CLK_CRYPTO_SEL_CLK_CRYPTO_NP5_DIV 1U 11097 /********Name=CLKSEL_CON23,Offset=0x15C********/ 11098 /********Name=CLKSEL_CON24,Offset=0x160********/ 11099 #define HCLK_TOP_BUS_SEL 0x02060018U 11100 #define HCLK_TOP_BUS_SEL_CLK_GPLL_MUX 0U 11101 #define HCLK_TOP_BUS_SEL_RF_AD_CLK80_SOC 1U 11102 #define HCLK_TOP_BUS_SEL_XIN_OSC0_FUNC 2U 11103 #define PCLK_TOP_BUS_SEL 0x020E0018U 11104 #define PCLK_TOP_BUS_SEL_CLK_GPLL_MUX 0U 11105 #define PCLK_TOP_BUS_SEL_RF_AD_CLK80_SOC 1U 11106 #define PCLK_TOP_BUS_SEL_XIN_OSC0_FUNC 2U 11107 /********Name=CLKSEL_CON25,Offset=0x164********/ 11108 #define MCLK_PDM_SEL 0x02060019U 11109 #define MCLK_PDM_SEL_CLK_GPLL_MUX 0U 11110 #define MCLK_PDM_SEL_CLK_VPLL_MUX 1U 11111 #define MCLK_PDM_SEL_RF_AD_CLK80_SOC 2U 11112 #define MCLK_PDM_SEL_XIN_OSC0_FUNC 3U 11113 /********Name=CLKSEL_CON26,Offset=0x168********/ 11114 #define CLK_I2S8CH_0_TX_PLL_SEL 0x0208001AU 11115 #define CLK_I2S8CH_0_TX_PLL_SEL_CLK_GPLL_MUX 0U 11116 #define CLK_I2S8CH_0_TX_PLL_SEL_CLK_VPLL_MUX 1U 11117 #define CLK_I2S8CH_0_TX_PLL_SEL_CLK_USBPLL_MUX 2U 11118 #define CLK_I2S8CH_0_TX_PLL_SEL_XIN_OSC0_FUNC 3U 11119 #define MCLK_I2S8CH_0_TX_MUX_SEL 0x020A001AU 11120 #define MCLK_I2S8CH_0_TX_MUX_SEL_CLK_I2S8CH_0_TX_DIV 0U 11121 #define MCLK_I2S8CH_0_TX_MUX_SEL_CLK_I2S8CH_0_TX_FRAC_DIV 1U 11122 #define MCLK_I2S8CH_0_TX_MUX_SEL_I2S8CH_0_MCLKIN 2U 11123 #define MCLKOUT_I2S8CH_0_SEL 0x020E001AU 11124 #define MCLKOUT_I2S8CH_0_SEL_MCLK_I2S8CH_0_TX_MUX 0U 11125 #define MCLKOUT_I2S8CH_0_SEL_MCLK_I2S8CH_0_RX_MUX 1U 11126 #define MCLKOUT_I2S8CH_0_SEL_XIN_OSC0_HALF 2U 11127 /********Name=CLKSEL_CON27,Offset=0x16C********/ 11128 /********Name=CLKSEL_CON28,Offset=0x170********/ 11129 #define CLK_I2S8CH_0_RX_PLL_SEL 0x0208001CU 11130 #define CLK_I2S8CH_0_RX_PLL_SEL_CLK_GPLL_MUX 0U 11131 #define CLK_I2S8CH_0_RX_PLL_SEL_CLK_VPLL_MUX 1U 11132 #define CLK_I2S8CH_0_RX_PLL_SEL_CLK_USBPLL_MUX 2U 11133 #define CLK_I2S8CH_0_RX_PLL_SEL_XIN_OSC0_FUNC 3U 11134 #define MCLK_I2S8CH_0_RX_MUX_SEL 0x020A001CU 11135 #define MCLK_I2S8CH_0_RX_MUX_SEL_CLK_I2S8CH_0_RX_DIV 0U 11136 #define MCLK_I2S8CH_0_RX_MUX_SEL_CLK_I2S8CH_0_RX_FRAC_DIV 1U 11137 #define MCLK_I2S8CH_0_RX_MUX_SEL_I2S8CH_0_MCLKIN 2U 11138 /********Name=CLKSEL_CON29,Offset=0x174********/ 11139 /********Name=CLKSEL_CON30,Offset=0x178********/ 11140 #define CLK_I2S8CH_1_TX_PLL_SEL 0x0208001EU 11141 #define CLK_I2S8CH_1_TX_PLL_SEL_CLK_GPLL_MUX 0U 11142 #define CLK_I2S8CH_1_TX_PLL_SEL_CLK_VPLL_MUX 1U 11143 #define CLK_I2S8CH_1_TX_PLL_SEL_CLK_USBPLL_MUX 2U 11144 #define CLK_I2S8CH_1_TX_PLL_SEL_XIN_OSC0_FUNC 3U 11145 #define MCLK_I2S8CH_1_TX_MUX_SEL 0x020A001EU 11146 #define MCLK_I2S8CH_1_TX_MUX_SEL_CLK_I2S8CH_1_TX_DIV 0U 11147 #define MCLK_I2S8CH_1_TX_MUX_SEL_CLK_I2S8CH_1_TX_FRAC_DIV 1U 11148 #define MCLK_I2S8CH_1_TX_MUX_SEL_I2S8CH_1_MCLKIN 2U 11149 #define CLK_CODEC_SEL 0x010F001EU 11150 #define CLK_CODEC_SEL_MCLK_I2S8CH_1_TX_MUX 0U 11151 #define CLK_CODEC_SEL_MCLK_I2S8CH_1_RX_MUX 1U 11152 /********Name=CLKSEL_CON31,Offset=0x17C********/ 11153 /********Name=CLKSEL_CON32,Offset=0x180********/ 11154 #define CLK_I2S8CH_1_RX_PLL_SEL 0x02080020U 11155 #define CLK_I2S8CH_1_RX_PLL_SEL_CLK_GPLL_MUX 0U 11156 #define CLK_I2S8CH_1_RX_PLL_SEL_CLK_VPLL_MUX 1U 11157 #define CLK_I2S8CH_1_RX_PLL_SEL_CLK_USBPLL_MUX 2U 11158 #define CLK_I2S8CH_1_RX_PLL_SEL_XIN_OSC0_FUNC 3U 11159 #define MCLK_I2S8CH_1_RX_MUX_SEL 0x020A0020U 11160 #define MCLK_I2S8CH_1_RX_MUX_SEL_CLK_I2S8CH_1_RX_DIV 0U 11161 #define MCLK_I2S8CH_1_RX_MUX_SEL_CLK_I2S8CH_1_RX_FRAC_DIV 1U 11162 #define MCLK_I2S8CH_1_RX_MUX_SEL_I2S8CH_1_MCLKIN 2U 11163 /********Name=CLKSEL_CON33,Offset=0x184********/ 11164 /********Name=CLKSEL_CON34,Offset=0x188********/ 11165 /********Name=CLKSEL_CON35,Offset=0x18C********/ 11166 #define OUTCLOCK_TEST_SEL 0x05040023U 11167 #define OUTCLOCK_TEST_SEL_XIN_OSC0 0U 11168 #define OUTCLOCK_TEST_SEL_CLK_32K 1U 11169 #define OUTCLOCK_TEST_SEL_CLK_GPLL_MUX 2U 11170 #define OUTCLOCK_TEST_SEL_CLK_VPLL_MUX 3U 11171 #define OUTCLOCK_TEST_SEL_CLK_USBPLL_MUX 4U 11172 #define OUTCLOCK_TEST_SEL_HCLK_MCU_BUS 5U 11173 #define OUTCLOCK_TEST_SEL_ACLK_PERI_BUS 6U 11174 #define OUTCLOCK_TEST_SEL_HCLK_PERI_BUS 7U 11175 #define OUTCLOCK_TEST_SEL_HCLK_TOP_BUS 8U 11176 #define OUTCLOCK_TEST_SEL_ACLK_WIFI_BUS 9U 11177 #define OUTCLOCK_TEST_SEL_CLK_HIFI3 10U 11178 #define OUTCLOCK_TEST_SEL_SCLK_AUDIOPWM 11U 11179 #define OUTCLOCK_TEST_SEL_CLK_EFUSE 12U 11180 #define OUTCLOCK_TEST_SEL_CLK_I2C0 13U 11181 #define OUTCLOCK_TEST_SEL_CLK_I2C1 14U 11182 #define OUTCLOCK_TEST_SEL_CLK_PWM0 15U 11183 #define OUTCLOCK_TEST_SEL_CLK_SPI0 16U 11184 #define OUTCLOCK_TEST_SEL_CLK_SPI1 17U 11185 #define OUTCLOCK_TEST_SEL_CLK_TIMER 18U 11186 #define OUTCLOCK_TEST_SEL_CLK_XIP_HYPERX8 19U 11187 #define OUTCLOCK_TEST_SEL_CLK_XIP_SFC0 20U 11188 #define OUTCLOCK_TEST_SEL_CLK_XIP_SFC1 21U 11189 #define OUTCLOCK_TEST_SEL_SCLK_UART0 22U 11190 #define OUTCLOCK_TEST_SEL_SCLK_UART1 23U 11191 #define OUTCLOCK_TEST_SEL_CLK_CRYPTO 24U 11192 #define OUTCLOCK_TEST_SEL_CLK_SDMMC 25U 11193 #define OUTCLOCK_TEST_SEL_CLK_VIP_OUT 26U 11194 #define OUTCLOCK_TEST_SEL_CLK_CODEC 27U 11195 #define OUTCLOCK_TEST_SEL_MCLK_I2S8CH_1_RX 28U 11196 #define OUTCLOCK_TEST_SEL_MCLK_I2S8CH_1_TX 29U 11197 #define OUTCLOCK_TEST_SEL_USB_PHYCLK 30U 11198 #define OUTCLOCK_TEST_SEL_CLK_OTG_USBPHY 31U 11199 11200 #define CLK(mux, div) \ 11201 (((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | (((div) & 0x0F0F0000U) << 4)) 11202 11203 #ifndef __ASSEMBLY__ 11204 typedef enum CLOCK_Name { 11205 CLK_INVALID = 0U, 11206 PLL_GPLL, 11207 PLL_VPLL, 11208 CLK_32K_FRAC = CLK(CLK_32K_FRAC_SEL, CLK_32K_FRAC_DIV), 11209 CLK_32K = CLK(CLK_32K_SEL, 0U), 11210 CLK_GPLL_MUX_NP5 = CLK(0U, CLK_GPLL_MUX_NP5_DIV), 11211 HCLK_MCU_BUS = CLK(HCLK_MCU_BUS_SEL, HCLK_MCU_BUS_DIV), 11212 PCLK_MCU_BUS = CLK(0U, PCLK_MCU_BUS_DIV), 11213 CLK_HIFI3_SRC = CLK(CLK_HIFI3_SRC_SEL, 0U), 11214 CLK_HIFI3_D = CLK(0U, CLK_HIFI3_DIV), 11215 CLK_HIFI3_NP5 = CLK(0U, CLK_HIFI3_NP5_DIV), 11216 CLK_HIFI3 = CLK(CLK_HIFI3_SEL, 0U), 11217 CLK_UART0_PLL = CLK(CLK_UART0_PLL_SEL, CLK_UART0_DIV), 11218 CLK_UART0_FRAC = CLK(0U, CLK_UART0_FRAC_DIV), 11219 CLK_UART0 = CLK(CLK_UART0_SEL, 0U), 11220 CLK_UART1_PLL = CLK(CLK_UART1_PLL_SEL, CLK_UART1_DIV), 11221 CLK_UART1_FRAC = CLK(0U, CLK_UART1_FRAC_DIV), 11222 CLK_UART1 = CLK(CLK_UART1_SEL, 0U), 11223 CLK_UART2_PLL = CLK(CLK_UART2_PLL_SEL, CLK_UART2_DIV), 11224 CLK_UART2_FRAC = CLK(0U, CLK_UART2_FRAC_DIV), 11225 CLK_UART2 = CLK(CLK_UART2_SEL, 0U), 11226 CLK_I2C0 = CLK(CLK_I2C0_SEL, CLK_I2C0_DIV), 11227 CLK_I2C1 = CLK(CLK_I2C1_SEL, CLK_I2C1_DIV), 11228 CLK_I2C2 = CLK(CLK_I2C2_SEL, CLK_I2C2_DIV), 11229 CLK_I2C_CODEC = CLK(CLK_I2C_CODEC_SEL, CLK_I2C_CODEC_DIV), 11230 CLK_PWM0 = CLK(CLK_PWM0_SEL, CLK_PWM0_DIV), 11231 CLK_PWM1 = CLK(CLK_PWM1_SEL, CLK_PWM1_DIV), 11232 CLK_PWM2 = CLK(CLK_PWM2_SEL, CLK_PWM2_DIV), 11233 CLK_EFUSE = CLK(0U, CLK_EFUSE_DIV), 11234 CLK_SPI0 = CLK(CLK_SPI0_SEL, CLK_SPI0_DIV), 11235 CLK_SPI1 = CLK(CLK_SPI1_SEL, CLK_SPI1_DIV), 11236 CLK_TIMER = CLK(CLK_TIMER_SEL, CLK_TIMER_DIV), 11237 CLK_TOP_TIMER = CLK(CLK_TOP_TIMER_SEL, CLK_TOP_TIMER_DIV), 11238 CLK_XIP_SFC0 = CLK(CLK_XIP_SFC0_SEL, CLK_XIP_SFC0_DIV), 11239 CLK_XIP_SFC1 = CLK(CLK_XIP_SFC1_SEL, CLK_XIP_SFC1_DIV), 11240 CLK_XIP_HYPERX8 = CLK(CLK_XIP_HYPERX8_SEL, CLK_XIP_HYPERX8_DIV), 11241 SCLK_M4F0 = CLK(0U, SCLK_M4F0_DIV), 11242 CLK_AUDIOPWM_PLL = CLK(CLK_AUDIOPWM_SRC_SEL, CLK_AUDIOPWM_DIV), 11243 CLK_AUDIOPWM_FRAC = CLK(0U, CLK_AUDIOPWM_FRAC_DIV), 11244 CLK_AUDIOPWM = CLK(SCLK_AUDIOPWM_SEL, 0U), 11245 ACLK_PERI_BUS = CLK(ACLK_PERI_BUS_SEL, ACLK_PERI_BUS_DIV), 11246 HCLK_PERI_BUS = CLK(0U, HCLK_PERI_BUS_DIV), 11247 CLK_VIP_OUT = CLK(CLK_VIP_OUT_SEL, CLK_VIP_OUT_DIV), 11248 CLK_SDMMC = CLK(CLK_SDMMC_SEL, CLK_SDMMC_DIV), 11249 CLK_CRYPTO_D = CLK(CLK_CRYPTO_SRC_SEL, CLK_CRYPTO_DIV), 11250 CLK_CRYPTO_NP5 = CLK(CLK_CRYPTO_SRC_SEL, CLK_CRYPTO_NP5_DIV), 11251 CLK_CRYPTO = CLK(CLK_CRYPTO_SEL, 0U), 11252 CLK_CRYPTO_PKA = CLK(CLK_CRYPTO_PKA_SEL, 0U), 11253 CLK_SARADC = CLK(0U, CLK_SARADC_DIV), 11254 CLK_TSADC = CLK(0U, CLK_TSADC_DIV), 11255 HCLK_TOP_BUS = CLK(HCLK_TOP_BUS_SEL, HCLK_TOP_BUS_DIV), 11256 PCLK_TOP_BUS = CLK(PCLK_TOP_BUS_SEL, PCLK_TOP_BUS_DIV), 11257 MCLK_PDM = CLK(MCLK_PDM_SEL, MCLK_PDM_DIV), 11258 CLK_I2S8CH_0_TX_PLL = CLK(CLK_I2S8CH_0_TX_PLL_SEL, CLK_I2S8CH_0_TX_DIV), 11259 CLK_I2S8CH_0_TX_FRAC = CLK(0U, CLK_I2S8CH_0_TX_FRAC_DIV), 11260 MCLK_I2S8CH_0_TX = CLK(MCLK_I2S8CH_0_TX_MUX_SEL, 0U), 11261 MCLKOUT_I2S8CH_0 = CLK(MCLKOUT_I2S8CH_0_SEL, 0U), 11262 CLK_I2S8CH_0_RX_PLL = CLK(CLK_I2S8CH_0_RX_PLL_SEL, CLK_I2S8CH_0_RX_DIV), 11263 CLK_I2S8CH_0_RX_FRAC = CLK(0U, CLK_I2S8CH_0_RX_FRAC_DIV), 11264 MCLK_I2S8CH_0_RX = CLK(MCLK_I2S8CH_0_RX_MUX_SEL, 0U), 11265 CLK_I2S8CH_1_TX_PLL = CLK(CLK_I2S8CH_1_TX_PLL_SEL, CLK_I2S8CH_1_TX_DIV), 11266 CLK_I2S8CH_1_TX_FRAC = CLK(0U, CLK_I2S8CH_1_TX_FRAC_DIV), 11267 MCLK_I2S8CH_1_TX = CLK(MCLK_I2S8CH_1_TX_MUX_SEL, 0U), 11268 CLK_CODEC = CLK(CLK_CODEC_SEL, 0U), 11269 CLK_I2S8CH_1_RX_PLL = CLK(CLK_I2S8CH_1_RX_PLL_SEL, CLK_I2S8CH_1_RX_DIV), 11270 CLK_I2S8CH_1_RX_FRAC = CLK(0U, CLK_I2S8CH_1_RX_FRAC_DIV), 11271 MCLK_I2S8CH_1_RX = CLK(MCLK_I2S8CH_1_RX_MUX_SEL, 0U), 11272 CLK_OTG_USBPHY = CLK(0U, CLK_OTG_USBPHY_DIV), 11273 SCLK_M0 = CLK(0U, SCLK_M0_DIV), 11274 } eCLOCK_Name; 11275 11276 #endif /* __ASSEMBLY__ */ 11277 11278 #ifdef __cplusplus 11279 } 11280 #endif /* __cplusplus */ 11281 #endif /* __RK2206_H */ 11282